diff --git a/src/arduino.c b/src/arduino.c
index f3e7f8d1..3ca83615 100644
--- a/src/arduino.c
+++ b/src/arduino.c
@@ -88,7 +88,13 @@ static int arduino_open(PROGRAMMER *pgm, const char *port) {
   // This code assumes a negative-logic USB to TTL serial adapter
   // Set RTS/DTR high to discharge the series-capacitor, if present
   serial_set_dtr_rts(&pgm->fd, 0);
-  usleep(50 * 1000);
+  /*
+   * Long wait needed for optiboot: otherwise the second of two bootloader
+   * calls in quick succession fails:
+   *
+   * avrdude -c arduino -qqp m328p -U x.hex; avrdude -c arduino -qqp m328p -U x.hex
+   */
+  usleep(250 * 1000);
   // Pull the RTS/DTR line low to reset AVR
   serial_set_dtr_rts(&pgm->fd, 1);
   usleep(50 * 1000);
diff --git a/src/stk500.c b/src/stk500.c
index f6bf70e9..71c35069 100644
--- a/src/stk500.c
+++ b/src/stk500.c
@@ -98,15 +98,11 @@ int stk500_getsync(const PROGRAMMER *pgm) {
     // Restart Arduino bootloader for every sync attempt
     if (strcmp(pgm->type, "Arduino") == 0 && attempt > 0) {
       // This code assumes a negative-logic USB to TTL serial adapter
-      // Set RTS/DTR high to discharge the series-capacitor, if present
-      serial_set_dtr_rts(&pgm->fd, 0);
-      usleep(50 * 1000);
-      // Pull the RTS/DTR line low to reset AVR
+      // Pull the RTS/DTR line low to reset AVR: it is still high from open()/last attempt
       serial_set_dtr_rts(&pgm->fd, 1);
-      usleep(50 * 1000);
+      usleep(20*1000);
       // Set the RTS/DTR line back to high
       serial_set_dtr_rts(&pgm->fd, 0);
-      usleep(50 * 1000);
       stk500_drain(pgm, 0);
     }
 
diff --git a/src/urclock.c b/src/urclock.c
index a15a37e7..b728be7f 100644
--- a/src/urclock.c
+++ b/src/urclock.c
@@ -2240,16 +2240,15 @@ static int urclock_open(PROGRAMMER *pgm, const char *port) {
   // This code assumes a negative-logic USB to TTL serial adapter
   // Set RTS/DTR high to discharge the series-capacitor, if present
   serial_set_dtr_rts(&pgm->fd, 0);
-  usleep(50 * 1000);
+  usleep(20*1000);
   // Pull the RTS/DTR line low to reset AVR
   serial_set_dtr_rts(&pgm->fd, 1);
-  usleep(50 * 1000);
+  usleep(20*1000);
   // Set the RTS/DTR line back to high
   serial_set_dtr_rts(&pgm->fd, 0);
-  usleep(50 * 1000);
 
-  if((70+ur.delay) > 0)
-    usleep((70+ur.delay)*1000); // Wait until board comes out of reset
+  if((100+ur.delay) > 0)
+    usleep((100+ur.delay)*1000); // Wait until board comes out of reset
 
   pmsg_debug("%4ld ms: enter urclock_getsync()\n", avr_mstimestamp());
   if(urclock_getsync(pgm) < 0)