From 524e25affe5bc6c4f7a8a423a053b695c8c93d1b Mon Sep 17 00:00:00 2001 From: Stefan Rueger Date: Sun, 18 Aug 2024 01:54:16 +0100 Subject: [PATCH] Reformat spacing/comments in src/jtagmkI_private.h --- src/jtagmkI_private.h | 121 +++++++++++++++++++----------------------- 1 file changed, 55 insertions(+), 66 deletions(-) diff --git a/src/jtagmkI_private.h b/src/jtagmkI_private.h index e2134823..bee84d95 100644 --- a/src/jtagmkI_private.h +++ b/src/jtagmkI_private.h @@ -17,73 +17,66 @@ * along with this program. If not, see . */ +// JTAG ICE mkI definitions -/* - * JTAG ICE mkI definitions - */ +// ICE command codes -/* ICE command codes */ -/* 0x20 Get Synch [Resp_OK] */ +// 0x20 Get Synch [Resp_OK] #define CMD_GET_SYNC ' ' -/* 0x31 Single Step [Sync_CRC/EOP] [Resp_OK] */ -/* 0x32 Read PC [Sync_CRC/EOP] [Resp_OK] [program counter] - * [Resp_OK] */ -/* 0x33 Write PC [program counter] [Sync_CRC/EOP] [Resp_OK] - * [Resp_OK] */ -/* 0xA2 Firmware Upgrade [upgrade string] [Sync_CRC/EOP] [Resp_OK] - * [Resp_OK] */ -/* 0xA0 Set Device Descriptor [device info] [Sync_CRC/EOP] [Resp_OK] - * [Resp_OK] */ +// 0x31 Single Step [Sync_CRC/EOP] [Resp_OK] + +// 0x32 Read PC [Sync_CRC/EOP] [Resp_OK] [program counter] [Resp_OK] + +// 0x33 Write PC [program counter] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] + +// 0xA2 Firmware Upgrade [upgrade string] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] + +// 0xA0 Set Device Descriptor [device info] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] #define CMD_SET_DEVICE_DESCRIPTOR 0xA0 -/* 0x42 Set Parameter [parameter] [setting] [Sync_CRC/EOP] [Resp_OK] - * [Resp_OK] */ +// 0x42 Set Parameter [parameter] [setting] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] #define CMD_SET_PARAM 'B' -/* 0x46 Forced Stop [Sync_CRC/EOP] [Resp_OK] [checksum][program - * counter] [Resp_OK] */ +// 0x46 Forced Stop [Sync_CRC/EOP] [Resp_OK] [checksum][program counter] [Resp_OK] #define CMD_STOP 'F' -/* 0x47 Go [Sync_CRC/EOP] [Resp_OK] */ +// 0x47 Go [Sync_CRC/EOP] [Resp_OK] #define CMD_GO 'G' -/* 0x52 Read Memory [memory type] [word count] [start address] - * [Sync_CRC/EOP] [Resp_OK] [word 0] ... [word n] [checksum] - * [Resp_OK] */ +// 0x52 Read Memory [memory type] [word count] [start address] [Sync_CRC/EOP] [Resp_OK] [word 0] ... [word n] [checksum] [Resp_OK] #define CMD_READ_MEM 'R' -/* 0x53 Get Sign On [Sync_CRC/EOP] [Resp_OK] ["AVRNOCD"] [Resp_OK] */ +// 0x53 Get Sign On [Sync_CRC/EOP] [Resp_OK] ["AVRNOCD"] [Resp_OK] #define CMD_GET_SIGNON 'S' -/* 0XA1 Erase Page spm [address] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */ +// 0xa1 Erase Page spm [address] [Sync_CRC/EOP] [Resp_OK] [Resp_OK] -/* 0x57 Write Memory [memory type] [word count] [start address] - * [Sync_CRC/EOP] [Resp_OK] [Cmd_DATA] [word 0] ... [word n] */ +// 0x57 Write Memory [memory type] [word count] [start address] [Sync_CRC/EOP] [Resp_OK] [Cmd_DATA] [word 0] ... [word n] #define CMD_WRITE_MEM 'W' -/* Second half of write memory: the data command. Undocumented. */ +// Second half of write memory: the data command; undocumented #define CMD_DATA 'h' -/* 0x64 Get Debug Info [Sync_CRC/EOP] [Resp_OK] [0x00] [Resp_OK] */ +// 0x64 Get Debug Info [Sync_CRC/EOP] [Resp_OK] [0x00] [Resp_OK] + /* 0x71 Get Parameter [parameter] [Sync_CRC/EOP] [Resp_OK] [setting] * [Resp_OK] */ #define CMD_GET_PARAM 'q' -/* 0x78 Reset [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */ +// 0x78 Reset [Sync_CRC/EOP] [Resp_OK] [Resp_OK] #define CMD_RESET 'x' -/* 0xA3 Enter Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */ +// 0xA3 Enter Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] #define CMD_ENTER_PROGMODE 0xa3 -/* 0xA4 Leave Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */ +// 0xA4 Leave Progmode [Sync_CRC/EOP] [Resp_OK] [Resp_OK] #define CMD_LEAVE_PROGMODE 0xa4 -/* 0xA5 Chip Erase [Sync_CRC/EOP] [Resp_OK] [Resp_OK] */ +// 0xA5 Chip Erase [Sync_CRC/EOP] [Resp_OK] [Resp_OK] #define CMD_CHIP_ERASE 0xa5 - -/* ICE responses */ +// ICE responses #define RESP_OK 'A' #define RESP_BREAK 'B' #define RESP_INFO 'G' @@ -130,37 +123,33 @@ #define JTAG_BITRATE_250_kHz 0xfd #define JTAG_BITRATE_125_kHz 0xfb -/* memories for CMND_{READ,WRITE}_MEMORY */ -#define MTYPE_IO_SHADOW 0x30 /* cached IO registers? */ -#define MTYPE_SRAM 0x20 /* target's SRAM or [ext.] IO registers */ -#define MTYPE_EEPROM 0x22 /* EEPROM, what way? */ -#define MTYPE_EVENT 0x60 /* ICE event memory */ -#define MTYPE_SPM 0xA0 /* flash through LPM/SPM */ -#define MTYPE_FLASH_PAGE 0xB0 /* flash in programming mode */ -#define MTYPE_EEPROM_PAGE 0xB1 /* EEPROM in programming mode */ -#define MTYPE_FUSE_BITS 0xB2 /* fuse bits in programming mode */ -#define MTYPE_LOCK_BITS 0xB3 /* lock bits in programming mode */ -#define MTYPE_SIGN_JTAG 0xB4 /* signature in programming mode */ -#define MTYPE_OSCCAL_BYTE 0xB5 /* osccal cells in programming mode */ +// Memories for CMND_{READ,WRITE}_MEMORY +#define MTYPE_IO_SHADOW 0x30 // Cached IO registers? +#define MTYPE_SRAM 0x20 // Target's SRAM or [ext.] IO registers +#define MTYPE_EEPROM 0x22 // EEPROM, what way? +#define MTYPE_EVENT 0x60 // ICE event memory +#define MTYPE_SPM 0xA0 // Flash through LPM/SPM +#define MTYPE_FLASH_PAGE 0xB0 // Flash in programming mode +#define MTYPE_EEPROM_PAGE 0xB1 // EEPROM in programming mode +#define MTYPE_FUSE_BITS 0xB2 // Fuse bits in programming mode +#define MTYPE_LOCK_BITS 0xB3 // Lock bits in programming mode +#define MTYPE_SIGN_JTAG 0xB4 // Signature in programming mode +#define MTYPE_OSCCAL_BYTE 0xB5 // Osccal cells in programming mode -struct device_descriptor -{ - unsigned char ucReadIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */ - unsigned char ucWriteIO[8]; /*LSB = IOloc 0, MSB = IOloc63 */ - unsigned char ucReadIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */ - unsigned char ucWriteIOShadow[8]; /*LSB = IOloc 0, MSB = IOloc63 */ - unsigned char ucReadExtIO[20]; /*LSB = IOloc 96, MSB = IOloc255 */ - unsigned char ucWriteExtIO[20]; /*LSB = IOloc 96, MSB = IOloc255 */ - unsigned char ucReadIOExtShadow[20]; /*LSB = IOloc 96, MSB = IOloc255 */ - unsigned char ucWriteIOExtShadow[20];/*LSB = IOloc 96, MSB = IOloc255 */ - unsigned char ucIDRAddress; /*IDR address */ - unsigned char ucSPMCRAddress; /*SPMCR Register address and dW BasePC */ - unsigned char ucRAMPZAddress; /*RAMPZ Register address in SRAM I/O */ - /*space */ - unsigned char uiFlashPageSize[2]; /*Device Flash Page Size, Size = */ - /*2 exp ucFlashPageSize */ - unsigned char ucEepromPageSize; /*Device Eeprom Page Size in bytes */ - unsigned char ulBootAddress[4]; /*Device Boot Loader Start Address */ - unsigned char uiUpperExtIOLoc; /*Topmost (last) extended I/O */ - /*location, 0 if no external I/O */ +struct device_descriptor { + unsigned char ucReadIO[8]; // LSB = IOloc 0, MSB = IOloc63 + unsigned char ucWriteIO[8]; // LSB = IOloc 0, MSB = IOloc63 + unsigned char ucReadIOShadow[8]; // LSB = IOloc 0, MSB = IOloc63 + unsigned char ucWriteIOShadow[8]; // LSB = IOloc 0, MSB = IOloc63 + unsigned char ucReadExtIO[20]; // LSB = IOloc 96, MSB = IOloc255 + unsigned char ucWriteExtIO[20]; // LSB = IOloc 96, MSB = IOloc255 + unsigned char ucReadIOExtShadow[20]; // LSB = IOloc 96, MSB = IOloc255 + unsigned char ucWriteIOExtShadow[20]; // LSB = IOloc 96, MSB = IOloc255 + unsigned char ucIDRAddress; // IDR address + unsigned char ucSPMCRAddress; // SPMCR Register address and dW BasePC + unsigned char ucRAMPZAddress; // RAMPZ Register address in SRAM I/O space + unsigned char uiFlashPageSize[2]; // Device Flash Page Size, Size = 2 exp ucFlashPageSize + unsigned char ucEepromPageSize; // Device Eeprom Page Size in bytes + unsigned char ulBootAddress[4]; // Device Boot Loader Start Address + unsigned char uiUpperExtIOLoc; // Topmost (last) extended I/O location, 0 if no external I/O };