From 5830fbfdc36ca1d57f921382ab37b2a27144908f Mon Sep 17 00:00:00 2001 From: stefanrueger Date: Mon, 27 Nov 2023 00:04:00 +1300 Subject: [PATCH] Update avrintel.[ch] with register files --- src/avrintel.c | 39285 ++++++++++++++++++++++++++++++++++++++++++++++- src/avrintel.h | 514 +- 2 files changed, 39413 insertions(+), 386 deletions(-) diff --git a/src/avrintel.c b/src/avrintel.c index 5b033cb6..a2af3279 100644 --- a/src/avrintel.c +++ b/src/avrintel.c @@ -9,7 +9,7 @@ * Meta-author Stefan Rueger * * v 1.3 - * 15.08.2023 + * 27.11.2023 * */ @@ -107,1925 +107,2309 @@ const uPcore_t uP_table[] = { // Value of -1 typically means unknown //ATtiny4 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny4", 0, F_AVR8L, {0x1E, 0x8F, 0x0A}, // ID /*ATtiny4*/ 0, 0x00200, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny4*/ 1, 1, 10, vtab_attiny9, 4, cfgtab_attiny4}, // Config, ISRs + /*ATtiny4*/ 1, 1, 10, vtab_attiny9, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny4*/ 36, rgftab_attiny4}, // Register file //ATtiny5 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny5", 1, F_AVR8L, {0x1E, 0x8F, 0x09}, // ID /*ATtiny5*/ 0, 0x00200, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny5*/ 1, 1, 11, vtab_attiny10, 4, cfgtab_attiny4}, // Config, ISRs + /*ATtiny5*/ 1, 1, 11, vtab_attiny10, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny5*/ 41, rgftab_attiny5}, // Register file //ATtiny9 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny9", 2, F_AVR8L, {0x1E, 0x90, 0x08}, // ID /*ATtiny9*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny9*/ 1, 1, 10, vtab_attiny9, 4, cfgtab_attiny4}, // Config, ISRs + /*ATtiny9*/ 1, 1, 10, vtab_attiny9, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny9*/ 36, rgftab_attiny4}, // Register file //ATtiny10 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny10", 3, F_AVR8L, {0x1E, 0x90, 0x03}, // ID /*ATtiny10*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny10*/ 1, 1, 11, vtab_attiny10, 4, cfgtab_attiny4}, // Config, ISRs + /*ATtiny10*/ 1, 1, 11, vtab_attiny10, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny10*/ 41, rgftab_attiny5}, // Register file //ATtiny20 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny20", 4, F_AVR8L, {0x1E, 0x91, 0x0F}, // ID /*ATtiny20*/ 0, 0x00800, 0x020, 0, 0, 0, 0, 0, 0x0040, 0x0080, // Mem - /*ATtiny20*/ 1, 1, 17, vtab_attiny20, 5, cfgtab_attiny20}, // Config, ISRs + /*ATtiny20*/ 1, 1, 17, vtab_attiny20, 5, cfgtab_attiny20, // ISRs, Config + /*ATtiny20*/ 61, rgftab_attiny20}, // Register file //ATtiny40 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny40", 5, F_AVR8L, {0x1E, 0x92, 0x0E}, // ID /*ATtiny40*/ 0, 0x01000, 0x040, 0, 0, 0, 0, 0, 0x0040, 0x0100, // Mem - /*ATtiny40*/ 1, 1, 18, vtab_attiny40, 5, cfgtab_attiny20}, // Config, ISRs + /*ATtiny40*/ 1, 1, 18, vtab_attiny40, 5, cfgtab_attiny20, // ISRs, Config + /*ATtiny40*/ 63, rgftab_attiny40}, // Register file //ATtiny102 atdf, avrdude, boot size (manual) // Sources {"ATtiny102", 6, F_AVR8L, {0x1E, 0x90, 0x0C}, // ID /*ATtiny102*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny102*/ 1, 1, 16, vtab_attiny104, 5, cfgtab_attiny102}, // Config, ISRs + /*ATtiny102*/ 1, 1, 16, vtab_attiny104, 5, cfgtab_attiny102, // ISRs, Config + /*ATtiny102*/ 55, rgftab_attiny102}, // Register file //ATtiny104 atdf, avrdude, boot size (manual) // Sources {"ATtiny104", 7, F_AVR8L, {0x1E, 0x90, 0x0B}, // ID /*ATtiny104*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny104*/ 1, 1, 16, vtab_attiny104, 5, cfgtab_attiny102}, // Config, ISRs + /*ATtiny104*/ 1, 1, 16, vtab_attiny104, 5, cfgtab_attiny102, // ISRs, Config + /*ATtiny104*/ 55, rgftab_attiny102}, // Register file //ATtiny11 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny11", 8, F_AVR8, {0x1E, 0x90, 0x04}, // ID /*ATtiny11*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 1, 0x0060, 0x0020, // Mem - /*ATtiny11*/ 1, 1, 5, vtab_attiny11, 4, cfgtab_attiny11}, // Config, ISRs + /*ATtiny11*/ 1, 1, 5, vtab_attiny11, 4, cfgtab_attiny11, // ISRs, Config + /*ATtiny11*/ 14, rgftab_attiny11}, // Register file //ATtiny12 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny12", 9, F_AVR8, {0x1E, 0x90, 0x05}, // ID /*ATtiny12*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, // Mem - /*ATtiny12*/ 1, 1, 6, vtab_attiny12, 6, cfgtab_attiny12}, // Config, ISRs + /*ATtiny12*/ 1, 1, 6, vtab_attiny12, 6, cfgtab_attiny12, // ISRs, Config + /*ATtiny12*/ 18, rgftab_attiny12}, // Register file //ATtiny13 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny13", 10, F_AVR8, {0x1E, 0x90, 0x07}, // ID /*ATtiny13*/ 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, // Mem - /*ATtiny13*/ 2, 1, 10, vtab_attiny13a, 10, cfgtab_attiny13}, // Config, ISRs + /*ATtiny13*/ 2, 1, 10, vtab_attiny13a, 10, cfgtab_attiny13, // ISRs, Config + /*ATtiny13*/ 35, rgftab_attiny13}, // Register file //ATtiny13A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny13A", 11, F_AVR8, {0x1E, 0x90, 0x07}, // ID /*ATtiny13A*/ 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, // Mem - /*ATtiny13A*/ 2, 1, 10, vtab_attiny13a, 10, cfgtab_attiny13}, // Config, ISRs + /*ATtiny13A*/ 2, 1, 10, vtab_attiny13a, 10, cfgtab_attiny13, // ISRs, Config + /*ATtiny13A*/ 37, rgftab_attiny13a}, // Register file //ATtiny15 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny15", 12, F_AVR8, {0x1E, 0x90, 0x06}, // ID /*ATtiny15*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, // Mem - /*ATtiny15*/ 1, 1, 9, vtab_attiny15, 6, cfgtab_attiny15}, // Config, ISRs + /*ATtiny15*/ 1, 1, 9, vtab_attiny15, 6, cfgtab_attiny15, // ISRs, Config + /*ATtiny15*/ 28, rgftab_attiny15}, // Register file //ATtiny22 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny22", 13, F_AVR8, {0x1E, 0x91, 0x06}, // ID /*ATtiny22*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*ATtiny22*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_attiny22}, // Config, ISRs + /*ATtiny22*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_attiny22, // ISRs, Config + /*ATtiny22*/ 0, NULL}, // Register file //ATtiny24 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny24", 14, F_AVR8, {0x1E, 0x91, 0x0B}, // ID /*ATtiny24*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny24*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24}, // Config, ISRs + /*ATtiny24*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny24*/ 55, rgftab_attiny24}, // Register file //ATtiny24A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny24A", 15, F_AVR8, {0x1E, 0x91, 0x0B}, // ID /*ATtiny24A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny24A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24}, // Config, ISRs + /*ATtiny24A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny24A*/ 55, rgftab_attiny24}, // Register file //ATtiny25 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny25", 16, F_AVR8, {0x1E, 0x91, 0x08}, // ID /*ATtiny25*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny25*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25}, // Config, ISRs + /*ATtiny25*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25, // ISRs, Config + /*ATtiny25*/ 55, rgftab_attiny25}, // Register file //ATtiny26 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny26", 17, F_AVR8, {0x1E, 0x91, 0x09}, // ID /*ATtiny26*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny26*/ 2, 1, 12, vtab_attiny26, 8, cfgtab_attiny26}, // Config, ISRs + /*ATtiny26*/ 2, 1, 12, vtab_attiny26, 8, cfgtab_attiny26, // ISRs, Config + /*ATtiny26*/ 37, rgftab_attiny26}, // Register file //ATtiny28 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny28", 18, F_AVR8, {0x1E, 0x91, 0x07}, // ID /*ATtiny28*/ 0, 0x00800, 0x002, 0, 0, 0, 0, 0, 0x0060, 0x0020, // Mem - /*ATtiny28*/ 1, 1, 6, vtab_attiny28, 3, cfgtab_attiny28}, // Config, ISRs + /*ATtiny28*/ 1, 1, 6, vtab_attiny28, 3, cfgtab_attiny28, // ISRs, Config + /*ATtiny28*/ 20, rgftab_attiny28}, // Register file //ATtiny43U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny43U", 19, F_AVR8, {0x1E, 0x92, 0x0C}, // ID /*ATtiny43U*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0060, 0x0100, // Mem - /*ATtiny43U*/ 3, 1, 16, vtab_attiny43u, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny43U*/ 3, 1, 16, vtab_attiny43u, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny43U*/ 54, rgftab_attiny43u}, // Register file //ATtiny44 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny44", 20, F_AVR8, {0x1E, 0x92, 0x07}, // ID /*ATtiny44*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny44*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24}, // Config, ISRs + /*ATtiny44*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny44*/ 55, rgftab_attiny44}, // Register file //ATtiny44A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny44A", 21, F_AVR8, {0x1E, 0x92, 0x07}, // ID /*ATtiny44A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny44A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24}, // Config, ISRs + /*ATtiny44A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny44A*/ 55, rgftab_attiny44}, // Register file //ATtiny45 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny45", 22, F_AVR8, {0x1E, 0x92, 0x06}, // ID /*ATtiny45*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny45*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25}, // Config, ISRs + /*ATtiny45*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25, // ISRs, Config + /*ATtiny45*/ 55, rgftab_attiny45}, // Register file //ATtiny48 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny48", 23, F_AVR8, {0x1E, 0x92, 0x09}, // ID /*ATtiny48*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0100, // Mem - /*ATtiny48*/ 3, 1, 20, vtab_attiny88, 11, cfgtab_attiny48}, // Config, ISRs + /*ATtiny48*/ 3, 1, 20, vtab_attiny88, 11, cfgtab_attiny48, // ISRs, Config + /*ATtiny48*/ 74, rgftab_attiny48}, // Register file //ATtiny84 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny84", 24, F_AVR8, {0x1E, 0x93, 0x0C}, // ID /*ATtiny84*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny84*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24}, // Config, ISRs + /*ATtiny84*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny84*/ 55, rgftab_attiny84}, // Register file //ATtiny84A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny84A", 25, F_AVR8, {0x1E, 0x93, 0x0C}, // ID /*ATtiny84A*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny84A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24}, // Config, ISRs + /*ATtiny84A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny84A*/ 55, rgftab_attiny84}, // Register file //ATtiny85 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny85", 26, F_AVR8, {0x1E, 0x93, 0x0B}, // ID /*ATtiny85*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny85*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25}, // Config, ISRs + /*ATtiny85*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25, // ISRs, Config + /*ATtiny85*/ 55, rgftab_attiny45}, // Register file //ATtiny87 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny87", 27, F_AVR8, {0x1E, 0x93, 0x87}, // ID /*ATtiny87*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATtiny87*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87}, // Config, ISRs + /*ATtiny87*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config + /*ATtiny87*/ 80, rgftab_attiny87}, // Register file //ATtiny88 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny88", 28, F_AVR8, {0x1E, 0x93, 0x11}, // ID /*ATtiny88*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0200, // Mem - /*ATtiny88*/ 3, 1, 20, vtab_attiny88, 11, cfgtab_attiny48}, // Config, ISRs + /*ATtiny88*/ 3, 1, 20, vtab_attiny88, 11, cfgtab_attiny48, // ISRs, Config + /*ATtiny88*/ 74, rgftab_attiny88}, // Register file //ATtiny167 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny167", 29, F_AVR8, {0x1E, 0x94, 0x87}, // ID /*ATtiny167*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATtiny167*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87}, // Config, ISRs + /*ATtiny167*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config + /*ATtiny167*/ 80, rgftab_attiny87}, // Register file //ATtiny261 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny261", 30, F_AVR8, {0x1E, 0x91, 0x0C}, // ID /*ATtiny261*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny261*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny261*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny261*/ 63, rgftab_attiny261}, // Register file //ATtiny261A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny261A", 31, F_AVR8, {0x1E, 0x91, 0x0C}, // ID /*ATtiny261A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny261A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny261A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny261A*/ 63, rgftab_attiny261}, // Register file //ATtiny441 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny441", 32, F_AVR8, {0x1E, 0x92, 0x15}, // ID /*ATtiny441*/ 0, 0x01000, 0x010, 0, 0, 0, 0x0100, 4, 0x0100, 0x0100, // Mem - /*ATtiny441*/ 3, 1, 30, vtab_attiny841, 14, cfgtab_attiny441}, // Config, ISRs + /*ATtiny441*/ 3, 1, 30, vtab_attiny841, 14, cfgtab_attiny441, // ISRs, Config + /*ATtiny441*/ 101, rgftab_attiny441}, // Register file //ATtiny461 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny461", 33, F_AVR8, {0x1E, 0x92, 0x08}, // ID /*ATtiny461*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny461*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny461*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny461*/ 63, rgftab_attiny461}, // Register file //ATtiny461A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny461A", 34, F_AVR8, {0x1E, 0x92, 0x08}, // ID /*ATtiny461A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny461A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny461A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny461A*/ 63, rgftab_attiny461}, // Register file //ATtiny828 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny828", 35, F_AVR8, {0x1E, 0x93, 0x14}, // ID /*ATtiny828*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATtiny828*/ 3, 1, 26, vtab_attiny828r, 16, cfgtab_attiny828}, // Config, ISRs + /*ATtiny828*/ 3, 1, 26, vtab_attiny828r, 16, cfgtab_attiny828, // ISRs, Config + /*ATtiny828*/ 94, rgftab_attiny828}, // Register file //ATtiny828R avrdude, from ATtiny828 // Sources {"ATtiny828R", 36, F_AVR8, {0x1E, 0x93, 0x14}, // ID /*ATtiny828R*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATtiny828R*/ 3, 1, 26, vtab_attiny828r, 16, cfgtab_attiny828}, // Config, ISRs + /*ATtiny828R*/ 3, 1, 26, vtab_attiny828r, 16, cfgtab_attiny828, // ISRs, Config + /*ATtiny828R*/ 94, rgftab_attiny828}, // Register file //ATtiny841 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny841", 37, F_AVR8, {0x1E, 0x93, 0x15}, // ID /*ATtiny841*/ 0, 0x02000, 0x010, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATtiny841*/ 3, 1, 30, vtab_attiny841, 14, cfgtab_attiny441}, // Config, ISRs + /*ATtiny841*/ 3, 1, 30, vtab_attiny841, 14, cfgtab_attiny441, // ISRs, Config + /*ATtiny841*/ 101, rgftab_attiny441}, // Register file //ATtiny861 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny861", 38, F_AVR8, {0x1E, 0x93, 0x0D}, // ID /*ATtiny861*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny861*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny861*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny861*/ 63, rgftab_attiny861}, // Register file //ATtiny861A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny861A", 39, F_AVR8, {0x1E, 0x93, 0x0D}, // ID /*ATtiny861A*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny861A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u}, // Config, ISRs + /*ATtiny861A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny861A*/ 63, rgftab_attiny861}, // Register file //ATtiny1634 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1634", 40, F_AVR8, {0x1E, 0x94, 0x12}, // ID /*ATtiny1634*/ 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, // Mem - /*ATtiny1634*/ 3, 1, 28, vtab_attiny1634r, 13, cfgtab_attiny1634}, // Config, ISRs + /*ATtiny1634*/ 3, 1, 28, vtab_attiny1634r, 13, cfgtab_attiny1634, // ISRs, Config + /*ATtiny1634*/ 89, rgftab_attiny1634}, // Register file //ATtiny1634R avrdude, from ATtiny1634 // Sources {"ATtiny1634R", 41, F_AVR8, {0x1E, 0x94, 0x12}, // ID /*ATtiny1634R*/ 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, // Mem - /*ATtiny1634R*/ 3, 1, 28, vtab_attiny1634r, 13, cfgtab_attiny1634}, // Config, ISRs + /*ATtiny1634R*/ 3, 1, 28, vtab_attiny1634r, 13, cfgtab_attiny1634, // ISRs, Config + /*ATtiny1634R*/ 89, rgftab_attiny1634}, // Register file //ATtiny2313 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny2313", 42, F_AVR8, {0x1E, 0x91, 0x0A}, // ID /*ATtiny2313*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny2313*/ 3, 1, 19, vtab_attiny2313, 11, cfgtab_attiny2313}, // Config, ISRs + /*ATtiny2313*/ 3, 1, 19, vtab_attiny2313, 11, cfgtab_attiny2313, // ISRs, Config + /*ATtiny2313*/ 54, rgftab_attiny2313}, // Register file //ATtiny2313A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny2313A", 43, F_AVR8, {0x1E, 0x91, 0x0A}, // ID /*ATtiny2313A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny2313A*/ 3, 1, 21, vtab_attiny4313, 11, cfgtab_attiny2313a}, // Config, ISRs + /*ATtiny2313A*/ 3, 1, 21, vtab_attiny4313, 11, cfgtab_attiny2313a, // ISRs, Config + /*ATtiny2313A*/ 58, rgftab_attiny2313a}, // Register file //ATtiny4313 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny4313", 44, F_AVR8, {0x1E, 0x92, 0x0D}, // ID /*ATtiny4313*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny4313*/ 3, 1, 21, vtab_attiny4313, 11, cfgtab_attiny2313a}, // Config, ISRs + /*ATtiny4313*/ 3, 1, 21, vtab_attiny4313, 11, cfgtab_attiny2313a, // ISRs, Config + /*ATtiny4313*/ 58, rgftab_attiny4313}, // Register file //ATmega8 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega8", 45, F_AVR8, {0x1E, 0x93, 0x07}, // ID /*ATmega8*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega8*/ 2, 1, 19, vtab_atmega8a, 13, cfgtab_atmega8}, // Config, ISRs + /*ATmega8*/ 2, 1, 19, vtab_atmega8a, 13, cfgtab_atmega8, // ISRs, Config + /*ATmega8*/ 61, rgftab_atmega8}, // Register file //ATmega8A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega8A", 46, F_AVR8, {0x1E, 0x93, 0x07}, // ID /*ATmega8A*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega8A*/ 2, 1, 19, vtab_atmega8a, 13, cfgtab_atmega8}, // Config, ISRs + /*ATmega8A*/ 2, 1, 19, vtab_atmega8a, 13, cfgtab_atmega8, // ISRs, Config + /*ATmega8A*/ 61, rgftab_atmega8}, // Register file //ATmega8HVA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega8HVA", 47, F_AVR8, {0x1E, 0x93, 0x10}, // ID /*ATmega8HVA*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega8HVA*/ 1, 1, 21, vtab_atmega16hva, 7, cfgtab_atmega8hva}, // Config, ISRs + /*ATmega8HVA*/ 1, 1, 21, vtab_atmega16hva, 7, cfgtab_atmega8hva, // ISRs, Config + /*ATmega8HVA*/ 74, rgftab_atmega8hva}, // Register file //ATmega8U2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega8U2", 48, F_AVR8, {0x1E, 0x93, 0x89}, // ID /*ATmega8U2*/ 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATmega8U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_atmega8u2}, // Config, ISRs + /*ATmega8U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_atmega8u2, // ISRs, Config + /*ATmega8U2*/ 92, rgftab_atmega8u2}, // Register file //ATmega16 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16", 49, F_AVR8, {0x1E, 0x94, 0x03}, // ID /*ATmega16*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega16*/ 2, 1, 21, vtab_atmega16a, 13, cfgtab_atmega16}, // Config, ISRs + /*ATmega16*/ 2, 1, 21, vtab_atmega16a, 13, cfgtab_atmega16, // ISRs, Config + /*ATmega16*/ 70, rgftab_atmega16}, // Register file //ATmega16A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16A", 50, F_AVR8, {0x1E, 0x94, 0x03}, // ID /*ATmega16A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega16A*/ 2, 1, 21, vtab_atmega16a, 13, cfgtab_atmega16}, // Config, ISRs + /*ATmega16A*/ 2, 1, 21, vtab_atmega16a, 13, cfgtab_atmega16, // ISRs, Config + /*ATmega16A*/ 70, rgftab_atmega16a}, // Register file //ATmega16HVA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16HVA", 51, F_AVR8, {0x1E, 0x94, 0x0C}, // ID /*ATmega16HVA*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega16HVA*/ 1, 1, 21, vtab_atmega16hva, 7, cfgtab_atmega8hva}, // Config, ISRs + /*ATmega16HVA*/ 1, 1, 21, vtab_atmega16hva, 7, cfgtab_atmega8hva, // ISRs, Config + /*ATmega16HVA*/ 74, rgftab_atmega8hva}, // Register file //ATmega16HVB atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16HVB", 52, F_AVR8, {0x1E, 0x94, 0x0D}, // ID /*ATmega16HVB*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega16HVB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega16hvb}, // Config, ISRs + /*ATmega16HVB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega16hvb, // ISRs, Config + /*ATmega16HVB*/ 91, rgftab_atmega32hvbrevb}, // Register file //ATmega16HVBrevB atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16HVBrevB", 53, F_AVR8, {0x1E, 0x94, 0x0D}, // ID /*ATmega16HVBrevB*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega16HVBrevB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega16hvbrevb}, // Config, ISRs + /*ATmega16HVBrevB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega16hvbrevb, // ISRs, Config + /*ATmega16HVBrevB*/ 91, rgftab_atmega32hvbrevb}, // Register file //ATmega16M1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16M1", 54, F_AVR8, {0x1E, 0x94, 0x84}, // ID /*ATmega16M1*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega16M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega16m1}, // Config, ISRs + /*ATmega16M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega16m1, // ISRs, Config + /*ATmega16M1*/ 136, rgftab_atmega16m1}, // Register file //ATmega16HVA2 xml, avr-gcc 12.2.0 // Sources {"ATmega16HVA2", 55, F_AVR8, {0x1E, 0x94, 0x0E}, // ID /*ATmega16HVA2*/ 0, 0x04000, 0x080, -1, -1, -1, -1, -1, 0x0100, 0x0400, // Mem - /*ATmega16HVA2*/ 2, 1, 22, vtab_atmega16hva2, 9, cfgtab_atmega16hva2}, // Config, ISRs + /*ATmega16HVA2*/ 2, 1, 22, vtab_atmega16hva2, 9, cfgtab_atmega16hva2, // ISRs, Config + /*ATmega16HVA2*/ 0, NULL}, // Register file //ATmega16U2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16U2", 56, F_AVR8, {0x1E, 0x94, 0x89}, // ID /*ATmega16U2*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATmega16U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162}, // Config, ISRs + /*ATmega16U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162, // ISRs, Config + /*ATmega16U2*/ 92, rgftab_atmega8u2}, // Register file //ATmega16U4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega16U4", 57, F_AVR8, {0x1E, 0x94, 0x88}, // ID /*ATmega16U4*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0500, // Mem - /*ATmega16U4*/ 3, 1, 43, vtab_atmega32u4, 15, cfgtab_atmega16u4}, // Config, ISRs + /*ATmega16U4*/ 3, 1, 43, vtab_atmega32u4, 15, cfgtab_atmega16u4, // ISRs, Config + /*ATmega16U4*/ 139, rgftab_atmega16u4}, // Register file //ATmega32 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32", 58, F_AVR8, {0x1E, 0x95, 0x02}, // ID /*ATmega32*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, // Mem - /*ATmega32*/ 2, 1, 21, vtab_atmega323, 13, cfgtab_atmega32}, // Config, ISRs + /*ATmega32*/ 2, 1, 21, vtab_atmega323, 13, cfgtab_atmega32, // ISRs, Config + /*ATmega32*/ 68, rgftab_atmega32}, // Register file //ATmega32A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32A", 59, F_AVR8, {0x1E, 0x95, 0x02}, // ID /*ATmega32A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, // Mem - /*ATmega32A*/ 2, 1, 21, vtab_atmega323, 13, cfgtab_atmega32}, // Config, ISRs + /*ATmega32A*/ 2, 1, 21, vtab_atmega323, 13, cfgtab_atmega32, // ISRs, Config + /*ATmega32A*/ 66, rgftab_atmega32a}, // Register file //ATmega32HVB atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32HVB", 60, F_AVR8, {0x1E, 0x95, 0x10}, // ID /*ATmega32HVB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32HVB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega32hvb}, // Config, ISRs + /*ATmega32HVB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega32hvb, // ISRs, Config + /*ATmega32HVB*/ 91, rgftab_atmega32hvbrevb}, // Register file //ATmega32HVBrevB atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32HVBrevB", 61, F_AVR8, {0x1E, 0x95, 0x10}, // ID /*ATmega32HVBrevB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32HVBrevB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega32hvbrevb}, // Config, ISRs + /*ATmega32HVBrevB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega32hvbrevb, // ISRs, Config + /*ATmega32HVBrevB*/ 91, rgftab_atmega32hvbrevb}, // Register file //ATmega32C1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32C1", 62, F_AVR8, {0x1E, 0x95, 0x86}, // ID /*ATmega32C1*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32C1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega32c1}, // Config, ISRs + /*ATmega32C1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega32c1, // ISRs, Config + /*ATmega32C1*/ 117, rgftab_atmega32c1}, // Register file //ATmega32M1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32M1", 63, F_AVR8, {0x1E, 0x95, 0x84}, // ID /*ATmega32M1*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega32c1}, // Config, ISRs + /*ATmega32M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega32c1, // ISRs, Config + /*ATmega32M1*/ 136, rgftab_atmega16m1}, // Register file //ATmega32HVE2 avrdude, boot size (manual) // Sources {"ATmega32HVE2", 379, F_AVR8, {0x1E, 0x95, 0x13}, // ID /*ATmega32HVE2*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, -1, -1, // Mem - /*ATmega32HVE2*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve2}, // Config, ISRs + /*ATmega32HVE2*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve2, // ISRs, Config + /*ATmega32HVE2*/ 0, NULL}, // Register file //ATmega32U2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32U2", 64, F_AVR8, {0x1E, 0x95, 0x8A}, // ID /*ATmega32U2*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0400, // Mem - /*ATmega32U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_atmega32u2}, // Config, ISRs + /*ATmega32U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_atmega32u2, // ISRs, Config + /*ATmega32U2*/ 92, rgftab_atmega8u2}, // Register file //ATmega32U4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega32U4", 65, F_AVR8, {0x1E, 0x95, 0x87}, // ID /*ATmega32U4*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0a00, // Mem - /*ATmega32U4*/ 3, 1, 43, vtab_atmega32u4, 15, cfgtab_atmega32u4}, // Config, ISRs + /*ATmega32U4*/ 3, 1, 43, vtab_atmega32u4, 15, cfgtab_atmega32u4, // ISRs, Config + /*ATmega32U4*/ 139, rgftab_atmega16u4}, // Register file //ATmega32U6 xml, avr-gcc 12.2.0, boot size (manual) // Sources {"ATmega32U6", 66, F_AVR8, {0x1E, 0x95, 0x88}, // ID /*ATmega32U6*/ 0, 0x08000, 0x080, 4, 0x0200, -1, -1, -1, 0x0100, 0x0a00, // Mem - /*ATmega32U6*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_atmega32u6}, // Config, ISRs + /*ATmega32U6*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_atmega32u6, // ISRs, Config + /*ATmega32U6*/ 0, NULL}, // Register file //ATmega48 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega48", 67, F_AVR8, {0x1E, 0x92, 0x05}, // ID /*ATmega48*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48}, // Config, ISRs + /*ATmega48*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48*/ 81, rgftab_atmega48}, // Register file //ATmega48A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega48A", 68, F_AVR8, {0x1E, 0x92, 0x05}, // ID /*ATmega48A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48A*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48}, // Config, ISRs + /*ATmega48A*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48A*/ 82, rgftab_atmega48a}, // Register file //ATmega48P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega48P", 69, F_AVR8, {0x1E, 0x92, 0x0A}, // ID /*ATmega48P*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48P*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48}, // Config, ISRs + /*ATmega48P*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48P*/ 81, rgftab_atmega48}, // Register file //ATmega48PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega48PA", 70, F_AVR8, {0x1E, 0x92, 0x0A}, // ID /*ATmega48PA*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48PA*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48}, // Config, ISRs + /*ATmega48PA*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48PA*/ 82, rgftab_atmega48a}, // Register file //ATmega48PB atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega48PB", 71, F_AVR8, {0x1E, 0x92, 0x10}, // ID /*ATmega48PB*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48PB*/ 3, 1, 27, vtab_atmega168pb, 11, cfgtab_atmega48pb}, // Config, ISRs + /*ATmega48PB*/ 3, 1, 27, vtab_atmega168pb, 11, cfgtab_atmega48pb, // ISRs, Config + /*ATmega48PB*/ 95, rgftab_atmega48pb}, // Register file //ATmega64 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega64", 72, F_AVR8, {0x1E, 0x96, 0x02}, // ID /*ATmega64*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega64}, // Config, ISRs + /*ATmega64*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega64, // ISRs, Config + /*ATmega64*/ 103, rgftab_atmega64}, // Register file //ATmega64A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega64A", 73, F_AVR8, {0x1E, 0x96, 0x02}, // ID /*ATmega64A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64A*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega64}, // Config, ISRs + /*ATmega64A*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega64, // ISRs, Config + /*ATmega64A*/ 103, rgftab_atmega64}, // Register file //ATmega64HVE xml, avr-gcc 12.2.0, boot size (manual) // Sources {"ATmega64HVE", 74, F_AVR8, {0x1E, 0x96, 0x10}, // ID /*ATmega64HVE*/ 0, 0x10000, 0x080, 4, 0x0400, -1, -1, -1, 0x0100, 0x1000, // Mem - /*ATmega64HVE*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve}, // Config, ISRs + /*ATmega64HVE*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve, // ISRs, Config + /*ATmega64HVE*/ 0, NULL}, // Register file //ATmega64C1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega64C1", 75, F_AVR8, {0x1E, 0x96, 0x86}, // ID /*ATmega64C1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64C1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1}, // Config, ISRs + /*ATmega64C1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1, // ISRs, Config + /*ATmega64C1*/ 122, rgftab_atmega64c1}, // Register file //ATmega64M1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega64M1", 76, F_AVR8, {0x1E, 0x96, 0x84}, // ID /*ATmega64M1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1}, // Config, ISRs + /*ATmega64M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1, // ISRs, Config + /*ATmega64M1*/ 136, rgftab_atmega64m1}, // Register file //ATmega64HVE2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega64HVE2", 77, F_AVR8, {0x1E, 0x96, 0x10}, // ID /*ATmega64HVE2*/ 0, 0x10000, 0x080, 4, 0x0400, 0, 0x0400, 4, 0x0100, 0x1000, // Mem - /*ATmega64HVE2*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve2}, // Config, ISRs + /*ATmega64HVE2*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve2, // ISRs, Config + /*ATmega64HVE2*/ 89, rgftab_atmega64hve2}, // Register file //ATmega64RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega64RFR2", 78, F_AVR8, {0x1E, 0xA6, 0x02}, // ID /*ATmega64RFR2*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, // Mem - /*ATmega64RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega64rfr2}, // Config, ISRs + /*ATmega64RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega64rfr2, // ISRs, Config + /*ATmega64RFR2*/ 269, rgftab_atmega64rfr2}, // Register file //ATmega88 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega88", 79, F_AVR8, {0x1E, 0x93, 0x0A}, // ID /*ATmega88*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88}, // Config, ISRs + /*ATmega88*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88*/ 81, rgftab_atmega88}, // Register file //ATmega88A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega88A", 80, F_AVR8, {0x1E, 0x93, 0x0A}, // ID /*ATmega88A*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88A*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88}, // Config, ISRs + /*ATmega88A*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88A*/ 81, rgftab_atmega88}, // Register file //ATmega88P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega88P", 81, F_AVR8, {0x1E, 0x93, 0x0F}, // ID /*ATmega88P*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88}, // Config, ISRs + /*ATmega88P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88P*/ 81, rgftab_atmega88}, // Register file //ATmega88PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega88PA", 82, F_AVR8, {0x1E, 0x93, 0x0F}, // ID /*ATmega88PA*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88PA*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88}, // Config, ISRs + /*ATmega88PA*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88PA*/ 81, rgftab_atmega88}, // Register file //ATmega88PB atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega88PB", 83, F_AVR8, {0x1E, 0x93, 0x16}, // ID /*ATmega88PB*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88PB*/ 3, 1, 27, vtab_atmega168pb, 14, cfgtab_atmega88pb}, // Config, ISRs + /*ATmega88PB*/ 3, 1, 27, vtab_atmega168pb, 14, cfgtab_atmega88pb, // ISRs, Config + /*ATmega88PB*/ 95, rgftab_atmega88pb}, // Register file //ATmega103 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATmega103", 84, F_AVR8, {0x1E, 0x97, 0x01}, // ID /*ATmega103*/ 0, 0x20000, 0x100, 0, 0, 0, 0x1000, 1, 0x0060, 0x0fa0, // Mem - /*ATmega103*/ 1, 1, 24, vtab_atmega103, 4, cfgtab_atmega103}, // Config, ISRs + /*ATmega103*/ 1, 1, 24, vtab_atmega103, 4, cfgtab_atmega103, // ISRs, Config + /*ATmega103*/ 0, NULL}, // Register file //ATmega103comp xml // Sources {"ATmega103comp", 374, F_AVR8, {0x1E, 0x97, 0x01}, // ID /*ATmega103comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*ATmega103comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega103comp}, // Config, ISRs + /*ATmega103comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega103comp, // ISRs, Config + /*ATmega103comp*/ 0, NULL}, // Register file //ATmega128 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega128", 85, F_AVR8, {0x1E, 0x97, 0x02}, // ID /*ATmega128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*ATmega128*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128}, // Config, ISRs + /*ATmega128*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128, // ISRs, Config + /*ATmega128*/ 103, rgftab_atmega128}, // Register file //ATmega128A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega128A", 86, F_AVR8, {0x1E, 0x97, 0x02}, // ID /*ATmega128A*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*ATmega128A*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128}, // Config, ISRs + /*ATmega128A*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128, // ISRs, Config + /*ATmega128A*/ 103, rgftab_atmega128a}, // Register file //ATmega128RFA1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega128RFA1", 87, F_AVR8, {0x1E, 0xA7, 0x01}, // ID /*ATmega128RFA1*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem - /*ATmega128RFA1*/ 3, 1, 72, vtab_atmega128rfa1, 14, cfgtab_atmega128rfa1}, // Config, ISRs + /*ATmega128RFA1*/ 3, 1, 72, vtab_atmega128rfa1, 14, cfgtab_atmega128rfa1, // ISRs, Config + /*ATmega128RFA1*/ 237, rgftab_atmega128rfa1}, // Register file //ATmega128RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega128RFR2", 88, F_AVR8, {0x1E, 0xA7, 0x02}, // ID /*ATmega128RFR2*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem - /*ATmega128RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega128rfr2}, // Config, ISRs + /*ATmega128RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega128rfr2, // ISRs, Config + /*ATmega128RFR2*/ 270, rgftab_atmega128rfr2}, // Register file //ATmega161 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATmega161", 89, F_AVR8, {0x1E, 0x94, 0x01}, // ID /*ATmega161*/ 0, 0x04000, 0x080, 1, 0x0400, 0, 0x0200, 1, 0x0060, 0x0400, // Mem - /*ATmega161*/ 1, 1, 21, vtab_atmega161, 7, cfgtab_atmega161}, // Config, ISRs + /*ATmega161*/ 1, 1, 21, vtab_atmega161, 7, cfgtab_atmega161, // ISRs, Config + /*ATmega161*/ 0, NULL}, // Register file //ATmega161comp xml // Sources {"ATmega161comp", 375, F_AVR8, {0x1E, 0x94, 0x01}, // ID /*ATmega161comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*ATmega161comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega161comp}, // Config, ISRs + /*ATmega161comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega161comp, // ISRs, Config + /*ATmega161comp*/ 0, NULL}, // Register file //ATmega162 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega162", 90, F_AVR8, {0x1E, 0x94, 0x04}, // ID /*ATmega162*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega162*/ 3, 1, 28, vtab_atmega162, 15, cfgtab_atmega162}, // Config, ISRs + /*ATmega162*/ 3, 1, 28, vtab_atmega162, 15, cfgtab_atmega162, // ISRs, Config + /*ATmega162*/ 79, rgftab_atmega162}, // Register file //ATmega163 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATmega163", 91, F_AVR8, {0x1E, 0x94, 0x02}, // ID /*ATmega163*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 1, 0x0060, 0x0400, // Mem - /*ATmega163*/ 2, 1, 18, vtab_atmega163, 9, cfgtab_atmega163}, // Config, ISRs + /*ATmega163*/ 2, 1, 18, vtab_atmega163, 9, cfgtab_atmega163, // ISRs, Config + /*ATmega163*/ 0, NULL}, // Register file //ATmega164A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega164A", 92, F_AVR8, {0x1E, 0x94, 0x0F}, // ID /*ATmega164A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega164A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a}, // Config, ISRs + /*ATmega164A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a, // ISRs, Config + /*ATmega164A*/ 96, rgftab_atmega164a}, // Register file //ATmega164P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega164P", 93, F_AVR8, {0x1E, 0x94, 0x0A}, // ID /*ATmega164P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega164P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a}, // Config, ISRs + /*ATmega164P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a, // ISRs, Config + /*ATmega164P*/ 96, rgftab_atmega164a}, // Register file //ATmega164PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega164PA", 94, F_AVR8, {0x1E, 0x94, 0x0A}, // ID /*ATmega164PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega164PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a}, // Config, ISRs + /*ATmega164PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a, // ISRs, Config + /*ATmega164PA*/ 96, rgftab_atmega164a}, // Register file //ATmega165 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATmega165", 95, F_AVR8, {0x1E, 0x94, 0x07}, // ID /*ATmega165*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega165*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega165*/ 0, NULL}, // Register file //ATmega165A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega165A", 96, F_AVR8, {0x1E, 0x94, 0x10}, // ID /*ATmega165A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega165A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega165A*/ 86, rgftab_atmega165a}, // Register file //ATmega165P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega165P", 97, F_AVR8, {0x1E, 0x94, 0x07}, // ID /*ATmega165P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega165P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega165P*/ 86, rgftab_atmega165a}, // Register file //ATmega165PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega165PA", 98, F_AVR8, {0x1E, 0x94, 0x07}, // ID /*ATmega165PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165PA*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega165PA*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega165PA*/ 86, rgftab_atmega165a}, // Register file //ATmega168 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega168", 99, F_AVR8, {0x1E, 0x94, 0x06}, // ID /*ATmega168*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168*/ 3, 1, 26, vtab_atmega328, 14, cfgtab_atmega168}, // Config, ISRs + /*ATmega168*/ 3, 1, 26, vtab_atmega328, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168*/ 81, rgftab_atmega88}, // Register file //ATmega168A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega168A", 100, F_AVR8, {0x1E, 0x94, 0x06}, // ID /*ATmega168A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168A*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168}, // Config, ISRs + /*ATmega168A*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168A*/ 81, rgftab_atmega88}, // Register file //ATmega168P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega168P", 101, F_AVR8, {0x1E, 0x94, 0x0B}, // ID /*ATmega168P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168}, // Config, ISRs + /*ATmega168P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168P*/ 81, rgftab_atmega88}, // Register file //ATmega168PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega168PA", 102, F_AVR8, {0x1E, 0x94, 0x0B}, // ID /*ATmega168PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168PA*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168}, // Config, ISRs + /*ATmega168PA*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168PA*/ 81, rgftab_atmega88}, // Register file //ATmega168PB atdf, avr-gcc 7.3.0, avrdude // Sources {"ATmega168PB", 103, F_AVR8, {0x1E, 0x94, 0x15}, // ID /*ATmega168PB*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168PB*/ 3, 1, 27, vtab_atmega168pb, 14, cfgtab_atmega168pb}, // Config, ISRs + /*ATmega168PB*/ 3, 1, 27, vtab_atmega168pb, 14, cfgtab_atmega168pb, // ISRs, Config + /*ATmega168PB*/ 95, rgftab_atmega88pb}, // Register file //ATmega169 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATmega169", 104, F_AVR8, {0x1E, 0x94, 0x05}, // ID /*ATmega169*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega169*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega169*/ 0, NULL}, // Register file //ATmega169A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega169A", 105, F_AVR8, {0x1E, 0x94, 0x11}, // ID /*ATmega169A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega169A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega169A*/ 106, rgftab_atmega169a}, // Register file //ATmega169P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega169P", 106, F_AVR8, {0x1E, 0x94, 0x05}, // ID /*ATmega169P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega169P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega169P*/ 106, rgftab_atmega169a}, // Register file //ATmega169PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega169PA", 107, F_AVR8, {0x1E, 0x94, 0x05}, // ID /*ATmega169PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169PA*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165}, // Config, ISRs + /*ATmega169PA*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega169PA*/ 106, rgftab_atmega169a}, // Register file //ATmega256RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega256RFR2", 108, F_AVR8, {0x1E, 0xA8, 0x02}, // ID /*ATmega256RFR2*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, // Mem - /*ATmega256RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega256rfr2}, // Config, ISRs + /*ATmega256RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega256rfr2, // ISRs, Config + /*ATmega256RFR2*/ 271, rgftab_atmega256rfr2}, // Register file //ATmega323 xml, avr-gcc 12.2.0, boot size (manual) // Sources {"ATmega323", 109, F_AVR8, {0x1E, 0x95, 0x01}, // ID /*ATmega323*/ 0, 0x08000, 0x080, 4, 0x0200, -1, -1, -1, 0x0060, 0x0800, // Mem - /*ATmega323*/ 2, 1, 21, vtab_atmega323, 12, cfgtab_atmega323}, // Config, ISRs + /*ATmega323*/ 2, 1, 21, vtab_atmega323, 12, cfgtab_atmega323, // ISRs, Config + /*ATmega323*/ 0, NULL}, // Register file //ATmega324A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega324A", 110, F_AVR8, {0x1E, 0x95, 0x15}, // ID /*ATmega324A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a}, // Config, ISRs + /*ATmega324A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a, // ISRs, Config + /*ATmega324A*/ 96, rgftab_atmega164a}, // Register file //ATmega324P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega324P", 111, F_AVR8, {0x1E, 0x95, 0x08}, // ID /*ATmega324P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a}, // Config, ISRs + /*ATmega324P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a, // ISRs, Config + /*ATmega324P*/ 96, rgftab_atmega164a}, // Register file //ATmega324PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega324PA", 112, F_AVR8, {0x1E, 0x95, 0x11}, // ID /*ATmega324PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a}, // Config, ISRs + /*ATmega324PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a, // ISRs, Config + /*ATmega324PA*/ 96, rgftab_atmega164a}, // Register file //ATmega324PB atdf, avrdude // Sources {"ATmega324PB", 113, F_AVR8, {0x1E, 0x95, 0x17}, // ID /*ATmega324PB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324PB*/ 3, 1, 51, vtab_atmega324pb, 15, cfgtab_atmega324pb}, // Config, ISRs + /*ATmega324PB*/ 3, 1, 51, vtab_atmega324pb, 15, cfgtab_atmega324pb, // ISRs, Config + /*ATmega324PB*/ 134, rgftab_atmega324pb}, // Register file //ATmega325 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega325", 114, F_AVR8, {0x1E, 0x95, 0x05}, // ID /*ATmega325*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega325*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325*/ 86, rgftab_atmega325}, // Register file //ATmega325A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega325A", 115, F_AVR8, {0x1E, 0x95, 0x05}, // ID /*ATmega325A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega325A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325A*/ 86, rgftab_atmega325}, // Register file //ATmega325P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega325P", 116, F_AVR8, {0x1E, 0x95, 0x0D}, // ID /*ATmega325P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega325P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325P*/ 86, rgftab_atmega325}, // Register file //ATmega325PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega325PA", 117, F_AVR8, {0x1E, 0x95, 0x0D}, // ID /*ATmega325PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325PA*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega325PA*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325PA*/ 86, rgftab_atmega325}, // Register file //ATmega328 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega328", 118, F_AVR8, {0x1E, 0x95, 0x14}, // ID /*ATmega328*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega328*/ 3, 1, 26, vtab_atmega328, 14, cfgtab_atmega328}, // Config, ISRs + /*ATmega328*/ 3, 1, 26, vtab_atmega328, 14, cfgtab_atmega328, // ISRs, Config + /*ATmega328*/ 81, rgftab_atmega328}, // Register file //ATmega328P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega328P", 119, F_AVR8, {0x1E, 0x95, 0x0F}, // ID /*ATmega328P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega328P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega328}, // Config, ISRs + /*ATmega328P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega328, // ISRs, Config + /*ATmega328P*/ 81, rgftab_atmega328}, // Register file //ATmega328PB atdf, avr-gcc 7.3.0, avrdude // Sources {"ATmega328PB", 120, F_AVR8, {0x1E, 0x95, 0x16}, // ID /*ATmega328PB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega328PB*/ 3, 1, 45, vtab_atmega328pb, 15, cfgtab_atmega328pb}, // Config, ISRs + /*ATmega328PB*/ 3, 1, 45, vtab_atmega328pb, 15, cfgtab_atmega328pb, // ISRs, Config + /*ATmega328PB*/ 123, rgftab_atmega328pb}, // Register file //ATmega329 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega329", 121, F_AVR8, {0x1E, 0x95, 0x03}, // ID /*ATmega329*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega329*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329*/ 106, rgftab_atmega329}, // Register file //ATmega329A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega329A", 122, F_AVR8, {0x1E, 0x95, 0x03}, // ID /*ATmega329A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega329A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329A*/ 106, rgftab_atmega329a}, // Register file //ATmega329P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega329P", 123, F_AVR8, {0x1E, 0x95, 0x0B}, // ID /*ATmega329P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega329P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329P*/ 106, rgftab_atmega329p}, // Register file //ATmega329PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega329PA", 124, F_AVR8, {0x1E, 0x95, 0x0B}, // ID /*ATmega329PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329PA*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega329PA*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329PA*/ 106, rgftab_atmega329a}, // Register file //ATmega406 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega406", 125, F_AVR8, {0x1E, 0x95, 0x07}, // ID /*ATmega406*/ 0, 0x0a000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0800, // Mem - /*ATmega406*/ 2, 1, 23, vtab_atmega406, 10, cfgtab_atmega406}, // Config, ISRs + /*ATmega406*/ 2, 1, 23, vtab_atmega406, 10, cfgtab_atmega406, // ISRs, Config + /*ATmega406*/ 79, rgftab_atmega406}, // Register file //ATmega640 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega640", 126, F_AVR8, {0x1E, 0x96, 0x08}, // ID /*ATmega640*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega640*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega640}, // Config, ISRs + /*ATmega640*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega640, // ISRs, Config + /*ATmega640*/ 160, rgftab_atmega640}, // Register file //ATmega644 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega644", 127, F_AVR8, {0x1E, 0x96, 0x09}, // ID /*ATmega644*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644*/ 3, 1, 28, vtab_atmega644, 14, cfgtab_atmega644}, // Config, ISRs + /*ATmega644*/ 3, 1, 28, vtab_atmega644, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644*/ 88, rgftab_atmega644}, // Register file //ATmega644A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega644A", 128, F_AVR8, {0x1E, 0x96, 0x09}, // ID /*ATmega644A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644}, // Config, ISRs + /*ATmega644A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644A*/ 93, rgftab_atmega644a}, // Register file //ATmega644P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega644P", 129, F_AVR8, {0x1E, 0x96, 0x0A}, // ID /*ATmega644P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644}, // Config, ISRs + /*ATmega644P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644P*/ 93, rgftab_atmega644a}, // Register file //ATmega644PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega644PA", 130, F_AVR8, {0x1E, 0x96, 0x0A}, // ID /*ATmega644PA*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644}, // Config, ISRs + /*ATmega644PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644PA*/ 93, rgftab_atmega644a}, // Register file //ATmega644RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega644RFR2", 131, F_AVR8, {0x1E, 0xA6, 0x03}, // ID /*ATmega644RFR2*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, // Mem - /*ATmega644RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega64rfr2}, // Config, ISRs + /*ATmega644RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega64rfr2, // ISRs, Config + /*ATmega644RFR2*/ 269, rgftab_atmega64rfr2}, // Register file //ATmega645 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega645", 132, F_AVR8, {0x1E, 0x96, 0x05}, // ID /*ATmega645*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega645*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega645*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega645*/ 86, rgftab_atmega645}, // Register file //ATmega645A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega645A", 133, F_AVR8, {0x1E, 0x96, 0x05}, // ID /*ATmega645A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega645A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega645A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega645A*/ 86, rgftab_atmega645}, // Register file //ATmega645P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega645P", 134, F_AVR8, {0x1E, 0x96, 0x0D}, // ID /*ATmega645P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega645P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega645P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega645P*/ 86, rgftab_atmega645}, // Register file //ATmega649 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega649", 135, F_AVR8, {0x1E, 0x96, 0x03}, // ID /*ATmega649*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega649*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega649*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega649*/ 106, rgftab_atmega649}, // Register file //ATmega649A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega649A", 136, F_AVR8, {0x1E, 0x96, 0x03}, // ID /*ATmega649A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega649A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega649A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega649A*/ 106, rgftab_atmega649}, // Register file //ATmega649P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega649P", 137, F_AVR8, {0x1E, 0x96, 0x0B}, // ID /*ATmega649P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega649P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega649P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega649P*/ 106, rgftab_atmega649}, // Register file //ATmega1280 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1280", 138, F_AVR8, {0x1E, 0x97, 0x03}, // ID /*ATmega1280*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega1280*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega1280}, // Config, ISRs + /*ATmega1280*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega1280, // ISRs, Config + /*ATmega1280*/ 161, rgftab_atmega1280}, // Register file //ATmega1281 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1281", 139, F_AVR8, {0x1E, 0x97, 0x04}, // ID /*ATmega1281*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega1281*/ 3, 1, 57, vtab_atmega2561, 14, cfgtab_atmega1280}, // Config, ISRs + /*ATmega1281*/ 3, 1, 57, vtab_atmega2561, 14, cfgtab_atmega1280, // ISRs, Config + /*ATmega1281*/ 138, rgftab_atmega1281}, // Register file //ATmega1284 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1284", 140, F_AVR8, {0x1E, 0x97, 0x06}, // ID /*ATmega1284*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, // Mem - /*ATmega1284*/ 3, 1, 35, vtab_atmega1284p, 14, cfgtab_atmega1284}, // Config, ISRs + /*ATmega1284*/ 3, 1, 35, vtab_atmega1284p, 14, cfgtab_atmega1284, // ISRs, Config + /*ATmega1284*/ 104, rgftab_atmega1284}, // Register file //ATmega1284P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1284P", 141, F_AVR8, {0x1E, 0x97, 0x05}, // ID /*ATmega1284P*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, // Mem - /*ATmega1284P*/ 3, 1, 35, vtab_atmega1284p, 14, cfgtab_atmega1284}, // Config, ISRs + /*ATmega1284P*/ 3, 1, 35, vtab_atmega1284p, 14, cfgtab_atmega1284, // ISRs, Config + /*ATmega1284P*/ 104, rgftab_atmega1284}, // Register file //ATmega1284RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1284RFR2", 142, F_AVR8, {0x1E, 0xA7, 0x03}, // ID /*ATmega1284RFR2*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem - /*ATmega1284RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega128rfr2}, // Config, ISRs + /*ATmega1284RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega128rfr2, // ISRs, Config + /*ATmega1284RFR2*/ 270, rgftab_atmega128rfr2}, // Register file //ATmega2560 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega2560", 143, F_AVR8, {0x1E, 0x98, 0x01}, // ID /*ATmega2560*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega2560*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega2560}, // Config, ISRs + /*ATmega2560*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega2560, // ISRs, Config + /*ATmega2560*/ 161, rgftab_atmega1280}, // Register file //ATmega2561 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega2561", 144, F_AVR8, {0x1E, 0x98, 0x02}, // ID /*ATmega2561*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega2561*/ 3, 1, 57, vtab_atmega2561, 14, cfgtab_atmega2560}, // Config, ISRs + /*ATmega2561*/ 3, 1, 57, vtab_atmega2561, 14, cfgtab_atmega2560, // ISRs, Config + /*ATmega2561*/ 139, rgftab_atmega2561}, // Register file //ATmega2564RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega2564RFR2", 145, F_AVR8, {0x1E, 0xA8, 0x03}, // ID /*ATmega2564RFR2*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, // Mem - /*ATmega2564RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega256rfr2}, // Config, ISRs + /*ATmega2564RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega256rfr2, // ISRs, Config + /*ATmega2564RFR2*/ 271, rgftab_atmega2564rfr2}, // Register file //ATmega3250 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3250", 146, F_AVR8, {0x1E, 0x95, 0x06}, // ID /*ATmega3250*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3250*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250*/ 94, rgftab_atmega3250}, // Register file //ATmega3250A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3250A", 147, F_AVR8, {0x1E, 0x95, 0x06}, // ID /*ATmega3250A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250A*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3250A*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250A*/ 94, rgftab_atmega3250}, // Register file //ATmega3250P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3250P", 148, F_AVR8, {0x1E, 0x95, 0x0E}, // ID /*ATmega3250P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250P*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3250P*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250P*/ 94, rgftab_atmega3250}, // Register file //ATmega3250PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3250PA", 149, F_AVR8, {0x1E, 0x95, 0x0E}, // ID /*ATmega3250PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250PA*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3250PA*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250PA*/ 94, rgftab_atmega3250}, // Register file //ATmega3290 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3290", 150, F_AVR8, {0x1E, 0x95, 0x04}, // ID /*ATmega3290*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3290*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290*/ 118, rgftab_atmega3290}, // Register file //ATmega3290A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3290A", 151, F_AVR8, {0x1E, 0x95, 0x04}, // ID /*ATmega3290A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290A*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3290A*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290A*/ 118, rgftab_atmega3290}, // Register file //ATmega3290P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3290P", 152, F_AVR8, {0x1E, 0x95, 0x0C}, // ID /*ATmega3290P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290P*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3290P*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290P*/ 118, rgftab_atmega3290p}, // Register file //ATmega3290PA atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3290PA", 153, F_AVR8, {0x1E, 0x95, 0x0C}, // ID /*ATmega3290PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290PA*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325}, // Config, ISRs + /*ATmega3290PA*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290PA*/ 118, rgftab_atmega3290pa}, // Register file //ATmega6450 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega6450", 154, F_AVR8, {0x1E, 0x96, 0x06}, // ID /*ATmega6450*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6450*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega6450*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6450*/ 94, rgftab_atmega6450}, // Register file //ATmega6450A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega6450A", 155, F_AVR8, {0x1E, 0x96, 0x06}, // ID /*ATmega6450A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6450A*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega6450A*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6450A*/ 94, rgftab_atmega6450}, // Register file //ATmega6450P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega6450P", 156, F_AVR8, {0x1E, 0x96, 0x0E}, // ID /*ATmega6450P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6450P*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega6450P*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6450P*/ 94, rgftab_atmega6450}, // Register file //ATmega6490 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega6490", 157, F_AVR8, {0x1E, 0x96, 0x04}, // ID /*ATmega6490*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6490*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega6490*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6490*/ 118, rgftab_atmega6490}, // Register file //ATmega6490A atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega6490A", 158, F_AVR8, {0x1E, 0x96, 0x04}, // ID /*ATmega6490A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6490A*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega6490A*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6490A*/ 118, rgftab_atmega6490}, // Register file //ATmega6490P atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega6490P", 159, F_AVR8, {0x1E, 0x96, 0x0C}, // ID /*ATmega6490P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6490P*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645}, // Config, ISRs + /*ATmega6490P*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6490P*/ 118, rgftab_atmega6490}, // Register file //ATmega8515 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega8515", 160, F_AVR8, {0x1E, 0x93, 0x06}, // ID /*ATmega8515*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATmega8515*/ 2, 1, 17, vtab_atmega8515, 13, cfgtab_atmega8515}, // Config, ISRs + /*ATmega8515*/ 2, 1, 17, vtab_atmega8515, 13, cfgtab_atmega8515, // ISRs, Config + /*ATmega8515*/ 52, rgftab_atmega8515}, // Register file //ATmega8535 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega8535", 161, F_AVR8, {0x1E, 0x93, 0x08}, // ID /*ATmega8535*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATmega8535*/ 2, 1, 21, vtab_atmega8535, 13, cfgtab_atmega8535}, // Config, ISRs + /*ATmega8535*/ 2, 1, 21, vtab_atmega8535, 13, cfgtab_atmega8535, // ISRs, Config + /*ATmega8535*/ 67, rgftab_atmega8535}, // Register file //AT43USB320 avr-gcc 12.2.0 // Sources {"AT43USB320", 162, F_AVR8, {0xff, -1, -1}, // ID /*AT43USB320*/ 0, 0x10000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0200, // Mem - /*AT43USB320*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT43USB320*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT43USB320*/ 0, NULL}, // Register file //AT43USB355 avr-gcc 12.2.0 // Sources {"AT43USB355", 163, F_AVR8, {0xff, -1, -1}, // ID /*AT43USB355*/ 0, 0x06000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0400, // Mem - /*AT43USB355*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT43USB355*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT43USB355*/ 0, NULL}, // Register file //AT76C711 avr-gcc 12.2.0 // Sources {"AT76C711", 164, F_AVR8, {0xff, -1, -1}, // ID /*AT76C711*/ 0, 0x04000, -1, -1, -1, -1, -1, -1, 0x0060, 0x07a0, // Mem - /*AT76C711*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT76C711*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT76C711*/ 0, NULL}, // Register file //AT86RF401 avr-gcc 12.2.0 // Sources {"AT86RF401", 165, F_AVR8, {0x1E, 0x91, 0x81}, // ID /*AT86RF401*/ 0, 0x00800, -1, -1, -1, -1, -1, -1, 0x0060, 0x0080, // Mem - /*AT86RF401*/ 0, 1, 3, vtab_at86rf401, 0, NULL}, // Config, ISRs + /*AT86RF401*/ 0, 1, 3, vtab_at86rf401, 0, NULL, // ISRs, Config + /*AT86RF401*/ 0, NULL}, // Register file //AT89S51 avrdude // Sources {"AT89S51", 372, F_AVR8, {0x1E, 0x51, 0x06}, // ID /*AT89S51*/ 0, 0x01000, 0x001, -1, -1, 0, 0, 0, -1, -1, // Mem - /*AT89S51*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT89S51*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT89S51*/ 0, NULL}, // Register file //AT89S52 avrdude // Sources {"AT89S52", 373, F_AVR8, {0x1E, 0x52, 0x06}, // ID /*AT89S52*/ 0, 0x02000, 0x001, -1, -1, 0, 0, 0, -1, -1, // Mem - /*AT89S52*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT89S52*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT89S52*/ 0, NULL}, // Register file //AT90PWM1 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM1", 166, F_AVR8, {0x1E, 0x93, 0x83}, // ID /*AT90PWM1*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM1*/ 3, 1, 32, vtab_at90pwm1, 17, cfgtab_at90pwm1}, // Config, ISRs + /*AT90PWM1*/ 3, 1, 32, vtab_at90pwm1, 17, cfgtab_at90pwm1, // ISRs, Config + /*AT90PWM1*/ 92, rgftab_at90pwm1}, // Register file //AT90PWM2 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90PWM2", 167, F_AVR8, {0x1E, 0x93, 0x81}, // ID /*AT90PWM2*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM2*/ 3, 1, 32, vtab_at90pwm2, 18, cfgtab_at90pwm2}, // Config, ISRs + /*AT90PWM2*/ 3, 1, 32, vtab_at90pwm2, 18, cfgtab_at90pwm2, // ISRs, Config + /*AT90PWM2*/ 0, NULL}, // Register file //AT90PWM2B atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM2B", 168, F_AVR8, {0x1E, 0x93, 0x83}, // ID /*AT90PWM2B*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM2B*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2b}, // Config, ISRs + /*AT90PWM2B*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2b, // ISRs, Config + /*AT90PWM2B*/ 100, rgftab_at90pwm2b}, // Register file //AT90PWM3 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM3", 169, F_AVR8, {0x1E, 0x93, 0x81}, // ID /*AT90PWM3*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM3*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2}, // Config, ISRs + /*AT90PWM3*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2, // ISRs, Config + /*AT90PWM3*/ 115, rgftab_at90pwm3}, // Register file //AT90PWM3B atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM3B", 170, F_AVR8, {0x1E, 0x93, 0x83}, // ID /*AT90PWM3B*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM3B*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2b}, // Config, ISRs + /*AT90PWM3B*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2b, // ISRs, Config + /*AT90PWM3B*/ 115, rgftab_at90pwm3b}, // Register file //AT90CAN32 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90CAN32", 171, F_AVR8, {0x1E, 0x95, 0x81}, // ID /*AT90CAN32*/ 0, 0x08000, 0x100, 4, 0x0400, 0, 0x0400, 8, 0x0100, 0x0800, // Mem - /*AT90CAN32*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can32}, // Config, ISRs + /*AT90CAN32*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can32, // ISRs, Config + /*AT90CAN32*/ 137, rgftab_at90can128}, // Register file //AT90CAN64 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90CAN64", 172, F_AVR8, {0x1E, 0x96, 0x81}, // ID /*AT90CAN64*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*AT90CAN64*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can64}, // Config, ISRs + /*AT90CAN64*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can64, // ISRs, Config + /*AT90CAN64*/ 137, rgftab_at90can128}, // Register file //AT90PWM81 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM81", 173, F_AVR8, {0x1E, 0x93, 0x88}, // ID /*AT90PWM81*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0100, // Mem - /*AT90PWM81*/ 3, 1, 20, vtab_at90pwm161, 19, cfgtab_at90pwm81}, // Config, ISRs + /*AT90PWM81*/ 3, 1, 20, vtab_at90pwm161, 19, cfgtab_at90pwm81, // ISRs, Config + /*AT90PWM81*/ 84, rgftab_at90pwm81}, // Register file //AT90USB82 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90USB82", 174, F_AVR8, {0x1E, 0x93, 0x82}, // ID /*AT90USB82*/ 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90USB82*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162}, // Config, ISRs + /*AT90USB82*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162, // ISRs, Config + /*AT90USB82*/ 92, rgftab_at90usb162}, // Register file //AT90SCR100 avr-gcc 12.2.0, boot size (manual) // Sources {"AT90SCR100", 175, F_AVR8, {0x1E, 0x96, 0xC1}, // ID /*AT90SCR100*/ 0, 0x10000, 0x100, 4, 0x0200, -1, -1, -1, 0x0100, 0x1000, // Mem - /*AT90SCR100*/ 3, 1, 38, vtab_at90scr100h, 13, cfgtab_at90scr100h}, // Config, ISRs + /*AT90SCR100*/ 3, 1, 38, vtab_at90scr100h, 13, cfgtab_at90scr100h, // ISRs, Config + /*AT90SCR100*/ 0, NULL}, // Register file //AT90SCR100H xml, from AT90SCR100 // Sources {"AT90SCR100H", 376, F_AVR8, {0x1E, 0x96, 0xC1}, // ID /*AT90SCR100H*/ -1, -1, -1, 4, 0x0200, -1, -1, -1, 0x0100, 0x1000, // Mem - /*AT90SCR100H*/ 3, 1, 38, vtab_at90scr100h, 13, cfgtab_at90scr100h}, // Config, ISRs + /*AT90SCR100H*/ 3, 1, 38, vtab_at90scr100h, 13, cfgtab_at90scr100h, // ISRs, Config + /*AT90SCR100H*/ 0, NULL}, // Register file //AT90CAN128 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90CAN128", 176, F_AVR8, {0x1E, 0x97, 0x81}, // ID /*AT90CAN128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*AT90CAN128*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can128}, // Config, ISRs + /*AT90CAN128*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can128, // ISRs, Config + /*AT90CAN128*/ 137, rgftab_at90can128}, // Register file //AT90PWM161 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM161", 177, F_AVR8, {0x1E, 0x94, 0x8B}, // ID /*AT90PWM161*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*AT90PWM161*/ 3, 1, 20, vtab_at90pwm161, 19, cfgtab_at90pwm81}, // Config, ISRs + /*AT90PWM161*/ 3, 1, 20, vtab_at90pwm161, 19, cfgtab_at90pwm81, // ISRs, Config + /*AT90PWM161*/ 86, rgftab_at90pwm161}, // Register file //AT90USB162 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90USB162", 178, F_AVR8, {0x1E, 0x94, 0x82}, // ID /*AT90USB162*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90USB162*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162}, // Config, ISRs + /*AT90USB162*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162, // ISRs, Config + /*AT90USB162*/ 92, rgftab_at90usb162}, // Register file //AT90PWM216 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM216", 179, F_AVR8, {0x1E, 0x94, 0x83}, // ID /*AT90PWM216*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*AT90PWM216*/ 3, 1, 32, vtab_at90pwm316, 18, cfgtab_at90pwm216}, // Config, ISRs + /*AT90PWM216*/ 3, 1, 32, vtab_at90pwm316, 18, cfgtab_at90pwm216, // ISRs, Config + /*AT90PWM216*/ 102, rgftab_at90pwm216}, // Register file //AT90PWM316 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90PWM316", 180, F_AVR8, {0x1E, 0x94, 0x83}, // ID /*AT90PWM316*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*AT90PWM316*/ 3, 1, 32, vtab_at90pwm316, 18, cfgtab_at90pwm316}, // Config, ISRs + /*AT90PWM316*/ 3, 1, 32, vtab_at90pwm316, 18, cfgtab_at90pwm316, // ISRs, Config + /*AT90PWM316*/ 117, rgftab_at90pwm316}, // Register file //AT90USB646 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90USB646", 181, F_AVR8, {0x1E, 0x96, 0x82}, // ID /*AT90USB646*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*AT90USB646*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb646}, // Config, ISRs + /*AT90USB646*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb646, // ISRs, Config + /*AT90USB646*/ 157, rgftab_at90usb646}, // Register file //AT90USB647 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90USB647", 182, F_AVR8, {0x1E, 0x96, 0x82}, // ID /*AT90USB647*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*AT90USB647*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb646}, // Config, ISRs + /*AT90USB647*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb646, // ISRs, Config + /*AT90USB647*/ 157, rgftab_at90usb646}, // Register file //AT90S1200 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S1200", 183, F_AVR8, {0x1E, 0x90, 0x01}, // ID /*AT90S1200*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 1, 0x0060, 0x0020, // Mem - /*AT90S1200*/ 1, 1, 4, vtab_at90s1200, 3, cfgtab_at90s1200}, // Config, ISRs + /*AT90S1200*/ 1, 1, 4, vtab_at90s1200, 3, cfgtab_at90s1200, // ISRs, Config + /*AT90S1200*/ 0, NULL}, // Register file //AT90USB1286 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90USB1286", 184, F_AVR8, {0x1E, 0x97, 0x82}, // ID /*AT90USB1286*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, // Mem - /*AT90USB1286*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb1286}, // Config, ISRs + /*AT90USB1286*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb1286, // ISRs, Config + /*AT90USB1286*/ 132, rgftab_at90usb1286}, // Register file //AT90USB1287 atdf, avr-gcc 12.2.0, avrdude // Sources {"AT90USB1287", 185, F_AVR8, {0x1E, 0x97, 0x82}, // ID /*AT90USB1287*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, // Mem - /*AT90USB1287*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb1286}, // Config, ISRs + /*AT90USB1287*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb1286, // ISRs, Config + /*AT90USB1287*/ 157, rgftab_at90usb646}, // Register file //AT90S2313 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2313", 186, F_AVR8, {0x1E, 0x91, 0x01}, // ID /*AT90S2313*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2313*/ 1, 1, 11, vtab_at90s2313, 3, cfgtab_at90s2313}, // Config, ISRs + /*AT90S2313*/ 1, 1, 11, vtab_at90s2313, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S2313*/ 0, NULL}, // Register file //AT90S2323 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2323", 187, F_AVR8, {0x1E, 0x91, 0x02}, // ID /*AT90S2323*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2323*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_at90s2323}, // Config, ISRs + /*AT90S2323*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_at90s2323, // ISRs, Config + /*AT90S2323*/ 0, NULL}, // Register file //AT90S2333 avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2333", 188, F_AVR8, {0x1E, 0x91, 0x05}, // ID /*AT90S2333*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2333*/ 1, 1, 14, vtab_at90s4433, 5, cfgtab_at90s2333}, // Config, ISRs + /*AT90S2333*/ 1, 1, 14, vtab_at90s4433, 5, cfgtab_at90s2333, // ISRs, Config + /*AT90S2333*/ 0, NULL}, // Register file //AT90S2343 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2343", 189, F_AVR8, {0x1E, 0x91, 0x03}, // ID /*AT90S2343*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2343*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_at90s2343}, // Config, ISRs + /*AT90S2343*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_at90s2343, // ISRs, Config + /*AT90S2343*/ 0, NULL}, // Register file //AT90S4414 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S4414", 190, F_AVR8, {0x1E, 0x92, 0x01}, // ID /*AT90S4414*/ 0, 0x01000, 0x001, 0, 0, 0, 0x0100, 1, 0x0060, 0x0100, // Mem - /*AT90S4414*/ 1, 1, 13, vtab_at90s8515, 3, cfgtab_at90s2313}, // Config, ISRs + /*AT90S4414*/ 1, 1, 13, vtab_at90s8515, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S4414*/ 0, NULL}, // Register file //AT90S4433 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S4433", 191, F_AVR8, {0x1E, 0x92, 0x03}, // ID /*AT90S4433*/ 0, 0x01000, 0x001, 0, 0, 0, 0x0100, 1, 0x0060, 0x0080, // Mem - /*AT90S4433*/ 1, 1, 14, vtab_at90s4433, 5, cfgtab_at90s4433}, // Config, ISRs + /*AT90S4433*/ 1, 1, 14, vtab_at90s4433, 5, cfgtab_at90s4433, // ISRs, Config + /*AT90S4433*/ 0, NULL}, // Register file //AT90S4434 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S4434", 192, F_AVR8, {0x1E, 0x92, 0x02}, // ID /*AT90S4434*/ 0, 0x01000, 0x001, 0, 0, 0, 0x0100, 1, 0x0060, 0x0100, // Mem - /*AT90S4434*/ 1, 1, 17, vtab_at90s8535, 3, cfgtab_at90s2313}, // Config, ISRs + /*AT90S4434*/ 1, 1, 17, vtab_at90s8535, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S4434*/ 0, NULL}, // Register file //AT90S8515 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S8515", 193, F_AVR8, {0x1E, 0x93, 0x01}, // ID /*AT90S8515*/ 0, 0x02000, 0x001, 0, 0, 0, 0x0200, 1, 0x0060, 0x0200, // Mem - /*AT90S8515*/ 1, 1, 13, vtab_at90s8515, 3, cfgtab_at90s2313}, // Config, ISRs + /*AT90S8515*/ 1, 1, 13, vtab_at90s8515, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S8515*/ 0, NULL}, // Register file //AT90S8515comp xml // Sources {"AT90S8515comp", 377, F_AVR8, {0x1E, 0x93, 0x01}, // ID /*AT90S8515comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*AT90S8515comp*/ -1, -1, 0, NULL, 13, cfgtab_at90s8515comp}, // Config, ISRs + /*AT90S8515comp*/ -1, -1, 0, NULL, 13, cfgtab_at90s8515comp, // ISRs, Config + /*AT90S8515comp*/ 0, NULL}, // Register file //AT90C8534 avr-gcc 12.2.0 // Sources {"AT90C8534", 194, F_AVR8, {0xff, -1, -1}, // ID /*AT90C8534*/ 0, 0x02000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0100, // Mem - /*AT90C8534*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT90C8534*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT90C8534*/ 0, NULL}, // Register file //AT90S8535 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S8535", 195, F_AVR8, {0x1E, 0x93, 0x03}, // ID /*AT90S8535*/ 0, 0x02000, 0x001, 0, 0, 0, 0x0200, 1, 0x0060, 0x0200, // Mem - /*AT90S8535*/ 1, 1, 17, vtab_at90s8535, 3, cfgtab_at90s2313}, // Config, ISRs + /*AT90S8535*/ 1, 1, 17, vtab_at90s8535, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S8535*/ 0, NULL}, // Register file //AT90S8535comp xml // Sources {"AT90S8535comp", 378, F_AVR8, {0x1E, 0x93, 0x03}, // ID /*AT90S8535comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*AT90S8535comp*/ -1, -1, 0, NULL, 13, cfgtab_at90s8535comp}, // Config, ISRs + /*AT90S8535comp*/ -1, -1, 0, NULL, 13, cfgtab_at90s8535comp, // ISRs, Config + /*AT90S8535comp*/ 0, NULL}, // Register file //AT94K avr-gcc 12.2.0 // Sources {"AT94K", 196, F_AVR8, {0xff, -1, -1}, // ID /*AT94K*/ 0, 0x08000, -1, -1, -1, -1, -1, -1, 0x0060, 0x0fa0, // Mem - /*AT94K*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AT94K*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT94K*/ 0, NULL}, // Register file //ATA5272 atdf, avr-gcc 12.2.0 // Sources {"ATA5272", 197, F_AVR8, {0x1E, 0x93, 0x87}, // ID /*ATA5272*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA5272*/ 3, 1, 37, vtab_ata5272, 11, cfgtab_attiny87}, // Config, ISRs + /*ATA5272*/ 3, 1, 37, vtab_ata5272, 11, cfgtab_attiny87, // ISRs, Config + /*ATA5272*/ 80, rgftab_ata5272}, // Register file //ATA5505 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA5505", 198, F_AVR8, {0x1E, 0x94, 0x87}, // ID /*ATA5505*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA5505*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87}, // Config, ISRs + /*ATA5505*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config + /*ATA5505*/ 80, rgftab_ata5272}, // Register file //ATA5700M322 atdf // Sources {"ATA5700M322", 199, F_AVR8, {0x1E, 0x95, 0x67}, // ID /*ATA5700M322*/ 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, // Mem - /*ATA5700M322*/ 1, 1, 51, vtab_ata5702m322, 9, cfgtab_ata5700m322}, // Config, ISRs + /*ATA5700M322*/ 1, 1, 51, vtab_ata5702m322, 9, cfgtab_ata5700m322, // ISRs, Config + /*ATA5700M322*/ 337, rgftab_ata5700m322}, // Register file //ATA5702M322 atdf, avr-gcc 12.2.0 // Sources {"ATA5702M322", 200, F_AVR8, {0x1E, 0x95, 0x69}, // ID /*ATA5702M322*/ 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, // Mem - /*ATA5702M322*/ 1, 1, 51, vtab_ata5702m322, 9, cfgtab_ata5700m322}, // Config, ISRs + /*ATA5702M322*/ 1, 1, 51, vtab_ata5702m322, 9, cfgtab_ata5700m322, // ISRs, Config + /*ATA5702M322*/ 378, rgftab_ata5702m322}, // Register file //ATA5781 atdf // Sources {"ATA5781", 201, F_AVR8, {0x1E, 0x95, 0x64}, // ID /*ATA5781*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5781*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA5781*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5781*/ 262, rgftab_ata5781}, // Register file //ATA5782 atdf, avr-gcc 12.2.0 // Sources {"ATA5782", 202, F_AVR8, {0x1E, 0x95, 0x65}, // ID /*ATA5782*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5782*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA5782*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5782*/ 262, rgftab_ata5781}, // Register file //ATA5783 atdf // Sources {"ATA5783", 203, F_AVR8, {0x1E, 0x95, 0x66}, // ID /*ATA5783*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5783*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA5783*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5783*/ 262, rgftab_ata5781}, // Register file //ATA5787 atdf // Sources {"ATA5787", 204, F_AVR8, {0x1E, 0x94, 0x6C}, // ID /*ATA5787*/ 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, // Mem - /*ATA5787*/ 1, 1, 44, vtab_ata5835, 11, cfgtab_ata5787}, // Config, ISRs + /*ATA5787*/ 1, 1, 44, vtab_ata5835, 11, cfgtab_ata5787, // ISRs, Config + /*ATA5787*/ 292, rgftab_ata5787}, // Register file //ATA5790 atdf, avr-gcc 12.2.0 // Sources {"ATA5790", 205, F_AVR8, {0x1E, 0x94, 0x61}, // ID /*ATA5790*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5790*/ 1, 1, 30, vtab_ata5790, 11, cfgtab_ata5790}, // Config, ISRs + /*ATA5790*/ 1, 1, 30, vtab_ata5790, 11, cfgtab_ata5790, // ISRs, Config + /*ATA5790*/ 112, rgftab_ata5790}, // Register file //ATA5790N atdf, avr-gcc 12.2.0 // Sources {"ATA5790N", 206, F_AVR8, {0x1E, 0x94, 0x62}, // ID /*ATA5790N*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5790N*/ 1, 1, 31, vtab_ata5791, 10, cfgtab_ata5790n}, // Config, ISRs + /*ATA5790N*/ 1, 1, 31, vtab_ata5791, 10, cfgtab_ata5790n, // ISRs, Config + /*ATA5790N*/ 117, rgftab_ata5790n}, // Register file //ATA5791 atdf, avr-gcc 7.3.0 // Sources {"ATA5791", 207, F_AVR8, {0x1E, 0x94, 0x62}, // ID /*ATA5791*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5791*/ 1, 1, 31, vtab_ata5791, 11, cfgtab_ata5790}, // Config, ISRs + /*ATA5791*/ 1, 1, 31, vtab_ata5791, 11, cfgtab_ata5790, // ISRs, Config + /*ATA5791*/ 117, rgftab_ata5790n}, // Register file //ATA5795 atdf, avr-gcc 12.2.0 // Sources {"ATA5795", 208, F_AVR8, {0x1E, 0x93, 0x61}, // ID /*ATA5795*/ 0, 0x02000, 0x040, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5795*/ 1, 1, 23, vtab_ata5795, 10, cfgtab_ata5790n}, // Config, ISRs + /*ATA5795*/ 1, 1, 23, vtab_ata5795, 10, cfgtab_ata5790n, // ISRs, Config + /*ATA5795*/ 84, rgftab_ata5795}, // Register file //ATA5831 atdf, avr-gcc 12.2.0 // Sources {"ATA5831", 209, F_AVR8, {0x1E, 0x95, 0x61}, // ID /*ATA5831*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5831*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA5831*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5831*/ 279, rgftab_ata5831}, // Register file //ATA5832 atdf // Sources {"ATA5832", 210, F_AVR8, {0x1E, 0x95, 0x62}, // ID /*ATA5832*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5832*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA5832*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5832*/ 279, rgftab_ata5831}, // Register file //ATA5833 atdf // Sources {"ATA5833", 211, F_AVR8, {0x1E, 0x95, 0x63}, // ID /*ATA5833*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5833*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA5833*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5833*/ 279, rgftab_ata5831}, // Register file //ATA5835 atdf // Sources {"ATA5835", 212, F_AVR8, {0x1E, 0x94, 0x6B}, // ID /*ATA5835*/ 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, // Mem - /*ATA5835*/ 1, 1, 44, vtab_ata5835, 11, cfgtab_ata5787}, // Config, ISRs + /*ATA5835*/ 1, 1, 44, vtab_ata5835, 11, cfgtab_ata5787, // ISRs, Config + /*ATA5835*/ 307, rgftab_ata5835}, // Register file //ATA6285 atdf, avr-gcc 12.2.0 // Sources {"ATA6285", 213, F_AVR8, {0x1E, 0x93, 0x82}, // ID /*ATA6285*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, // Mem - /*ATA6285*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6285}, // Config, ISRs + /*ATA6285*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6285, // ISRs, Config + /*ATA6285*/ 79, rgftab_ata6285}, // Register file //ATA6286 atdf, avr-gcc 12.2.0 // Sources {"ATA6286", 214, F_AVR8, {0x1E, 0x93, 0x82}, // ID /*ATA6286*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, // Mem - /*ATA6286*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6285}, // Config, ISRs + /*ATA6286*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6285, // ISRs, Config + /*ATA6286*/ 79, rgftab_ata6285}, // Register file //ATA6289 xml, avr-gcc 12.2.0, boot size (manual) // Sources {"ATA6289", 215, F_AVR8, {0x1E, 0x93, 0x82}, // ID /*ATA6289*/ 0, 0x02000, 0x040, 4, 0x0100, -1, -1, -1, 0x0100, 0x0200, // Mem - /*ATA6289*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6289}, // Config, ISRs + /*ATA6289*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6289, // ISRs, Config + /*ATA6289*/ 0, NULL}, // Register file //ATA6612C atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA6612C", 216, F_AVR8, {0x1E, 0x93, 0x0A}, // ID /*ATA6612C*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATA6612C*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88}, // Config, ISRs + /*ATA6612C*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config + /*ATA6612C*/ 81, rgftab_ata6612c}, // Register file //ATA6613C atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA6613C", 217, F_AVR8, {0x1E, 0x94, 0x06}, // ID /*ATA6613C*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATA6613C*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168}, // Config, ISRs + /*ATA6613C*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config + /*ATA6613C*/ 81, rgftab_ata6612c}, // Register file //ATA6614Q atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA6614Q", 218, F_AVR8, {0x1E, 0x95, 0x0F}, // ID /*ATA6614Q*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATA6614Q*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega328}, // Config, ISRs + /*ATA6614Q*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega328, // ISRs, Config + /*ATA6614Q*/ 81, rgftab_ata6614q}, // Register file //ATA6616C atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA6616C", 219, F_AVR8, {0x1E, 0x93, 0x87}, // ID /*ATA6616C*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA6616C*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87}, // Config, ISRs + /*ATA6616C*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config + /*ATA6616C*/ 81, rgftab_ata6616c}, // Register file //ATA6617C atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA6617C", 220, F_AVR8, {0x1E, 0x94, 0x87}, // ID /*ATA6617C*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA6617C*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87}, // Config, ISRs + /*ATA6617C*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config + /*ATA6617C*/ 81, rgftab_ata6616c}, // Register file //ATA8210 atdf, avr-gcc 7.3.0 // Sources {"ATA8210", 221, F_AVR8, {0x1E, 0x95, 0x65}, // ID /*ATA8210*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8210*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA8210*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA8210*/ 262, rgftab_ata5781}, // Register file //ATA8215 atdf // Sources {"ATA8215", 222, F_AVR8, {0x1E, 0x95, 0x64}, // ID /*ATA8215*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8215*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA8215*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA8215*/ 262, rgftab_ata5781}, // Register file //ATA8510 atdf, avr-gcc 7.3.0 // Sources {"ATA8510", 223, F_AVR8, {0x1E, 0x95, 0x61}, // ID /*ATA8510*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8510*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA8510*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA8510*/ 279, rgftab_ata5831}, // Register file //ATA8515 atdf // Sources {"ATA8515", 224, F_AVR8, {0x1E, 0x95, 0x63}, // ID /*ATA8515*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8515*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781}, // Config, ISRs + /*ATA8515*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config + /*ATA8515*/ 279, rgftab_ata5831}, // Register file //ATA664251 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATA664251", 225, F_AVR8, {0x1E, 0x94, 0x87}, // ID /*ATA664251*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA664251*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87}, // Config, ISRs + /*ATA664251*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config + /*ATA664251*/ 81, rgftab_ata6616c}, // Register file //M3000 avr-gcc 12.2.0 // Sources {"M3000", 226, F_AVR8, {0xff, -1, -1}, // ID /*M3000*/ 0, 0x10000, -1, -1, -1, -1, -1, -1, 0x1000, 0x1000, // Mem - /*M3000*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*M3000*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*M3000*/ 0, NULL}, // Register file //LGT8F88P avrdude, from ATmega88 // Sources {"LGT8F88P", 227, F_AVR8, {0x1E, 0x93, 0x0F}, // ID /*LGT8F88P*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*LGT8F88P*/ -1, -1, 26, vtab_atmega328p, 0, NULL}, // Config, ISRs + /*LGT8F88P*/ -1, -1, 26, vtab_atmega328p, 0, NULL, // ISRs, Config + /*LGT8F88P*/ 81, rgftab_atmega88}, // Register file //LGT8F168P avrdude, from ATmega168P // Sources {"LGT8F168P", 228, F_AVR8, {0x1E, 0x94, 0x0B}, // ID /*LGT8F168P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*LGT8F168P*/ -1, -1, 26, vtab_atmega328p, 0, NULL}, // Config, ISRs + /*LGT8F168P*/ -1, -1, 26, vtab_atmega328p, 0, NULL, // ISRs, Config + /*LGT8F168P*/ 81, rgftab_atmega88}, // Register file //LGT8F328P avrdude, from ATmega328P // Sources {"LGT8F328P", 229, F_AVR8, {0x1E, 0x95, 0x0F}, // ID /*LGT8F328P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*LGT8F328P*/ -1, -1, 26, vtab_atmega328p, 0, NULL}, // Config, ISRs + /*LGT8F328P*/ -1, -1, 26, vtab_atmega328p, 0, NULL, // ISRs, Config + /*LGT8F328P*/ 81, rgftab_atmega328}, // Register file //ATxmega8E5 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega8E5", 230, F_XMEGA, {0x1E, 0x93, 0x41}, // ID /*ATxmega8E5*/ 0, 0x02800, 0x080, 1, 0x0800, 0, 0x0200, 32, 0x2000, 0x0400, // Mem - /*ATxmega8E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5}, // Config, ISRs + /*ATxmega8E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5, // ISRs, Config + /*ATxmega8E5*/ 438, rgftab_atxmega16e5}, // Register file //ATxmega16A4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega16A4", 231, F_XMEGA, {0x1E, 0x94, 0x41}, // ID /*ATxmega16A4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16A4*/ 6, 1, 94, vtab_atxmega32a4, 16, cfgtab_atxmega16a4}, // Config, ISRs + /*ATxmega16A4*/ 6, 1, 94, vtab_atxmega32a4, 16, cfgtab_atxmega16a4, // ISRs, Config + /*ATxmega16A4*/ 553, rgftab_atxmega16a4}, // Register file //ATxmega16A4U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega16A4U", 232, F_XMEGA, {0x1E, 0x94, 0x41}, // ID /*ATxmega16A4U*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega16A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega16A4U*/ 630, rgftab_atxmega16a4u}, // Register file //ATxmega16C4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega16C4", 233, F_XMEGA, {0x1E, 0x94, 0x43}, // ID /*ATxmega16C4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16C4*/ 6, 1, 127, vtab_atxmega32c4, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega16C4*/ 6, 1, 127, vtab_atxmega32c4, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega16C4*/ 482, rgftab_atxmega16c4}, // Register file //ATxmega16D4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega16D4", 234, F_XMEGA, {0x1E, 0x94, 0x42}, // ID /*ATxmega16D4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16D4*/ 6, 1, 91, vtab_atxmega32d4, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega16D4*/ 6, 1, 91, vtab_atxmega32d4, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega16D4*/ 460, rgftab_atxmega16d4}, // Register file //ATxmega16E5 atdf, avr-gcc 7.3.0, avrdude // Sources {"ATxmega16E5", 235, F_XMEGA, {0x1E, 0x94, 0x45}, // ID /*ATxmega16E5*/ 0, 0x05000, 0x080, 1, 0x1000, 0, 0x0200, 32, 0x2000, 0x0800, // Mem - /*ATxmega16E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5}, // Config, ISRs + /*ATxmega16E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5, // ISRs, Config + /*ATxmega16E5*/ 438, rgftab_atxmega16e5}, // Register file //ATxmega32C3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32C3", 236, F_XMEGA, {0x1E, 0x95, 0x49}, // ID /*ATxmega32C3*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega32C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega32C3*/ 569, rgftab_atxmega32c3}, // Register file //ATxmega32D3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32D3", 237, F_XMEGA, {0x1E, 0x95, 0x4A}, // ID /*ATxmega32D3*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega32D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega32D3*/ 567, rgftab_atxmega32d3}, // Register file //ATxmega32A4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32A4", 238, F_XMEGA, {0x1E, 0x95, 0x41}, // ID /*ATxmega32A4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32A4*/ 6, 1, 94, vtab_atxmega32a4, 16, cfgtab_atxmega16a4}, // Config, ISRs + /*ATxmega32A4*/ 6, 1, 94, vtab_atxmega32a4, 16, cfgtab_atxmega16a4, // ISRs, Config + /*ATxmega32A4*/ 553, rgftab_atxmega16a4}, // Register file //ATxmega32A4U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32A4U", 239, F_XMEGA, {0x1E, 0x95, 0x41}, // ID /*ATxmega32A4U*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega32A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega32A4U*/ 630, rgftab_atxmega16a4u}, // Register file //ATxmega32C4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32C4", 240, F_XMEGA, {0x1E, 0x95, 0x44}, // ID /*ATxmega32C4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32C4*/ 6, 1, 127, vtab_atxmega32c4, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega32C4*/ 6, 1, 127, vtab_atxmega32c4, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega32C4*/ 482, rgftab_atxmega16c4}, // Register file //ATxmega32D4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32D4", 241, F_XMEGA, {0x1E, 0x95, 0x42}, // ID /*ATxmega32D4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32D4*/ 6, 1, 91, vtab_atxmega32d4, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega32D4*/ 6, 1, 91, vtab_atxmega32d4, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega32D4*/ 460, rgftab_atxmega16d4}, // Register file //ATxmega32E5 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega32E5", 242, F_XMEGA, {0x1E, 0x95, 0x4C}, // ID /*ATxmega32E5*/ 0, 0x09000, 0x080, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5}, // Config, ISRs + /*ATxmega32E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5, // ISRs, Config + /*ATxmega32E5*/ 438, rgftab_atxmega16e5}, // Register file //ATxmega64A1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64A1", 243, F_XMEGA, {0x1E, 0x96, 0x4E}, // ID /*ATxmega64A1*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A1*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega64A1*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega64A1*/ 814, rgftab_atxmega64a1}, // Register file //ATxmega64A1U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64A1U", 244, F_XMEGA, {0x1E, 0x96, 0x4E}, // ID /*ATxmega64A1U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A1U*/ 6, 1, 127, vtab_atxmega128a1u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega64A1U*/ 6, 1, 127, vtab_atxmega128a1u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega64A1U*/ 943, rgftab_atxmega64a1u}, // Register file //ATxmega64B1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64B1", 245, F_XMEGA, {0x1E, 0x96, 0x52}, // ID /*ATxmega64B1*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64B1*/ 6, 1, 81, vtab_atxmega128b1, 17, cfgtab_atxmega64b1}, // Config, ISRs + /*ATxmega64B1*/ 6, 1, 81, vtab_atxmega128b1, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega64B1*/ 574, rgftab_atxmega64b1}, // Register file //ATxmega64A3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64A3", 246, F_XMEGA, {0x1E, 0x96, 0x42}, // ID /*ATxmega64A3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega64A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega64A3*/ 680, rgftab_atxmega128a3}, // Register file //ATxmega64A3U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64A3U", 247, F_XMEGA, {0x1E, 0x96, 0x42}, // ID /*ATxmega64A3U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega64A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega64A3U*/ 792, rgftab_atxmega128a3u}, // Register file //ATxmega64B3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64B3", 248, F_XMEGA, {0x1E, 0x96, 0x51}, // ID /*ATxmega64B3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64B3*/ 6, 1, 54, vtab_atxmega128b3, 17, cfgtab_atxmega64b1}, // Config, ISRs + /*ATxmega64B3*/ 6, 1, 54, vtab_atxmega128b3, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega64B3*/ 458, rgftab_atxmega64b3}, // Register file //ATxmega64C3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64C3", 249, F_XMEGA, {0x1E, 0x96, 0x49}, // ID /*ATxmega64C3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega64C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega64C3*/ 569, rgftab_atxmega32c3}, // Register file //ATxmega64D3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64D3", 250, F_XMEGA, {0x1E, 0x96, 0x4A}, // ID /*ATxmega64D3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega64D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega64D3*/ 567, rgftab_atxmega32d3}, // Register file //ATxmega64A4 avrdude // Sources {"ATxmega64A4", 251, F_XMEGA, {0x1E, 0x96, 0x46}, // ID /*ATxmega64A4*/ 0, 0x11000, 0x100, -1, -1, 0, 0x0800, 32, -1, -1, // Mem - /*ATxmega64A4*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*ATxmega64A4*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*ATxmega64A4*/ 0, NULL}, // Register file //ATxmega64A4U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64A4U", 252, F_XMEGA, {0x1E, 0x96, 0x46}, // ID /*ATxmega64A4U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega64A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega64A4U*/ 632, rgftab_atxmega64a4u}, // Register file //ATxmega64D4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega64D4", 253, F_XMEGA, {0x1E, 0x96, 0x47}, // ID /*ATxmega64D4*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64D4*/ 6, 1, 91, vtab_atxmega128d4, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega64D4*/ 6, 1, 91, vtab_atxmega128d4, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega64D4*/ 460, rgftab_atxmega64d4}, // Register file //ATxmega128A1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128A1", 254, F_XMEGA, {0x1E, 0x97, 0x4C}, // ID /*ATxmega128A1*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A1*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega128A1*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega128A1*/ 814, rgftab_atxmega64a1}, // Register file //ATxmega128A1revD avrdude, from ATxmega128A1 // Sources {"ATxmega128A1revD", 255, F_XMEGA, {0x1E, 0x97, 0x41}, // ID /*ATxmega128A1revD*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A1revD*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega128A1revD*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega128A1revD*/ 814, rgftab_atxmega64a1}, // Register file //ATxmega128A1U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128A1U", 256, F_XMEGA, {0x1E, 0x97, 0x4C}, // ID /*ATxmega128A1U*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A1U*/ 6, 1, 127, vtab_atxmega128a1u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega128A1U*/ 6, 1, 127, vtab_atxmega128a1u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega128A1U*/ 943, rgftab_atxmega64a1u}, // Register file //ATxmega128B1 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128B1", 257, F_XMEGA, {0x1E, 0x97, 0x4D}, // ID /*ATxmega128B1*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128B1*/ 6, 1, 81, vtab_atxmega128b1, 17, cfgtab_atxmega64b1}, // Config, ISRs + /*ATxmega128B1*/ 6, 1, 81, vtab_atxmega128b1, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega128B1*/ 574, rgftab_atxmega64b1}, // Register file //ATxmega128A3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128A3", 258, F_XMEGA, {0x1E, 0x97, 0x42}, // ID /*ATxmega128A3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega128A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega128A3*/ 680, rgftab_atxmega128a3}, // Register file //ATxmega128A3U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128A3U", 259, F_XMEGA, {0x1E, 0x97, 0x42}, // ID /*ATxmega128A3U*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega128A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega128A3U*/ 792, rgftab_atxmega128a3u}, // Register file //ATxmega128B3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128B3", 260, F_XMEGA, {0x1E, 0x97, 0x4B}, // ID /*ATxmega128B3*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128B3*/ 6, 1, 54, vtab_atxmega128b3, 17, cfgtab_atxmega64b1}, // Config, ISRs + /*ATxmega128B3*/ 6, 1, 54, vtab_atxmega128b3, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega128B3*/ 458, rgftab_atxmega64b3}, // Register file //ATxmega128C3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128C3", 261, F_XMEGA, {0x1E, 0x97, 0x52}, // ID /*ATxmega128C3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega128C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega128C3*/ 569, rgftab_atxmega32c3}, // Register file //ATxmega128D3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128D3", 262, F_XMEGA, {0x1E, 0x97, 0x48}, // ID /*ATxmega128D3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega128D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega128D3*/ 567, rgftab_atxmega32d3}, // Register file //ATxmega128A4 avrdude // Sources {"ATxmega128A4", 263, F_XMEGA, {0x1E, 0x97, 0x46}, // ID /*ATxmega128A4*/ 0, 0x22000, 0x200, -1, -1, 0, 0x0800, 32, -1, -1, // Mem - /*ATxmega128A4*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*ATxmega128A4*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*ATxmega128A4*/ 0, NULL}, // Register file //ATxmega128A4U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128A4U", 264, F_XMEGA, {0x1E, 0x97, 0x46}, // ID /*ATxmega128A4U*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega128A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega128A4U*/ 632, rgftab_atxmega64a4u}, // Register file //ATxmega128D4 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega128D4", 265, F_XMEGA, {0x1E, 0x97, 0x47}, // ID /*ATxmega128D4*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128D4*/ 6, 1, 91, vtab_atxmega128d4, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega128D4*/ 6, 1, 91, vtab_atxmega128d4, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega128D4*/ 460, rgftab_atxmega64d4}, // Register file //ATxmega192A1 avrdude // Sources {"ATxmega192A1", 266, F_XMEGA, {0x1E, 0x97, 0x4E}, // ID /*ATxmega192A1*/ 0, 0x32000, 0x200, -1, -1, 0, 0x0800, 32, -1, -1, // Mem - /*ATxmega192A1*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*ATxmega192A1*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*ATxmega192A1*/ 0, NULL}, // Register file //ATxmega192A3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega192A3", 267, F_XMEGA, {0x1E, 0x97, 0x44}, // ID /*ATxmega192A3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega192A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega192A3*/ 680, rgftab_atxmega128a3}, // Register file //ATxmega192A3U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega192A3U", 268, F_XMEGA, {0x1E, 0x97, 0x44}, // ID /*ATxmega192A3U*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega192A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega192A3U*/ 792, rgftab_atxmega128a3u}, // Register file //ATxmega192C3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega192C3", 269, F_XMEGA, {0x1E, 0x97, 0x51}, // ID /*ATxmega192C3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega192C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega192C3*/ 569, rgftab_atxmega32c3}, // Register file //ATxmega192D3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega192D3", 270, F_XMEGA, {0x1E, 0x97, 0x49}, // ID /*ATxmega192D3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega192D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega192D3*/ 567, rgftab_atxmega32d3}, // Register file //ATxmega256A1 avrdude // Sources {"ATxmega256A1", 271, F_XMEGA, {0x1E, 0x98, 0x46}, // ID /*ATxmega256A1*/ 0, 0x42000, 0x200, -1, -1, 0, 0x1000, 32, -1, -1, // Mem - /*ATxmega256A1*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*ATxmega256A1*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*ATxmega256A1*/ 0, NULL}, // Register file //ATxmega256A3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega256A3", 272, F_XMEGA, {0x1E, 0x98, 0x42}, // ID /*ATxmega256A3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega256A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega256A3*/ 680, rgftab_atxmega128a3}, // Register file //ATxmega256A3B atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega256A3B", 273, F_XMEGA, {0x1E, 0x98, 0x43}, // ID /*ATxmega256A3B*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3B*/ 6, 1, 122, vtab_atxmega256a3b, 16, cfgtab_atxmega128a3}, // Config, ISRs + /*ATxmega256A3B*/ 6, 1, 122, vtab_atxmega256a3b, 16, cfgtab_atxmega128a3, // ISRs, Config + /*ATxmega256A3B*/ 665, rgftab_atxmega256a3b}, // Register file //ATxmega256A3BU atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega256A3BU", 274, F_XMEGA, {0x1E, 0x98, 0x43}, // ID /*ATxmega256A3BU*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3BU*/ 6, 1, 127, vtab_atxmega256a3bu, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega256A3BU*/ 6, 1, 127, vtab_atxmega256a3bu, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega256A3BU*/ 780, rgftab_atxmega256a3bu}, // Register file //ATxmega256A3U atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega256A3U", 275, F_XMEGA, {0x1E, 0x98, 0x42}, // ID /*ATxmega256A3U*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u}, // Config, ISRs + /*ATxmega256A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config + /*ATxmega256A3U*/ 792, rgftab_atxmega128a3u}, // Register file //ATxmega256C3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega256C3", 276, F_XMEGA, {0x1E, 0x98, 0x46}, // ID /*ATxmega256C3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega256C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega256C3*/ 569, rgftab_atxmega32c3}, // Register file //ATxmega256D3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega256D3", 277, F_XMEGA, {0x1E, 0x98, 0x44}, // ID /*ATxmega256D3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega256D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega256D3*/ 567, rgftab_atxmega32d3}, // Register file //ATxmega384C3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega384C3", 278, F_XMEGA, {0x1E, 0x98, 0x45}, // ID /*ATxmega384C3*/ 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, // Mem - /*ATxmega384C3*/ 6, 1, 127, vtab_atxmega384c3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega384C3*/ 6, 1, 127, vtab_atxmega384c3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega384C3*/ 603, rgftab_atxmega384c3}, // Register file //ATxmega384D3 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATxmega384D3", 279, F_XMEGA, {0x1E, 0x98, 0x47}, // ID /*ATxmega384D3*/ 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, // Mem - /*ATxmega384D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4}, // Config, ISRs + /*ATxmega384D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config + /*ATxmega384D3*/ 560, rgftab_atxmega384d3}, // Register file //ATtiny202 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny202", 280, F_AVR8X, {0x1E, 0x91, 0x23}, // ID /*ATtiny202*/ 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny202*/ 10, 1, 26, vtab_attiny402, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny202*/ 10, 1, 26, vtab_attiny402, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny202*/ 217, rgftab_attiny202}, // Register file //ATtiny204 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny204", 281, F_AVR8X, {0x1E, 0x91, 0x22}, // ID /*ATtiny204*/ 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny204*/ 10, 1, 26, vtab_attiny404, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny204*/ 10, 1, 26, vtab_attiny404, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny204*/ 235, rgftab_attiny204}, // Register file //ATtiny212 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny212", 282, F_AVR8X, {0x1E, 0x91, 0x21}, // ID /*ATtiny212*/ 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny212*/ 10, 1, 26, vtab_attiny412, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny212*/ 10, 1, 26, vtab_attiny412, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny212*/ 247, rgftab_attiny212}, // Register file //ATtiny214 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny214", 283, F_AVR8X, {0x1E, 0x91, 0x20}, // ID /*ATtiny214*/ 0, 0x00800, 0x040, 1, 0, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny214*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny214*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny214*/ 265, rgftab_attiny214}, // Register file //ATtiny402 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny402", 284, F_AVR8X, {0x1E, 0x92, 0x27}, // ID /*ATtiny402*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny402*/ 10, 1, 26, vtab_attiny402, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny402*/ 10, 1, 26, vtab_attiny402, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny402*/ 217, rgftab_attiny202}, // Register file //ATtiny404 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny404", 285, F_AVR8X, {0x1E, 0x92, 0x26}, // ID /*ATtiny404*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny404*/ 10, 1, 26, vtab_attiny404, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny404*/ 10, 1, 26, vtab_attiny404, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny404*/ 235, rgftab_attiny204}, // Register file //ATtiny406 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny406", 286, F_AVR8X, {0x1E, 0x92, 0x25}, // ID /*ATtiny406*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny406*/ 10, 1, 26, vtab_attiny406, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny406*/ 10, 1, 26, vtab_attiny406, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny406*/ 253, rgftab_attiny406}, // Register file //ATtiny412 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny412", 287, F_AVR8X, {0x1E, 0x92, 0x23}, // ID /*ATtiny412*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny412*/ 10, 1, 26, vtab_attiny412, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny412*/ 10, 1, 26, vtab_attiny412, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny412*/ 247, rgftab_attiny212}, // Register file //ATtiny414 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny414", 288, F_AVR8X, {0x1E, 0x92, 0x22}, // ID /*ATtiny414*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny414*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny414*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny414*/ 265, rgftab_attiny214}, // Register file //ATtiny416 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny416", 289, F_AVR8X, {0x1E, 0x92, 0x21}, // ID /*ATtiny416*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny416*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny416*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny416*/ 283, rgftab_attiny416}, // Register file //ATtiny416auto atdf, avrdude // Sources {"ATtiny416auto", 290, F_AVR8X, {0x1E, 0x92, 0x28}, // ID /*ATtiny416auto*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny416auto*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny416auto}, // Config, ISRs + /*ATtiny416auto*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny416auto, // ISRs, Config + /*ATtiny416auto*/ 283, rgftab_attiny416auto}, // Register file //ATtiny417 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny417", 291, F_AVR8X, {0x1E, 0x92, 0x20}, // ID /*ATtiny417*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny417*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny417*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny417*/ 283, rgftab_attiny417}, // Register file //ATtiny424 atdf, avrdude // Sources {"ATtiny424", 292, F_AVR8X, {0x1E, 0x92, 0x2C}, // ID /*ATtiny424*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny424*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny424*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny424*/ 307, rgftab_attiny1624}, // Register file //ATtiny426 atdf, avrdude // Sources {"ATtiny426", 293, F_AVR8X, {0x1E, 0x92, 0x2B}, // ID /*ATtiny426*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny426*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny426*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny426*/ 308, rgftab_attiny426}, // Register file //ATtiny427 atdf, avrdude // Sources {"ATtiny427", 294, F_AVR8X, {0x1E, 0x92, 0x2A}, // ID /*ATtiny427*/ 0, 0x01000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny427*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny427*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny427*/ 308, rgftab_attiny426}, // Register file //ATtiny804 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny804", 295, F_AVR8X, {0x1E, 0x93, 0x25}, // ID /*ATtiny804*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny804*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804}, // Config, ISRs + /*ATtiny804*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny804*/ 255, rgftab_attiny804}, // Register file //ATtiny806 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny806", 296, F_AVR8X, {0x1E, 0x93, 0x24}, // ID /*ATtiny806*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny806*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804}, // Config, ISRs + /*ATtiny806*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny806*/ 255, rgftab_attiny804}, // Register file //ATtiny807 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny807", 297, F_AVR8X, {0x1E, 0x93, 0x23}, // ID /*ATtiny807*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny807*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804}, // Config, ISRs + /*ATtiny807*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny807*/ 255, rgftab_attiny804}, // Register file //ATtiny814 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny814", 298, F_AVR8X, {0x1E, 0x93, 0x22}, // ID /*ATtiny814*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny814*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny814*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny814*/ 265, rgftab_attiny814}, // Register file //ATtiny816 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny816", 299, F_AVR8X, {0x1E, 0x93, 0x21}, // ID /*ATtiny816*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny816*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny816*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny816*/ 283, rgftab_attiny417}, // Register file //ATtiny817 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny817", 300, F_AVR8X, {0x1E, 0x93, 0x20}, // ID /*ATtiny817*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny817*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny817*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny817*/ 283, rgftab_attiny417}, // Register file //ATtiny824 atdf, avrdude // Sources {"ATtiny824", 301, F_AVR8X, {0x1E, 0x93, 0x29}, // ID /*ATtiny824*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem - /*ATtiny824*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny824*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny824*/ 307, rgftab_attiny1624}, // Register file //ATtiny826 atdf, avrdude // Sources {"ATtiny826", 302, F_AVR8X, {0x1E, 0x93, 0x28}, // ID /*ATtiny826*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem - /*ATtiny826*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny826*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny826*/ 308, rgftab_attiny426}, // Register file //ATtiny827 atdf, avrdude // Sources {"ATtiny827", 303, F_AVR8X, {0x1E, 0x93, 0x27}, // ID /*ATtiny827*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem - /*ATtiny827*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny827*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny827*/ 308, rgftab_attiny426}, // Register file //ATtiny1604 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1604", 304, F_AVR8X, {0x1E, 0x94, 0x25}, // ID /*ATtiny1604*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATtiny1604*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804}, // Config, ISRs + /*ATtiny1604*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny1604*/ 255, rgftab_attiny804}, // Register file //ATtiny1606 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1606", 305, F_AVR8X, {0x1E, 0x94, 0x24}, // ID /*ATtiny1606*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATtiny1606*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804}, // Config, ISRs + /*ATtiny1606*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny1606*/ 255, rgftab_attiny804}, // Register file //ATtiny1607 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1607", 306, F_AVR8X, {0x1E, 0x94, 0x23}, // ID /*ATtiny1607*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATtiny1607*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804}, // Config, ISRs + /*ATtiny1607*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny1607*/ 255, rgftab_attiny804}, // Register file //ATtiny1614 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1614", 307, F_AVR8X, {0x1E, 0x94, 0x22}, // ID /*ATtiny1614*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1614*/ 10, 1, 31, vtab_attiny1614, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny1614*/ 10, 1, 31, vtab_attiny1614, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny1614*/ 308, rgftab_attiny1614}, // Register file //ATtiny1616 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1616", 308, F_AVR8X, {0x1E, 0x94, 0x21}, // ID /*ATtiny1616*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1616*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny1616*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny1616*/ 326, rgftab_attiny1616}, // Register file //ATtiny1617 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny1617", 309, F_AVR8X, {0x1E, 0x94, 0x20}, // ID /*ATtiny1617*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1617*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny1617*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny1617*/ 326, rgftab_attiny1616}, // Register file //ATtiny1624 atdf, avrdude // Sources {"ATtiny1624", 310, F_AVR8X, {0x1E, 0x94, 0x2A}, // ID /*ATtiny1624*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1624*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny1624*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny1624*/ 307, rgftab_attiny1624}, // Register file //ATtiny1626 atdf, avrdude // Sources {"ATtiny1626", 311, F_AVR8X, {0x1E, 0x94, 0x29}, // ID /*ATtiny1626*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1626*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny1626*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny1626*/ 308, rgftab_attiny426}, // Register file //ATtiny1627 atdf, avrdude // Sources {"ATtiny1627", 312, F_AVR8X, {0x1E, 0x94, 0x28}, // ID /*ATtiny1627*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1627*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny1627*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny1627*/ 308, rgftab_attiny426}, // Register file //ATtiny3214 avr-gcc 12.2.0 // Sources {"ATtiny3214", 313, F_AVR8X, {0x1E, 0x95, 0x20}, // ID /*ATtiny3214*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem - /*ATtiny3214*/ 10, 1, 31, vtab_attiny3214, 0, NULL}, // Config, ISRs + /*ATtiny3214*/ 10, 1, 31, vtab_attiny3214, 0, NULL, // ISRs, Config + /*ATtiny3214*/ 0, NULL}, // Register file //ATtiny3216 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny3216", 314, F_AVR8X, {0x1E, 0x95, 0x21}, // ID /*ATtiny3216*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem - /*ATtiny3216*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny3216*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny3216*/ 326, rgftab_attiny3216}, // Register file //ATtiny3217 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATtiny3217", 315, F_AVR8X, {0x1E, 0x95, 0x22}, // ID /*ATtiny3217*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem - /*ATtiny3217*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204}, // Config, ISRs + /*ATtiny3217*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config + /*ATtiny3217*/ 326, rgftab_attiny3216}, // Register file //ATtiny3224 atdf, avrdude // Sources {"ATtiny3224", 316, F_AVR8X, {0x1E, 0x95, 0x28}, // ID /*ATtiny3224*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem - /*ATtiny3224*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny3224*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny3224*/ 307, rgftab_attiny1624}, // Register file //ATtiny3226 atdf, avrdude // Sources {"ATtiny3226", 317, F_AVR8X, {0x1E, 0x95, 0x27}, // ID /*ATtiny3226*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem - /*ATtiny3226*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny3226*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny3226*/ 308, rgftab_attiny426}, // Register file //ATtiny3227 atdf, avrdude // Sources {"ATtiny3227", 318, F_AVR8X, {0x1E, 0x95, 0x26}, // ID /*ATtiny3227*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem - /*ATtiny3227*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624}, // Config, ISRs + /*ATtiny3227*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config + /*ATtiny3227*/ 308, rgftab_attiny426}, // Register file //ATmega808 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega808", 319, F_AVR8X, {0x1E, 0x93, 0x26}, // ID /*ATmega808*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATmega808*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega808*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega808*/ 406, rgftab_atmega808}, // Register file //ATmega809 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega809", 320, F_AVR8X, {0x1E, 0x93, 0x2A}, // ID /*ATmega809*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATmega809*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega809*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega809*/ 432, rgftab_atmega809}, // Register file //ATmega1608 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1608", 321, F_AVR8X, {0x1E, 0x94, 0x27}, // ID /*ATmega1608*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATmega1608*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega1608*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega1608*/ 406, rgftab_atmega808}, // Register file //ATmega1609 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega1609", 322, F_AVR8X, {0x1E, 0x94, 0x26}, // ID /*ATmega1609*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATmega1609*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega1609*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega1609*/ 432, rgftab_atmega809}, // Register file //ATmega3208 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3208", 323, F_AVR8X, {0x1E, 0x95, 0x30}, // ID /*ATmega3208*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3000, 0x1000, // Mem - /*ATmega3208*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega3208*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega3208*/ 406, rgftab_atmega3208}, // Register file //ATmega3209 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega3209", 324, F_AVR8X, {0x1E, 0x95, 0x31}, // ID /*ATmega3209*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3000, 0x1000, // Mem - /*ATmega3209*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega3209*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega3209*/ 432, rgftab_atmega3209}, // Register file //ATmega4808 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega4808", 325, F_AVR8X, {0x1E, 0x96, 0x50}, // ID /*ATmega4808*/ 0, 0x0c000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x2800, 0x1800, // Mem - /*ATmega4808*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega4808*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega4808*/ 406, rgftab_atmega3208}, // Register file //ATmega4809 atdf, avr-gcc 12.2.0, avrdude // Sources {"ATmega4809", 326, F_AVR8X, {0x1E, 0x96, 0x51}, // ID /*ATmega4809*/ 0, 0x0c000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x2800, 0x1800, // Mem - /*ATmega4809*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808}, // Config, ISRs + /*ATmega4809*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega4809*/ 432, rgftab_atmega3209}, // Register file //AVR8EA28 avrdude // Sources {"AVR8EA28", 327, F_AVR8X, {0x1E, 0x93, 0x2C}, // ID /*AVR8EA28*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, // Mem - /*AVR8EA28*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AVR8EA28*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AVR8EA28*/ 0, NULL}, // Register file //AVR8EA32 avrdude // Sources {"AVR8EA32", 328, F_AVR8X, {0x1E, 0x93, 0x2B}, // ID /*AVR8EA32*/ 0, 0x02000, 0x040, 1, 0, 0x01400, 0x0200, 8, -1, -1, // Mem - /*AVR8EA32*/ -1, -1, 0, NULL, 0, NULL}, // Config, ISRs + /*AVR8EA32*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AVR8EA32*/ 0, NULL}, // Register file //AVR16DD14 atdf, avrdude // Sources {"AVR16DD14", 329, F_AVR8X, {0x1E, 0x94, 0x34}, // ID /*AVR16DD14*/ 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD14*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR16DD14*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR16DD14*/ 401, rgftab_avr32dd14}, // Register file //AVR16EB14 atdf, avrdude // Sources {"AVR16EB14", 380, F_AVR8X, {0x1E, 0x94, 0x49}, // ID /*AVR16EB14*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB14*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14}, // Config, ISRs + /*AVR16EB14*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB14*/ 390, rgftab_avr16eb14}, // Register file //AVR16DD20 atdf, avrdude // Sources {"AVR16DD20", 330, F_AVR8X, {0x1E, 0x94, 0x33}, // ID /*AVR16DD20*/ 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD20*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR16DD20*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR16DD20*/ 401, rgftab_avr32dd14}, // Register file //AVR16EB20 atdf, avrdude // Sources {"AVR16EB20", 381, F_AVR8X, {0x1E, 0x94, 0x40}, // ID /*AVR16EB20*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB20*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14}, // Config, ISRs + /*AVR16EB20*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB20*/ 391, rgftab_avr16eb20}, // Register file //AVR16DD28 atdf, avrdude // Sources {"AVR16DD28", 331, F_AVR8X, {0x1E, 0x94, 0x32}, // ID /*AVR16DD28*/ 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR16DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR16DD28*/ 401, rgftab_avr32dd14}, // Register file //AVR16EA28 atdf, avrdude // Sources {"AVR16EA28", 332, F_AVR8X, {0x1E, 0x94, 0x37}, // ID /*AVR16EA28*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EA28*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR16EA28*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR16EA28*/ 402, rgftab_avr16ea28}, // Register file //AVR16EB28 atdf, avrdude // Sources {"AVR16EB28", 382, F_AVR8X, {0x1E, 0x94, 0x3F}, // ID /*AVR16EB28*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB28*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14}, // Config, ISRs + /*AVR16EB28*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB28*/ 391, rgftab_avr16eb20}, // Register file //AVR16DD32 atdf, avrdude // Sources {"AVR16DD32", 333, F_AVR8X, {0x1E, 0x94, 0x31}, // ID /*AVR16DD32*/ 0, 0x04000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR16DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR16DD32*/ 401, rgftab_avr32dd14}, // Register file //AVR16EA32 atdf, avrdude // Sources {"AVR16EA32", 334, F_AVR8X, {0x1E, 0x94, 0x36}, // ID /*AVR16EA32*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EA32*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR16EA32*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR16EA32*/ 402, rgftab_avr16ea28}, // Register file //AVR16EB32 atdf, avrdude // Sources {"AVR16EB32", 383, F_AVR8X, {0x1E, 0x94, 0x3E}, // ID /*AVR16EB32*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB32*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14}, // Config, ISRs + /*AVR16EB32*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB32*/ 391, rgftab_avr16eb20}, // Register file //AVR16EA48 atdf, avrdude // Sources {"AVR16EA48", 335, F_AVR8X, {0x1E, 0x94, 0x35}, // ID /*AVR16EA48*/ 0, 0x04000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR16EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR16EA48*/ 502, rgftab_avr64ea48}, // Register file //AVR32DD14 atdf, avrdude // Sources {"AVR32DD14", 336, F_AVR8X, {0x1E, 0x95, 0x3B}, // ID /*AVR32DD14*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD14*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR32DD14*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR32DD14*/ 401, rgftab_avr32dd14}, // Register file //AVR32DD20 atdf, avrdude // Sources {"AVR32DD20", 337, F_AVR8X, {0x1E, 0x95, 0x3A}, // ID /*AVR32DD20*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD20*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR32DD20*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR32DD20*/ 401, rgftab_avr32dd14}, // Register file //AVR32DA28 atdf, avrdude // Sources {"AVR32DA28", 338, F_AVR8X, {0x1E, 0x95, 0x34}, // ID /*AVR32DA28*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA28*/ 16, 4, 41, vtab_avr128da28, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR32DA28*/ 16, 4, 41, vtab_avr128da28, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR32DA28*/ 432, rgftab_avr32da28}, // Register file //AVR32DB28 atdf, avrdude // Sources {"AVR32DB28", 339, F_AVR8X, {0x1E, 0x95, 0x37}, // ID /*AVR32DB28*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR32DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR32DB28*/ 462, rgftab_avr32db28}, // Register file //AVR32DD28 atdf, avrdude // Sources {"AVR32DD28", 340, F_AVR8X, {0x1E, 0x95, 0x39}, // ID /*AVR32DD28*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR32DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR32DD28*/ 401, rgftab_avr32dd14}, // Register file //AVR32EA28 atdf, avrdude // Sources {"AVR32EA28", 341, F_AVR8X, {0x1E, 0x95, 0x3E}, // ID /*AVR32EA28*/ 0, 0x08000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem - /*AVR32EA28*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR32EA28*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR32EA28*/ 402, rgftab_avr16ea28}, // Register file //AVR32DA32 atdf, avrdude // Sources {"AVR32DA32", 342, F_AVR8X, {0x1E, 0x95, 0x33}, // ID /*AVR32DA32*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA32*/ 16, 4, 44, vtab_avr128da32, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR32DA32*/ 16, 4, 44, vtab_avr128da32, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR32DA32*/ 447, rgftab_avr32da32}, // Register file //AVR32DB32 atdf, avrdude // Sources {"AVR32DB32", 343, F_AVR8X, {0x1E, 0x95, 0x36}, // ID /*AVR32DB32*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR32DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR32DB32*/ 477, rgftab_avr32db32}, // Register file //AVR32DD32 atdf, avrdude // Sources {"AVR32DD32", 344, F_AVR8X, {0x1E, 0x95, 0x38}, // ID /*AVR32DD32*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR32DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR32DD32*/ 401, rgftab_avr32dd14}, // Register file //AVR32EA32 atdf, avrdude // Sources {"AVR32EA32", 345, F_AVR8X, {0x1E, 0x95, 0x3D}, // ID /*AVR32EA32*/ 0, 0x08000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem - /*AVR32EA32*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR32EA32*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR32EA32*/ 402, rgftab_avr16ea28}, // Register file //AVR32DA48 atdf, avrdude // Sources {"AVR32DA48", 346, F_AVR8X, {0x1E, 0x95, 0x32}, // ID /*AVR32DA48*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA48*/ 16, 4, 58, vtab_avr128da48, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR32DA48*/ 16, 4, 58, vtab_avr128da48, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR32DA48*/ 600, rgftab_avr32da48}, // Register file //AVR32DB48 atdf, avrdude // Sources {"AVR32DB48", 347, F_AVR8X, {0x1E, 0x95, 0x35}, // ID /*AVR32DB48*/ 0, 0x08000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR32DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR32DB48*/ 643, rgftab_avr32db48}, // Register file //AVR32EA48 atdf, avrdude // Sources {"AVR32EA48", 348, F_AVR8X, {0x1E, 0x95, 0x3C}, // ID /*AVR32EA48*/ 0, 0x08000, 0x040, 1, 0, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem - /*AVR32EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR32EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR32EA48*/ 502, rgftab_avr64ea48}, // Register file //AVR64DD14 atdf, avrdude // Sources {"AVR64DD14", 349, F_AVR8X, {0x1E, 0x96, 0x1D}, // ID /*AVR64DD14*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD14*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR64DD14*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR64DD14*/ 401, rgftab_avr32dd14}, // Register file //AVR64DD20 atdf, avrdude // Sources {"AVR64DD20", 350, F_AVR8X, {0x1E, 0x96, 0x1C}, // ID /*AVR64DD20*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD20*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR64DD20*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR64DD20*/ 401, rgftab_avr32dd14}, // Register file //AVR64DA28 atdf, avrdude // Sources {"AVR64DA28", 351, F_AVR8X, {0x1E, 0x96, 0x15}, // ID /*AVR64DA28*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA28*/ 16, 4, 41, vtab_avr128da28, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR64DA28*/ 16, 4, 41, vtab_avr128da28, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA28*/ 433, rgftab_avr64da28}, // Register file //AVR64DB28 atdf, avrdude // Sources {"AVR64DB28", 352, F_AVR8X, {0x1E, 0x96, 0x19}, // ID /*AVR64DB28*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR64DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB28*/ 462, rgftab_avr32db28}, // Register file //AVR64DD28 atdf, avrdude // Sources {"AVR64DD28", 353, F_AVR8X, {0x1E, 0x96, 0x1B}, // ID /*AVR64DD28*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR64DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR64DD28*/ 401, rgftab_avr32dd14}, // Register file //AVR64EA28 atdf, avrdude // Sources {"AVR64EA28", 354, F_AVR8X, {0x1E, 0x96, 0x20}, // ID /*AVR64EA28*/ 0, 0x10000, 0x080, 1, 0, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem - /*AVR64EA28*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR64EA28*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR64EA28*/ 402, rgftab_avr16ea28}, // Register file //AVR64DA32 atdf, avrdude // Sources {"AVR64DA32", 355, F_AVR8X, {0x1E, 0x96, 0x14}, // ID /*AVR64DA32*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA32*/ 16, 4, 44, vtab_avr128da32, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR64DA32*/ 16, 4, 44, vtab_avr128da32, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA32*/ 448, rgftab_avr64da32}, // Register file //AVR64DB32 atdf, avrdude // Sources {"AVR64DB32", 356, F_AVR8X, {0x1E, 0x96, 0x18}, // ID /*AVR64DB32*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR64DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB32*/ 477, rgftab_avr32db32}, // Register file //AVR64DD32 atdf, avrdude // Sources {"AVR64DD32", 357, F_AVR8X, {0x1E, 0x96, 0x1A}, // ID /*AVR64DD32*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14}, // Config, ISRs + /*AVR64DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config + /*AVR64DD32*/ 401, rgftab_avr32dd14}, // Register file //AVR64EA32 atdf, avrdude // Sources {"AVR64EA32", 358, F_AVR8X, {0x1E, 0x96, 0x1F}, // ID /*AVR64EA32*/ 0, 0x10000, 0x080, 1, 0, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem - /*AVR64EA32*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR64EA32*/ 16, 4, 37, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR64EA32*/ 402, rgftab_avr16ea28}, // Register file //AVR64DA48 atdf, avrdude // Sources {"AVR64DA48", 359, F_AVR8X, {0x1E, 0x96, 0x13}, // ID /*AVR64DA48*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA48*/ 16, 4, 58, vtab_avr128da48, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR64DA48*/ 16, 4, 58, vtab_avr128da48, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA48*/ 601, rgftab_avr64da48}, // Register file //AVR64DB48 atdf, avrdude // Sources {"AVR64DB48", 360, F_AVR8X, {0x1E, 0x96, 0x17}, // ID /*AVR64DB48*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR64DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB48*/ 643, rgftab_avr32db48}, // Register file //AVR64EA48 atdf, avrdude // Sources {"AVR64EA48", 361, F_AVR8X, {0x1E, 0x96, 0x1E}, // ID /*AVR64EA48*/ 0, 0x10000, 0x080, 1, 0, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem - /*AVR64EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48}, // Config, ISRs + /*AVR64EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48, // ISRs, Config + /*AVR64EA48*/ 502, rgftab_avr64ea48}, // Register file //AVR64DA64 atdf, avrdude // Sources {"AVR64DA64", 362, F_AVR8X, {0x1E, 0x96, 0x12}, // ID /*AVR64DA64*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA64*/ 16, 4, 64, vtab_avr128da64, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR64DA64*/ 16, 4, 64, vtab_avr128da64, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA64*/ 659, rgftab_avr64da64}, // Register file //AVR64DB64 atdf, avrdude // Sources {"AVR64DB64", 363, F_AVR8X, {0x1E, 0x96, 0x16}, // ID /*AVR64DB64*/ 0, 0x10000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB64*/ 16, 4, 65, vtab_avr128db64, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR64DB64*/ 16, 4, 65, vtab_avr128db64, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB64*/ 698, rgftab_avr64db64}, // Register file //AVR128DA28 atdf, avrdude // Sources {"AVR128DA28", 364, F_AVR8X, {0x1E, 0x97, 0x0A}, // ID /*AVR128DA28*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA28*/ 16, 4, 41, vtab_avr128da28, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR128DA28*/ 16, 4, 41, vtab_avr128da28, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA28*/ 433, rgftab_avr64da28}, // Register file //AVR128DB28 atdf, avrdude // Sources {"AVR128DB28", 365, F_AVR8X, {0x1E, 0x97, 0x0E}, // ID /*AVR128DB28*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR128DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB28*/ 462, rgftab_avr32db28}, // Register file //AVR128DA32 atdf, avrdude // Sources {"AVR128DA32", 366, F_AVR8X, {0x1E, 0x97, 0x09}, // ID /*AVR128DA32*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA32*/ 16, 4, 44, vtab_avr128da32, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR128DA32*/ 16, 4, 44, vtab_avr128da32, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA32*/ 448, rgftab_avr64da32}, // Register file //AVR128DB32 atdf, avrdude // Sources {"AVR128DB32", 367, F_AVR8X, {0x1E, 0x97, 0x0D}, // ID /*AVR128DB32*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR128DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB32*/ 477, rgftab_avr32db32}, // Register file //AVR128DA48 atdf, avrdude // Sources {"AVR128DA48", 368, F_AVR8X, {0x1E, 0x97, 0x08}, // ID /*AVR128DA48*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA48*/ 16, 4, 58, vtab_avr128da48, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR128DA48*/ 16, 4, 58, vtab_avr128da48, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA48*/ 601, rgftab_avr64da48}, // Register file //AVR128DB48 atdf, avrdude // Sources {"AVR128DB48", 369, F_AVR8X, {0x1E, 0x97, 0x0C}, // ID /*AVR128DB48*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR128DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB48*/ 643, rgftab_avr32db48}, // Register file //AVR128DA64 atdf, avrdude // Sources {"AVR128DA64", 370, F_AVR8X, {0x1E, 0x97, 0x07}, // ID /*AVR128DA64*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA64*/ 16, 4, 64, vtab_avr128da64, 15, cfgtab_avr32da28}, // Config, ISRs + /*AVR128DA64*/ 16, 4, 64, vtab_avr128da64, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA64*/ 659, rgftab_avr64da64}, // Register file //AVR128DB64 atdf, avrdude // Sources {"AVR128DB64", 371, F_AVR8X, {0x1E, 0x97, 0x0B}, // ID /*AVR128DB64*/ 0, 0x20000, 0x200, 1, 0, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB64*/ 16, 4, 65, vtab_avr128db64, 16, cfgtab_avr32db28}, // Config, ISRs + /*AVR128DB64*/ 16, 4, 65, vtab_avr128db64, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB64*/ 698, rgftab_avr64db64}, // Register file }; @@ -12513,3 +12897,38134 @@ const Configitem_t cfgtab_avr32db28[16] = { {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of pages]"}, {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, }; + + +// I/O Register files + +// ATmega328 ATmega328P +const Register_file_t rgftab_atmega328[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega16M1 ATmega32M1 +const Register_file_t rgftab_atmega16m1[136] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"psc.pocr0sa", 0x80, 2, 0x0fff, -1, "PSC module 0 output compare SA register (16 bits)"}, + {"psc.pocr0ra", 0x82, 2, 0x0fff, -1, "PSC module 0 output compare RA register (16 bits)"}, + {"psc.pocr0sb", 0x84, 2, 0x0fff, -1, "PSC module 0 output compare SB register (16 bits)"}, + {"psc.pocr1sa", 0x86, 2, 0x0fff, -1, "PSC module 1 output compare SA register (16 bits)"}, + {"psc.pocr1ra", 0x88, 2, 0x0fff, -1, "PSC module 1 output compare RA register (16 bits)"}, + {"psc.pocr1sb", 0x8a, 2, 0x0fff, -1, "PSC module 1 output compare SB register (16 bits)"}, + {"psc.pocr2sa", 0x8c, 2, 0x0fff, -1, "PSC module 2 output compare SA register (16 bits)"}, + {"psc.pocr2ra", 0x8e, 2, 0x0fff, -1, "PSC module 2 output compare RA register (16 bits)"}, + {"psc.pocr2sb", 0x90, 2, 0x0fff, -1, "PSC module 2 output compare SB register (16 bits)"}, + {"psc.pocr_rb", 0x92, 2, 0x0fff, -1, "PSC output compare RB register (16 bits)"}, + {"psc.psync", 0x94, 1, -1, -1, "PSC synchro configuration register"}, + {"psc.pcnf", 0x95, 1, -1, -1, "PSC configuration register"}, + {"psc.poc", 0x96, 1, -1, -1, "PSC output configuration register"}, + {"psc.pctl", 0x97, 1, -1, -1, "PSC control register"}, + {"psc.pmic0", 0x98, 1, -1, -1, "PSC module 0 input control register"}, + {"psc.pmic1", 0x99, 1, -1, -1, "PSC module 1 input control register"}, + {"psc.pmic2", 0x9a, 1, -1, -1, "PSC module 2 input control register"}, + {"psc.pim", 0x9b, 1, -1, -1, "PSC interrupt mask register"}, + {"psc.pifr", 0x9c, 1, -1, -1, "PSC interrupt flag register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// ATmega32HVBrevB ATmega16HVB ATmega16HVBrevB ATmega32HVB +const Register_file_t rgftab_atmega32hvbrevb[91] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0x0f, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0x0f, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0x0f, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x1f, -1, "port C input register"}, + {"portc.portc", 0x08, 1, 0x3f, -1, "port C data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.osicsr", 0x17, 1, -1, -1, "oscillator sampling interface control and status register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0x0f, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, + {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, + {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, + {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twbcsr", 0x9e, 1, -1, -1, "TWI bus control and status register"}, + {"voltage_regulator.rocr", 0xa8, 1, -1, -1, "regulator operating condition register"}, + {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, + {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, + {"bandgap.bgcsr", 0xb2, 1, -1, -1, "bandgap control and status register"}, + {"charger_detect.chgdcsr", 0xb4, 1, -1, -1, "charger detect control and status register"}, + {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadic", 0xc4, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, + {"coulomb_counter.cadcsra", 0xc6, 1, -1, -1, "CC-ADC control and status register A"}, + {"coulomb_counter.cadcsrb", 0xc7, 1, -1, -1, "CC-ADC control and status register B"}, + {"coulomb_counter.cadcsrc", 0xc8, 1, -1, -1, "CC-ADC control and status register C"}, + {"coulomb_counter.cadrcc", 0xc9, 1, 0xff, -1, "CC-ADC regular charge current register"}, + {"coulomb_counter.cadrdc", 0xca, 1, 0xff, -1, "CC-ADC regular discharge current register"}, + {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, + {"cell_balancing.cbcr", 0xd1, 1, -1, -1, "cell balancing control register"}, + {"battery_protection.bpimsk", 0xd2, 1, -1, -1, "battery protection interrupt mask register"}, + {"battery_protection.bpifr", 0xd3, 1, -1, -1, "battery protection interrupt flag register"}, + {"battery_protection.bpscd", 0xd5, 1, 0xff, -1, "battery protection short-circuit detection level register"}, + {"battery_protection.bpdocd", 0xd6, 1, 0xff, -1, "battery protection discharge-over-current detection level register"}, + {"battery_protection.bpcocd", 0xd7, 1, 0xff, -1, "battery protection charge-over-current detection level register"}, + {"battery_protection.bpdhcd", 0xd8, 1, 0xff, -1, "battery protection discharge-high-current detection level register"}, + {"battery_protection.bpchcd", 0xd9, 1, 0xff, -1, "battery protection charge-high-current detection level register"}, + {"battery_protection.bpsctr", 0xda, 1, 0x7f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpoctr", 0xdb, 1, 0x3f, -1, "battery protection over-current timing register"}, + {"battery_protection.bphctr", 0xdc, 1, 0x3f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpcr", 0xdd, 1, -1, -1, "battery protection control register"}, + {"battery_protection.bpplr", 0xde, 1, -1, -1, "battery protection parameter lock register"}, +}; + +// ATmega328PB +const Register_file_t rgftab_atmega328pb[123] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi0.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi0.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi0.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"ac.acsra", 0x30, 1, -1, -1, "analog comparator control and status register A"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cfd.xfdcsr", 0x42, 1, -1, -1, "XOSC failure detection control and status register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc4.tccr4a", 0x80, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x81, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x82, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x84, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x86, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x88, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x8a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"spi1.spcr1", 0x8c, 1, -1, -1, "SPI control register"}, + {"spi1.spsr1", 0x8d, 1, -1, -1, "SPI status register"}, + {"spi1.spdr1", 0x8e, 1, 0xff, -1, "SPI data register"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi0.twbr0", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi0.twsr0", 0x99, 1, -1, -1, "TWI status register"}, + {"twi0.twar0", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi0.twdr0", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi0.twcr0", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi0.twamr0", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"twi1.twbr1", 0xb8, 1, 0xff, -1, "TWI bit rate register"}, + {"twi1.twsr1", 0xb9, 1, -1, -1, "TWI status register"}, + {"twi1.twar1", 0xba, 1, -1, -1, "TWI peripheral address register"}, + {"twi1.twdr1", 0xbb, 1, 0xff, -1, "TWI data register"}, + {"twi1.twcr1", 0xbc, 1, -1, -1, "TWI control register"}, + {"twi1.twamr1", 0xbd, 1, -1, -1, "TWI peripheral address mask register"}, +}; + +// ATmega8515 +const Register_file_t rgftab_atmega8515[52] = { // I/O memory [0, 63] + 32 + {"cpu.osccal", 0x04, 1, 0xff, -1, "oscillator calibration register"}, + {"porte.pine", 0x05, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x06, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x07, 1, 0x07, -1, "port E data register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, + {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny102 ATtiny104 +const Register_file_t rgftab_attiny102[55] = { // I/O memory [0, 63] + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"usart.udr", 0x08, 1, 0xff, -1, "USART I/O data register"}, + {"usart.ubrr", 0x09, 2, 0x0fff, -1, "USART baud rate register (16 bits)"}, + {"usart.ucsrd", 0x0b, 1, -1, -1, "USART control and status register D"}, + {"usart.ucsrc", 0x0c, 1, -1, -1, "USART control and status register C"}, + {"usart.ucsrb", 0x0d, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0e, 1, -1, -1, "USART control and status register A"}, + {"exint.pcmsk0", 0x0f, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x10, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, + {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, + {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, + {"porta.portcr", 0x16, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x16, 1, -1, -1, "port control register"}, + {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.adcl", 0x19, 1, 0xff, -1, "ADC data register low byte"}, + {"adc.adch", 0x1a, 1, 0xff, -1, "ADC data register high byte"}, + {"adc.admux", 0x1b, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x1c, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x1d, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsrb", 0x1e, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x1f, 1, -1, -1, "analog comparator control and status register A"}, + {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, + {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, + {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, + {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, + {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, -1, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny28 +const Register_file_t rgftab_attiny28[20] = { // I/O memory [0, 63] + 32 + {"cpu.osccal", 0x00, 1, 0xff, -1, "oscillator calibration register"}, + {"watchdog.wdtcr", 0x01, 1, -1, -1, "watchdog timer control register"}, + {"modulator.modcr", 0x02, 1, -1, -1, "modulation control register"}, + {"timer_counter_0.tcnt0", 0x03, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.tccr0", 0x04, 1, -1, -1, "T/C 0 control register"}, + {"external_interrupt.ifr", 0x05, 1, -1, -1, "interrupt flag register"}, + {"timer_counter_0.ifr", 0x05, 1, -1, -1, "interrupt flag register"}, + {"cpu.icr", 0x06, 1, -1, -1, "interrupt control register"}, + {"external_interrupt.icr", 0x06, 1, -1, -1, "interrupt control register"}, + {"timer_counter_0.icr", 0x06, 1, -1, -1, "interrupt control register"}, + {"cpu.mcucs", 0x07, 1, -1, -1, "MCU control and status register"}, + {"analog_comparator.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"porta.pina", 0x19, 1, 0x0b, -1, "port A input register"}, + {"porta.pacr", 0x1a, 1, 0x0f, -1, "port A control register"}, + {"porta.porta", 0x1b, 1, 0x0f, -1, "port A data register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny441 ATtiny841 +const Register_file_t rgftab_attiny441[101] = { // I/O memory [0, 223] + 32 + {"adc.adcsrb", 0x04, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x05, 1, -1, -1, "ADC control and status register A"}, + {"adc.adc", 0x06, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.admuxb", 0x08, 1, -1, -1, "ADC multiplexer selection register B"}, + {"adc.admuxa", 0x09, 1, -1, -1, "ADC multiplexer selection register A"}, + {"ac.acsr0a", 0x0a, 1, -1, -1, "analog comparator 0 control and status register A"}, + {"ac.acsr0b", 0x0b, 1, -1, -1, "analog comparator 0 control and status register B"}, + {"ac.acsr1a", 0x0c, 1, -1, -1, "analog comparator 1 control and status register A"}, + {"ac.acsr1b", 0x0d, 1, -1, -1, "analog comparator 1 control and status register B"}, + {"tc1.tifr1", 0x0e, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.tifr2", 0x10, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc2.timsk2", 0x11, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"adc.didr0", 0x40, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x41, 1, -1, -1, "digital input disable register 1"}, + {"portb.pueb", 0x42, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"porta.puea", 0x43, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"porta.portcr", 0x44, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x44, 1, -1, -1, "port control register"}, + {"spi.remap", 0x45, 1, -1, -1, "remap port pins register"}, + {"usart0.remap", 0x45, 1, -1, -1, "remap port pins register"}, + {"tocpm.tocpmcoe", 0x46, 1, -1, -1, "timer output compare pin mux channel output enable register"}, + {"tocpm.tocpmsa0", 0x47, 1, -1, -1, "timer output compare pin mux selection 0 register"}, + {"tocpm.tocpmsa1", 0x48, 1, -1, -1, "timer output compare pin mux selection 1 register"}, + {"porta.phde", 0x4a, 1, -1, -1, "port high drive enable register"}, + {"cpu.prr", 0x50, 1, -1, -1, "power reduction register"}, + {"cpu.ccp", 0x51, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.clkcr", 0x52, 1, -1, -1, "clock control register"}, + {"cpu.clkpr", 0x53, 1, -1, -1, "clock prescaler register"}, + {"cpu.osccal0", 0x54, 1, 0xff, -1, "oscillator calibration register 8 MHz"}, + {"cpu.osctcal0a", 0x55, 1, 0xff, -1, "oscillator temperature calibration register A"}, + {"cpu.osctcal0b", 0x56, 1, 0xff, -1, "oscillator temperature calibration register B"}, + {"cpu.osccal1", 0x57, 1, 0x03, -1, "oscillator calibration register 32 kHz"}, + {"usart0.udr0", 0x60, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart0.ubrr0", 0x61, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.ucsr0d", 0x63, 1, -1, -1, "USART control and status register D"}, + {"usart0.ucsr0c", 0x64, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0b", 0x65, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x66, 1, -1, -1, "USART 0 control and status register A"}, + {"usart1.udr1", 0x70, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ubrr1", 0x71, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.ucsr1d", 0x73, 1, -1, -1, "USART control and status register D"}, + {"usart1.ucsr1c", 0x74, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1b", 0x75, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x76, 1, -1, -1, "USART 1 control and status register A"}, + {"twi.twsd", 0x80, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x81, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x82, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x83, 1, -1, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x84, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x85, 1, -1, -1, "TWI peripheral control register A"}, + {"spi.spdr", 0x90, 1, 0xff, -1, "SPI data register"}, + {"spi.spsr", 0x91, 1, -1, -1, "SPI status register"}, + {"spi.spcr", 0x92, 1, -1, -1, "SPI control register"}, + {"tc2.icr2", 0xa0, 2, 0xffff, -1, "T/C 2 input capture register (16 bits)"}, + {"tc2.ocr2b", 0xa2, 2, 0xffff, -1, "T/C 2 output compare register B (16 bits)"}, + {"tc2.ocr2a", 0xa4, 2, 0xffff, -1, "T/C 2 output compare register A (16 bits)"}, + {"tc2.tcnt2", 0xa6, 2, 0xffff, -1, "timer/counter 2 (16 bits)"}, + {"tc2.tccr2c", 0xa8, 1, -1, -1, "T/C 2 control register C"}, + {"tc2.tccr2b", 0xa9, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tccr2a", 0xaa, 1, -1, -1, "T/C 2 control register A"}, +}; + +// AT90PWM81 +const Register_file_t rgftab_at90pwm81[84] = { // I/O memory [0, 223] + 32 + {"ac.acsr", 0x00, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.timsk1", 0x01, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc1.tifr1", 0x02, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x07, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x08, 1, -1, -1, "ADC multiplexer selection register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"psc0.pim0", 0x0f, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc0.pifr0", 0x10, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pcnf0", 0x11, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0x12, 1, -1, -1, "PSC 0 control register"}, + {"psc2.pim2", 0x13, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"psc2.pifr2", 0x14, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pcnf2", 0x15, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0x16, 1, -1, -1, "PSC 2 control register"}, + {"spi.spcr", 0x17, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x18, 1, -1, -1, "SPI status register"}, + {"cpu.gpior0", 0x19, 1, -1, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x1a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1b, 1, -1, -1, "general purpose I/O register 2"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, -1, -1, "EEPROM address register (16 bits)"}, + {"exint.eifr", 0x20, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x21, 1, -1, -1, "external interrupt mask register"}, + {"psc0.ocr0sb", 0x22, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0x24, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc2.ocr2sb", 0x26, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0x28, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc0.ocr0ra", 0x2a, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"adc.adc", 0x2c, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"psc2.ocr2ra", 0x2e, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"spi.spdr", 0x36, 1, -1, -1, "SPI data register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"dac.dac", 0x38, 2, 0xffff, -1, "DAC data register (16 bits)"}, + {"tc1.tcnt1", 0x3a, 2, -1, -1, "timer/counter 1 (16 bits)"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"psc0.ocr0sa", 0x40, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.pfrc0a", 0x42, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0x43, 1, -1, -1, "PSC 0 input B control register"}, + {"psc2.ocr2sa", 0x44, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.pfrc2a", 0x46, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0x47, 1, -1, -1, "PSC 2 input B control register"}, + {"psc0.picr0", 0x48, 2, -1, -1, "PSC 0 input capture register (16 bits)"}, + {"psc0.psoc0", 0x4a, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc2.picr2", 0x4c, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, + {"psc2.psoc2", 0x4e, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0x4f, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.pcnfe2", 0x50, 1, -1, -1, "PSC 2 enhanced configuration register"}, + {"psc2.pasdly2", 0x51, 1, -1, -1, "analog synchronization delay register"}, + {"dac.dacon", 0x56, 1, -1, -1, "DAC control register"}, + {"adc.didr0", 0x57, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x58, 1, -1, -1, "digital input disable register 1"}, + {"adc.amp0csr", 0x59, 1, -1, -1, "amplifier 0 control and status register"}, + {"ac.ac1econ", 0x5a, 1, -1, -1, "analog comparator 1 extended control register"}, + {"ac.ac2econ", 0x5b, 1, -1, -1, "analog comparator 2 extended control register"}, + {"ac.ac3econ", 0x5c, 1, -1, -1, "analog comparator 3 extended control register"}, + {"ac.ac1con", 0x5d, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x5e, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x5f, 1, -1, -1, "analog comparator 3 control register"}, + {"cpu.bgcrr", 0x60, 1, -1, -1, "bandgap resistor calibration register"}, + {"cpu.bgccr", 0x61, 1, -1, -1, "bandgap current calibration register"}, + {"wdt.wdtcsr", 0x62, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x63, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x64, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x65, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x66, 1, -1, -1, "power reduction register"}, + {"cpu.pllcsr", 0x67, 1, -1, -1, "PLL control and status register"}, + {"cpu.osccal", 0x68, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x69, 1, -1, -1, "external interrupt control register A"}, + {"tc1.tccr1b", 0x6a, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.icr1", 0x6c, 2, -1, -1, "T/C 1 input capture register (16 bits)"}, +}; + +// AT90CAN128 AT90CAN32 AT90CAN64 +const Register_file_t rgftab_at90can128[137] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, 0xff, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x7f, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, 0xff, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x7f, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, 0xff, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x7f, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, -1, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, -1, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, 0xff, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, -1, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, -1, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, -1, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, -1, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// AT90USB162 AT90USB82 +const Register_file_t rgftab_at90usb162[92] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, -1, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, -1, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"wdt.wdtckd", 0x42, 1, -1, -1, "watchdog timer clock divider register"}, + {"usb_device.regcr", 0x43, 1, -1, -1, "regulator control register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"cpu.clksel0", 0xb0, 1, -1, -1, "clock selection register 0"}, + {"cpu.clksel1", 0xb1, 1, -1, -1, "clock selection register 1"}, + {"cpu.clksta", 0xb2, 1, -1, -1, "clock status register"}, + {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.ueint", 0xd4, 1, 0x1f, -1, "USB endpoint number interrupt register"}, + {"ps2.ps2con", 0xda, 1, -1, -1, "PS 2 pad enable register"}, + {"ps2.upoe", 0xdb, 1, -1, -1, "USB software output enable register"}, +}; + +// ATA5700M322 +const Register_file_t rgftab_ata5700m322[337] = { // I/O memory [0, 479] + 32 + {"gpioregs_dvcc.gpior0", 0x000, 1, 0xff, -1, "general purpose I/O register 0"}, + {"clk.prr1", 0x001, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x002, 1, -1, -1, "power reduction register 2"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0x07, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0x07, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0x07, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"lf_transponder.tpcr2", 0x00c, 1, -1, -1, "transponder control register 2"}, + {"lf_transponder.tpfr", 0x00d, 1, -1, -1, "transponder flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"lf_timer.ltcmr", 0x015, 1, -1, -1, "LF timer control mode register"}, + {"eeprom.eecr2", 0x016, 1, -1, -1, "EEPROM control register 2"}, + {"lf_protocol_handler.phtcr", 0x017, 1, -1, -1, "PH telegram configuration register"}, + {"lf_fifo.ldffl", 0x018, 1, -1, -1, "LF data FIFO fill level register"}, + {"lf_fifo.ldfd", 0x019, 1, 0xff, -1, "LF data FIFO data register"}, + {"clk.prr0", 0x01a, 1, -1, -1, "power reduction register 0"}, + {"lf_protocol_handler.phfr", 0x01b, 1, -1, -1, "protocol handler flag register"}, + {"lf_receiver.lffr", 0x01c, 1, -1, -1, "LF flag register"}, + {"aes.aescr", 0x01d, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x01e, 1, -1, -1, "AES status register"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs_dvcc.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs_dvcc.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"lf_fifo.ldfcksw", 0x029, 1, -1, -1, "LF data FIFO clock switch register"}, + {"sup.vmscr", 0x02a, 1, -1, -1, "voltage monitor status and control register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"lf_receiver.lfcr0", 0x02f, 1, -1, -1, "LF receiver control register 0"}, + {"lf_receiver.lfcr1", 0x030, 1, -1, -1, "LF receiver control register 1"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"timer0_wdt.t0ifr", 0x032, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.smcr", 0x038, 1, -1, -1, "sleep mode control register"}, + {"lf_transponder.tpsr", 0x039, 1, -1, -1, "transponder status register"}, + {"lf_receiver.lfcr2", 0x03a, 1, -1, -1, "LF receiver control register 2"}, + {"lf_receiver.lfcr3", 0x03b, 1, -1, -1, "LF receiver control register 3"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5temp", 0x069, 1, 0xff, -1, "timer 5 temp register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"tplf_cal.lfcalr1", 0x070, 1, -1, -1, "LF receiver calibration register 1"}, + {"tplf_cal.lfcalr2", 0x071, 1, -1, -1, "LF receiver calibration register 2"}, + {"tplf_cal.lfcalr3", 0x072, 1, -1, -1, "LF receiver calibration register 3"}, + {"tplf_cal.lfcalr4", 0x073, 1, -1, -1, "LF receiver calibration register 4"}, + {"tplf_cal.lfcalr5", 0x074, 1, -1, -1, "LF receiver calibration register 5"}, + {"tplf_cal.lfcalr6", 0x075, 1, -1, -1, "LF receiver calibration register 6"}, + {"tplf_cal.lfcalr7", 0x076, 1, 0xff, -1, "LF receiver calibration register 7"}, + {"tplf_cal.lfcalr8", 0x077, 1, 0x1f, -1, "LF receiver calibration register 8"}, + {"tplf_cal.lfcalr9", 0x078, 1, 0xff, -1, "LF receiver calibration register 9"}, + {"tplf_cal.lfcalr10", 0x079, 1, 0x7f, -1, "LF receiver calibration register 10"}, + {"tplf_cal.lfcalr11", 0x07a, 1, 0xff, -1, "LF receiver calibration register 11"}, + {"tplf_cal.lfcalr12", 0x07b, 1, 0xff, -1, "LF receiver calibration register 12"}, + {"tplf_cal.lfcalr13", 0x07c, 1, 0xff, -1, "LF receiver calibration register 13"}, + {"tplf_cal.lfcalr14", 0x07d, 1, 0x7f, -1, "LF receiver calibration register 14"}, + {"tplf_cal.lfcalr15", 0x07e, 1, 0xff, -1, "LF receiver calibration register 15"}, + {"tplf_cal.lfcalr16", 0x07f, 1, 0x1f, -1, "LF receiver calibration register 16"}, + {"tplf_cal.lfcalr17", 0x080, 1, 0x1f, -1, "LF receiver calibration register 17"}, + {"tplf_cal.lfcalr18", 0x081, 1, 0xff, -1, "LF receiver calibration register 18"}, + {"tplf_cal.lfcalr19", 0x082, 1, 0x7f, -1, "LF receiver calibration register 19"}, + {"tplf_cal.lfcalr20", 0x083, 1, 0xff, -1, "LF receiver calibration register 20"}, + {"tplf_cal.lfcalr21", 0x084, 1, 0xff, -1, "LF receiver calibration register 21"}, + {"tplf_cal.lfcalr22", 0x085, 1, 0xff, -1, "LF receiver calibration register 22"}, + {"tplf_cal.lfcalr23", 0x086, 1, 0x7f, -1, "LF receiver calibration register 23"}, + {"tplf_cal.lfcalr24", 0x087, 1, 0xff, -1, "LF receiver calibration register 24"}, + {"tplf_cal.lfcalr25", 0x088, 1, 0x1f, -1, "LF receiver calibration register 25"}, + {"tplf_cal.lfcalr26", 0x089, 1, 0x1f, -1, "LF receiver calibration register 26"}, + {"tplf_cal.lfcalr27", 0x08a, 1, 0xff, -1, "LF receiver calibration register 27"}, + {"tplf_cal.lfcalr28", 0x08b, 1, 0x7f, -1, "LF receiver calibration register 28"}, + {"tplf_cal.lfcalr29", 0x08c, 1, 0xff, -1, "LF receiver calibration register 29"}, + {"tplf_cal.lfcalr30", 0x08d, 1, 0xff, -1, "LF receiver calibration register 30"}, + {"tplf_cal.lfcalr31", 0x08e, 1, 0xff, -1, "LF receiver calibration register 31"}, + {"tplf_cal.lfcalr32", 0x08f, 1, 0x7f, -1, "LF receiver calibration register 32"}, + {"tplf_cal.lfcalr33", 0x090, 1, 0xff, -1, "LF receiver calibration register 33"}, + {"tplf_cal.lfcalr34", 0x091, 1, 0x1f, -1, "LF receiver calibration register 34"}, + {"tplf_cal.lfcalr35", 0x092, 1, 0xff, -1, "LF receiver calibration register 35"}, + {"tplf_cal.lfcalr36", 0x093, 1, 0x7f, -1, "LF receiver calibration register 36"}, + {"tplf_cal.lfcalr37", 0x094, 1, 0x3f, -1, "LF receiver calibration register 37"}, + {"tplf_cal.lfcalr38", 0x095, 1, 0x0f, -1, "LF receiver calibration register 38"}, + {"tplf_cal.lfcalr39", 0x096, 1, 0x0f, -1, "LF receiver calibration register 39"}, + {"tplf_cal.lfcalr40", 0x097, 1, 0x0f, -1, "LF receiver calibration register 40"}, + {"tplf_cal.lfcalr41", 0x098, 1, 0xff, -1, "LF receiver calibration register 41"}, + {"tplf_cal.lfcalr42", 0x099, 1, 0xff, -1, "LF receiver calibration register 42"}, + {"tplf_cal.lfcalr43", 0x09a, 1, 0xff, -1, "LF receiver calibration register 43"}, + {"tplf_cal.lfcalr44", 0x09b, 1, 0x3f, -1, "LF receiver calibration register 44"}, + {"tplf_cal.lfcalr45", 0x09c, 1, 0xff, -1, "LF receiver calibration register 45"}, + {"tplf_cal.lfcalr46", 0x09d, 1, 0xff, -1, "LF receiver calibration register 46"}, + {"tplf_cal.lfcalr47", 0x09e, 1, 0xff, -1, "LF receiver calibration register 47"}, + {"tplf_cal.lfcalr48", 0x09f, 1, 0x3f, -1, "LF receiver calibration register 48"}, + {"tplf_cal.lfcalr49", 0x0a0, 1, 0xff, -1, "LF receiver calibration register 49"}, + {"tplf_cal.lfcalr50", 0x0a1, 1, 0xff, -1, "LF receiver calibration register 50"}, + {"tplf_cal.lfcalr51", 0x0a2, 1, 0xff, -1, "LF receiver calibration register 51"}, + {"tplf_cal.lfcalr52", 0x0a3, 1, 0x3f, -1, "LF receiver calibration register 52"}, + {"tplf_cal.lfcalr53", 0x0a4, 1, 0xff, -1, "LF receiver calibration register 53"}, + {"clk.xfuse", 0x0a5, 1, -1, -1, "XFUSE register"}, + {"clk.mrccal", 0x0a6, 1, 0xfe, -1, "middle RC oscillator calibration register"}, + {"clk.frccal", 0x0a7, 1, 0x1f, -1, "fast RC oscillator calibration register"}, + {"sup.rctcal", 0x0a8, 1, -1, -1, "RC oscillator temperature compensation register"}, + {"clk.cmsr", 0x0a9, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0aa, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0ab, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0ac, 1, -1, -1, "supply control register"}, + {"sup.supca1", 0x0ad, 1, -1, -1, "supply calibration register 1"}, + {"sup.supca2", 0x0ae, 1, -1, -1, "supply calibration register 2"}, + {"sup.supca3", 0x0af, 1, -1, -1, "supply calibration register 3"}, + {"sup.supca4", 0x0b0, 1, -1, -1, "supply calibration register 4"}, + {"sup.calrdy", 0x0b1, 1, 0xff, -1, "calibration ready signature register"}, + {"dfifo.dfs", 0x0b2, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dfl", 0x0b5, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0b6, 1, 0x3f, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0b7, 1, 0x3f, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0b8, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0b9, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0ba, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0bb, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0bc, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0bd, 1, 0x1f, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0be, 1, 0x1f, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0bf, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0c0, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0c1, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0c2, 1, -1, -1, "sequencer state machine control register"}, + {"timer5.gtccr", 0x0c3, 1, -1, -1, "general T/C control register"}, + {"ssm.ssmfbr", 0x0c4, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0c5, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0c6, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0c7, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0c8, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0c9, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0ca, 1, -1, -1, "sequencer state machine state register"}, + {"vx_mode.vxmctrl", 0x0cb, 1, -1, -1, "VX mode control register"}, + {"ssm.msmcr1", 0x0cc, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0cd, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0ce, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0cf, 1, -1, -1, "master state machine control register 4"}, + {"spi2.sp2cr", 0x0d7, 1, -1, -1, "SPI 2 control register"}, + {"spi2.sp2dr", 0x0d8, 1, 0xff, -1, "SPI 2 data register"}, + {"spi2.sp2sr", 0x0d9, 1, -1, -1, "SPI 2 status register"}, + {"debug.trcid", 0x0dc, 2, 0xffff, -1, "trace ID register (16 bits)"}, + {"debug.trcdr", 0x0df, 1, 0xff, -1, "trace unit data register"}, + {"clk.clkod", 0x0f5, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0f6, 1, -1, -1, "clock output control register"}, + {"lf_receiver.lfdsr1", 0x110, 1, -1, -1, "LF decoder setting register 1"}, + {"lf_receiver.lfdsr2", 0x111, 1, -1, -1, "LF decoder setting register 2"}, + {"lf_receiver.lfdsr3", 0x112, 1, -1, -1, "LF decoder setting register 3"}, + {"lf_receiver.lfdsr4", 0x113, 1, -1, -1, "LF decoder setting register 4"}, + {"lf_receiver.lfdsr5", 0x114, 1, -1, -1, "LF decoder setting register 5"}, + {"lf_receiver.lfdsr6", 0x115, 1, -1, -1, "LF decoder setting register 6"}, + {"lf_receiver.lfdsr7", 0x116, 1, -1, -1, "LF decoder setting register 7"}, + {"lf_receiver.lfdsr8", 0x117, 1, -1, -1, "LF decoder setting register 8"}, + {"lf_receiver.lfdsr9", 0x118, 1, -1, -1, "LF decoder setting register 9"}, + {"lf_receiver.lfdsr10", 0x119, 1, -1, -1, "LF decoder setting register 10"}, + {"lf_receiver.lfdsr11", 0x11a, 1, -1, -1, "LF decoder setting register 11"}, + {"eeprom.eepr1", 0x11b, 1, -1, -1, "EEPROM protection register 1"}, + {"eeprom.eepr2", 0x11c, 1, -1, -1, "EEPROM protection register 2"}, + {"eeprom.eepr3", 0x11d, 1, -1, -1, "EEPROM protection register 3"}, + {"crc.crccr", 0x125, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x126, 1, 0xff, -1, "CRC data output register"}, + {"lf_receiver.lfsrctm", 0x131, 1, -1, -1, "LF receiver SRC tuning MSB register"}, + {"debounce.dbcr", 0x132, 1, -1, -1, "debounce control register"}, + {"debounce.dbtc", 0x133, 1, 0xff, -1, "debounce timer compare register"}, + {"debounce.dbenb", 0x134, 1, 0xff, -1, "debounce enable port B register"}, + {"debounce.dbenc", 0x135, 1, 0x07, -1, "debounce enable port C register"}, + {"debug.dbgsw", 0x136, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x137, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x138, 1, -1, -1, "SPI FIFO interrupt register"}, + {"timer2.t2ifr", 0x139, 1, -1, -1, "timer 2 interrupt flag register"}, + {"mem.pgmst", 0x13a, 1, -1, -1, "program memory status register"}, + {"mem.eest", 0x13b, 1, -1, -1, "EEPROM status register"}, + {"lf_receiver.lfsrctl", 0x13c, 1, -1, -1, "LF receiver SRC tuning LSB register"}, + {"int.pcifr", 0x141, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x142, 1, -1, -1, "timer 0 control register"}, + {"debounce.dbend", 0x144, 1, 0xff, -1, "debounce enable port D register"}, + {"lf_transponder.tpcr1", 0x145, 1, -1, -1, "transponder control register 1"}, + {"lf_transponder.tpimr", 0x146, 1, -1, -1, "transponder interrupt mask register"}, + {"lf_transponder.tpdcr1", 0x147, 1, -1, -1, "transponder decoder comparator register 1"}, + {"lf_transponder.tpdcr2", 0x148, 1, -1, -1, "transponder decoder comparator register 2"}, + {"lf_transponder.tpdcr3", 0x149, 1, -1, -1, "transponder decoder comparator register 3"}, + {"lf_transponder.tpdcr4", 0x14a, 1, -1, -1, "transponder decoder comparator register 4"}, + {"lf_transponder.tpdcr5", 0x14b, 1, -1, -1, "transponder decoder comparator register 5"}, + {"lf_transponder.tpecr1", 0x14c, 1, -1, -1, "transponder encoder comparator register 1"}, + {"lf_transponder.tpecr2", 0x14d, 1, -1, -1, "transponder encoder comparator register 2"}, + {"lf_transponder.tpecr3", 0x14e, 1, -1, -1, "transponder encoder comparator register 3"}, + {"lf_transponder.tpecr4", 0x14f, 1, -1, -1, "transponder encoder comparator register 4"}, + {"lf_transponder.tpecmr", 0x150, 1, -1, -1, "transponder encoder mode register"}, + {"lf_transponder.tpcr3", 0x151, 1, -1, -1, "transponder control register 3"}, + {"lf_transponder.tpcr4", 0x152, 1, -1, -1, "transponder control register 4"}, + {"lf_transponder.tpcr5", 0x153, 1, -1, -1, "transponder control register 5"}, + {"tplf_cal.tpcalr1", 0x155, 1, -1, -1, "transponder calibration register 1"}, + {"tplf_cal.tpcalr2", 0x156, 1, -1, -1, "transponder calibration register 2"}, + {"tplf_cal.tpcalr3", 0x157, 1, -1, -1, "transponder calibration register 3"}, + {"tplf_cal.tpcalr4", 0x158, 1, -1, -1, "transponder calibration register 4"}, + {"tplf_cal.tpcalr5", 0x159, 1, 0x0f, -1, "transponder calibration register 5"}, + {"tplf_cal.tpcalr6", 0x15a, 1, 0x1f, -1, "transponder calibration register 6"}, + {"tplf_cal.tpcalr7", 0x15b, 1, 0x07, -1, "transponder calibration register 7"}, + {"tplf_cal.tpcalr8", 0x15c, 1, 0x7f, -1, "transponder calibration register 8"}, + {"tplf_cal.tpcalr9", 0x15d, 1, 0xff, -1, "transponder calibration register 9"}, + {"tplf_cal.tpcalr10", 0x15e, 1, 0x7f, -1, "transponder calibration register 10"}, + {"aes.aesdpr", 0x15f, 1, 0x0f, -1, "AES data pointer register"}, + {"aes.aeskr", 0x160, 1, 0xff, -1, "AES key register"}, + {"aes.aesdr", 0x161, 1, 0xff, -1, "AES data register"}, + {"gpioregs_lfvcc.gpior3", 0x162, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs_lfvcc.gpior4", 0x163, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs_lfvcc.gpior5", 0x164, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs_lfvcc.gpior6", 0x165, 1, 0xff, -1, "general purpose I/O register 6"}, + {"gpioregs_lfvcc.gpior7", 0x166, 1, 0xff, -1, "general purpose I/O register 7"}, + {"gpioregs_lfvcc.gpior8", 0x167, 1, 0xff, -1, "general purpose I/O register 8"}, + {"lf_protocol_handler.phbcrr", 0x168, 1, 0xff, -1, "protocol handler bit counter read register"}, + {"tplf_cal.lfcpr", 0x16e, 1, -1, -1, "LF receiver calibration protect register"}, + {"lf_receiver.lfimr", 0x16f, 1, -1, -1, "LF interrupt mask register"}, + {"lf_protocol_handler.phid0", 0x170, 4, 0xffffffff, -1, "PH ID 0 register (32 bits)"}, + {"lf_protocol_handler.phid0l", 0x174, 1, 0x3f, -1, "PH identifier 0 length register"}, + {"lf_protocol_handler.phid1", 0x175, 4, 0xffffffff, -1, "PH ID 1 register (32 bits)"}, + {"lf_protocol_handler.phid1l", 0x179, 1, 0x3f, -1, "PH identifier 1 length register"}, + {"lf_protocol_handler.phidfr", 0x17a, 1, 0xff, -1, "protocol handler ID frame register"}, + {"lf_receiver.lfsysy", 0x17b, 4, 0xffffffff, -1, "LF receiver synchronization symbols register (32 bits)"}, + {"lf_receiver.lfsyle", 0x17f, 1, -1, -1, "LF receiver synchronization length register"}, + {"lf_receiver.lfstop", 0x180, 1, -1, -1, "LF receiver stop bit register"}, + {"lf_timer.ltcor", 0x181, 1, 0xff, -1, "LF timer compare register"}, + {"timer1.t1ifr", 0x182, 1, -1, -1, "timer 1 interrupt flag register"}, + {"lf_protocol_handler.phtblr", 0x184, 1, 0xff, -1, "protocol handler telegram bit length register"}, + {"lf_protocol_handler.phdfr", 0x185, 1, 0xff, -1, "protocol handler data frame end register"}, + {"lf_timer.ltemr", 0x186, 1, -1, -1, "LF timer event mask register"}, + {"lf_receiver.lfqc3", 0x187, 1, -1, -1, "LF receiver channel 3 quality factor register"}, + {"lf_receiver.lfqc2", 0x188, 1, -1, -1, "LF receiver channel 2 quality factor register"}, + {"lf_receiver.lfqc1", 0x189, 1, -1, -1, "LF receiver channel 1 quality factor register"}, + {"twi2.tw2br", 0x18a, 1, 0xff, -1, "TWI 2 bit rate register"}, + {"twi2.tw2cr", 0x18b, 1, -1, -1, "TWI 2 control register"}, + {"twi2.tw2sr", 0x18c, 1, -1, -1, "TWI 2 status register"}, + {"twi2.tw2dr", 0x18d, 1, 0xff, -1, "TWI 2 data register"}, + {"twi2.tw2ar", 0x18e, 1, -1, -1, "TWI 2 peripheral address register"}, + {"twi2.tw2amr", 0x18f, 1, -1, -1, "TWI 2 address mask register"}, + {"lf_rssi.rscr", 0x190, 1, -1, -1, "RSSI control register"}, + {"lf_rssi.rssr", 0x191, 1, -1, -1, "RSSI status register"}, + {"lf_rssi.rsms1r", 0x192, 1, -1, -1, "RSSI measurement setting 1 register"}, + {"lf_rssi.rsms2r", 0x193, 1, -1, -1, "RSSI measurement setting 2 register"}, + {"lf_rssi.rsfr", 0x194, 1, -1, -1, "RSSI flag register"}, + {"lf_rssi.rscalib", 0x196, 1, -1, -1, "RSSI calibration register"}, + {"lf_rssi.rsdlyr", 0x197, 1, -1, -1, "RSSI delay register"}, + {"lf_rssi.rsres1l", 0x198, 1, -1, -1, "RSSI result 1 low byte register"}, + {"lf_rssi.rsres1h", 0x199, 1, -1, -1, "RSSI result 1 high byte register"}, + {"lf_rssi.rsres2l", 0x19a, 1, -1, -1, "RSSI result 2 low byte register"}, + {"lf_rssi.rsres2h", 0x19b, 1, -1, -1, "RSSI result 2 high byte register"}, + {"lf_rssi.rsres3l", 0x19c, 1, -1, -1, "RSSI result 3 low byte register"}, + {"lf_rssi.rsres3h", 0x19d, 1, -1, -1, "RSSI result 3 high byte register"}, + {"lf_rssi.rsres4l", 0x19e, 1, -1, -1, "RSSI result 4 low byte register"}, + {"lf_rssi.rsres4h", 0x19f, 1, -1, -1, "RSSI result 4 high byte register"}, + {"lf_rssi.rssrcr", 0x1a0, 1, -1, -1, "RSSI SRC calibration register"}, + {"lf_rssi.sd12rr", 0x1a1, 1, -1, -1, "sign detection channel 1 vs 2 result register"}, + {"lf_rssi.sd13rr", 0x1a2, 1, -1, -1, "sign detection channel 1 vs 3 result register"}, + {"lf_rssi.sd23rr", 0x1a3, 1, -1, -1, "sign detection channel 2 vs 3 result register"}, + {"lf_rssi.sd360r", 0x1a4, 1, -1, -1, "sign detection 360 degree result register"}, + {"lf_rssi.rsdbgr", 0x1a5, 1, -1, -1, "RSSI debug register"}, + {"lf_fifo.ldfs", 0x1b1, 1, -1, -1, "LF data FIFO status register"}, + {"timer4.t4ifr", 0x1b2, 1, -1, -1, "timer 4 interrupt flag register"}, + {"lf_fifo.ldfwp", 0x1b3, 1, -1, -1, "LF data FIFO write pointer register"}, + {"lf_fifo.ldfrp", 0x1b4, 1, -1, -1, "LF data FIFO read pointer register"}, + {"timer5.t5ifr", 0x1b5, 1, -1, -1, "timer 5 interrupt flag register"}, + {"lf_fifo.ldfim", 0x1b6, 1, -1, -1, "LF data FIFO interrupt mask register"}, + {"lf_fifo.ldfc", 0x1b7, 1, -1, -1, "LF data FIFO configuration register"}, + {"lf_protocol_handler.phimr", 0x1b8, 1, -1, -1, "protocol handler interrupt mask register"}, + {"lf_protocol_handler.phcrcr", 0x1b9, 1, -1, -1, "protocol handler CRC control register"}, + {"lf_protocol_handler.phcst", 0x1ba, 2, 0xffff, -1, "PH CRC start value register (16 bits)"}, + {"lf_protocol_handler.phcrp", 0x1bc, 2, 0xffff, -1, "PH CRC polynomial register (16 bits)"}, + {"lf_protocol_handler.phcsr", 0x1be, 2, 0xffff, -1, "PH CRC checksum register (16 bits)"}, + {"crc.crcdir", 0x1c0, 1, 0xff, -1, "CRC data input register"}, + {"timer3.t3ifr", 0x1c1, 1, -1, -1, "timer 3 interrupt flag register"}, + {"cpu.cmcr", 0x1c3, 1, -1, -1, "clock management control register"}, + {"cpu.cmimr", 0x1c4, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clpr", 0x1c5, 1, -1, -1, "clock prescaler register"}, + {"sup.vmcr", 0x1c6, 1, -1, -1, "voltage monitor control register"}, + {"debug.dbondr", 0x1c7, 1, -1, -1, "downbond test register"}, + {"sup.calrdylf", 0x1c8, 1, 0xff, -1, "calibration ready signature LFVCC register"}, + {"twi1.tw1br", 0x1c9, 1, 0xff, -1, "TWI 1 bit rate register"}, + {"twi1.tw1cr", 0x1ca, 1, -1, -1, "TWI 1 control register"}, + {"twi1.tw1sr", 0x1cb, 1, -1, -1, "TWI 1 status register"}, + {"twi1.tw1dr", 0x1cc, 1, 0xff, -1, "TWI 1 data register"}, + {"twi1.tw1ar", 0x1cd, 1, -1, -1, "TWI 1 peripheral address register"}, + {"twi1.tw1amr", 0x1ce, 1, -1, -1, "TWI 1 address mask register"}, + {"led.pdscr", 0x1cf, 1, -1, -1, "pad driver strength control register"}, + {"tmo.tmocr", 0x1d0, 1, -1, -1, "timer modulator output control register"}, + {"tplf_cal.srccal", 0x1d1, 1, -1, -1, "slow RC oscillator calibration register"}, + {"tplf_cal.srctcal", 0x1d2, 1, -1, -1, "slow RC oscillator temperature compensation register"}, + {"sup.supca5", 0x1d3, 1, -1, -1, "supply calibration register 5"}, + {"sup.supca6", 0x1d4, 1, -1, -1, "supply calibration register 6"}, + {"sup.supca7", 0x1d5, 1, -1, -1, "supply calibration register 7"}, + {"sup.supca8", 0x1d6, 1, -1, -1, "supply calibration register 8"}, + {"sup.supca9", 0x1d7, 1, -1, -1, "supply calibration register 9"}, + {"sup.supca10", 0x1d8, 1, 0x1f, -1, "supply calibration register 10"}, + {"tplf_cal.tpcalr11", 0x1d9, 1, -1, -1, "transponder calibration register 11"}, + {"tplf_cal.tpcalr12", 0x1da, 1, -1, -1, "transponder calibration register 12"}, + {"tplf_cal.tpcalr13", 0x1db, 1, 0xff, -1, "transponder calibration register 13"}, + {"sup.pmter", 0x1de, 1, 0xff, -1, "power management test enable register"}, + {"tplf_cal.srccall", 0x1df, 1, -1, -1, "slow RC oscillator calibration register low byte"}, +}; + +// ATA5781 ATA5782 ATA5783 ATA8210 ATA8215 +const Register_file_t rgftab_ata5781[262] = { // I/O memory [0, 479] + 32 + {"clk.prr0", 0x001, 1, -1, -1, "power reduction register 0"}, + {"clk.prr1", 0x002, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x003, 1, -1, -1, "power reduction register 2"}, + {"clk.rdpr", 0x004, 1, -1, -1, "rx DSP power reduction register"}, + {"portb.pinb", 0x005, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x006, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x007, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x008, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x009, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x00a, 1, 0x3f, -1, "port C data register"}, + {"rxdsp.rdsifr", 0x00d, 1, -1, -1, "rx DSP status interrupt flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"int.pcifr", 0x00f, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x010, 1, -1, -1, "timer 0 control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"timer1.t1ifr", 0x015, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer2.t2ifr", 0x016, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer3.t3ifr", 0x017, 1, -1, -1, "timer 3 interrupt flag register"}, + {"timer4.t4ifr", 0x018, 1, -1, -1, "timer 4 interrupt flag register"}, + {"timer5.t5ifr", 0x019, 1, -1, -1, "timer 5 interrupt flag register"}, + {"gpioregs.gpior0", 0x01a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"gpioregs.gpior3", 0x01b, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs.gpior4", 0x01c, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs.gpior5", 0x01d, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs.gpior6", 0x01e, 1, 0xff, -1, "general purpose I/O register 6"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"crc.crcdir", 0x029, 1, 0xff, -1, "CRC data input register"}, + {"sup.vmcsr", 0x02a, 1, -1, -1, "voltage monitor control and status register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"timer0_wdt.t0ifr", 0x02f, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"rxdsp.rdcr", 0x033, 1, -1, -1, "rx DSP control register"}, + {"rxdsp.eotsa", 0x034, 1, -1, -1, "end of telegram status path A register"}, + {"rxdsp.eotca", 0x035, 1, -1, -1, "end of telegram conditions path A register"}, + {"rxdsp.eotsb", 0x036, 1, -1, -1, "end of telegram status path B register"}, + {"rxdsp.eotcb", 0x037, 1, -1, -1, "end of telegram conditions path B register"}, + {"cpu.smcr", 0x038, 1, -1, -1, "sleep mode control register"}, + {"cpu.cmcr", 0x039, 1, -1, -1, "clock management control register"}, + {"cpu.cmimr", 0x03a, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clpr", 0x03b, 1, -1, -1, "clock prescaler register"}, + {"cpu.spmcsr", 0x03c, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"freqs.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, + {"freqs.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, + {"freqs.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, + {"freqs.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, + {"freqs.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, + {"freqs.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, + {"freqs.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"timer5.gtccr", 0x070, 1, -1, -1, "general T/C control register"}, + {"rxdsp.sotsb", 0x071, 1, -1, -1, "start of telegram status path B register"}, + {"rxdsp.sotsa", 0x072, 1, -1, -1, "start of telegram status path A register"}, + {"rxdsp.sotcb", 0x073, 1, -1, -1, "start of telegram conditions path B register"}, + {"rxdsp.sotca", 0x074, 1, -1, -1, "start of telegram conditions path A register"}, + {"rxdsp.tesrb", 0x075, 1, -1, -1, "telegram status register path B"}, + {"rxdsp.tesra", 0x076, 1, -1, -1, "telegram status register path A"}, + {"rxdsp.rdsimr", 0x078, 1, -1, -1, "rx DSP status interrupt mask register"}, + {"rxdsp.rdocr", 0x079, 1, -1, -1, "rx DSP output control register"}, + {"temper.templ", 0x07b, 1, 0xff, -1, "temperature low byte"}, + {"temper.temph", 0x07c, 1, 0xff, -1, "temperature high byte"}, + {"symch.sycb", 0x07d, 1, -1, -1, "symbol check configuration path B register"}, + {"symch.syca", 0x07e, 1, -1, -1, "symbol check configuration path A register"}, + {"demod.rxfob", 0x07f, 1, 0xff, -1, "received frequency offset vs intermediate frequency path B register"}, + {"demod.rxfoa", 0x080, 1, 0xff, -1, "received frequency offset vs intermediate frequency path A register"}, + {"demod.dmmb", 0x081, 1, -1, -1, "demodulator mode path B register"}, + {"demod.dmma", 0x082, 1, -1, -1, "demodulator mode path A register"}, + {"demod.dmcdb", 0x083, 1, -1, -1, "demodulator carrier detect path B register"}, + {"demod.dmcda", 0x084, 1, -1, -1, "demodulator carrier detect path A register"}, + {"demod.dmcrb", 0x085, 1, -1, -1, "demodulator control path B register"}, + {"demod.dmcra", 0x086, 1, -1, -1, "demodulator control path A register"}, + {"demod.dmdrb", 0x087, 1, -1, -1, "demodulator data rate on path B register"}, + {"demod.dmdra", 0x088, 1, -1, -1, "demodulator data rate on path A register"}, + {"chflt.chcr", 0x089, 1, -1, -1, "channel filter configuration register"}, + {"chflt.chdn", 0x08a, 1, -1, -1, "channel filter down sampling register"}, + {"frsync.sfidcb", 0x08b, 1, -1, -1, "start frame ID configuration path B register"}, + {"frsync.sfidlb", 0x08c, 1, -1, -1, "start frame ID length path B register"}, + {"frsync.wuptb", 0x08d, 1, -1, -1, "wake-up pattern threshold path B register"}, + {"frsync.wuplb", 0x08e, 1, -1, -1, "wake-up pattern length path B register"}, + {"frsync.sfid1b", 0x08f, 1, 0xff, -1, "start frame ID byte 1 path B"}, + {"frsync.sfid2b", 0x090, 1, 0xff, -1, "start frame ID byte 2 path B"}, + {"frsync.sfid3b", 0x091, 1, 0xff, -1, "start frame ID byte 3 path B"}, + {"frsync.sfid4b", 0x092, 1, 0xff, -1, "start frame ID byte 4 path B"}, + {"frsync.wup1b", 0x093, 1, 0xff, -1, "wake-up pattern byte 1 path B"}, + {"frsync.wup2b", 0x094, 1, 0xff, -1, "wake-up pattern byte 2 path B"}, + {"frsync.wup3b", 0x095, 1, 0xff, -1, "wake-up pattern byte 3 path B"}, + {"frsync.wup4b", 0x096, 1, 0xff, -1, "wake-up pattern byte 4 path B"}, + {"frsync.sfidca", 0x097, 1, -1, -1, "start frame ID configuration path A register"}, + {"frsync.sfidla", 0x098, 1, -1, -1, "start frame ID length path A register"}, + {"frsync.wupta", 0x099, 1, -1, -1, "wake-up pattern threshold path A register"}, + {"frsync.wupla", 0x09a, 1, -1, -1, "wake-up pattern length path A register"}, + {"frsync.sfid1a", 0x09b, 1, 0xff, -1, "start frame ID byte 1 path A"}, + {"frsync.sfid2a", 0x09c, 1, 0xff, -1, "start frame ID byte 2 path A"}, + {"frsync.sfid3a", 0x09d, 1, 0xff, -1, "start frame ID byte 3 path A"}, + {"frsync.sfid4a", 0x09e, 1, 0xff, -1, "start frame ID byte 4 path A"}, + {"frsync.wup1a", 0x09f, 1, 0xff, -1, "wake-up pattern byte 1 path A"}, + {"frsync.wup2a", 0x0a0, 1, 0xff, -1, "wake-up pattern byte 2 path A"}, + {"frsync.wup3a", 0x0a1, 1, 0xff, -1, "wake-up pattern byte 3 path A"}, + {"frsync.wup4a", 0x0a2, 1, 0xff, -1, "wake-up pattern byte 4 path A"}, + {"clk.clkod", 0x0a3, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0a4, 1, -1, -1, "clock output control register"}, + {"clk.xfuse", 0x0a5, 1, -1, -1, "XFUSE register"}, + {"clk.srccal", 0x0a6, 1, -1, -1, "slow RC oscillator calibration register"}, + {"clk.frccal", 0x0a7, 1, -1, -1, "fast RC oscillator calibration register"}, + {"clk.cmsr", 0x0a8, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0a9, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0aa, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0ab, 1, -1, -1, "supply control register"}, + {"sup.supca2", 0x0ad, 1, -1, -1, "supply calibration register 2"}, + {"sup.supca3", 0x0ae, 1, -1, -1, "supply calibration register 3"}, + {"sup.supca4", 0x0af, 1, -1, -1, "supply calibration register 4"}, + {"sup.calrdy", 0x0b0, 1, 0xff, -1, "calibration ready signature register"}, + {"sup.vmcal", 0x0b1, 1, -1, -1, "voltage monitor calibration register"}, + {"dfifo.dfs", 0x0b2, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dftl", 0x0b3, 2, 0x0fff, -1, "data FIFO telegram length register (16 bits)"}, + {"dfifo.dfl", 0x0b5, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0b6, 1, -1, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0b7, 1, -1, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0b8, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0b9, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0ba, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0bb, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0bc, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0bd, 1, -1, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0be, 1, -1, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0bf, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0c0, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0c1, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0c2, 1, -1, -1, "sequencer state machine control register"}, + {"ssm.ssmrcr", 0x0c3, 1, -1, -1, "sequencer state machine rx control register"}, + {"ssm.ssmfbr", 0x0c4, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0c5, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0c6, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0c7, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0c8, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0c9, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0ca, 1, -1, -1, "sequencer state machine state register"}, + {"ssm.ssmxsr", 0x0cb, 1, -1, -1, "sequencer state machine extended state register"}, + {"ssm.msmcr1", 0x0cc, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0cd, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0ce, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0cf, 1, -1, -1, "master state machine control register 4"}, + {"ssm.gtcr", 0x0d0, 1, -1, -1, "get telegram control register"}, + {"ssm.sotc1a", 0x0d1, 1, -1, -1, "start of telegram conditions 1 path A register"}, + {"ssm.sotc2a", 0x0d2, 1, -1, -1, "start of telegram conditions 2 path A register"}, + {"ssm.sotc1b", 0x0d3, 1, -1, -1, "start of telegram conditions 1 path B register"}, + {"ssm.sotc2b", 0x0d4, 1, -1, -1, "start of telegram conditions 2 path B register"}, + {"ssm.eotc1a", 0x0d5, 1, -1, -1, "end of telegram conditions 1 path A register"}, + {"ssm.eotc2a", 0x0d6, 1, -1, -1, "end of telegram conditions 2 path A register"}, + {"ssm.eotc3a", 0x0d7, 1, -1, -1, "end of telegram conditions 3 path A register"}, + {"ssm.eotc1b", 0x0d8, 1, -1, -1, "end of telegram conditions 1 path B register"}, + {"ssm.eotc2b", 0x0d9, 1, -1, -1, "end of telegram conditions 2 path B register"}, + {"ssm.eotc3b", 0x0da, 1, -1, -1, "end of telegram conditions 3 path B register"}, + {"ssm.wcotoa", 0x0db, 1, 0xff, -1, "wake check ok timeout path A register"}, + {"ssm.wcotob", 0x0dc, 1, 0xff, -1, "wake check ok timeout path B register"}, + {"ssm.sottoa", 0x0dd, 1, 0xff, -1, "start of telegram time out path A register"}, + {"ssm.sottob", 0x0de, 1, 0xff, -1, "start of telegram time out path B register"}, + {"ssm.ssmfcr", 0x0df, 1, -1, -1, "sequencer state machine flow control register"}, + {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, + {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, + {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, + {"fe.felna", 0x0e3, 1, -1, -1, "front-end LNA bias register"}, + {"fe.fevct", 0x0e6, 1, -1, -1, "front-end VCO tuning register"}, + {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, + {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, + {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, + {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, + {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, + {"fe.fealr", 0x0ec, 1, -1, -1, "front-end antenna level detector range register"}, + {"fe.feant", 0x0ed, 1, -1, -1, "front-end antenna register"}, + {"fe.febia", 0x0ee, 1, -1, -1, "front-end IF amplifier BIAS register"}, + {"rxbuf.rxbc1", 0x10f, 1, -1, -1, "rx buffer configuration 1 register"}, + {"rxbuf.rxbc2", 0x110, 1, -1, -1, "rx buffer configuration 2 register"}, + {"rxbuf.rxtllb", 0x111, 1, 0xff, -1, "rx telegram length low byte path B"}, + {"rxbuf.rxtlhb", 0x112, 1, -1, -1, "rx telegram length high byte path B"}, + {"rxbuf.rxcrlb", 0x113, 1, 0xff, -1, "rx CRC result low byte path B"}, + {"rxbuf.rxcrhb", 0x114, 1, 0xff, -1, "rx CRC result high byte path B"}, + {"rxbuf.rxcsbb", 0x115, 1, 0xff, -1, "rx CRC skip bit number path B register"}, + {"rxbuf.rxcilb", 0x116, 1, 0xff, -1, "rx CRC init value low byte path B"}, + {"rxbuf.rxcihb", 0x117, 1, 0xff, -1, "rx CRC init value high byte path B"}, + {"rxbuf.rxcplb", 0x118, 1, 0xfe, -1, "rx CRC polynomial low byte path B"}, + {"rxbuf.rxcphb", 0x119, 1, 0xff, -1, "rx CRC polynomial high byte path B"}, + {"rxbuf.rxdsb", 0x11a, 1, 0xff, -1, "receive data shift register path B"}, + {"rxbuf.rxtlla", 0x11b, 1, 0xff, -1, "rx telegram length low byte path A"}, + {"rxbuf.rxtlha", 0x11c, 1, -1, -1, "rx telegram length high byte path A"}, + {"rxbuf.rxcrla", 0x11d, 1, 0xff, -1, "rx CRC result low byte path A"}, + {"rxbuf.rxcrha", 0x11e, 1, 0xff, -1, "rx CRC result high byte path A"}, + {"rxbuf.rxcsba", 0x11f, 1, 0xff, -1, "rx CRC skip bit number path A register"}, + {"rxbuf.rxcila", 0x120, 1, 0xff, -1, "rx CRC init value low byte path A"}, + {"rxbuf.rxciha", 0x121, 1, 0xff, -1, "rx CRC init value high byte path A"}, + {"rxbuf.rxcpla", 0x122, 1, 0xfe, -1, "rx CRC polynomial low byte path A"}, + {"rxbuf.rxcpha", 0x123, 1, 0xff, -1, "rx CRC polynomial high byte path A"}, + {"rxbuf.rxdsa", 0x124, 1, 0xff, -1, "receive data shift register path A"}, + {"crc.crccr", 0x125, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x126, 1, 0xff, -1, "CRC data output register"}, + {"idscan.idb0", 0x127, 1, 0xff, -1, "ID byte 0"}, + {"idscan.idb1", 0x128, 1, 0xff, -1, "ID byte 1"}, + {"idscan.idb2", 0x129, 1, 0xff, -1, "ID byte 2"}, + {"idscan.idb3", 0x12a, 1, 0xff, -1, "ID byte 3"}, + {"idscan.idc", 0x12b, 1, -1, -1, "ID configuration register"}, + {"idscan.ids", 0x12c, 1, -1, -1, "ID status register"}, + {"rssib.rssav", 0x12d, 1, 0xff, -1, "RSSI average register"}, + {"rssib.rsspk", 0x12e, 1, 0xff, -1, "RSSI peak register"}, + {"rssib.rssl", 0x12f, 1, 0xff, -1, "RSSI low threshold register"}, + {"rssib.rssh", 0x130, 1, 0xff, -1, "RSSI high threshold register"}, + {"rssib.rssc", 0x131, 1, -1, -1, "RSSI configuration register"}, + {"debounce.dbcr", 0x132, 1, -1, -1, "debounce control register"}, + {"debounce.dbtc", 0x133, 1, 0xff, -1, "debounce timer compare register"}, + {"debounce.dbenb", 0x134, 1, 0xff, -1, "debounce enable port B register"}, + {"debounce.dbenc", 0x135, 1, 0x3f, -1, "debounce enable port C register"}, + {"debug.dbgsw", 0x136, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x137, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x138, 1, -1, -1, "SPI FIFO interrupt register"}, + {"eeprom.eecr2", 0x139, 1, -1, -1, "EEPROM control register 2"}, + {"mem.pgmst", 0x13a, 1, -1, -1, "program memory status register"}, + {"mem.eest", 0x13b, 1, -1, -1, "EEPROM status register"}, + {"rssib.rsifg", 0x13c, 1, 0xff, -1, "RSSI IF amplifier gain register"}, + {"rssib.rsldv", 0x13d, 1, 0xff, -1, "RSSI low band damping value register"}, + {"rssib.rshdv", 0x13e, 1, 0xff, -1, "RSSI high band damping value register"}, + {"rssib.rscom", 0x13f, 1, -1, -1, "RSSI compensation register"}, +}; + +// ATA5790 +const Register_file_t rgftab_ata5790[112] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"afe.tpcr", 0x0d, 1, -1, -1, "transponder control register"}, + {"afe.tpfr", 0x0e, 1, -1, -1, "transponder status and flag register"}, + {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, + {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, + {"timer_counter_2.t2cr", 0x11, 1, -1, -1, "timer 2 control register"}, + {"timer_counter_3.t3cr", 0x12, 1, -1, -1, "timer 3 control register"}, + {"aes.aescr", 0x13, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x14, 1, -1, -1, "AES status register"}, + {"mod.tmifr", 0x15, 1, -1, -1, "timer modulator interrupt flag register"}, + {"cpu.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"vmon.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, + {"dddlfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, + {"timer_counter_0.t0ifr", 0x19, 1, -1, -1, "timer 0 interrupt flag register"}, + {"timer_counter_1.t1ifr", 0x1a, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, + {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, + {"cpu.gpior", 0x1e, 1, 0xff, -1, "general purpose I/O register"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x23, 1, -1, -1, "EEPROM protection register"}, + {"eeprom.eeccr", 0x24, 1, -1, -1, "EEPROM error correction code register"}, + {"external_interrupt.pcicr", 0x26, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eimsk", 0x27, 1, -1, -1, "external interrupt mask register"}, + {"mod.tmdr", 0x28, 1, 0xff, -1, "timer modulator data register"}, + {"aes.aesdr", 0x29, 1, 0xff, -1, "AES data register"}, + {"aes.aeskr", 0x2a, 1, -1, -1, "AES key register"}, + {"cpu.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"vmon.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"dddlfrx.lfcr0", 0x2f, 1, -1, -1, "LF receiver control register 0"}, + {"dddlfrx.lfcr1", 0x30, 1, -1, -1, "LF receiver control register 1"}, + {"dddlfrx.lfrdb", 0x32, 1, 0xff, -1, "LF receiver data buffer register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"dddlfrx.lfsr", 0x36, 1, -1, -1, "LF status register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, + {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, + {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.prr0", 0x43, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x44, 1, -1, -1, "power reduction register 1"}, + {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, + {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"irled.ldcr", 0x4d, 1, -1, -1, "LED driver control register"}, + {"timer_counter_2.t2cnt", 0x50, 1, 0xff, -1, "timer 2 counter"}, + {"timer_counter_2.t2cor", 0x51, 1, 0xff, -1, "timer 2 compare register"}, + {"timer_counter_2.t2mr", 0x53, 1, -1, -1, "timer 2 mode register"}, + {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer_counter_3.t3cnt", 0x56, 1, 0xff, -1, "timer 3 counter"}, + {"timer_counter_3.t3cor", 0x57, 1, 0xff, -1, "timer 3 compare register"}, + {"timer_counter_3.t3icr", 0x58, 1, 0xff, -1, "timer 3 input capture register"}, + {"timer_counter_3.t3mra", 0x59, 1, -1, -1, "timer 3 mode register A"}, + {"timer_counter_3.t3mrb", 0x5a, 1, -1, -1, "timer 3 mode register B"}, + {"timer_counter_3.t3imr", 0x5b, 1, -1, -1, "timer 3 interrupt mask register"}, + {"mod.tmcr", 0x5d, 1, -1, -1, "timer modulator control register"}, + {"mod.tmmr", 0x5e, 1, -1, -1, "timer modulator mode register"}, + {"mod.tmimr", 0x5f, 1, -1, -1, "timer modulator interrupt mask register"}, + {"dddlfrx.lfimr", 0x62, 1, -1, -1, "LF interrupt mask register"}, + {"dddlfrx.lfcad", 0x63, 1, 0xff, -1, "LF clock adjustment data register"}, + {"dddlfrx.lfid00", 0x64, 1, 0xff, -1, "LF ID 0 data register byte 0"}, + {"dddlfrx.lfid01", 0x65, 1, 0xff, -1, "LF ID 0 data register byte 1"}, + {"dddlfrx.lfid02", 0x66, 1, 0xff, -1, "LF ID 0 data register byte 2"}, + {"dddlfrx.lfid03", 0x67, 1, 0xff, -1, "LF ID 0 data register byte 3"}, + {"dddlfrx.lfid10", 0x68, 1, 0xff, -1, "LF ID 1 data register byte 0"}, + {"dddlfrx.lfid11", 0x69, 1, 0xff, -1, "LF ID 1 data register byte 1"}, + {"dddlfrx.lfid12", 0x6a, 1, 0xff, -1, "LF ID 1 data register byte 2"}, + {"dddlfrx.lfid13", 0x6b, 1, 0xff, -1, "LF ID 1 data register byte 3"}, + {"dddlfrx.lfrd0", 0x6c, 1, 0xff, -1, "LF receive data register byte 0"}, + {"dddlfrx.lfrd1", 0x6d, 1, 0xff, -1, "LF receive data register byte 1"}, + {"dddlfrx.lfrd2", 0x6e, 1, 0xff, -1, "LF receive data register byte 2"}, + {"dddlfrx.lfrd3", 0x6f, 1, 0xff, -1, "LF receive data register byte 3"}, + {"dddlfrx.lfid0m", 0x70, 1, -1, -1, "LF identifier 0 mask register"}, + {"dddlfrx.lfid1m", 0x71, 1, -1, -1, "LF identifier 1 mask register"}, + {"dddlfrx.lfrdf", 0x72, 1, -1, -1, "LF receive data frame register"}, + {"dddlfrx.lfrsd1", 0x73, 1, 0xff, -1, "LF RSSI data register 1"}, + {"dddlfrx.lfrsd2", 0x74, 1, 0xff, -1, "LF RSSI data register 2"}, + {"dddlfrx.lfrsd3", 0x75, 1, 0xff, -1, "LF RSSI data register 3"}, + {"dddlfrx.lfcc1", 0x76, 1, 0x0f, -1, "LF channel capacity select register 1"}, + {"dddlfrx.lfcc2", 0x77, 1, 0x0f, -1, "LF channel capacity select register 2"}, + {"dddlfrx.lfcc3", 0x78, 1, 0x0f, -1, "LF channel capacity select register 3"}, + {"afe.tpimr", 0x7c, 1, -1, -1, "transponder interrupt mask register"}, + {"rtc_timer.rtccr", 0x7e, 1, -1, -1, "real-time clock control register"}, + {"rtc_timer.rtcdr", 0x7f, 1, 0xff, -1, "real time clock data register"}, + {"mod.tmmdr", 0x88, 1, 0x0f, -1, "timer modulator manchester data register"}, + {"mod.tmbdr", 0x89, 1, 0x0f, -1, "timer modulator biphase data register"}, + {"mod.tmtdr", 0x8a, 1, 0xff, -1, "timer modulator transmit data register"}, + {"mod.tmsr", 0x8b, 1, 0xff, -1, "timer modulator shift register"}, + {"crc.crcdr", 0x8d, 1, 0xff, -1, "CRC data register"}, + {"crc.crccr", 0x8e, 1, -1, -1, "CRC control register"}, + {"crc.crcsr", 0x8f, 1, -1, -1, "CRC status register"}, +}; + +// ATA6285 ATA6286 +const Register_file_t rgftab_ata6285[79] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x07, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x07, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x07, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, + {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, + {"timer_counter_2.t2cra", 0x11, 1, -1, -1, "timer 2 control register A"}, + {"timer_counter_2.t2crb", 0x12, 1, -1, -1, "timer 2 control register B"}, + {"timer_counter_3.t3cra", 0x14, 1, -1, -1, "timer 3 control register A"}, + {"cpu.vmcsr", 0x16, 1, -1, -1, "voltage monitor control and status register"}, + {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, + {"lfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, + {"sensor_interface.ssfr", 0x19, 1, -1, -1, "sensor status + flag register"}, + {"timer_counter_0.t10ifr", 0x1a, 1, -1, -1, "timer1/0 interrupt flag register"}, + {"timer_counter_1.t10ifr", 0x1a, 1, -1, -1, "timer1/0 interrupt flag register"}, + {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, + {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"external_interrupt.pcicr", 0x23, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eimsk", 0x24, 1, -1, -1, "external interrupt mask register"}, + {"sensor_interface.svcr", 0x27, 1, 0x1f, -1, "sensor voltage control register"}, + {"sensor_interface.scr", 0x28, 1, -1, -1, "sensor control register"}, + {"sensor_interface.sccr", 0x29, 1, -1, -1, "sensor capacitor control register"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"timer_counter_2.t2mdr", 0x2f, 1, 0xff, -1, "timer 2 modulator data register"}, + {"lfrx.lfrr", 0x30, 1, 0x7f, -1, "LF RSSI data register"}, + {"lfrx.lfcdr", 0x32, 1, -1, -1, "LF receiver control und data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"lfrx.lfrb", 0x36, 1, 0xff, -1, "LF receiver data buffer register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, + {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, + {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"sensor_interface.simsk", 0x41, 1, -1, -1, "sensor interrupt mask register"}, + {"sensor_interface.tscr", 0x44, 1, -1, -1, "temperature sensor control register"}, + {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, + {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, + {"sensor_interface.msvcal", 0x47, 1, 0xff, -1, "motion sensor voltage calibration register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"external_interrupt.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"timer_counter_2.t2icrl", 0x4e, 1, 0xff, -1, "timer 2 input capture register low byte"}, + {"timer_counter_2.t2icr", 0x4f, 1, 0xff, -1, "timer 2 input capture register high byte"}, + {"timer_counter_2.t2cor", 0x50, 2, 0xffff, -1, "timer 2 compare register (16 bits)"}, + {"timer_counter_2.t2mra", 0x52, 1, -1, -1, "timer 2 mode register A"}, + {"timer_counter_2.t2mrb", 0x53, 1, -1, -1, "timer 2 mode register B"}, + {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer_counter_3.t3icr", 0x56, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer_counter_3.t3cora", 0x58, 2, 0xffff, -1, "timer 3 compare register A (16 bits)"}, + {"timer_counter_3.t3corb", 0x5a, 2, 0xffff, -1, "timer 3 compare register B (16 bits)"}, + {"timer_counter_3.t3mra", 0x5c, 1, -1, -1, "timer 3 mode register A"}, + {"timer_counter_3.t3mrb", 0x5d, 1, -1, -1, "timer 3 mode register B"}, + {"timer_counter_3.t3crb", 0x5e, 1, -1, -1, "timer 3 control register B"}, + {"timer_counter_3.t3imr", 0x5f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"lfrx.lfimr", 0x61, 1, -1, -1, "LF interrupt mask register"}, + {"lfrx.lfrcr", 0x62, 1, -1, -1, "LF receiver control register"}, + {"lfrx.lfhcr", 0x63, 1, 0x7f, -1, "LF header compare register"}, + {"lfrx.lfidc", 0x64, 2, 0xffff, -1, "LF ID compare register (16 bits)"}, + {"lfrx.lfcal", 0x66, 2, 0xffff, -1, "LF calibration register (16 bits)"}, +}; + +// ATxmega16E5 ATxmega8E5 ATxmega32E5 +const Register_file_t rgftab_atxmega16e5[438] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"osc.rc8mcal", 0x057, 1, -1, -1, "internal 8 MHz RC oscillator calibration register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.wexlock", 0x099, 1, -1, -1, "WEX lock register"}, + {"mcu.faultlock", 0x09a, 1, -1, -1, "FAULT lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.clkout", 0x0b4, 1, -1, -1, "clock out register"}, + {"portcfg.acevout", 0x0b6, 1, -1, -1, "analog comparator and event out register"}, + {"portcfg.srlctrl", 0x0b7, 1, -1, -1, "slew rate limit control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"edma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"edma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"edma.status", 0x104, 1, -1, -1, "status register"}, + {"edma.temp", 0x106, 1, -1, -1, "temporary register for 16-bit access"}, + {"edma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"edma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"edma.ch0.addrctrl", 0x112, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch0.destaddrctrl", 0x113, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch0.trigsrc", 0x114, 1, -1, -1, "channel trigger source register"}, + {"edma.ch0.trfcnt", 0x116, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch0.addr", 0x118, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch0.destaddr", 0x11c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, + {"edma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"edma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"edma.ch1.addrctrl", 0x122, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch1.destaddrctrl", 0x123, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch1.trigsrc", 0x124, 1, -1, -1, "channel trigger source register"}, + {"edma.ch1.trfcnt", 0x126, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch1.addr", 0x128, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch1.destaddr", 0x12c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, + {"edma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"edma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"edma.ch2.addrctrl", 0x132, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch2.destaddrctrl", 0x133, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch2.trigsrc", 0x134, 1, -1, -1, "channel trigger source register"}, + {"edma.ch2.trfcnt", 0x136, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch2.addr", 0x138, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch2.destaddr", 0x13c, 2, -1, -1, "channel destination address for standard channels only register (16 bits)"}, + {"edma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"edma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"edma.ch3.addrctrl", 0x142, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch3.destaddrctrl", 0x143, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch3.trigsrc", 0x144, 1, -1, -1, "channel trigger source register"}, + {"edma.ch3.trfcnt", 0x146, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch3.addr", 0x148, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch3.destaddr", 0x14c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"evsys.dfctrl", 0x192, 1, -1, -1, "digital filter control register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 1, -1, -1, "calibration register"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch0.corrctrl", 0x227, 1, -1, -1, "correction control register"}, + {"adc.ch0.offsetcorr0", 0x228, 1, -1, -1, "offset correction register 0"}, + {"adc.ch0.offsetcorr1", 0x229, 1, -1, -1, "offset correction register 1"}, + {"adc.ch0.gaincorr0", 0x22a, 1, -1, -1, "gain correction register 0"}, + {"adc.ch0.gaincorr1", 0x22b, 1, -1, -1, "gain correction register 1"}, + {"adc.ch0.avgctrl", 0x22c, 1, -1, -1, "average control register"}, + {"daca.ctrla", 0x300, 1, -1, -1, "control register A"}, + {"daca.ctrlb", 0x301, 1, -1, -1, "control register B"}, + {"daca.ctrlc", 0x302, 1, -1, -1, "control register C"}, + {"daca.evctrl", 0x303, 1, -1, -1, "event control register"}, + {"daca.status", 0x305, 1, -1, -1, "status register"}, + {"daca.ch0gaincal", 0x308, 1, -1, -1, "gain calibration register"}, + {"daca.ch0offsetcal", 0x309, 1, -1, -1, "offset calibration register"}, + {"daca.ch1gaincal", 0x30a, 1, -1, -1, "gain calibration register"}, + {"daca.ch1offsetcal", 0x30b, 1, -1, -1, "offset calibration register"}, + {"daca.ch0data", 0x318, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"daca.ch1data", 0x31a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.calib", 0x406, 1, -1, -1, "calibration register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"xcl.ctrla", 0x460, 1, -1, -1, "control register A"}, + {"xcl.ctrlb", 0x461, 1, -1, -1, "control register B"}, + {"xcl.ctrlc", 0x462, 1, -1, -1, "control register C"}, + {"xcl.ctrld", 0x463, 1, -1, -1, "control register D"}, + {"xcl.ctrle", 0x464, 1, -1, -1, "control register E"}, + {"xcl.ctrlf", 0x465, 1, -1, -1, "control register F"}, + {"xcl.ctrlg", 0x466, 1, -1, -1, "control register G"}, + {"xcl.intctrl", 0x467, 1, -1, -1, "interrupt control register"}, + {"xcl.intflags", 0x468, 1, -1, -1, "interrupt flags register"}, + {"xcl.plc", 0x469, 1, -1, -1, "peripheral length control register"}, + {"xcl.cntl", 0x46a, 1, -1, -1, "counter low byte"}, + {"xcl.cnth", 0x46b, 1, -1, -1, "counter high byte"}, + {"xcl.cmpl", 0x46c, 1, -1, -1, "compare register low byte"}, + {"xcl.cmph", 0x46d, 1, -1, -1, "compare register high byte"}, + {"xcl.percaptl", 0x46e, 1, -1, -1, "period or capture register low byte"}, + {"xcl.percapth", 0x46f, 1, -1, -1, "period or capture register high byte"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x481, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x482, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x483, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x484, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x485, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x486, 1, -1, -1, "address register"}, + {"twi.host.data", 0x487, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x488, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x489, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x48a, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x48b, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x48c, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x48d, 1, -1, -1, "address mask register"}, + {"twi.timeout.tos", 0x48e, 1, -1, -1, "timeout status register"}, + {"twi.timeout.toconf", 0x48f, 1, -1, -1, "timeout configuration register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.intmask", 0x60a, 1, -1, -1, "port interrupt mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.intmask", 0x64a, 1, -1, -1, "port interrupt mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.intmask", 0x66a, 1, -1, -1, "port interrupt mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.intmask", 0x7ea, 1, -1, -1, "port interrupt mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc4.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc4.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc4.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc4.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc4.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc4.ctrlf", 0x805, 1, -1, -1, "control register F"}, + {"tcc4.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc4.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc4.ctrlgclr", 0x808, 1, -1, -1, "control register G clear"}, + {"tcc4.ctrlgset", 0x809, 1, -1, -1, "control register G set"}, + {"tcc4.ctrlhclr", 0x80a, 1, -1, -1, "control register H clear"}, + {"tcc4.ctrlhset", 0x80b, 1, -1, -1, "control register H set"}, + {"tcc4.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc4.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc4.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc4.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc4.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc4.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc4.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc4.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc4.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc4.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc4.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc4.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc4.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc5.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc5.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc5.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc5.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc5.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc5.ctrlf", 0x845, 1, -1, -1, "control register F"}, + {"tcc5.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc5.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc5.ctrlgclr", 0x848, 1, -1, -1, "control register G clear"}, + {"tcc5.ctrlgset", 0x849, 1, -1, -1, "control register G set"}, + {"tcc5.ctrlhclr", 0x84a, 1, -1, -1, "control register H clear"}, + {"tcc5.ctrlhset", 0x84b, 1, -1, -1, "control register H set"}, + {"tcc5.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc5.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc5.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc5.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc5.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc5.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc5.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc5.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc5.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"faultc4.ctrla", 0x880, 1, -1, -1, "control register A"}, + {"faultc4.ctrlb", 0x881, 1, -1, -1, "control register B"}, + {"faultc4.ctrlc", 0x882, 1, -1, -1, "control register C"}, + {"faultc4.ctrld", 0x883, 1, -1, -1, "control register D"}, + {"faultc4.ctrle", 0x884, 1, -1, -1, "control register E"}, + {"faultc4.status", 0x885, 1, -1, -1, "status register"}, + {"faultc4.ctrlgclr", 0x886, 1, -1, -1, "control register G clear"}, + {"faultc4.ctrlgset", 0x887, 1, -1, -1, "control register G set"}, + {"faultc5.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"faultc5.ctrlb", 0x891, 1, -1, -1, "control register B"}, + {"faultc5.ctrlc", 0x892, 1, -1, -1, "control register C"}, + {"faultc5.ctrld", 0x893, 1, -1, -1, "control register D"}, + {"faultc5.ctrle", 0x894, 1, -1, -1, "control register E"}, + {"faultc5.status", 0x895, 1, -1, -1, "status register"}, + {"faultc5.ctrlgclr", 0x896, 1, -1, -1, "control register G clear"}, + {"faultc5.ctrlgset", 0x897, 1, -1, -1, "control register G set"}, + {"wexc.ctrl", 0x8a0, 1, -1, -1, "control register"}, + {"wexc.dtboth", 0x8a1, 1, -1, -1, "dead-time both sides register"}, + {"wexc.dtls", 0x8a2, 1, -1, -1, "dead-time low side register"}, + {"wexc.dths", 0x8a3, 1, -1, -1, "dead-time high side register"}, + {"wexc.statusclr", 0x8a4, 1, -1, -1, "status clear register"}, + {"wexc.statusset", 0x8a5, 1, -1, -1, "status set register"}, + {"wexc.swap", 0x8a6, 1, -1, -1, "swap register"}, + {"wexc.pgo", 0x8a7, 1, -1, -1, "pattern generation override register"}, + {"wexc.pgv", 0x8a8, 1, -1, -1, "pattern generation value register"}, + {"wexc.swapbuf", 0x8aa, 1, -1, -1, "dead time low side buffer register"}, + {"wexc.pgobuf", 0x8ab, 1, -1, -1, "pattern generation overwrite buffer register"}, + {"wexc.pgvbuf", 0x8ac, 1, -1, -1, "pattern generation value buffer register"}, + {"wexc.outovdis", 0x8af, 1, -1, -1, "output override disable register"}, + {"hiresc.ctrla", 0x8b0, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8c0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8c1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8c2, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8c3, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8c4, 1, -1, -1, "control register C"}, + {"usartc0.ctrld", 0x8c5, 1, -1, -1, "control register D"}, + {"usartc0.baudctrla", 0x8c6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8c7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8e0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8e1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8e2, 1, -1, -1, "status register"}, + {"spic.data", 0x8e3, 1, -1, -1, "data register"}, + {"spic.ctrlb", 0x8e4, 1, -1, -1, "control register B"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd5.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd5.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd5.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd5.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd5.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd5.ctrlf", 0x945, 1, -1, -1, "control register F"}, + {"tcd5.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd5.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd5.ctrlgclr", 0x948, 1, -1, -1, "control register G clear"}, + {"tcd5.ctrlgset", 0x949, 1, -1, -1, "control register G set"}, + {"tcd5.ctrlhclr", 0x94a, 1, -1, -1, "control register H clear"}, + {"tcd5.ctrlhset", 0x94b, 1, -1, -1, "control register H set"}, + {"tcd5.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd5.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd5.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd5.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd5.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd5.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd5.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd5.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd5.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"usartd0.data", 0x9c0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9c1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9c2, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9c3, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9c4, 1, -1, -1, "control register C"}, + {"usartd0.ctrld", 0x9c5, 1, -1, -1, "control register D"}, + {"usartd0.baudctrla", 0x9c6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9c7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega128A3 ATxmega64A3 ATxmega192A3 ATxmega256A3 +const Register_file_t rgftab_atxmega128a3[680] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, + {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, + {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, + {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, + {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, + {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, + {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, + {"usartf1.data", 0xbb0, 1, -1, -1, "data register"}, + {"usartf1.status", 0xbb1, 1, -1, -1, "status register"}, + {"usartf1.ctrla", 0xbb3, 1, -1, -1, "control register A"}, + {"usartf1.ctrlb", 0xbb4, 1, -1, -1, "control register B"}, + {"usartf1.ctrlc", 0xbb5, 1, -1, -1, "control register C"}, + {"usartf1.baudctrla", 0xbb6, 1, -1, -1, "baud rate control register A"}, + {"usartf1.baudctrlb", 0xbb7, 1, -1, -1, "baud rate control register B"}, + {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, + {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, + {"spif.status", 0xbc2, 1, -1, -1, "status register"}, + {"spif.data", 0xbc3, 1, -1, -1, "data register"}, +}; + +// ATxmega128A3U ATxmega64A3U ATxmega192A3U ATxmega256A3U +const Register_file_t rgftab_atxmega128a3u[792] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"acb.currctrl", 0x398, 1, -1, -1, "current source control register"}, + {"acb.currcalib", 0x399, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, + {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, + {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, + {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, + {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, + {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, + {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATtiny204 ATtiny404 +const Register_file_t rgftab_attiny204[235] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, -1, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny1624 ATtiny424 ATtiny824 ATtiny3224 +const Register_file_t rgftab_attiny1624[307] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.sweventa", 0x0180, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x01a8, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userusart0irda", 0x01ac, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x01ad, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x01ae, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x01af, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x01b0, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x01b1, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x01b2, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x01b3, 1, -1, 0x00, "user TCB 1 event register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e3, 1, -1, 0x00, "SPI route A register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, -1, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, -1, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +/* + * AVR32DD14 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 + * AVR64DD20 AVR64DD28 AVR64DD32 + */ +const Register_file_t rgftab_avr32dd14[401] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64EA48 AVR16EA48 AVR32EA48 +const Register_file_t rgftab_avr64ea48[502] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, 0x00, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, 0x00, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, 0x00, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, 0x00, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, 0x00, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, 0x00, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022a, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022b, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022c, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x022d, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x022e, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022f, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0230, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0231, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x0232, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0233, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x0234, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x0235, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x0236, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0237, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0238, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0239, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023a, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023b, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023c, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023d, 1, -1, 0x00, "user TCB 3 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrl", 0x0418, 1, -1, 0x00, "event generation control register"}, + {"portb.dir", 0x0420, 1, -1, 0x00, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, 0x00, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, 0x00, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, 0x00, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, 0x00, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, 0x00, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, 0x00, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, 0x00, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, 0x00, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portb.evgenctrl", 0x0438, 1, -1, 0x00, "event generation control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrl", 0x0458, 1, -1, 0x00, "event generation control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrl", 0x0478, 1, -1, 0x00, "event generation control register"}, + {"porte.dir", 0x0480, 1, -1, 0x00, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, 0x00, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, 0x00, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, 0x00, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, 0x00, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, 0x00, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, 0x00, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, 0x00, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, 0x00, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"porte.evgenctrl", 0x0498, 1, -1, 0x00, "event generation control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrl", 0x04b8, 1, -1, 0x00, "event generation control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, -1, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, -1, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, -1, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// ATtiny4 ATtiny9 +const Register_file_t rgftab_attiny4[36] = { // I/O memory [0, 63] + {"portb.pinb", 0x00, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x01, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x02, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x03, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"portb.portcr", 0x0c, 1, -1, -1, "port control register"}, + {"exint.pcmsk", 0x10, 1, -1, -1, "pin change interrupt mask register"}, + {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, + {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, + {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, + {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"ac.acsr", 0x1f, 1, -1, -1, "analog comparator control and status register"}, + {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, + {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, + {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, + {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, + {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny5 ATtiny10 +const Register_file_t rgftab_attiny5[41] = { // I/O memory [0, 63] + {"portb.pinb", 0x00, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x01, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x02, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x03, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"portb.portcr", 0x0c, 1, -1, -1, "port control register"}, + {"exint.pcmsk", 0x10, 1, -1, -1, "pin change interrupt mask register"}, + {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, + {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, + {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, + {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.adcl", 0x19, 1, 0xff, -1, "ADC data register low byte"}, + {"adc.admux", 0x1b, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x1c, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x1d, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsr", 0x1f, 1, -1, -1, "analog comparator control and status register"}, + {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, + {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, + {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, + {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, + {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny20 +const Register_file_t rgftab_attiny20[61] = { // I/O memory [0, 63] + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"porta.portcr", 0x08, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x08, 1, -1, -1, "port control register"}, + {"exint.pcmsk0", 0x09, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x0a, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.gifr", 0x0b, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x0c, 1, -1, -1, "general interrupt mask register"}, + {"adc.didr0", 0x0d, 1, -1, -1, "digital input disable register 0"}, + {"adc.adc", 0x0e, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.admux", 0x10, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x11, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x12, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsrb", 0x13, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x14, 1, -1, -1, "analog comparator control and status register A"}, + {"tc0.ocr0b", 0x15, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x16, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0", 0x17, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x18, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x19, 1, -1, -1, "T/C 0 control register A"}, + {"tc1.icr1", 0x1a, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x1c, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x1e, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x20, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tccr1b", 0x23, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x24, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, + {"tc0.gtccr", 0x27, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x27, 1, -1, -1, "general T/C control register"}, + {"twi.twsd", 0x28, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x29, 1, 0xff, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x2a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x2b, 1, 0xff, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x2c, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x2d, 1, -1, -1, "TWI peripheral control register A"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"spi.spsr", 0x2f, 1, -1, -1, "SPI status register"}, + {"spi.spcr", 0x30, 1, -1, -1, "SPI control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.mcucr", 0x3a, 1, 0xdf, -1, "MCU control register"}, + {"exint.mcucr", 0x3a, 1, -1, -1, "MCU control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny40 +const Register_file_t rgftab_attiny40[63] = { // I/O memory [0, 63] + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"porta.portcr", 0x08, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x08, 1, -1, -1, "port control register"}, + {"portc.portcr", 0x08, 1, -1, -1, "port control register"}, + {"exint.pcmsk0", 0x09, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x0a, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.gifr", 0x0b, 1, 0x71, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x0c, 1, 0x71, -1, "general interrupt mask register"}, + {"adc.didr0", 0x0d, 1, -1, -1, "digital input disable register 0"}, + {"adc.adc", 0x0e, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.admux", 0x10, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x11, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x12, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsrb", 0x13, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x14, 1, -1, -1, "analog comparator control and status register A"}, + {"tc0.ocr0b", 0x15, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x16, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0", 0x17, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x18, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x19, 1, -1, -1, "T/C 0 control register A"}, + {"exint.pcmsk2", 0x1a, 1, -1, -1, "pin change interrupt mask register 2"}, + {"portc.pinc", 0x1b, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x1c, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x1d, 1, 0x3f, -1, "port C data register"}, + {"portc.puec", 0x1e, 1, 0x3f, -1, "PORT C pull-up enable control register"}, + {"cpu.ramdr", 0x1f, 1, 0xff, -1, "RAM data register"}, + {"cpu.ramar", 0x20, 1, 0xff, -1, "RAM address register"}, + {"tc0.ocr1b", 0x21, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc0.ocr1a", 0x22, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc0.tcnt1l", 0x23, 1, 0xff, -1, "timer/counter 1 low byte"}, + {"tc0.tccr1a", 0x24, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, + {"tc0.tcnt1h", 0x27, 1, 0xff, -1, "timer/counter 1 high byte"}, + {"twi.twsd", 0x28, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x29, 1, 0xff, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x2a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x2b, 1, 0xff, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x2c, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x2d, 1, -1, -1, "TWI peripheral control register A"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"spi.spsr", 0x2f, 1, -1, -1, "SPI status register"}, + {"spi.spcr", 0x30, 1, -1, -1, "SPI control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.mcucr", 0x3a, 1, 0xdf, -1, "MCU control register"}, + {"exint.mcucr", 0x3a, 1, -1, -1, "MCU control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny11 +const Register_file_t rgftab_attiny11[14] = { // I/O memory [0, 63] + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x1f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny12 +const Register_file_t rgftab_attiny12[18] = { // I/O memory [0, 63] + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny13 +const Register_file_t rgftab_attiny13[35] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc0.gtccr", 0x28, 1, -1, -1, "general T/C control register"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.dwdr", 0x2e, 1, 0xff, -1, "debugWIRE data register"}, + {"tc0.tccr0a", 0x2f, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny13A +const Register_file_t rgftab_attiny13a[37] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.prr", 0x25, 1, -1, -1, "power reduction register"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc0.gtccr", 0x28, 1, -1, -1, "general T/C control register"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.dwdr", 0x2e, 1, 0xff, -1, "debugWIRE data register"}, + {"tc0.tccr0a", 0x2f, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.bodcr", 0x30, 1, -1, -1, "BOD control register"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny15 +const Register_file_t rgftab_attiny15[28] = { // I/O memory [0, 63] + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsr", 0x06, 1, -1, -1, "ADC control and status register"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.sfior", 0x2c, 1, -1, -1, "special function I/O register"}, + {"tc1.ocr1b", 0x2d, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny24 ATtiny24A +const Register_file_t rgftab_attiny24[55] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny25 +const Register_file_t rgftab_attiny25[55] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"cpu.gpior0", 0x11, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x12, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x13, 1, 0xff, -1, "general purpose I/O register 2"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.prr", 0x20, 1, -1, -1, "power reduction register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.dwdr", 0x22, 1, 0xff, -1, "debugWIRE data register"}, + {"tc1.dtps", 0x23, 1, -1, -1, "dead-time prescaler register"}, + {"tc1.dt1b", 0x24, 1, -1, -1, "T/C 1 dead-time register B"}, + {"tc1.dt1a", 0x25, 1, -1, -1, "T/C 1 dead-time register A"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x27, 1, -1, -1, "PLL control and status register"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x29, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tccr0a", 0x2a, 1, -1, -1, "T/C 0 control register A"}, + {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc0.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.ocr1c", 0x2d, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny26 +const Register_file_t rgftab_attiny26[37] = { // I/O memory [0, 63] + 32 + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsr", 0x06, 1, -1, -1, "ADC control and status register"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 1, 0xff, -1, "stack pointer"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny43U +const Register_file_t rgftab_attiny43u[54] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"exint.pcmsk1", 0x20, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2c, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2d, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny44 ATtiny44A +const Register_file_t rgftab_attiny44[55] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny45 ATtiny85 +const Register_file_t rgftab_attiny45[55] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"cpu.gpior0", 0x11, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x12, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x13, 1, 0xff, -1, "general purpose I/O register 2"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.prr", 0x20, 1, -1, -1, "power reduction register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.dwdr", 0x22, 1, 0xff, -1, "debugWIRE data register"}, + {"tc1.dtps", 0x23, 1, -1, -1, "dead-time prescaler register"}, + {"tc1.dt1b", 0x24, 1, -1, -1, "T/C 1 dead-time register B"}, + {"tc1.dt1a", 0x25, 1, -1, -1, "T/C 1 dead-time register A"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x27, 1, -1, -1, "PLL control and status register"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x29, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tccr0a", 0x2a, 1, -1, -1, "T/C 0 control register A"}, + {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc0.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.ocr1c", 0x2d, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny48 +const Register_file_t rgftab_attiny48[74] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porta.pina", 0x0c, 1, 0x0f, -1, "port A input register"}, + {"porta.ddra", 0x0d, 1, 0x0f, -1, "port A data direction register"}, + {"porta.porta", 0x0e, 1, 0x0f, -1, "port A data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0x3f, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sph", 0x3e, 1, 0x01, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk3", 0x4a, 1, -1, -1, "pin change interrupt mask register 3"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twhsr", 0x9e, 1, -1, -1, "TWHSR register"}, +}; + +// ATtiny84 ATtiny84A +const Register_file_t rgftab_attiny84[55] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny87 ATtiny167 +const Register_file_t rgftab_attiny87[80] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, + {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, +}; + +// ATtiny88 +const Register_file_t rgftab_attiny88[74] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porta.pina", 0x0c, 1, 0x0f, -1, "port A input register"}, + {"porta.ddra", 0x0d, 1, 0x0f, -1, "port A data direction register"}, + {"porta.porta", 0x0e, 1, 0x0f, -1, "port A data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0x3f, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sph", 0x3e, 1, 0x03, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk3", 0x4a, 1, -1, -1, "pin change interrupt mask register 3"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twhsr", 0x9e, 1, -1, -1, "TWHSR register"}, +}; + +// ATtiny261 ATtiny261A +const Register_file_t rgftab_attiny261[63] = { // I/O memory [0, 63] + 32 + {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, + {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, + {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, + {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, + {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, + {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, + {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny461 ATtiny461A +const Register_file_t rgftab_attiny461[63] = { // I/O memory [0, 63] + 32 + {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, + {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, + {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, + {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, + {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, + {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, + {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny828 +const Register_file_t rgftab_attiny828[94] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0xff, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0xff, -1, "PORT B pull-up enable control register"}, + {"portc.pinc", 0x08, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x09, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x0a, 1, 0xff, -1, "port C data register"}, + {"portc.puec", 0x0b, 1, 0xff, -1, "PORT C pull-up enable control register"}, + {"portd.pind", 0x0c, 1, 0x0f, -1, "port D input register"}, + {"portd.ddrd", 0x0d, 1, 0x0f, -1, "port D data direction register"}, + {"portd.portd", 0x0e, 1, 0x0f, -1, "port D data register"}, + {"portd.pued", 0x0f, 1, 0x0f, -1, "PORT D pull-up enable control register"}, + {"portc.phde", 0x14, 1, -1, -1, "port high drive enable register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 1, 0xff, -1, "EEPROM address register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x30, 1, -1, -1, "analog comparator control and status register A"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.ccp", 0x36, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal0", 0x46, 1, 0xff, -1, "oscillator calibration register 8 MHz"}, + {"cpu.osccal1", 0x47, 1, 0x03, -1, "oscillator calibration register 32 kHz"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admuxa", 0x5c, 1, -1, -1, "ADC multiplexer selection register A"}, + {"adc.admuxb", 0x5d, 1, -1, -1, "ADC multiplexer selection register B"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"twi.twscra", 0x98, 1, -1, -1, "TWI peripheral control register A"}, + {"twi.twscrb", 0x99, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twssra", 0x9a, 1, -1, -1, "TWI peripheral status register A"}, + {"twi.twsam", 0x9b, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x9c, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twsd", 0x9d, 1, -1, -1, "TWI peripheral data register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ucsrd", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart.ubrr", 0xa4, 2, 0x0fff, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, + {"adc.didr2", 0xbe, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr3", 0xbf, 1, -1, -1, "digital input disable register 3"}, + {"tocpm.tocpmcoe", 0xc2, 1, -1, -1, "timer output compare pin mux channel output enable register"}, + {"tocpm.tocpmsa0", 0xc8, 1, -1, -1, "timer output compare pin mux selection 0 register"}, + {"tocpm.tocpmsa1", 0xc9, 1, -1, -1, "timer output compare pin mux selection 1 register"}, + {"cpu.osctcal0a", 0xd0, 1, 0xff, -1, "oscillator temperature calibration register A"}, + {"cpu.osctcal0b", 0xd1, 1, 0xff, -1, "oscillator temperature calibration register B"}, +}; + +// ATtiny861 ATtiny861A +const Register_file_t rgftab_attiny861[63] = { // I/O memory [0, 63] + 32 + {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, + {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, + {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, + {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, + {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, + {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, + {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny1634 +const Register_file_t rgftab_attiny1634[89] = { // I/O memory [0, 223] + 32 + {"adc.adc", 0x00, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsrb", 0x02, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x03, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x04, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsrb", 0x05, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x06, 1, -1, -1, "analog comparator control and status register A"}, + {"portc.pinc", 0x07, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x08, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x09, 1, 0x3f, -1, "port C data register"}, + {"portc.puec", 0x0a, 1, -1, -1, "PORT C pull-up enable control register"}, + {"portb.pinb", 0x0b, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x0c, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x0d, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x0e, 1, -1, -1, "PORT B pull-up enable control register"}, + {"porta.pina", 0x0f, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x10, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x11, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x12, 1, -1, -1, "PORT A pull-up enable control register"}, + {"porta.portcr", 0x13, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x13, 1, -1, -1, "port control register"}, + {"portc.portcr", 0x13, 1, -1, -1, "port control register"}, + {"cpu.gpior0", 0x14, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x15, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x16, 1, 0xff, -1, "general purpose I/O register 2"}, + {"tc0.ocr0b", 0x17, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x18, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0", 0x19, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x1a, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x1b, 1, -1, -1, "T/C 0 control register A"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart0.udr0", 0x20, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart0.ubrr0", 0x21, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.ucsr0d", 0x23, 1, -1, -1, "USART control and status register D"}, + {"usart0.ucsr0c", 0x24, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0b", 0x25, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x26, 1, -1, -1, "USART 0 control and status register A"}, + {"exint.pcmsk0", 0x27, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x28, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x29, 1, -1, -1, "pin change interrupt mask register 2"}, + {"usi.usicr", 0x2a, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x2b, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x2c, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x2d, 1, 0xff, -1, "USI buffer register"}, + {"cpu.ccp", 0x2f, 1, 0xff, -1, "configuration change protection register"}, + {"wdt.wdtcsr", 0x30, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clksr", 0x32, 1, -1, -1, "clock setting register"}, + {"cpu.clkpr", 0x33, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x34, 1, -1, -1, "power reduction register"}, + {"cpu.mcusr", 0x35, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x36, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x39, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x39, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x3a, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x3a, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3b, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3c, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"adc.didr0", 0x40, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x41, 1, -1, -1, "digital input disable register 1"}, + {"adc.didr2", 0x42, 1, -1, -1, "digital input disable register 2"}, + {"cpu.osccal0", 0x43, 1, 0xff, -1, "oscillator calibration 0 register"}, + {"cpu.osctcal0a", 0x44, 1, 0xff, -1, "oscillator temperature calibration register A"}, + {"cpu.osctcal0b", 0x45, 1, 0xff, -1, "oscillator temperature calibration register B"}, + {"cpu.osccal1", 0x46, 1, 0x03, -1, "oscillator calibration 1 register"}, + {"tc0.gtccr", 0x47, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x47, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x48, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x4a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x4c, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x4e, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1c", 0x50, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tccr1b", 0x51, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x52, 1, -1, -1, "T/C 1 control register A"}, + {"usart1.udr1", 0x53, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ubrr1", 0x54, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.ucsr1d", 0x56, 1, -1, -1, "USART control and status register D"}, + {"usart1.ucsr1c", 0x57, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1b", 0x58, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x59, 1, -1, -1, "USART 1 control and status register A"}, + {"twi.twsd", 0x5a, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x5b, 1, 0xff, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x5c, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x5d, 1, -1, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x5e, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x5f, 1, -1, -1, "TWI peripheral control register A"}, +}; + +// ATtiny2313 +const Register_file_t rgftab_attiny2313[54] = { // I/O memory [0, 63] + 32 + {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, + {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"cpu.pcmsk", 0x20, 1, 0xff, -1, "pin change interrupt mask register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x3a, 1, -1, -1, "external interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny2313A +const Register_file_t rgftab_attiny2313a[58] = { // I/O memory [0, 63] + 32 + {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, + {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, + {"exint.pcmsk1", 0x04, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x05, 1, -1, -1, "pin change interrupt mask register 2"}, + {"cpu.prr", 0x06, 1, -1, -1, "power reduction register"}, + {"cpu.bodcr", 0x07, 1, -1, -1, "BOD control register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"exint.pcmsk0", 0x20, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny4313 +const Register_file_t rgftab_attiny4313[58] = { // I/O memory [0, 63] + 32 + {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, + {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, + {"exint.pcmsk1", 0x04, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x05, 1, -1, -1, "pin change interrupt mask register 2"}, + {"cpu.prr", 0x06, 1, -1, -1, "power reduction register"}, + {"cpu.bodcr", 0x07, 1, -1, -1, "BOD control register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"exint.pcmsk0", 0x20, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega8 ATmega8A +const Register_file_t rgftab_atmega8[61] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0x7f, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega8HVA ATmega16HVA +const Register_file_t rgftab_atmega8hva[74] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0x03, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0x03, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0x03, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0x0f, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x01, -1, "port C input register"}, + {"portc.portc", 0x08, 1, 0x01, -1, "port C data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.osicsr", 0x17, 1, -1, -1, "oscillator sampling interface control and status register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 1, 0xff, -1, "EEPROM address register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, + {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, + {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, + {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"voltage_regulator.rocr", 0xa8, 1, -1, -1, "regulator operating condition register"}, + {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, + {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, + {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadcsra", 0xc4, 1, -1, -1, "CC-ADC control and status register A"}, + {"coulomb_counter.cadcsrb", 0xc5, 1, -1, -1, "CC-ADC control and status register B"}, + {"coulomb_counter.cadrc", 0xc6, 1, 0xff, -1, "CC-ADC regular current register"}, + {"coulomb_counter.cadic", 0xc8, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, + {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, + {"battery_protection.bpimsk", 0xd2, 1, -1, -1, "battery protection interrupt mask register"}, + {"battery_protection.bpifr", 0xd3, 1, -1, -1, "battery protection interrupt flag register"}, + {"battery_protection.bpscd", 0xd5, 1, 0xff, -1, "battery protection short-circuit detection level register"}, + {"battery_protection.bpdocd", 0xd6, 1, 0xff, -1, "battery protection discharge-over-current detection level register"}, + {"battery_protection.bpcocd", 0xd7, 1, 0xff, -1, "battery protection charge-over-current detection level register"}, + {"battery_protection.bpdhcd", 0xd8, 1, 0xff, -1, "battery protection discharge-high-current detection level register"}, + {"battery_protection.bpchcd", 0xd9, 1, 0xff, -1, "battery protection charge-high-current detection level register"}, + {"battery_protection.bpsctr", 0xda, 1, 0x7f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpoctr", 0xdb, 1, 0x3f, -1, "battery protection over-current timing register"}, + {"battery_protection.bphctr", 0xdc, 1, 0x3f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpcr", 0xdd, 1, -1, -1, "battery protection control register"}, + {"battery_protection.bpplr", 0xde, 1, -1, -1, "battery protection parameter lock register"}, +}; + +// ATmega8U2 ATmega16U2 ATmega32U2 +const Register_file_t rgftab_atmega8u2[92] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, -1, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, -1, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"wdt.wdtckd", 0x42, 1, -1, -1, "watchdog timer clock divider register"}, + {"usb_device.regcr", 0x43, 1, -1, -1, "regulator control register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ac.acmux", 0x5d, 1, -1, -1, "analog comparator input multiplexer register"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"cpu.clksel0", 0xb0, 1, -1, -1, "clock selection register 0"}, + {"cpu.clksel1", 0xb1, 1, -1, -1, "clock selection register 1"}, + {"cpu.clksta", 0xb2, 1, -1, -1, "clock status register"}, + {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.ueint", 0xd4, 1, 0x1f, -1, "USB endpoint number interrupt register"}, + {"usb_device.upoe", 0xdb, 1, -1, -1, "USB software output enable register"}, +}; + +// ATmega16 +const Register_file_t rgftab_atmega16[70] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega16A +const Register_file_t rgftab_atmega16a[70] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x8f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega16U4 ATmega32U4 +const Register_file_t rgftab_atmega16u4[139] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xc0, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xc0, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xc0, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x44, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x44, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x44, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xf3, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xf3, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xf3, -1, "port F data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"pll.pllfrq", 0x32, 1, -1, -1, "PLL frequency control register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.rcctrl", 0x47, 1, -1, -1, "oscillator control register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x5d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"tc4.tcnt4", 0x9e, 1, 0xff, -1, "timer/counter 4"}, + {"tc4.tc4h", 0x9f, 1, 0x07, -1, "timer/counter 4 high byte"}, + {"tc4.tccr4a", 0xa0, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0xa1, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0xa2, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tccr4d", 0xa3, 1, -1, -1, "T/C 4 control register D"}, + {"tc4.tccr4e", 0xa4, 1, -1, -1, "T/C 4 control register E"}, + {"cpu.clksel0", 0xa5, 1, -1, -1, "clock selection register 0"}, + {"cpu.clksel1", 0xa6, 1, -1, -1, "clock selection register 1"}, + {"cpu.clksta", 0xa7, 1, -1, -1, "clock status register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"tc4.ocr4a", 0xaf, 1, 0xff, -1, "T/C 4 output compare register A"}, + {"tc4.ocr4b", 0xb0, 1, 0xff, -1, "T/C 4 output compare register B"}, + {"tc4.ocr4c", 0xb1, 1, 0xff, -1, "T/C 4 output compare register C"}, + {"tc4.ocr4d", 0xb2, 1, 0xff, -1, "T/C 4 output compare register D"}, + {"tc4.dt4", 0xb4, 1, -1, -1, "T/C 4 dead-time register"}, + {"usb_device.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, + {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_device.usbsta", 0xb9, 1, -1, -1, "USB status register"}, + {"usb_device.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, -1, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, + {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, +}; + +// ATmega32 +const Register_file_t rgftab_atmega32[68] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, 0x07, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega32A +const Register_file_t rgftab_atmega32a[66] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, 0x07, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega32C1 +const Register_file_t rgftab_atmega32c1[117] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// ATmega48 ATmega48P +const Register_file_t rgftab_atmega48[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega48A ATmega48PA +const Register_file_t rgftab_atmega48a[82] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"eeprom.eearh", 0x22, 1, 0x03, -1, "EEPROM address register high byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega48PB +const Register_file_t rgftab_atmega48pb[95] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"deviceid.devid0", 0xd0, 1, -1, -1, "device ID byte 0"}, + {"deviceid.devid1", 0xd1, 1, -1, -1, "device ID byte 1"}, + {"deviceid.devid2", 0xd2, 1, -1, -1, "device ID byte 2"}, + {"deviceid.devid3", 0xd3, 1, -1, -1, "device ID byte 3"}, + {"deviceid.devid4", 0xd4, 1, -1, -1, "device ID byte 4"}, + {"deviceid.devid5", 0xd5, 1, -1, -1, "device ID byte 5"}, + {"deviceid.devid6", 0xd6, 1, -1, -1, "device ID byte 6"}, + {"deviceid.devid7", 0xd7, 1, -1, -1, "device ID byte 7"}, + {"deviceid.devid8", 0xd8, 1, -1, -1, "device ID byte 8"}, +}; + +// ATmega64 ATmega64A +const Register_file_t rgftab_atmega64[103] = { // I/O memory [0, 223] + 32 + {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, + {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, + {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, + {"cpu.xdiv", 0x3c, 1, -1, -1, "XTAL divide control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, + {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, + {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, + {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, + {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, + {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, + {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, + {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, + {"adc.adcsrb", 0x6e, 1, -1, -1, "ADC control and status register B"}, + {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, + {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, +}; + +// ATmega64C1 +const Register_file_t rgftab_atmega64c1[122] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dacl", 0x71, 1, -1, -1, "DAC data register low byte"}, + {"dac.dach", 0x72, 1, -1, -1, "DAC data register high byte"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantiml", 0xc6, 1, 0xff, -1, "CAN timer low byte"}, + {"can.cantimh", 0xc7, 1, 0xff, -1, "CAN timer high byte"}, + {"can.canttcl", 0xc8, 1, 0xff, -1, "CAN TTC timer low byte"}, + {"can.canttch", 0xc9, 1, 0xff, -1, "CAN TTC timer high byte"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstml", 0xd8, 1, 0xff, -1, "CAN time stamp register low byte"}, + {"can.canstmh", 0xd9, 1, 0xff, -1, "CAN time stamp register high byte"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// ATmega64M1 +const Register_file_t rgftab_atmega64m1[136] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"psc.pocr0sa", 0x80, 2, 0x0fff, -1, "PSC module 0 output compare SA register (16 bits)"}, + {"psc.pocr0ra", 0x82, 2, 0x0fff, -1, "PSC module 0 output compare RA register (16 bits)"}, + {"psc.pocr0sb", 0x84, 2, 0x0fff, -1, "PSC module 0 output compare SB register (16 bits)"}, + {"psc.pocr1sa", 0x86, 2, 0x0fff, -1, "PSC module 1 output compare SA register (16 bits)"}, + {"psc.pocr1ra", 0x88, 2, 0x0fff, -1, "PSC module 1 output compare RA register (16 bits)"}, + {"psc.pocr1sb", 0x8a, 2, 0x0fff, -1, "PSC module 1 output compare SB register (16 bits)"}, + {"psc.pocr2sa", 0x8c, 2, 0x0fff, -1, "PSC module 2 output compare SA register (16 bits)"}, + {"psc.pocr2ra", 0x8e, 2, 0x0fff, -1, "PSC module 2 output compare RA register (16 bits)"}, + {"psc.pocr2sb", 0x90, 2, 0x0fff, -1, "PSC module 2 output compare SB register (16 bits)"}, + {"psc.pocr_rb", 0x92, 2, 0x0fff, -1, "PSC output compare RB register (16 bits)"}, + {"psc.psync", 0x94, 1, -1, -1, "PSC synchro configuration register"}, + {"psc.pcnf", 0x95, 1, -1, -1, "PSC configuration register"}, + {"psc.poc", 0x96, 1, -1, -1, "PSC output configuration register"}, + {"psc.pctl", 0x97, 1, -1, -1, "PSC control register"}, + {"psc.pmic0", 0x98, 1, -1, -1, "PSC module 0 input control register"}, + {"psc.pmic1", 0x99, 1, -1, -1, "PSC module 1 input control register"}, + {"psc.pmic2", 0x9a, 1, -1, -1, "PSC module 2 input control register"}, + {"psc.pim", 0x9b, 1, -1, -1, "PSC interrupt mask register"}, + {"psc.pifr", 0x9c, 1, -1, -1, "PSC interrupt flag register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// ATmega64HVE2 +const Register_file_t rgftab_atmega64hve2[89] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0x03, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0x03, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0x03, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"wakeup_timer.wutcsr", 0x42, 1, -1, -1, "wake-up timer control and status register"}, + {"wdt.wdtclr", 0x43, 1, -1, -1, "watchdog timer configuration lock register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.sosccala", 0x46, 1, 0xff, -1, "slow oscillator calibration register A"}, + {"cpu.sosccalb", 0x47, 1, 0xff, -1, "oscillator calibration register B"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0x03, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"linuart.lincr", 0xa0, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa1, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xa2, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xa3, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xa4, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xa5, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xa6, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xa7, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xa8, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xa9, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xaa, 1, -1, -1, "LIN data register"}, + {"bandgap.bgcsra", 0xb1, 1, -1, -1, "bandgap control and status register A"}, + {"bandgap.bgcrb", 0xb2, 1, -1, -1, "bandgap calibration register B"}, + {"bandgap.bgcra", 0xb3, 1, -1, -1, "bandgap calibration register A"}, + {"bandgap.bglr", 0xb4, 1, -1, -1, "band gap lock register"}, + {"cpu.pllcsr", 0xb8, 1, -1, -1, "PLL control and status register"}, + {"portb.pbov", 0xbc, 1, -1, -1, "port B override register"}, + {"adc.adscsra", 0xc0, 1, -1, -1, "ADC synchronization control and status register A"}, + {"adc.adscsrb", 0xc1, 1, -1, -1, "ADC synchronization control and status register B"}, + {"adc.adcra", 0xc2, 1, -1, -1, "ADC control register A"}, + {"adc.adcrb", 0xc3, 1, -1, -1, "ADC control register B"}, + {"adc.adcrc", 0xc4, 1, -1, -1, "ADC control register B"}, + {"adc.adcrd", 0xc5, 1, -1, -1, "ADC control register D"}, + {"adc.adcre", 0xc6, 1, -1, -1, "ADC control register E"}, + {"adc.adifr", 0xc7, 1, -1, -1, "ADC interrupt flag register"}, + {"adc.adimr", 0xc8, 1, -1, -1, "ADC interrupt mask register"}, + {"adc.cadrcl", 0xc9, 2, 0xffff, -1, "CC-ADC regulator current comparator threshold level register (16 bits)"}, + {"adc.cadic", 0xcb, 2, 0xffff, -1, "C-ADC instantaneous conversion result register (16 bits)"}, + {"adc.cadac0", 0xcd, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.cadac1", 0xce, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.cadac2", 0xcf, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.cadac3", 0xd0, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.vadic", 0xd1, 2, 0xffff, -1, "V-ADC instantaneous conversion result register (16 bits)"}, + {"adc.vadac0", 0xd3, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, + {"adc.vadac1", 0xd4, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, + {"adc.vadac2", 0xd5, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, + {"adc.vadac3", 0xd6, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, +}; + +// ATmega64RFR2 ATmega644RFR2 +const Register_file_t rgftab_atmega64rfr2[269] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA +const Register_file_t rgftab_atmega88[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega88PB ATmega168PB +const Register_file_t rgftab_atmega88pb[95] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"deviceid.devid0", 0xd0, 1, -1, -1, "device ID byte 0"}, + {"deviceid.devid1", 0xd1, 1, -1, -1, "device ID byte 1"}, + {"deviceid.devid2", 0xd2, 1, -1, -1, "device ID byte 2"}, + {"deviceid.devid3", 0xd3, 1, -1, -1, "device ID byte 3"}, + {"deviceid.devid4", 0xd4, 1, -1, -1, "device ID byte 4"}, + {"deviceid.devid5", 0xd5, 1, -1, -1, "device ID byte 5"}, + {"deviceid.devid6", 0xd6, 1, -1, -1, "device ID byte 6"}, + {"deviceid.devid7", 0xd7, 1, -1, -1, "device ID byte 7"}, + {"deviceid.devid8", 0xd8, 1, -1, -1, "device ID byte 8"}, +}; + +// ATmega128 +const Register_file_t rgftab_atmega128[103] = { // I/O memory [0, 223] + 32 + {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, + {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, + {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.xdiv", 0x3c, 1, -1, -1, "XTAL divide control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, + {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, + {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, + {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, + {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, + {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, + {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, + {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, + {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, + {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, +}; + +// ATmega128A +const Register_file_t rgftab_atmega128a[103] = { // I/O memory [0, 223] + 32 + {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, + {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, + {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.xdiv", 0x3c, 1, 0xff, -1, "XTAL divide control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, + {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, + {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, + {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, + {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, + {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, + {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, + {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, + {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, + {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, +}; + +// ATmega128RFA1 +const Register_file_t rgftab_atmega128rfa1[237] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega128RFR2 ATmega1284RFR2 +const Register_file_t rgftab_atmega128rfr2[270] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega162 +const Register_file_t rgftab_atmega162[79] = { // I/O memory [0, 223] + 32 + {"usart1.ubrr1l", 0x00, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x01, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x02, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x03, 1, 0xff, -1, "USART 1 I/O data register"}, + {"cpu.osccal", 0x04, 1, 0x7f, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x04, 1, -1, -1, "on-chip debug register"}, + {"porte.pine", 0x05, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x06, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x07, 1, 0x07, -1, "port E data register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart0.ubrr0h", 0x20, 1, 0x8f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x20, 1, -1, -1, "USART 0 control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.ocr2", 0x22, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x23, 1, 0xff, -1, "timer/counter 2"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc2.assr", 0x26, 1, -1, -1, "asynchronous status register"}, + {"tc2.tccr2", 0x27, 1, -1, -1, "T/C 2 control register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, + {"exint.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, + {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"usart1.ubrr1h", 0x3c, 1, 0x8f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ucsr1c", 0x3c, 1, -1, -1, "USART control and status register C"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, +}; + +// ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA +const Register_file_t rgftab_atmega164a[96] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"spi.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, +}; + +// ATmega165A ATmega165P ATmega165PA +const Register_file_t rgftab_atmega165a[86] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega169A ATmega169P ATmega169PA +const Register_file_t rgftab_atmega169a[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega256RFR2 +const Register_file_t rgftab_atmega256rfr2[271] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega324PB +const Register_file_t rgftab_atmega324pb[134] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x7f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x7f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x7f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi0.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi0.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi0.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cfd.xfdcsr", 0x42, 1, -1, -1, "XOSC failure detection control and status register"}, + {"cpu.prr2", 0x43, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"exint.pcmsk4", 0x55, 1, -1, -1, "pin change interrupt mask register 4"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc4.tccr4a", 0x80, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x81, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x82, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x84, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x86, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x88, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x8a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"spi1.spcr1", 0x8c, 1, -1, -1, "SPI control register"}, + {"spi1.spsr1", 0x8d, 1, -1, -1, "SPI status register"}, + {"spi1.spdr1", 0x8e, 1, 0xff, -1, "SPI data register"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi0.twbr0", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi0.twsr0", 0x99, 1, -1, -1, "TWI status register"}, + {"twi0.twar0", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi0.twdr0", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi0.twcr0", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi0.twamr0", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart2.ucsr2a", 0xb0, 1, -1, -1, "USART control and status register A"}, + {"usart2.ucsr2b", 0xb1, 1, -1, -1, "USART control and status register B"}, + {"usart2.ucsr2c", 0xb2, 1, -1, -1, "USART control and status register C"}, + {"usart2.ucsr2d", 0xb3, 1, -1, -1, "USART control and status register D"}, + {"usart2.ubrr2", 0xb4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, + {"usart2.udr2", 0xb6, 1, 0xff, -1, "USART 2 I/O data register"}, + {"twi1.twbr1", 0xb8, 1, 0xff, -1, "TWI bit rate register"}, + {"twi1.twsr1", 0xb9, 1, -1, -1, "TWI status register"}, + {"twi1.twar1", 0xba, 1, -1, -1, "TWI peripheral address register"}, + {"twi1.twdr1", 0xbb, 1, 0xff, -1, "TWI data register"}, + {"twi1.twcr1", 0xbc, 1, -1, -1, "TWI control register"}, + {"twi1.twamr1", 0xbd, 1, -1, -1, "TWI peripheral address mask register"}, +}; + +// ATmega325 ATmega325A ATmega325P ATmega325PA +const Register_file_t rgftab_atmega325[86] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega329 +const Register_file_t rgftab_atmega329[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega329A ATmega329PA +const Register_file_t rgftab_atmega329a[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega329P +const Register_file_t rgftab_atmega329p[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega406 +const Register_file_t rgftab_atmega406[79] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.portc", 0x08, 1, 0x01, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0x03, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0x03, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0x03, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"wakeup_timer.wutcsr", 0x42, 1, -1, -1, "wake-up timer control and status register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, + {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, + {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, + {"cpu.didr0", 0x5e, 1, 0x0f, -1, "digital input disable register 0"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1al", 0x68, 1, 0xff, -1, "output compare 1 register A low byte"}, + {"tc1.ocr1ah", 0x69, 1, 0xff, -1, "output compare 1 register A high byte"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twbcsr", 0x9e, 1, -1, -1, "TWI bus control and status register"}, + {"cpu.ccsr", 0xa0, 1, -1, -1, "clock control and status register"}, + {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, + {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, + {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadcsra", 0xc4, 1, -1, -1, "CC-ADC control and status register A"}, + {"coulomb_counter.cadcsrb", 0xc5, 1, -1, -1, "CC-ADC control and status register B"}, + {"coulomb_counter.cadrcc", 0xc6, 1, 0xff, -1, "CC-ADC regular charge current register"}, + {"coulomb_counter.cadrdc", 0xc7, 1, 0xff, -1, "CC-ADC regular discharge current register"}, + {"coulomb_counter.cadic", 0xc8, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, + {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, + {"cell_balancing.cbcr", 0xd1, 1, -1, -1, "cell balancing control register"}, + {"battery_protection.bpir", 0xd2, 1, -1, -1, "battery protection interrupt register"}, + {"battery_protection.bpduv", 0xd3, 1, -1, -1, "battery protection deep under voltage register"}, + {"battery_protection.bpscd", 0xd4, 1, -1, -1, "battery protection short-circuit detection level register"}, + {"battery_protection.bpocd", 0xd5, 1, -1, -1, "battery protection overcurrent detection level register"}, + {"battery_protection.cbptr", 0xd6, 1, -1, -1, "current battery protection timing register"}, + {"battery_protection.bpcr", 0xd7, 1, -1, -1, "battery protection control register"}, + {"battery_protection.bpplr", 0xd8, 1, -1, -1, "battery protection parameter lock register"}, +}; + +// ATmega640 +const Register_file_t rgftab_atmega640[160] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart2.ucsr2a", 0x0b0, 1, -1, -1, "USART control and status register A"}, + {"usart2.ucsr2b", 0x0b1, 1, -1, -1, "USART control and status register B"}, + {"usart2.ucsr2c", 0x0b2, 1, -1, -1, "USART control and status register C"}, + {"usart2.ubrr2", 0x0b4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, + {"usart2.udr2", 0x0b6, 1, 0xff, -1, "USART 2 I/O data register"}, + {"porth.pinh", 0x0e0, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0x0e1, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0x0e2, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0x0e3, 1, 0xff, -1, "PORT J input register"}, + {"portj.ddrj", 0x0e4, 1, 0xff, -1, "PORT J data direction register"}, + {"portj.portj", 0x0e5, 1, 0xff, -1, "PORT J data register"}, + {"portk.pink", 0x0e6, 1, 0xff, -1, "PORT K input register"}, + {"portk.ddrk", 0x0e7, 1, 0xff, -1, "PORT K data direction register"}, + {"portk.portk", 0x0e8, 1, 0xff, -1, "PORT K data register"}, + {"portl.pinl", 0x0e9, 1, 0xff, -1, "PORT L input register"}, + {"portl.ddrl", 0x0ea, 1, 0xff, -1, "PORT L data direction register"}, + {"portl.portl", 0x0eb, 1, 0xff, -1, "PORT L data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"usart3.ucsr3a", 0x110, 1, -1, -1, "USART control and status register A"}, + {"usart3.ucsr3b", 0x111, 1, -1, -1, "USART control and status register B"}, + {"usart3.ucsr3c", 0x112, 1, -1, -1, "USART control and status register C"}, + {"usart3.ubrr3", 0x114, 2, 0x0fff, -1, "USART 3 baud rate register (16 bits)"}, + {"usart3.udr3", 0x116, 1, 0xff, -1, "USART 3 I/O data register"}, +}; + +// ATmega644 +const Register_file_t rgftab_atmega644[88] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega644A ATmega644P ATmega644PA +const Register_file_t rgftab_atmega644a[93] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, +}; + +// ATmega645 ATmega645A ATmega645P +const Register_file_t rgftab_atmega645[86] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega649 ATmega649A ATmega649P +const Register_file_t rgftab_atmega649[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega1280 ATmega2560 +const Register_file_t rgftab_atmega1280[161] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart2.ucsr2a", 0x0b0, 1, -1, -1, "USART control and status register A"}, + {"usart2.ucsr2b", 0x0b1, 1, -1, -1, "USART control and status register B"}, + {"usart2.ucsr2c", 0x0b2, 1, -1, -1, "USART control and status register C"}, + {"usart2.ubrr2", 0x0b4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, + {"usart2.udr2", 0x0b6, 1, 0xff, -1, "USART 2 I/O data register"}, + {"porth.pinh", 0x0e0, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0x0e1, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0x0e2, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0x0e3, 1, 0xff, -1, "PORT J input register"}, + {"portj.ddrj", 0x0e4, 1, 0xff, -1, "PORT J data direction register"}, + {"portj.portj", 0x0e5, 1, 0xff, -1, "PORT J data register"}, + {"portk.pink", 0x0e6, 1, 0xff, -1, "PORT K input register"}, + {"portk.ddrk", 0x0e7, 1, 0xff, -1, "PORT K data direction register"}, + {"portk.portk", 0x0e8, 1, 0xff, -1, "PORT K data register"}, + {"portl.pinl", 0x0e9, 1, 0xff, -1, "PORT L input register"}, + {"portl.ddrl", 0x0ea, 1, 0xff, -1, "PORT L data direction register"}, + {"portl.portl", 0x0eb, 1, 0xff, -1, "PORT L data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"usart3.ucsr3a", 0x110, 1, -1, -1, "USART control and status register A"}, + {"usart3.ucsr3b", 0x111, 1, -1, -1, "USART control and status register B"}, + {"usart3.ucsr3c", 0x112, 1, -1, -1, "USART control and status register C"}, + {"usart3.ubrr3", 0x114, 2, 0x0fff, -1, "USART 3 baud rate register (16 bits)"}, + {"usart3.udr3", 0x116, 1, 0xff, -1, "USART 3 I/O data register"}, +}; + +// ATmega1281 +const Register_file_t rgftab_atmega1281[138] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, +}; + +// ATmega1284 ATmega1284P +const Register_file_t rgftab_atmega1284[104] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, +}; + +// ATmega2561 +const Register_file_t rgftab_atmega2561[139] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, +}; + +// ATmega2564RFR2 +const Register_file_t rgftab_atmega2564rfr2[271] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega3250 ATmega3250A ATmega3250P ATmega3250PA +const Register_file_t rgftab_atmega3250[94] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, +}; + +// ATmega3290 ATmega3290A +const Register_file_t rgftab_atmega3290[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr04", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr09", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega3290P +const Register_file_t rgftab_atmega3290p[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr04", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr09", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega3290PA +const Register_file_t rgftab_atmega3290pa[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr4", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr9", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega6450 ATmega6450A ATmega6450P +const Register_file_t rgftab_atmega6450[94] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, +}; + +// ATmega6490 ATmega6490A ATmega6490P +const Register_file_t rgftab_atmega6490[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr4", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr9", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega8535 +const Register_file_t rgftab_atmega8535[67] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// AT90PWM1 +const Register_file_t rgftab_at90pwm1[92] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, 0x9f, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, -1, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, 0x0fff, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM2B +const Register_file_t rgftab_at90pwm2b[100] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM3 +const Register_file_t rgftab_at90pwm3[115] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, -1, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, -1, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, + {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x0fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.ocr1sa", 0xc2, 2, 0x0fff, -1, "T/C 1 output compare SA register (16 bits)"}, + {"psc1.ocr1ra", 0xc4, 2, 0x0fff, -1, "T/C 1 output compare RA register (16 bits)"}, + {"psc1.ocr1sb", 0xc6, 2, 0x0fff, -1, "T/C 1 output compare SB register (16 bits)"}, + {"psc1.ocr1rb", 0xc8, 2, 0xffff, -1, "T/C 1 output compare RB register (16 bits)"}, + {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, 0x0fff, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM3B +const Register_file_t rgftab_at90pwm3b[115] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, -1, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, -1, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, + {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.ocr1sa", 0xc2, 2, -1, -1, "T/C 1 output compare SA register (16 bits)"}, + {"psc1.ocr1ra", 0xc4, 2, -1, -1, "T/C 1 output compare RA register (16 bits)"}, + {"psc1.ocr1sb", 0xc6, 2, -1, -1, "T/C 1 output compare SB register (16 bits)"}, + {"psc1.ocr1rb", 0xc8, 2, -1, -1, "T/C 1 output compare RB register (16 bits)"}, + {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, -1, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM161 +const Register_file_t rgftab_at90pwm161[86] = { // I/O memory [0, 223] + 32 + {"ac.acsr", 0x00, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.timsk1", 0x01, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc1.tifr1", 0x02, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x07, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x08, 1, -1, -1, "ADC multiplexer selection register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"psc0.pim0", 0x0f, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc0.pifr0", 0x10, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pcnf0", 0x11, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0x12, 1, -1, -1, "PSC 0 control register"}, + {"psc2.pim2", 0x13, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"psc2.pifr2", 0x14, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pcnf2", 0x15, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0x16, 1, -1, -1, "PSC 2 control register"}, + {"spi.spcr", 0x17, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x18, 1, -1, -1, "SPI status register"}, + {"cpu.gpior0", 0x19, 1, -1, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x1a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1b, 1, -1, -1, "general purpose I/O register 2"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.eifr", 0x20, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x21, 1, -1, -1, "external interrupt mask register"}, + {"psc0.ocr0sb", 0x22, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0x24, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc2.ocr2sb", 0x26, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0x28, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc0.ocr0ra", 0x2a, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"adc.adc", 0x2c, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"psc2.ocr2ra", 0x2e, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"spi.spdr", 0x36, 1, 0xff, -1, "SPI data register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"dac.dacl", 0x38, 1, -1, -1, "DAC data register low byte"}, + {"dac.dach", 0x39, 1, -1, -1, "DAC data register high byte"}, + {"tc1.tcnt1", 0x3a, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"psc0.ocr0sa", 0x40, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.pfrc0a", 0x42, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0x43, 1, -1, -1, "PSC 0 input B control register"}, + {"psc2.ocr2sa", 0x44, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.pfrc2a", 0x46, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0x47, 1, -1, -1, "PSC 2 input B control register"}, + {"psc0.picr0", 0x48, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc0.psoc0", 0x4a, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc2.picr2l", 0x4c, 1, 0xff, -1, "PSC 2 input capture register low byte"}, + {"psc2.picr2h", 0x4d, 1, -1, -1, "PSC 2 input capture register high byte"}, + {"psc2.psoc2", 0x4e, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0x4f, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.pcnfe2", 0x50, 1, -1, -1, "PSC 2 enhanced configuration register"}, + {"psc2.pasdly2", 0x51, 1, 0xff, -1, "analog synchronization delay register"}, + {"dac.dacon", 0x56, 1, -1, -1, "DAC control register"}, + {"adc.didr0", 0x57, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x58, 1, -1, -1, "digital input disable register 1"}, + {"adc.amp0csr", 0x59, 1, -1, -1, "amplifier 0 control and status register"}, + {"ac.ac1econ", 0x5a, 1, -1, -1, "analog comparator 1 extended control register"}, + {"ac.ac2econ", 0x5b, 1, -1, -1, "analog comparator 2 extended control register"}, + {"ac.ac3econ", 0x5c, 1, -1, -1, "analog comparator 3 extended control register"}, + {"ac.ac1con", 0x5d, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x5e, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x5f, 1, -1, -1, "analog comparator 3 control register"}, + {"cpu.bgcrr", 0x60, 1, -1, -1, "bandgap resistor calibration register"}, + {"cpu.bgccr", 0x61, 1, -1, -1, "bandgap current calibration register"}, + {"wdt.wdtcsr", 0x62, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x63, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x64, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x65, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x66, 1, -1, -1, "power reduction register"}, + {"cpu.pllcsr", 0x67, 1, -1, -1, "PLL control and status register"}, + {"cpu.osccal", 0x68, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x69, 1, -1, -1, "external interrupt control register A"}, + {"tc1.tccr1b", 0x6a, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.icr1", 0x6c, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, +}; + +// AT90PWM216 +const Register_file_t rgftab_at90pwm216[102] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, 0x8f, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrrl", 0xa4, 1, -1, -1, "USART baud rate register low byte"}, + {"usart.ubrrh", 0xa5, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrrl", 0xac, 1, -1, -1, "manchester receiver baud rate register low byte"}, + {"eusart.mubrrh", 0xad, 1, -1, -1, "manchester receiver baud rate register high byte"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, 0x8fff, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM316 +const Register_file_t rgftab_at90pwm316[117] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, 0x8f, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, + {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrrl", 0xa4, 1, -1, -1, "USART baud rate register low byte"}, + {"usart.ubrrh", 0xa5, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrrl", 0xac, 1, -1, -1, "manchester receiver baud rate register low byte"}, + {"eusart.mubrrh", 0xad, 1, -1, -1, "manchester receiver baud rate register high byte"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.ocr1sa", 0xc2, 2, 0x0fff, -1, "T/C 1 output compare SA register (16 bits)"}, + {"psc1.ocr1ra", 0xc4, 2, 0x0fff, -1, "T/C 1 output compare RA register (16 bits)"}, + {"psc1.ocr1sb", 0xc6, 2, 0x0fff, -1, "T/C 1 output compare SB register (16 bits)"}, + {"psc1.ocr1rb", 0xc8, 2, 0xffff, -1, "T/C 1 output compare RB register (16 bits)"}, + {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, 0x8fff, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, 0x8fff, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90USB646 AT90USB647 AT90USB1287 +const Register_file_t rgftab_at90usb646[157] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"usb_host.uhcon", 0x7e, 1, -1, -1, "UHCON register"}, + {"usb_host.uhint", 0x7f, 1, -1, -1, "UHINT register"}, + {"usb_host.uhien", 0x80, 1, -1, -1, "UHIEN register"}, + {"usb_host.uhaddr", 0x81, 1, 0x7f, -1, "USB host address register"}, + {"usb_host.uhfnum", 0x82, 2, 0x07ff, -1, "UHFNUM register (16 bits)"}, + {"usb_host.uhflen", 0x84, 1, 0xff, -1, "UHFLEN register"}, + {"usb_host.upinrqx", 0x85, 1, 0xff, -1, "UPINRQX register"}, + {"usb_host.upintx", 0x86, 1, -1, -1, "UPINTX register"}, + {"usb_host.upnum", 0x87, 1, 0x07, -1, "UPNUM register"}, + {"usb_host.uprst", 0x88, 1, -1, -1, "UPRST register"}, + {"usb_host.upconx", 0x89, 1, -1, -1, "UPCONX register"}, + {"usb_host.upcfg0x", 0x8a, 1, -1, -1, "UPCFG0X register"}, + {"usb_host.upcfg1x", 0x8b, 1, -1, -1, "UPCFG1X register"}, + {"usb_host.upstax", 0x8c, 1, -1, -1, "UPSTAX register"}, + {"usb_host.upcfg2x", 0x8d, 1, 0xff, -1, "UPCFG2X register"}, + {"usb_host.upienx", 0x8e, 1, -1, -1, "UPIENX register"}, + {"usb_host.updatx", 0x8f, 1, 0xff, -1, "UPDATX register"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usb_global.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, + {"usb_global.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_global.usbsta", 0xb9, 1, -1, -1, "USB status register"}, + {"usb_global.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, + {"usb_global.otgcon", 0xbd, 1, -1, -1, "OTGCON register"}, + {"usb_global.otgien", 0xbe, 1, -1, -1, "OTGIEN register"}, + {"usb_global.otgint", 0xbf, 1, -1, -1, "OTGINT register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, + {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, + {"usb_host.uperrx", 0xd5, 1, -1, -1, "UPERRX register"}, + {"usb_host.upbclx", 0xd6, 1, 0xff, -1, "UPBCLX register"}, + {"usb_host.upbchx", 0xd7, 1, 0x07, -1, "UPBCHX register"}, + {"usb_host.upint", 0xd8, 1, 0x7f, -1, "UPINT register"}, + {"usb_global.otgtcon", 0xd9, 1, -1, -1, "OTGTCON register"}, +}; + +// AT90USB1286 +const Register_file_t rgftab_at90usb1286[132] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usb_global.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, + {"usb_global.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_global.usbsta", 0xb9, 1, -1, -1, "USB status register"}, + {"usb_global.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, + {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, +}; + +// ATA5272 ATA5505 +const Register_file_t rgftab_ata5272[80] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"timer_counter_0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"timer_counter_1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"external_interrupt.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"external_interrupt.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"external_interrupt.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"timer_counter_0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"timer_counter_0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, + {"timer_counter_0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"analog_comparator.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"external_interrupt.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer_counter_0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"timer_counter_1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ad_converter.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, + {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, + {"ad_converter.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"ad_converter.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ad_converter.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, + {"analog_comparator.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, + {"ad_converter.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"ad_converter.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ad_converter.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"timer_counter_1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"timer_counter_1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"timer_counter_1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"timer_counter_1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, + {"timer_counter_1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"timer_counter_1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"timer_counter_1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"timer_counter_1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"timer_counter_0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, +}; + +// ATA5702M322 +const Register_file_t rgftab_ata5702m322[378] = { // I/O memory [0, 479] + 32 + {"gpioregs_dvcc.gpior0", 0x000, 1, 0xff, -1, "general purpose I/O register 0"}, + {"clk.prr1", 0x001, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x002, 1, -1, -1, "power reduction register 2"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0x07, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0x07, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0x07, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"lf_transponder.tpcr2", 0x00c, 1, -1, -1, "transponder control register 2"}, + {"lf_transponder.tpfr", 0x00d, 1, -1, -1, "transponder flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"txdsp.fscr", 0x00f, 1, -1, -1, "frequency synthesizer control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"lf_timer.ltcmr", 0x015, 1, -1, -1, "LF timer control mode register"}, + {"eeprom.eecr2", 0x016, 1, -1, -1, "EEPROM control register 2"}, + {"lf_protocol_handler.phtcr", 0x017, 1, -1, -1, "PH telegram configuration register"}, + {"lf_fifo.ldffl", 0x018, 1, -1, -1, "LF data FIFO fill level register"}, + {"lf_fifo.ldfd", 0x019, 1, 0xff, -1, "LF data FIFO data register"}, + {"clk.prr0", 0x01a, 1, -1, -1, "power reduction register 0"}, + {"lf_protocol_handler.phfr", 0x01b, 1, -1, -1, "protocol handler flag register"}, + {"lf_receiver.lffr", 0x01c, 1, -1, -1, "LF flag register"}, + {"aes.aescr", 0x01d, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x01e, 1, -1, -1, "AES status register"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs_dvcc.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs_dvcc.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"lf_fifo.ldfcksw", 0x029, 1, -1, -1, "LF data FIFO clock switch register"}, + {"sup.vmscr", 0x02a, 1, -1, -1, "voltage monitor status and control register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"lf_receiver.lfcr0", 0x02f, 1, -1, -1, "LF receiver control register 0"}, + {"lf_receiver.lfcr1", 0x030, 1, -1, -1, "LF receiver control register 1"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"timer0_wdt.t0ifr", 0x032, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.smcr", 0x038, 1, -1, -1, "sleep mode control register"}, + {"lf_transponder.tpsr", 0x039, 1, -1, -1, "transponder status register"}, + {"lf_receiver.lfcr2", 0x03a, 1, -1, -1, "LF receiver control register 2"}, + {"lf_receiver.lfcr3", 0x03b, 1, -1, -1, "LF receiver control register 3"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"txdsp.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, + {"txdsp.fsfcr", 0x041, 1, -1, -1, "frequency synthesizer filter control register"}, + {"txdsp.gacdiv", 0x042, 2, 0x1fff, -1, "Gauss clock divider register (16 bits)"}, + {"txdsp.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, + {"txdsp.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, + {"txdsp.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, + {"txdsp.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, + {"txdsp.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, + {"txdsp.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, + {"txdsp.bbte2", 0x04a, 1, -1, -1, "base band test enable 2 register"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5temp", 0x069, 1, 0xff, -1, "timer 5 temp register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"tplf_cal.lfcalr1", 0x070, 1, -1, -1, "LF receiver calibration register 1"}, + {"tplf_cal.lfcalr2", 0x071, 1, -1, -1, "LF receiver calibration register 2"}, + {"tplf_cal.lfcalr3", 0x072, 1, -1, -1, "LF receiver calibration register 3"}, + {"tplf_cal.lfcalr4", 0x073, 1, -1, -1, "LF receiver calibration register 4"}, + {"tplf_cal.lfcalr5", 0x074, 1, -1, -1, "LF receiver calibration register 5"}, + {"tplf_cal.lfcalr6", 0x075, 1, -1, -1, "LF receiver calibration register 6"}, + {"tplf_cal.lfcalr7", 0x076, 1, 0xff, -1, "LF receiver calibration register 7"}, + {"tplf_cal.lfcalr8", 0x077, 1, 0x1f, -1, "LF receiver calibration register 8"}, + {"tplf_cal.lfcalr9", 0x078, 1, 0xff, -1, "LF receiver calibration register 9"}, + {"tplf_cal.lfcalr10", 0x079, 1, 0x7f, -1, "LF receiver calibration register 10"}, + {"tplf_cal.lfcalr11", 0x07a, 1, 0xff, -1, "LF receiver calibration register 11"}, + {"tplf_cal.lfcalr12", 0x07b, 1, 0xff, -1, "LF receiver calibration register 12"}, + {"tplf_cal.lfcalr13", 0x07c, 1, 0xff, -1, "LF receiver calibration register 13"}, + {"tplf_cal.lfcalr14", 0x07d, 1, 0x7f, -1, "LF receiver calibration register 14"}, + {"tplf_cal.lfcalr15", 0x07e, 1, 0xff, -1, "LF receiver calibration register 15"}, + {"tplf_cal.lfcalr16", 0x07f, 1, 0x1f, -1, "LF receiver calibration register 16"}, + {"tplf_cal.lfcalr17", 0x080, 1, 0x1f, -1, "LF receiver calibration register 17"}, + {"tplf_cal.lfcalr18", 0x081, 1, 0xff, -1, "LF receiver calibration register 18"}, + {"tplf_cal.lfcalr19", 0x082, 1, 0x7f, -1, "LF receiver calibration register 19"}, + {"tplf_cal.lfcalr20", 0x083, 1, 0xff, -1, "LF receiver calibration register 20"}, + {"tplf_cal.lfcalr21", 0x084, 1, 0xff, -1, "LF receiver calibration register 21"}, + {"tplf_cal.lfcalr22", 0x085, 1, 0xff, -1, "LF receiver calibration register 22"}, + {"tplf_cal.lfcalr23", 0x086, 1, 0x7f, -1, "LF receiver calibration register 23"}, + {"tplf_cal.lfcalr24", 0x087, 1, 0xff, -1, "LF receiver calibration register 24"}, + {"tplf_cal.lfcalr25", 0x088, 1, 0x1f, -1, "LF receiver calibration register 25"}, + {"tplf_cal.lfcalr26", 0x089, 1, 0x1f, -1, "LF receiver calibration register 26"}, + {"tplf_cal.lfcalr27", 0x08a, 1, 0xff, -1, "LF receiver calibration register 27"}, + {"tplf_cal.lfcalr28", 0x08b, 1, 0x7f, -1, "LF receiver calibration register 28"}, + {"tplf_cal.lfcalr29", 0x08c, 1, 0xff, -1, "LF receiver calibration register 29"}, + {"tplf_cal.lfcalr30", 0x08d, 1, 0xff, -1, "LF receiver calibration register 30"}, + {"tplf_cal.lfcalr31", 0x08e, 1, 0xff, -1, "LF receiver calibration register 31"}, + {"tplf_cal.lfcalr32", 0x08f, 1, 0x7f, -1, "LF receiver calibration register 32"}, + {"tplf_cal.lfcalr33", 0x090, 1, 0xff, -1, "LF receiver calibration register 33"}, + {"tplf_cal.lfcalr34", 0x091, 1, 0x1f, -1, "LF receiver calibration register 34"}, + {"tplf_cal.lfcalr35", 0x092, 1, 0xff, -1, "LF receiver calibration register 35"}, + {"tplf_cal.lfcalr36", 0x093, 1, 0x7f, -1, "LF receiver calibration register 36"}, + {"tplf_cal.lfcalr37", 0x094, 1, 0x3f, -1, "LF receiver calibration register 37"}, + {"tplf_cal.lfcalr38", 0x095, 1, 0x0f, -1, "LF receiver calibration register 38"}, + {"tplf_cal.lfcalr39", 0x096, 1, 0x0f, -1, "LF receiver calibration register 39"}, + {"tplf_cal.lfcalr40", 0x097, 1, 0x0f, -1, "LF receiver calibration register 40"}, + {"tplf_cal.lfcalr41", 0x098, 1, 0xff, -1, "LF receiver calibration register 41"}, + {"tplf_cal.lfcalr42", 0x099, 1, 0xff, -1, "LF receiver calibration register 42"}, + {"tplf_cal.lfcalr43", 0x09a, 1, 0xff, -1, "LF receiver calibration register 43"}, + {"tplf_cal.lfcalr44", 0x09b, 1, 0x3f, -1, "LF receiver calibration register 44"}, + {"tplf_cal.lfcalr45", 0x09c, 1, 0xff, -1, "LF receiver calibration register 45"}, + {"tplf_cal.lfcalr46", 0x09d, 1, 0xff, -1, "LF receiver calibration register 46"}, + {"tplf_cal.lfcalr47", 0x09e, 1, 0xff, -1, "LF receiver calibration register 47"}, + {"tplf_cal.lfcalr48", 0x09f, 1, 0x3f, -1, "LF receiver calibration register 48"}, + {"tplf_cal.lfcalr49", 0x0a0, 1, 0xff, -1, "LF receiver calibration register 49"}, + {"tplf_cal.lfcalr50", 0x0a1, 1, 0xff, -1, "LF receiver calibration register 50"}, + {"tplf_cal.lfcalr51", 0x0a2, 1, 0xff, -1, "LF receiver calibration register 51"}, + {"tplf_cal.lfcalr52", 0x0a3, 1, 0x3f, -1, "LF receiver calibration register 52"}, + {"tplf_cal.lfcalr53", 0x0a4, 1, 0xff, -1, "LF receiver calibration register 53"}, + {"clk.xfuse", 0x0a5, 1, -1, -1, "XFUSE register"}, + {"clk.mrccal", 0x0a6, 1, 0xfe, -1, "middle RC oscillator calibration register"}, + {"clk.frccal", 0x0a7, 1, 0x1f, -1, "fast RC oscillator calibration register"}, + {"sup.rctcal", 0x0a8, 1, -1, -1, "RC oscillator temperature compensation register"}, + {"clk.cmsr", 0x0a9, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0aa, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0ab, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0ac, 1, -1, -1, "supply control register"}, + {"sup.supca1", 0x0ad, 1, -1, -1, "supply calibration register 1"}, + {"sup.supca2", 0x0ae, 1, -1, -1, "supply calibration register 2"}, + {"sup.supca3", 0x0af, 1, -1, -1, "supply calibration register 3"}, + {"sup.supca4", 0x0b0, 1, -1, -1, "supply calibration register 4"}, + {"sup.calrdy", 0x0b1, 1, 0xff, -1, "calibration ready signature register"}, + {"dfifo.dfs", 0x0b2, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dfl", 0x0b5, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0b6, 1, 0x3f, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0b7, 1, 0x3f, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0b8, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0b9, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0ba, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0bb, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0bc, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0bd, 1, 0x1f, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0be, 1, 0x1f, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0bf, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0c0, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0c1, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0c2, 1, -1, -1, "sequencer state machine control register"}, + {"timer5.gtccr", 0x0c3, 1, -1, -1, "general T/C control register"}, + {"ssm.ssmfbr", 0x0c4, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0c5, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0c6, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0c7, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0c8, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0c9, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0ca, 1, -1, -1, "sequencer state machine state register"}, + {"vx_mode.vxmctrl", 0x0cb, 1, -1, -1, "VX mode control register"}, + {"ssm.msmcr1", 0x0cc, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0cd, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0ce, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0cf, 1, -1, -1, "master state machine control register 4"}, + {"spi2.sp2cr", 0x0d7, 1, -1, -1, "SPI 2 control register"}, + {"spi2.sp2dr", 0x0d8, 1, 0xff, -1, "SPI 2 data register"}, + {"spi2.sp2sr", 0x0d9, 1, -1, -1, "SPI 2 status register"}, + {"debug.trcid", 0x0dc, 2, 0xffff, -1, "trace ID register (16 bits)"}, + {"debug.trcdr", 0x0df, 1, 0xff, -1, "trace unit data register"}, + {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, + {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, + {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, + {"fe.felna", 0x0e3, 1, 0xff, -1, "reserved register"}, + {"fe.feat", 0x0e4, 1, -1, -1, "front-end antenna tuning register"}, + {"fe.fepac", 0x0e5, 1, -1, -1, "front-end power amplifier control register"}, + {"fe.fevct", 0x0e6, 1, 0x0f, -1, "front-end VCO tuning register"}, + {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, + {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, + {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, + {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, + {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, + {"fe.fealr", 0x0ec, 1, -1, -1, "front-end antenna level detector range register"}, + {"fe.feant", 0x0ed, 1, -1, -1, "front-end antenna register"}, + {"fe.febia", 0x0ee, 1, 0xff, -1, "reserved register"}, + {"clk.clkod", 0x0f5, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0f6, 1, -1, -1, "clock output control register"}, + {"fe.fete1", 0x0fc, 1, -1, -1, "front-end test enable register 1"}, + {"fe.fete2", 0x0fd, 1, -1, -1, "front-end test enable register 2"}, + {"fe.fete3", 0x0fe, 1, -1, -1, "front-end test enable register 3"}, + {"fe.fetd", 0x0ff, 1, 0xff, -1, "front-end test data register"}, + {"txm.tmfsm", 0x100, 1, -1, -1, "tx modulator finite state machine register"}, + {"txm.tmcrc", 0x101, 2, 0xffff, -1, "tx modulator CRC result register (16 bits)"}, + {"txm.tmcsb", 0x103, 1, 0xff, -1, "tx modulator CRC skip bit number register"}, + {"txm.tmci", 0x104, 2, 0xffff, -1, "tx modulator CRC init value register (16 bits)"}, + {"txm.tmcp", 0x106, 2, 0xffff, -1, "tx modulator CRC polynomial register (16 bits)"}, + {"txm.tmshr", 0x108, 1, 0xff, -1, "tx modulator shift register"}, + {"txm.tmtll", 0x109, 2, 0x0fff, -1, "tx modulator telegram length register (16 bits)"}, + {"txm.tmssc", 0x10b, 1, -1, -1, "tx modulator stop sequence configuration register"}, + {"txm.tmsr", 0x10c, 1, -1, -1, "tx modulator status register"}, + {"txm.tmcr2", 0x10d, 1, -1, -1, "tx modulator control register 2"}, + {"txm.tmcr1", 0x10e, 1, -1, -1, "tx modulator control register 1"}, + {"lf_receiver.lfdsr1", 0x110, 1, -1, -1, "LF decoder setting register 1"}, + {"lf_receiver.lfdsr2", 0x111, 1, -1, -1, "LF decoder setting register 2"}, + {"lf_receiver.lfdsr3", 0x112, 1, -1, -1, "LF decoder setting register 3"}, + {"lf_receiver.lfdsr4", 0x113, 1, -1, -1, "LF decoder setting register 4"}, + {"lf_receiver.lfdsr5", 0x114, 1, -1, -1, "LF decoder setting register 5"}, + {"lf_receiver.lfdsr6", 0x115, 1, -1, -1, "LF decoder setting register 6"}, + {"lf_receiver.lfdsr7", 0x116, 1, -1, -1, "LF decoder setting register 7"}, + {"lf_receiver.lfdsr8", 0x117, 1, -1, -1, "LF decoder setting register 8"}, + {"lf_receiver.lfdsr9", 0x118, 1, -1, -1, "LF decoder setting register 9"}, + {"lf_receiver.lfdsr10", 0x119, 1, -1, -1, "LF decoder setting register 10"}, + {"lf_receiver.lfdsr11", 0x11a, 1, -1, -1, "LF decoder setting register 11"}, + {"eeprom.eepr1", 0x11b, 1, -1, -1, "EEPROM protection register 1"}, + {"eeprom.eepr2", 0x11c, 1, -1, -1, "EEPROM protection register 2"}, + {"eeprom.eepr3", 0x11d, 1, -1, -1, "EEPROM protection register 3"}, + {"crc.crccr", 0x125, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x126, 1, 0xff, -1, "CRC data output register"}, + {"lf_receiver.lfsrctm", 0x131, 1, -1, -1, "LF receiver SRC tuning MSB register"}, + {"debounce.dbcr", 0x132, 1, -1, -1, "debounce control register"}, + {"debounce.dbtc", 0x133, 1, 0xff, -1, "debounce timer compare register"}, + {"debounce.dbenb", 0x134, 1, 0xff, -1, "debounce enable port B register"}, + {"debounce.dbenc", 0x135, 1, 0x07, -1, "debounce enable port C register"}, + {"debug.dbgsw", 0x136, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x137, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x138, 1, -1, -1, "SPI FIFO interrupt register"}, + {"timer2.t2ifr", 0x139, 1, -1, -1, "timer 2 interrupt flag register"}, + {"mem.pgmst", 0x13a, 1, -1, -1, "program memory status register"}, + {"mem.eest", 0x13b, 1, -1, -1, "EEPROM status register"}, + {"lf_receiver.lfsrctl", 0x13c, 1, -1, -1, "LF receiver SRC tuning LSB register"}, + {"int.pcifr", 0x141, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x142, 1, -1, -1, "timer 0 control register"}, + {"debounce.dbend", 0x144, 1, 0xff, -1, "debounce enable port D register"}, + {"lf_transponder.tpcr1", 0x145, 1, -1, -1, "transponder control register 1"}, + {"lf_transponder.tpimr", 0x146, 1, -1, -1, "transponder interrupt mask register"}, + {"lf_transponder.tpdcr1", 0x147, 1, -1, -1, "transponder decoder comparator register 1"}, + {"lf_transponder.tpdcr2", 0x148, 1, -1, -1, "transponder decoder comparator register 2"}, + {"lf_transponder.tpdcr3", 0x149, 1, -1, -1, "transponder decoder comparator register 3"}, + {"lf_transponder.tpdcr4", 0x14a, 1, -1, -1, "transponder decoder comparator register 4"}, + {"lf_transponder.tpdcr5", 0x14b, 1, -1, -1, "transponder decoder comparator register 5"}, + {"lf_transponder.tpecr1", 0x14c, 1, -1, -1, "transponder encoder comparator register 1"}, + {"lf_transponder.tpecr2", 0x14d, 1, -1, -1, "transponder encoder comparator register 2"}, + {"lf_transponder.tpecr3", 0x14e, 1, -1, -1, "transponder encoder comparator register 3"}, + {"lf_transponder.tpecr4", 0x14f, 1, -1, -1, "transponder encoder comparator register 4"}, + {"lf_transponder.tpecmr", 0x150, 1, -1, -1, "transponder encoder mode register"}, + {"lf_transponder.tpcr3", 0x151, 1, -1, -1, "transponder control register 3"}, + {"lf_transponder.tpcr4", 0x152, 1, -1, -1, "transponder control register 4"}, + {"lf_transponder.tpcr5", 0x153, 1, -1, -1, "transponder control register 5"}, + {"tplf_cal.tpcalr1", 0x155, 1, -1, -1, "transponder calibration register 1"}, + {"tplf_cal.tpcalr2", 0x156, 1, -1, -1, "transponder calibration register 2"}, + {"tplf_cal.tpcalr3", 0x157, 1, -1, -1, "transponder calibration register 3"}, + {"tplf_cal.tpcalr4", 0x158, 1, -1, -1, "transponder calibration register 4"}, + {"tplf_cal.tpcalr5", 0x159, 1, 0x0f, -1, "transponder calibration register 5"}, + {"tplf_cal.tpcalr6", 0x15a, 1, 0x1f, -1, "transponder calibration register 6"}, + {"tplf_cal.tpcalr7", 0x15b, 1, 0x07, -1, "transponder calibration register 7"}, + {"tplf_cal.tpcalr8", 0x15c, 1, 0x7f, -1, "transponder calibration register 8"}, + {"tplf_cal.tpcalr9", 0x15d, 1, 0xff, -1, "transponder calibration register 9"}, + {"tplf_cal.tpcalr10", 0x15e, 1, 0x7f, -1, "transponder calibration register 10"}, + {"aes.aesdpr", 0x15f, 1, 0x0f, -1, "AES data pointer register"}, + {"aes.aeskr", 0x160, 1, 0xff, -1, "AES key register"}, + {"aes.aesdr", 0x161, 1, 0xff, -1, "AES data register"}, + {"gpioregs_lfvcc.gpior3", 0x162, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs_lfvcc.gpior4", 0x163, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs_lfvcc.gpior5", 0x164, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs_lfvcc.gpior6", 0x165, 1, 0xff, -1, "general purpose I/O register 6"}, + {"gpioregs_lfvcc.gpior7", 0x166, 1, 0xff, -1, "general purpose I/O register 7"}, + {"gpioregs_lfvcc.gpior8", 0x167, 1, 0xff, -1, "general purpose I/O register 8"}, + {"lf_protocol_handler.phbcrr", 0x168, 1, 0xff, -1, "protocol handler bit counter read register"}, + {"tplf_cal.lfcpr", 0x16e, 1, -1, -1, "LF receiver calibration protect register"}, + {"lf_receiver.lfimr", 0x16f, 1, -1, -1, "LF interrupt mask register"}, + {"lf_protocol_handler.phid0", 0x170, 4, 0xffffffff, -1, "PH ID 0 register (32 bits)"}, + {"lf_protocol_handler.phid0l", 0x174, 1, 0x3f, -1, "PH identifier 0 length register"}, + {"lf_protocol_handler.phid1", 0x175, 4, 0xffffffff, -1, "PH ID 1 register (32 bits)"}, + {"lf_protocol_handler.phid1l", 0x179, 1, 0x3f, -1, "PH identifier 1 length register"}, + {"lf_protocol_handler.phidfr", 0x17a, 1, 0xff, -1, "protocol handler ID frame register"}, + {"lf_receiver.lfsysy", 0x17b, 4, 0xffffffff, -1, "LF receiver synchronization symbols register (32 bits)"}, + {"lf_receiver.lfsyle", 0x17f, 1, -1, -1, "LF receiver synchronization length register"}, + {"lf_receiver.lfstop", 0x180, 1, -1, -1, "LF receiver stop bit register"}, + {"lf_timer.ltcor", 0x181, 1, 0xff, -1, "LF timer compare register"}, + {"timer1.t1ifr", 0x182, 1, -1, -1, "timer 1 interrupt flag register"}, + {"lf_protocol_handler.phtblr", 0x184, 1, 0xff, -1, "protocol handler telegram bit length register"}, + {"lf_protocol_handler.phdfr", 0x185, 1, 0xff, -1, "protocol handler data frame end register"}, + {"lf_timer.ltemr", 0x186, 1, -1, -1, "LF timer event mask register"}, + {"lf_receiver.lfqc3", 0x187, 1, -1, -1, "LF receiver channel 3 quality factor register"}, + {"lf_receiver.lfqc2", 0x188, 1, -1, -1, "LF receiver channel 2 quality factor register"}, + {"lf_receiver.lfqc1", 0x189, 1, -1, -1, "LF receiver channel 1 quality factor register"}, + {"twi2.tw2br", 0x18a, 1, 0xff, -1, "TWI 2 bit rate register"}, + {"twi2.tw2cr", 0x18b, 1, -1, -1, "TWI 2 control register"}, + {"twi2.tw2sr", 0x18c, 1, -1, -1, "TWI 2 status register"}, + {"twi2.tw2dr", 0x18d, 1, 0xff, -1, "TWI 2 data register"}, + {"twi2.tw2ar", 0x18e, 1, -1, -1, "TWI 2 peripheral address register"}, + {"twi2.tw2amr", 0x18f, 1, -1, -1, "TWI 2 address mask register"}, + {"lf_rssi.rscr", 0x190, 1, -1, -1, "RSSI control register"}, + {"lf_rssi.rssr", 0x191, 1, -1, -1, "RSSI status register"}, + {"lf_rssi.rsms1r", 0x192, 1, -1, -1, "RSSI measurement setting 1 register"}, + {"lf_rssi.rsms2r", 0x193, 1, -1, -1, "RSSI measurement setting 2 register"}, + {"lf_rssi.rsfr", 0x194, 1, -1, -1, "RSSI flag register"}, + {"lf_rssi.rscalib", 0x196, 1, -1, -1, "RSSI calibration register"}, + {"lf_rssi.rsdlyr", 0x197, 1, -1, -1, "RSSI delay register"}, + {"lf_rssi.rsres1l", 0x198, 1, -1, -1, "RSSI result 1 low byte register"}, + {"lf_rssi.rsres1h", 0x199, 1, -1, -1, "RSSI result 1 high byte register"}, + {"lf_rssi.rsres2l", 0x19a, 1, -1, -1, "RSSI result 2 low byte register"}, + {"lf_rssi.rsres2h", 0x19b, 1, -1, -1, "RSSI result 2 high byte register"}, + {"lf_rssi.rsres3l", 0x19c, 1, -1, -1, "RSSI result 3 low byte register"}, + {"lf_rssi.rsres3h", 0x19d, 1, -1, -1, "RSSI result 3 high byte register"}, + {"lf_rssi.rsres4l", 0x19e, 1, -1, -1, "RSSI result 4 low byte register"}, + {"lf_rssi.rsres4h", 0x19f, 1, -1, -1, "RSSI result 4 high byte register"}, + {"lf_rssi.rssrcr", 0x1a0, 1, -1, -1, "RSSI SRC calibration register"}, + {"lf_rssi.sd12rr", 0x1a1, 1, -1, -1, "sign detection channel 1 vs 2 result register"}, + {"lf_rssi.sd13rr", 0x1a2, 1, -1, -1, "sign detection channel 1 vs 3 result register"}, + {"lf_rssi.sd23rr", 0x1a3, 1, -1, -1, "sign detection channel 2 vs 3 result register"}, + {"lf_rssi.sd360r", 0x1a4, 1, -1, -1, "sign detection 360 degree result register"}, + {"lf_rssi.rsdbgr", 0x1a5, 1, -1, -1, "RSSI debug register"}, + {"lf_fifo.ldfs", 0x1b1, 1, -1, -1, "LF data FIFO status register"}, + {"timer4.t4ifr", 0x1b2, 1, -1, -1, "timer 4 interrupt flag register"}, + {"lf_fifo.ldfwp", 0x1b3, 1, -1, -1, "LF data FIFO write pointer register"}, + {"lf_fifo.ldfrp", 0x1b4, 1, -1, -1, "LF data FIFO read pointer register"}, + {"timer5.t5ifr", 0x1b5, 1, -1, -1, "timer 5 interrupt flag register"}, + {"lf_fifo.ldfim", 0x1b6, 1, -1, -1, "LF data FIFO interrupt mask register"}, + {"lf_fifo.ldfc", 0x1b7, 1, -1, -1, "LF data FIFO configuration register"}, + {"lf_protocol_handler.phimr", 0x1b8, 1, -1, -1, "protocol handler interrupt mask register"}, + {"lf_protocol_handler.phcrcr", 0x1b9, 1, -1, -1, "protocol handler CRC control register"}, + {"lf_protocol_handler.phcst", 0x1ba, 2, 0xffff, -1, "PH CRC start value register (16 bits)"}, + {"lf_protocol_handler.phcrp", 0x1bc, 2, 0xffff, -1, "PH CRC polynomial register (16 bits)"}, + {"lf_protocol_handler.phcsr", 0x1be, 2, 0xffff, -1, "PH CRC checksum register (16 bits)"}, + {"crc.crcdir", 0x1c0, 1, 0xff, -1, "CRC data input register"}, + {"timer3.t3ifr", 0x1c1, 1, -1, -1, "timer 3 interrupt flag register"}, + {"cpu.cmcr", 0x1c3, 1, -1, -1, "clock management control register"}, + {"cpu.cmimr", 0x1c4, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clpr", 0x1c5, 1, -1, -1, "clock prescaler register"}, + {"sup.vmcr", 0x1c6, 1, -1, -1, "voltage monitor control register"}, + {"debug.dbondr", 0x1c7, 1, -1, -1, "downbond test register"}, + {"sup.calrdylf", 0x1c8, 1, 0xff, -1, "calibration ready signature LFVCC register"}, + {"twi1.tw1br", 0x1c9, 1, 0xff, -1, "TWI 1 bit rate register"}, + {"twi1.tw1cr", 0x1ca, 1, -1, -1, "TWI 1 control register"}, + {"twi1.tw1sr", 0x1cb, 1, -1, -1, "TWI 1 status register"}, + {"twi1.tw1dr", 0x1cc, 1, 0xff, -1, "TWI 1 data register"}, + {"twi1.tw1ar", 0x1cd, 1, -1, -1, "TWI 1 peripheral address register"}, + {"twi1.tw1amr", 0x1ce, 1, -1, -1, "TWI 1 address mask register"}, + {"led.pdscr", 0x1cf, 1, -1, -1, "pad driver strength control register"}, + {"tmo.tmocr", 0x1d0, 1, -1, -1, "timer modulator output control register"}, + {"tplf_cal.srccal", 0x1d1, 1, -1, -1, "slow RC oscillator calibration register"}, + {"tplf_cal.srctcal", 0x1d2, 1, -1, -1, "slow RC oscillator temperature compensation register"}, + {"sup.supca5", 0x1d3, 1, -1, -1, "supply calibration register 5"}, + {"sup.supca6", 0x1d4, 1, -1, -1, "supply calibration register 6"}, + {"sup.supca7", 0x1d5, 1, -1, -1, "supply calibration register 7"}, + {"sup.supca8", 0x1d6, 1, -1, -1, "supply calibration register 8"}, + {"sup.supca9", 0x1d7, 1, -1, -1, "supply calibration register 9"}, + {"sup.supca10", 0x1d8, 1, 0x1f, -1, "supply calibration register 10"}, + {"tplf_cal.tpcalr11", 0x1d9, 1, -1, -1, "transponder calibration register 11"}, + {"tplf_cal.tpcalr12", 0x1da, 1, -1, -1, "transponder calibration register 12"}, + {"tplf_cal.tpcalr13", 0x1db, 1, 0xff, -1, "transponder calibration register 13"}, + {"sup.pmter", 0x1de, 1, 0xff, -1, "power management test enable register"}, + {"tplf_cal.srccall", 0x1df, 1, -1, -1, "slow RC oscillator calibration register low byte"}, +}; + +// ATA5787 +const Register_file_t rgftab_ata5787[292] = { // I/O memory [0, 479] + 32 + {"clk.prr0", 0x001, 1, -1, -1, "power reduction register 0"}, + {"clk.prr1", 0x002, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x003, 1, -1, -1, "power reduction register 2"}, + {"rxdsp.rdpr", 0x004, 1, -1, -1, "rx DSP power reduction register"}, + {"portb.pinb", 0x005, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x006, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x007, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x008, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x009, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x00a, 1, 0x3f, -1, "port C data register"}, + {"rxdsp.rdsifr", 0x00d, 1, -1, -1, "rx DSP status interrupt flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"int.pcifr", 0x00f, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x010, 1, -1, -1, "timer 0 control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"timer1.t1ifr", 0x015, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer2.t2ifr", 0x016, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer3.t3ifr", 0x017, 1, -1, -1, "timer 3 interrupt flag register"}, + {"timer4.t4ifr", 0x018, 1, -1, -1, "timer 4 interrupt flag register"}, + {"timer5.t5ifr", 0x019, 1, -1, -1, "timer 5 interrupt flag register"}, + {"gpioregs.gpior0", 0x01a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"gpioregs.gpior3", 0x01b, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs.gpior4", 0x01c, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs.gpior5", 0x01d, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs.gpior6", 0x01e, 1, 0xff, -1, "general purpose I/O register 6"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"crc.crcdir", 0x029, 1, 0xff, -1, "CRC data input register"}, + {"vmon.vmcsr", 0x02a, 1, -1, -1, "voltage monitor control and status register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"timer0_wdt.t0ifr", 0x02f, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"rxdsp.rdcr", 0x032, 1, -1, -1, "rx DSP control register"}, + {"rxdsp.eotsa", 0x033, 1, -1, -1, "end of telegram status path A register"}, + {"rxdsp.eotca", 0x034, 1, -1, -1, "end of telegram conditions path A register"}, + {"rxdsp.eotsb", 0x035, 1, -1, -1, "end of telegram status path B register"}, + {"rxdsp.eotcb", 0x036, 1, -1, -1, "end of telegram conditions path B register"}, + {"cpu.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"clk.smcr", 0x039, 1, -1, -1, "sleep mode control register"}, + {"clk.cmcr", 0x03a, 1, -1, -1, "clock management control register"}, + {"clk.cmimr", 0x03b, 1, -1, -1, "clock management interrupt mask register"}, + {"clk.clpr", 0x03c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"freqs.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, + {"freqs.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, + {"freqs.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, + {"freqs.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, + {"freqs.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, + {"freqs.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, + {"freqs.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"timer5.gtccr", 0x070, 1, -1, -1, "general T/C control register"}, + {"rxdsp.sotsb", 0x071, 1, -1, -1, "start of telegram status path B register"}, + {"rxdsp.sotsa", 0x072, 1, -1, -1, "start of telegram status path A register"}, + {"rxdsp.sotcb", 0x073, 1, -1, -1, "start of telegram conditions path B register"}, + {"rxdsp.sotca", 0x074, 1, -1, -1, "start of telegram conditions path A register"}, + {"rxdsp.tesrb", 0x075, 1, -1, -1, "telegram status register path B"}, + {"rxdsp.tesra", 0x076, 1, -1, -1, "telegram status register path A"}, + {"rxdsp.rdsimr", 0x078, 1, -1, -1, "rx DSP status interrupt mask register"}, + {"rxdsp.rdocr", 0x079, 1, -1, -1, "rx DSP output control register"}, + {"rxdsp.temp", 0x07b, 2, 0xffff, -1, "temperature register (16 bits)"}, + {"demod.sycb", 0x07d, 1, -1, -1, "symbol check configuration path B register"}, + {"demod.syca", 0x07e, 1, -1, -1, "symbol check configuration path A register"}, + {"demod.rxfob", 0x07f, 1, 0xff, -1, "received frequency offset vs intermediate frequency path B register"}, + {"demod.rxfoa", 0x080, 1, 0xff, -1, "received frequency offset vs intermediate frequency path A register"}, + {"demod.dmpatb", 0x081, 1, 0xff, -1, "demodulator signal check pattern path B register"}, + {"demod.dmpata", 0x082, 1, 0xff, -1, "demodulator signal check pattern path A register"}, + {"demod.dmpc", 0x083, 1, -1, -1, "demodulator pattern check control register"}, + {"demod.dmpcb", 0x084, 1, -1, -1, "demodulator pattern check control path B register"}, + {"demod.dmpca", 0x085, 1, -1, -1, "demodulator pattern check control path A register"}, + {"demod.dmsrb", 0x086, 1, 0xff, -1, "demodulator symbol rate path B register"}, + {"demod.dmsra", 0x087, 1, 0xff, -1, "demodulator symbol rate path A register"}, + {"demod.dmmb", 0x088, 1, -1, -1, "demodulator mode path B register"}, + {"demod.dmma", 0x089, 1, -1, -1, "demodulator mode path A register"}, + {"demod.dmcdb", 0x08a, 1, -1, -1, "demodulator carrier detect path B register"}, + {"demod.dmcda", 0x08b, 1, -1, -1, "demodulator carrier detect path A register"}, + {"demod.dmcrb", 0x08c, 1, -1, -1, "demodulator control path B register"}, + {"demod.dmcra", 0x08d, 1, -1, -1, "demodulator control path A register"}, + {"demod.dmdn", 0x08e, 1, -1, -1, "demodulator down sampling register"}, + {"chflt.chcr", 0x08f, 1, -1, -1, "channel filter configuration register"}, + {"chflt.chdn", 0x090, 1, -1, -1, "channel filter down sampling register"}, + {"frsync.sfidcb", 0x091, 1, -1, -1, "start frame ID configuration path B register"}, + {"frsync.sfidlb", 0x092, 1, 0x3f, -1, "start frame ID length path B register"}, + {"frsync.wuptb", 0x093, 1, 0x1f, -1, "wake-up pattern threshold path B register"}, + {"frsync.wuplb", 0x094, 1, 0x3f, -1, "wake-up pattern length path B register"}, + {"frsync.sfid1b", 0x095, 1, 0xff, -1, "start frame ID byte 1 path B"}, + {"frsync.sfid2b", 0x096, 1, 0xff, -1, "start frame ID byte 2 path B"}, + {"frsync.sfid3b", 0x097, 1, 0xff, -1, "start frame ID byte 3 path B"}, + {"frsync.sfid4b", 0x098, 1, 0xff, -1, "start frame ID byte 4 path B"}, + {"frsync.wup1b", 0x099, 1, 0xff, -1, "wake-up pattern byte 1 path B"}, + {"frsync.wup2b", 0x09a, 1, 0xff, -1, "wake-up pattern byte 2 path B"}, + {"frsync.wup3b", 0x09b, 1, 0xff, -1, "wake-up pattern byte 3 path B"}, + {"frsync.wup4b", 0x09c, 1, 0xff, -1, "wake-up pattern byte 4 path B"}, + {"frsync.sfidca", 0x09d, 1, -1, -1, "start frame ID configuration path A register"}, + {"frsync.sfidla", 0x09e, 1, 0x3f, -1, "start frame ID length path A register"}, + {"frsync.wupta", 0x09f, 1, 0x1f, -1, "wake-up pattern threshold path A register"}, + {"frsync.wupla", 0x0a0, 1, 0x3f, -1, "wake-up pattern length path A register"}, + {"frsync.sfid1a", 0x0a1, 1, 0xff, -1, "start frame ID byte 1 path A"}, + {"frsync.sfid2a", 0x0a2, 1, 0xff, -1, "start frame ID byte 2 path A"}, + {"frsync.sfid3a", 0x0a3, 1, 0xff, -1, "start frame ID byte 3 path A"}, + {"frsync.sfid4a", 0x0a4, 1, 0xff, -1, "start frame ID byte 4 path A"}, + {"frsync.wup1a", 0x0a5, 1, 0xff, -1, "wake-up pattern byte 1 path A"}, + {"frsync.wup2a", 0x0a6, 1, 0xff, -1, "wake-up pattern byte 2 path A"}, + {"frsync.wup3a", 0x0a7, 1, 0xff, -1, "wake-up pattern byte 3 path A"}, + {"frsync.wup4a", 0x0a8, 1, 0xff, -1, "wake-up pattern byte 4 path A"}, + {"clk.clkod", 0x0a9, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0aa, 1, -1, -1, "clock output control register"}, + {"calib.xfuse", 0x0ab, 1, -1, -1, "XROW fuse register"}, + {"calib.srccal", 0x0ac, 1, -1, -1, "slow RC oscillator calibration register"}, + {"calib.frccal", 0x0ad, 1, -1, -1, "fast RC oscillator calibration register"}, + {"clk.cmsr", 0x0ae, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0af, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0b0, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0b1, 1, -1, -1, "supply control register"}, + {"calib.supca1", 0x0b2, 1, -1, -1, "supply calibration register 1"}, + {"calib.supca2", 0x0b3, 1, -1, -1, "supply calibration register 2"}, + {"calib.supca3", 0x0b4, 1, -1, -1, "supply calibration register 3"}, + {"calib.supca4", 0x0b5, 1, -1, -1, "supply calibration register 4"}, + {"sup.dccal1", 0x0b6, 1, -1, -1, "DCDC converter calibration register 1"}, + {"sup.dccal2", 0x0b7, 1, -1, -1, "DCDC converter calibration register 2"}, + {"sup.dccal3", 0x0b8, 1, -1, -1, "DCDC converter calibration register 3"}, + {"sup.dctst", 0x0b9, 1, -1, -1, "DCDC converter test mode register"}, + {"calib.calrdy", 0x0ba, 1, 0xff, -1, "calibration ready signature register"}, + {"sup.rctune4", 0x0bc, 1, -1, -1, "resistor capacitor 4 bit tuning register"}, + {"sup.dcc1", 0x0bd, 1, -1, -1, "DCDC converter control register 1"}, + {"sup.dcc2", 0x0be, 1, -1, -1, "DCDC converter control register 2"}, + {"dfifo.dfs", 0x0bf, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dftl", 0x0c0, 2, 0x0fff, -1, "data FIFO telegram length register (16 bits)"}, + {"dfifo.dfl", 0x0c2, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0c3, 1, 0x1f, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0c4, 1, 0x3f, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0c5, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0c6, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0c7, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0c8, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0c9, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0ca, 1, 0x1f, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0cb, 1, 0x1f, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0cc, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0cd, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0ce, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0cf, 1, -1, -1, "sequencer state machine control register"}, + {"ssm.ssmrcr", 0x0d0, 1, -1, -1, "sequencer state machine rx control register"}, + {"ssm.ssmfbr", 0x0d1, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0d2, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0d3, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0d4, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0d5, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0d6, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0d7, 1, -1, -1, "sequencer state machine state register"}, + {"ssm.ssmxsr", 0x0d8, 1, -1, -1, "sequencer state machine extended state register"}, + {"ssm.msmcr1", 0x0d9, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0da, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0db, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0dc, 1, -1, -1, "master state machine control register 4"}, + {"ssm.gtcr", 0x0dd, 1, -1, -1, "get telegram control register"}, + {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, + {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, + {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, + {"fe.felna", 0x0e3, 1, -1, -1, "front-end LNA bias register"}, + {"fe.feas", 0x0e4, 1, -1, -1, "RF front-end antenna switch register"}, + {"fe.fevct", 0x0e6, 1, 0x0f, -1, "front-end VCO tuning register"}, + {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, + {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, + {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, + {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, + {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, + {"fe.febia", 0x0ec, 1, -1, -1, "front-end amplifier bias register"}, + {"fe.spare1", 0x0ed, 1, -1, -1, "RF front-end spare register 1"}, + {"ssm.sotc1a", 0x100, 1, -1, -1, "start of telegram conditions 1 path A register"}, + {"ssm.sotc2a", 0x101, 1, -1, -1, "start of telegram conditions 2 path A register"}, + {"ssm.sotc1b", 0x102, 1, -1, -1, "start of telegram conditions 1 path B register"}, + {"ssm.sotc2b", 0x103, 1, -1, -1, "start of telegram conditions 2 path B register"}, + {"ssm.eotc1a", 0x104, 1, -1, -1, "end of telegram conditions 1 path A register"}, + {"ssm.eotc2a", 0x105, 1, -1, -1, "end of telegram conditions 2 path A register"}, + {"ssm.eotc3a", 0x106, 1, -1, -1, "end of telegram conditions 3 path A register"}, + {"ssm.eotc1b", 0x107, 1, -1, -1, "end of telegram conditions 1 path B register"}, + {"ssm.eotc2b", 0x108, 1, -1, -1, "end of telegram conditions 2 path B register"}, + {"ssm.eotc3b", 0x109, 1, -1, -1, "end of telegram conditions 3 path B register"}, + {"ssm.wcotoa", 0x10a, 1, 0xff, -1, "wake check ok timeout path A register"}, + {"ssm.wcotob", 0x10b, 1, 0xff, -1, "wake check ok timeout path B register"}, + {"ssm.sottoa", 0x10c, 1, 0xff, -1, "start of telegram time out path A register"}, + {"ssm.sottob", 0x10d, 1, 0xff, -1, "start of telegram time out path B register"}, + {"ssm.ssmfcr", 0x10e, 1, -1, -1, "sequencer state machine flow control register"}, + {"rxbuf.rxbc1", 0x11e, 1, -1, -1, "rx buffer configuration 1 register"}, + {"rxbuf.rxbc2", 0x11f, 1, -1, -1, "rx buffer configuration 2 register"}, + {"rxbuf.rxtllb", 0x120, 1, 0xff, -1, "rx telegram length low byte path B"}, + {"rxbuf.rxtlhb", 0x121, 1, 0x0f, -1, "rx telegram length high byte path B"}, + {"rxbuf.rxcrlb", 0x122, 1, 0xff, -1, "rx CRC result low byte path B"}, + {"rxbuf.rxcrhb", 0x123, 1, 0xff, -1, "rx CRC result high byte path B"}, + {"rxbuf.rxcsbb", 0x124, 1, 0xff, -1, "rx CRC skip bit number path B register"}, + {"rxbuf.rxcilb", 0x125, 1, 0xff, -1, "rx CRC init value low byte path B"}, + {"rxbuf.rxcihb", 0x126, 1, 0xff, -1, "rx CRC init value high byte path B"}, + {"rxbuf.rxcplb", 0x127, 1, 0xff, -1, "rx CRC polynomial low byte path B"}, + {"rxbuf.rxcphb", 0x128, 1, 0xff, -1, "rx CRC polynomial high byte path B"}, + {"rxbuf.rxdsb", 0x129, 1, 0xff, -1, "receive data shift register path B"}, + {"rxbuf.rxtlla", 0x12a, 1, 0xff, -1, "rx telegram length low byte path A"}, + {"rxbuf.rxtlha", 0x12b, 1, 0x0f, -1, "rx telegram length high byte path A"}, + {"rxbuf.rxcrla", 0x12c, 1, 0xff, -1, "rx CRC result low byte path A"}, + {"rxbuf.rxcrha", 0x12d, 1, 0xff, -1, "rx CRC result high byte path A"}, + {"rxbuf.rxcsba", 0x12e, 1, 0xff, -1, "rx CRC skip bit number path A register"}, + {"rxbuf.rxcila", 0x12f, 1, 0xff, -1, "rx CRC init value low byte path A"}, + {"rxbuf.rxciha", 0x130, 1, 0xff, -1, "rx CRC init value high byte path A"}, + {"rxbuf.rxcpla", 0x131, 1, 0xff, -1, "rx CRC polynomial low byte path A"}, + {"rxbuf.rxcpha", 0x132, 1, 0xff, -1, "rx CRC polynomial high byte path A"}, + {"rxbuf.rxdsa", 0x133, 1, 0xff, -1, "receive data shift register path A"}, + {"crc.crccr", 0x134, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x135, 1, 0xff, -1, "CRC data output register"}, + {"idchk.idb0", 0x136, 1, 0xff, -1, "ID byte 0"}, + {"idchk.idb1", 0x137, 1, 0xff, -1, "ID byte 1"}, + {"idchk.idb2", 0x138, 1, 0xff, -1, "ID byte 2"}, + {"idchk.idb3", 0x139, 1, 0xff, -1, "ID byte 3"}, + {"idchk.idc", 0x13a, 1, -1, -1, "ID configuration register"}, + {"idchk.ids", 0x13b, 1, -1, -1, "ID status register"}, + {"rssib.rssav", 0x13c, 1, 0xff, -1, "RSSI average register"}, + {"rssib.rsspk", 0x13d, 1, 0xff, -1, "RSSI peak register"}, + {"rssib.rssl", 0x13e, 1, 0xff, -1, "RSSI low threshold register"}, + {"rssib.rssh", 0x13f, 1, 0xff, -1, "RSSI high threshold register"}, + {"rssib.rssc", 0x140, 1, -1, -1, "RSSI configuration register"}, + {"ports.dbcr", 0x141, 1, -1, -1, "debounce control register"}, + {"ports.dbtc", 0x142, 1, 0xff, -1, "debounce timer compare register"}, + {"ports.dbenb", 0x143, 1, 0xff, -1, "debounce enable port B register"}, + {"ports.dbenc", 0x144, 1, 0x3f, -1, "debounce enable port C register"}, + {"ports.dbgsw", 0x145, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x146, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x147, 1, -1, -1, "SPI FIFO interrupt register"}, + {"eeprom.eecr2", 0x148, 1, -1, -1, "EEPROM control register 2"}, + {"eeprom.pgmst", 0x149, 1, -1, -1, "program memory status register"}, + {"eeprom.eest", 0x14a, 1, -1, -1, "EEPROM status register"}, + {"rssib.rshsg", 0x14b, 1, 0xff, -1, "RSSI LNA high sensitivity gain register"}, + {"rssib.rsifg", 0x14c, 1, 0xff, -1, "RSSI IF amplifier gain register"}, + {"rssib.rsldv", 0x14d, 1, 0xff, -1, "RSSI low band damping value register"}, + {"rssib.rshdv", 0x14e, 1, 0xff, -1, "RSSI high band damping value register"}, + {"rssib.rscom", 0x14f, 1, -1, -1, "RSSI compensation register"}, + {"occount.occr", 0x150, 1, -1, -1, "oscillator calibration counter configuration register"}, + {"occount.occnt", 0x151, 1, 0xff, -1, "oscillator calibration counter register"}, + {"occount.ocgate", 0x152, 1, 0xff, -1, "oscillator calibration counter gate register"}, + {"lin_uart.lincr", 0x153, 1, -1, -1, "LIN control register"}, + {"lin_uart.linsir", 0x154, 1, -1, -1, "LIN status and interrupt register"}, + {"lin_uart.linenir", 0x155, 1, -1, -1, "LIN enable interrupt register"}, + {"lin_uart.linerr", 0x156, 1, -1, -1, "LIN error register"}, + {"lin_uart.linbtr", 0x157, 1, -1, -1, "LIN bit timing register"}, + {"lin_uart.linbrrl", 0x158, 1, -1, -1, "LIN baud rate low register low byte"}, + {"lin_uart.linbrrh", 0x159, 1, -1, -1, "LIN baud rate high register high byte"}, + {"lin_uart.lindlr", 0x15a, 1, -1, -1, "LIN data length register"}, + {"lin_uart.linidr", 0x15b, 1, -1, -1, "LIN identifier register"}, + {"lin_uart.linsel", 0x15c, 1, -1, -1, "LIN data buffer selection register"}, + {"lin_uart.lindat", 0x15d, 1, -1, -1, "LIN data register"}, + {"trace.trccr", 0x15e, 1, -1, -1, "trace unit control register"}, + {"trace.trcdr", 0x15f, 1, 0xff, -1, "trace unit data register"}, + {"trace.trcid", 0x160, 2, 0xffff, -1, "trace ID register (16 bits)"}, +}; + +// ATA5790N ATA5791 +const Register_file_t rgftab_ata5790n[117] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"timer_counter_3.t3cr2", 0x0c, 1, -1, -1, "timer 3 control register 2"}, + {"afe.tpcr", 0x0d, 1, -1, -1, "transponder control register"}, + {"afe.tpfr", 0x0e, 1, -1, -1, "transponder status and flag register"}, + {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, + {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, + {"timer_counter_2.t2cr", 0x11, 1, -1, -1, "timer 2 control register"}, + {"timer_counter_3.t3cr", 0x12, 1, -1, -1, "timer 3 control register"}, + {"aes.aescr", 0x13, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x14, 1, -1, -1, "AES status register"}, + {"mod.tmifr", 0x15, 1, -1, -1, "timer modulator interrupt flag register"}, + {"cpu.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"vmon.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, + {"dddlfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, + {"timer_counter_0.t0ifr", 0x19, 1, -1, -1, "timer 0 interrupt flag register"}, + {"timer_counter_1.t1ifr", 0x1a, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, + {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, + {"cpu.gpior", 0x1e, 1, 0xff, -1, "general purpose I/O register"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x23, 1, -1, -1, "EEPROM protection register"}, + {"eeprom.eeccr", 0x24, 1, -1, -1, "EEPROM error correction code register"}, + {"eeprom.eecr2", 0x25, 1, -1, -1, "EEPROM control register 2"}, + {"external_interrupt.pcicr", 0x26, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eimsk", 0x27, 1, -1, -1, "external interrupt mask register"}, + {"mod.tmdr", 0x28, 1, 0xff, -1, "timer modulator data register"}, + {"aes.aesdr", 0x29, 1, 0xff, -1, "AES data register"}, + {"aes.aeskr", 0x2a, 1, -1, -1, "AES key register"}, + {"cpu.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"vmon.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"dddlfrx.lfcr0", 0x2f, 1, -1, -1, "LF receiver control register 0"}, + {"dddlfrx.lfcr1", 0x30, 1, -1, -1, "LF receiver control register 1"}, + {"dddlfrx.lfrdb", 0x32, 1, 0xff, -1, "LF receiver data buffer register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"dddlfrx.lfsr", 0x36, 1, -1, -1, "LF status register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, + {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, + {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.prr0", 0x43, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x44, 1, -1, -1, "power reduction register 1"}, + {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, + {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"irled.ldcr", 0x4d, 1, -1, -1, "LED driver control register"}, + {"timer_counter_2.t2cnt", 0x50, 1, 0xff, -1, "timer 2 counter"}, + {"timer_counter_2.t2cor", 0x51, 1, 0xff, -1, "timer 2 compare register"}, + {"timer_counter_2.t2mr", 0x53, 1, -1, -1, "timer 2 mode register"}, + {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer_counter_3.t3co2r", 0x55, 1, 0xff, -1, "timer 3 compare 2 register"}, + {"timer_counter_3.t3cnt", 0x56, 1, 0xff, -1, "timer 3 counter"}, + {"timer_counter_3.t3cor", 0x57, 1, 0xff, -1, "timer 3 compare register"}, + {"timer_counter_3.t3icr", 0x58, 1, 0xff, -1, "timer 3 input capture register"}, + {"timer_counter_3.t3mra", 0x59, 1, -1, -1, "timer 3 mode register A"}, + {"timer_counter_3.t3mrb", 0x5a, 1, -1, -1, "timer 3 mode register B"}, + {"timer_counter_3.t3imr", 0x5b, 1, -1, -1, "timer 3 interrupt mask register"}, + {"mod.tmcr", 0x5d, 1, -1, -1, "timer modulator control register"}, + {"mod.tmmr", 0x5e, 1, -1, -1, "timer modulator mode register"}, + {"mod.tmimr", 0x5f, 1, -1, -1, "timer modulator interrupt mask register"}, + {"dddlfrx.lfimr", 0x62, 1, -1, -1, "LF interrupt mask register"}, + {"dddlfrx.lfcad", 0x63, 1, 0xff, -1, "LF clock adjustment data register"}, + {"dddlfrx.lfid00", 0x64, 1, 0xff, -1, "LF ID 0 data register byte 0"}, + {"dddlfrx.lfid01", 0x65, 1, 0xff, -1, "LF ID 0 data register byte 1"}, + {"dddlfrx.lfid02", 0x66, 1, 0xff, -1, "LF ID 0 data register byte 2"}, + {"dddlfrx.lfid03", 0x67, 1, 0xff, -1, "LF ID 0 data register byte 3"}, + {"dddlfrx.lfid10", 0x68, 1, 0xff, -1, "LF ID 1 data register byte 0"}, + {"dddlfrx.lfid11", 0x69, 1, 0xff, -1, "LF ID 1 data register byte 1"}, + {"dddlfrx.lfid12", 0x6a, 1, 0xff, -1, "LF ID 1 data register byte 2"}, + {"dddlfrx.lfid13", 0x6b, 1, 0xff, -1, "LF ID 1 data register byte 3"}, + {"dddlfrx.lfrd0", 0x6c, 1, 0xff, -1, "LF receive data register byte 0"}, + {"dddlfrx.lfrd1", 0x6d, 1, 0xff, -1, "LF receive data register byte 1"}, + {"dddlfrx.lfrd2", 0x6e, 1, 0xff, -1, "LF receive data register byte 2"}, + {"dddlfrx.lfrd3", 0x6f, 1, 0xff, -1, "LF receive data register byte 3"}, + {"dddlfrx.lfid0m", 0x70, 1, -1, -1, "LF identifier 0 mask register"}, + {"dddlfrx.lfid1m", 0x71, 1, -1, -1, "LF identifier 1 mask register"}, + {"dddlfrx.lfrdf", 0x72, 1, -1, -1, "LF receive data frame register"}, + {"dddlfrx.lfrsd1", 0x73, 1, 0xff, -1, "LF RSSI data register 1"}, + {"dddlfrx.lfrsd2", 0x74, 1, 0xff, -1, "LF RSSI data register 2"}, + {"dddlfrx.lfrsd3", 0x75, 1, 0xff, -1, "LF RSSI data register 3"}, + {"dddlfrx.lfcc1", 0x76, 1, 0x0f, -1, "LF channel capacity select register 1"}, + {"dddlfrx.lfcc2", 0x77, 1, 0x0f, -1, "LF channel capacity select register 2"}, + {"dddlfrx.lfcc3", 0x78, 1, 0x0f, -1, "LF channel capacity select register 3"}, + {"dddlfrx.lfqcr", 0x79, 1, -1, -1, "LF receiver quality control register"}, + {"afe.tpimr", 0x7c, 1, -1, -1, "transponder interrupt mask register"}, + {"rtc_timer.rtccr", 0x7e, 1, -1, -1, "real-time clock control register"}, + {"rtc_timer.rtcdr", 0x7f, 1, 0xff, -1, "real time clock data register"}, + {"mod.tmmdr", 0x88, 1, 0x0f, -1, "timer modulator manchester data register"}, + {"mod.tmbdr", 0x89, 1, 0x0f, -1, "timer modulator biphase data register"}, + {"mod.tmtdr", 0x8a, 1, 0xff, -1, "timer modulator transmit data register"}, + {"mod.tmsr", 0x8b, 1, 0xff, -1, "timer modulator shift register"}, + {"crc.crcpol", 0x8c, 1, 0xff, -1, "CRC polynomial data register"}, + {"crc.crcdr", 0x8d, 1, 0xff, -1, "CRC data register"}, + {"crc.crccr", 0x8e, 1, -1, -1, "CRC control register"}, + {"crc.crcsr", 0x8f, 1, -1, -1, "CRC status register"}, +}; + +// ATA5795 +const Register_file_t rgftab_ata5795[84] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x1f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x1f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x1f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"afe.tpcr", 0x0d, 1, -1, -1, "transponder control register"}, + {"afe.tpfr", 0x0e, 1, -1, -1, "transponder status and flag register"}, + {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, + {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, + {"timer_counter_2.t2cr", 0x11, 1, -1, -1, "timer 2 control register"}, + {"timer_counter_3.t3cr", 0x12, 1, -1, -1, "timer 3 control register"}, + {"aes.aescr", 0x13, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x14, 1, -1, -1, "AES status register"}, + {"mod.tmifr", 0x15, 1, -1, -1, "timer modulator interrupt flag register"}, + {"cpu.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"vmon.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, + {"timer_counter_0.t0ifr", 0x19, 1, -1, -1, "timer 0 interrupt flag register"}, + {"timer_counter_1.t1ifr", 0x1a, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, + {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x23, 1, -1, -1, "EEPROM protection register"}, + {"eeprom.eeccr", 0x24, 1, -1, -1, "EEPROM error correction code register"}, + {"external_interrupt.pcicr", 0x26, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eimsk", 0x27, 1, -1, -1, "external interrupt mask register"}, + {"mod.tmdr", 0x28, 1, 0xff, -1, "timer modulator data register"}, + {"aes.aesdr", 0x29, 1, 0xff, -1, "AES data register"}, + {"aes.aeskr", 0x2a, 1, -1, -1, "AES key register"}, + {"cpu.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"vmon.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, + {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, + {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.prr0", 0x43, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x44, 1, -1, -1, "power reduction register 1"}, + {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, + {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"irled.ldcr", 0x4d, 1, -1, -1, "LED driver control register"}, + {"timer_counter_2.t2cnt", 0x50, 1, 0xff, -1, "timer 2 counter"}, + {"timer_counter_2.t2cor", 0x51, 1, 0xff, -1, "timer 2 compare register"}, + {"timer_counter_2.t2mr", 0x53, 1, -1, -1, "timer 2 mode register"}, + {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer_counter_3.t3cnt", 0x56, 1, 0xff, -1, "timer 3 counter"}, + {"timer_counter_3.t3cor", 0x57, 1, 0xff, -1, "timer 3 compare register"}, + {"timer_counter_3.t3icr", 0x58, 1, 0xff, -1, "timer 3 input capture register"}, + {"timer_counter_3.t3mra", 0x59, 1, -1, -1, "timer 3 mode register A"}, + {"timer_counter_3.t3mrb", 0x5a, 1, -1, -1, "timer 3 mode register B"}, + {"timer_counter_3.t3imr", 0x5b, 1, -1, -1, "timer 3 interrupt mask register"}, + {"mod.tmcr", 0x5d, 1, -1, -1, "timer modulator control register"}, + {"mod.tmmr", 0x5e, 1, -1, -1, "timer modulator mode register"}, + {"mod.tmimr", 0x5f, 1, -1, -1, "timer modulator interrupt mask register"}, + {"afe.tpimr", 0x7c, 1, -1, -1, "transponder interrupt mask register"}, + {"rtc_timer.rtccr", 0x7e, 1, -1, -1, "real-time clock control register"}, + {"rtc_timer.rtcdr", 0x7f, 1, 0xff, -1, "real time clock data register"}, + {"mod.tmmdr", 0x88, 1, 0x0f, -1, "timer modulator manchester data register"}, + {"mod.tmbdr", 0x89, 1, 0x0f, -1, "timer modulator biphase data register"}, + {"mod.tmtdr", 0x8a, 1, 0xff, -1, "timer modulator transmit data register"}, + {"mod.tmsr", 0x8b, 1, 0xff, -1, "timer modulator shift register"}, + {"crc.crcdr", 0x8d, 1, 0xff, -1, "CRC data register"}, + {"crc.crccr", 0x8e, 1, -1, -1, "CRC control register"}, + {"crc.crcsr", 0x8f, 1, -1, -1, "CRC status register"}, +}; + +// ATA5831 ATA5832 ATA5833 ATA8510 ATA8515 +const Register_file_t rgftab_ata5831[279] = { // I/O memory [0, 479] + 32 + {"clk.prr0", 0x001, 1, -1, -1, "power reduction register 0"}, + {"clk.prr1", 0x002, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x003, 1, -1, -1, "power reduction register 2"}, + {"clk.rdpr", 0x004, 1, -1, -1, "rx DSP power reduction register"}, + {"portb.pinb", 0x005, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x006, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x007, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x008, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x009, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x00a, 1, 0x3f, -1, "port C data register"}, + {"freqs.fscr", 0x00b, 1, -1, -1, "frequency synthesizer control register"}, + {"rxdsp.rdsifr", 0x00d, 1, -1, -1, "rx DSP status interrupt flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"int.pcifr", 0x00f, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x010, 1, -1, -1, "timer 0 control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"timer1.t1ifr", 0x015, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer2.t2ifr", 0x016, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer3.t3ifr", 0x017, 1, -1, -1, "timer 3 interrupt flag register"}, + {"timer4.t4ifr", 0x018, 1, -1, -1, "timer 4 interrupt flag register"}, + {"timer5.t5ifr", 0x019, 1, -1, -1, "timer 5 interrupt flag register"}, + {"gpioregs.gpior0", 0x01a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"gpioregs.gpior3", 0x01b, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs.gpior4", 0x01c, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs.gpior5", 0x01d, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs.gpior6", 0x01e, 1, 0xff, -1, "general purpose I/O register 6"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"crc.crcdir", 0x029, 1, 0xff, -1, "CRC data input register"}, + {"sup.vmcsr", 0x02a, 1, -1, -1, "voltage monitor control and status register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"timer0_wdt.t0ifr", 0x02f, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"rxdsp.rdcr", 0x033, 1, -1, -1, "rx DSP control register"}, + {"rxdsp.eotsa", 0x034, 1, -1, -1, "end of telegram status path A register"}, + {"rxdsp.eotca", 0x035, 1, -1, -1, "end of telegram conditions path A register"}, + {"rxdsp.eotsb", 0x036, 1, -1, -1, "end of telegram status path B register"}, + {"rxdsp.eotcb", 0x037, 1, -1, -1, "end of telegram conditions path B register"}, + {"cpu.smcr", 0x038, 1, -1, -1, "sleep mode control register"}, + {"cpu.cmcr", 0x039, 1, -1, -1, "clock management control register"}, + {"cpu.cmimr", 0x03a, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clpr", 0x03b, 1, -1, -1, "clock prescaler register"}, + {"cpu.spmcsr", 0x03c, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"freqs.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, + {"freqs.fsfcr", 0x041, 1, -1, -1, "frequency synthesizer filter control register"}, + {"freqs.gacdiv", 0x042, 2, 0x1fff, -1, "Gauss clock divider register (16 bits)"}, + {"freqs.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, + {"freqs.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, + {"freqs.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, + {"freqs.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, + {"freqs.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, + {"freqs.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"timer5.gtccr", 0x070, 1, -1, -1, "general T/C control register"}, + {"rxdsp.sotsb", 0x071, 1, -1, -1, "start of telegram status path B register"}, + {"rxdsp.sotsa", 0x072, 1, -1, -1, "start of telegram status path A register"}, + {"rxdsp.sotcb", 0x073, 1, -1, -1, "start of telegram conditions path B register"}, + {"rxdsp.sotca", 0x074, 1, -1, -1, "start of telegram conditions path A register"}, + {"rxdsp.tesrb", 0x075, 1, -1, -1, "telegram status register path B"}, + {"rxdsp.tesra", 0x076, 1, -1, -1, "telegram status register path A"}, + {"rxdsp.rdsimr", 0x078, 1, -1, -1, "rx DSP status interrupt mask register"}, + {"rxdsp.rdocr", 0x079, 1, -1, -1, "rx DSP output control register"}, + {"temper.templ", 0x07b, 1, 0xff, -1, "temperature low byte"}, + {"temper.temph", 0x07c, 1, 0xff, -1, "temperature high byte"}, + {"symch.sycb", 0x07d, 1, -1, -1, "symbol check configuration path B register"}, + {"symch.syca", 0x07e, 1, -1, -1, "symbol check configuration path A register"}, + {"demod.rxfob", 0x07f, 1, 0xff, -1, "received frequency offset vs intermediate frequency path B register"}, + {"demod.rxfoa", 0x080, 1, 0xff, -1, "received frequency offset vs intermediate frequency path A register"}, + {"demod.dmmb", 0x081, 1, -1, -1, "demodulator mode path B register"}, + {"demod.dmma", 0x082, 1, -1, -1, "demodulator mode path A register"}, + {"demod.dmcdb", 0x083, 1, -1, -1, "demodulator carrier detect path B register"}, + {"demod.dmcda", 0x084, 1, -1, -1, "demodulator carrier detect path A register"}, + {"demod.dmcrb", 0x085, 1, -1, -1, "demodulator control path B register"}, + {"demod.dmcra", 0x086, 1, -1, -1, "demodulator control path A register"}, + {"demod.dmdrb", 0x087, 1, -1, -1, "demodulator data rate on path B register"}, + {"demod.dmdra", 0x088, 1, -1, -1, "demodulator data rate on path A register"}, + {"chflt.chcr", 0x089, 1, -1, -1, "channel filter configuration register"}, + {"chflt.chdn", 0x08a, 1, -1, -1, "channel filter down sampling register"}, + {"frsync.sfidcb", 0x08b, 1, -1, -1, "start frame ID configuration path B register"}, + {"frsync.sfidlb", 0x08c, 1, -1, -1, "start frame ID length path B register"}, + {"frsync.wuptb", 0x08d, 1, -1, -1, "wake-up pattern threshold path B register"}, + {"frsync.wuplb", 0x08e, 1, -1, -1, "wake-up pattern length path B register"}, + {"frsync.sfid1b", 0x08f, 1, 0xff, -1, "start frame ID byte 1 path B"}, + {"frsync.sfid2b", 0x090, 1, 0xff, -1, "start frame ID byte 2 path B"}, + {"frsync.sfid3b", 0x091, 1, 0xff, -1, "start frame ID byte 3 path B"}, + {"frsync.sfid4b", 0x092, 1, 0xff, -1, "start frame ID byte 4 path B"}, + {"frsync.wup1b", 0x093, 1, 0xff, -1, "wake-up pattern byte 1 path B"}, + {"frsync.wup2b", 0x094, 1, 0xff, -1, "wake-up pattern byte 2 path B"}, + {"frsync.wup3b", 0x095, 1, 0xff, -1, "wake-up pattern byte 3 path B"}, + {"frsync.wup4b", 0x096, 1, 0xff, -1, "wake-up pattern byte 4 path B"}, + {"frsync.sfidca", 0x097, 1, -1, -1, "start frame ID configuration path A register"}, + {"frsync.sfidla", 0x098, 1, -1, -1, "start frame ID length path A register"}, + {"frsync.wupta", 0x099, 1, -1, -1, "wake-up pattern threshold path A register"}, + {"frsync.wupla", 0x09a, 1, -1, -1, "wake-up pattern length path A register"}, + {"frsync.sfid1a", 0x09b, 1, 0xff, -1, "start frame ID byte 1 path A"}, + {"frsync.sfid2a", 0x09c, 1, 0xff, -1, "start frame ID byte 2 path A"}, + {"frsync.sfid3a", 0x09d, 1, 0xff, -1, "start frame ID byte 3 path A"}, + {"frsync.sfid4a", 0x09e, 1, 0xff, -1, "start frame ID byte 4 path A"}, + {"frsync.wup1a", 0x09f, 1, 0xff, -1, "wake-up pattern byte 1 path A"}, + {"frsync.wup2a", 0x0a0, 1, 0xff, -1, "wake-up pattern byte 2 path A"}, + {"frsync.wup3a", 0x0a1, 1, 0xff, -1, "wake-up pattern byte 3 path A"}, + {"frsync.wup4a", 0x0a2, 1, 0xff, -1, "wake-up pattern byte 4 path A"}, + {"clk.clkod", 0x0a3, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0a4, 1, -1, -1, "clock output control register"}, + {"clk.xfuse", 0x0a5, 1, -1, -1, "XFUSE register"}, + {"clk.srccal", 0x0a6, 1, -1, -1, "slow RC oscillator calibration register"}, + {"clk.frccal", 0x0a7, 1, -1, -1, "fast RC oscillator calibration register"}, + {"clk.cmsr", 0x0a8, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0a9, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0aa, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0ab, 1, -1, -1, "supply control register"}, + {"sup.supca1", 0x0ac, 1, -1, -1, "supply calibration register 1"}, + {"sup.supca2", 0x0ad, 1, -1, -1, "supply calibration register 2"}, + {"sup.supca3", 0x0ae, 1, -1, -1, "supply calibration register 3"}, + {"sup.supca4", 0x0af, 1, -1, -1, "supply calibration register 4"}, + {"sup.calrdy", 0x0b0, 1, 0xff, -1, "calibration ready signature register"}, + {"sup.vmcal", 0x0b1, 1, -1, -1, "voltage monitor calibration register"}, + {"dfifo.dfs", 0x0b2, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dftl", 0x0b3, 2, 0x0fff, -1, "data FIFO telegram length register (16 bits)"}, + {"dfifo.dfl", 0x0b5, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0b6, 1, -1, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0b7, 1, -1, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0b8, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0b9, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0ba, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0bb, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0bc, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0bd, 1, -1, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0be, 1, -1, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0bf, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0c0, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0c1, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0c2, 1, -1, -1, "sequencer state machine control register"}, + {"ssm.ssmrcr", 0x0c3, 1, -1, -1, "sequencer state machine rx control register"}, + {"ssm.ssmfbr", 0x0c4, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0c5, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0c6, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0c7, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0c8, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0c9, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0ca, 1, -1, -1, "sequencer state machine state register"}, + {"ssm.ssmxsr", 0x0cb, 1, -1, -1, "sequencer state machine extended state register"}, + {"ssm.msmcr1", 0x0cc, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0cd, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0ce, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0cf, 1, -1, -1, "master state machine control register 4"}, + {"ssm.gtcr", 0x0d0, 1, -1, -1, "get telegram control register"}, + {"ssm.sotc1a", 0x0d1, 1, -1, -1, "start of telegram conditions 1 path A register"}, + {"ssm.sotc2a", 0x0d2, 1, -1, -1, "start of telegram conditions 2 path A register"}, + {"ssm.sotc1b", 0x0d3, 1, -1, -1, "start of telegram conditions 1 path B register"}, + {"ssm.sotc2b", 0x0d4, 1, -1, -1, "start of telegram conditions 2 path B register"}, + {"ssm.eotc1a", 0x0d5, 1, -1, -1, "end of telegram conditions 1 path A register"}, + {"ssm.eotc2a", 0x0d6, 1, -1, -1, "end of telegram conditions 2 path A register"}, + {"ssm.eotc3a", 0x0d7, 1, -1, -1, "end of telegram conditions 3 path A register"}, + {"ssm.eotc1b", 0x0d8, 1, -1, -1, "end of telegram conditions 1 path B register"}, + {"ssm.eotc2b", 0x0d9, 1, -1, -1, "end of telegram conditions 2 path B register"}, + {"ssm.eotc3b", 0x0da, 1, -1, -1, "end of telegram conditions 3 path B register"}, + {"ssm.wcotoa", 0x0db, 1, 0xff, -1, "wake check ok timeout path A register"}, + {"ssm.wcotob", 0x0dc, 1, 0xff, -1, "wake check ok timeout path B register"}, + {"ssm.sottoa", 0x0dd, 1, 0xff, -1, "start of telegram time out path A register"}, + {"ssm.sottob", 0x0de, 1, 0xff, -1, "start of telegram time out path B register"}, + {"ssm.ssmfcr", 0x0df, 1, -1, -1, "sequencer state machine flow control register"}, + {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, + {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, + {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, + {"fe.felna", 0x0e3, 1, -1, -1, "front-end LNA bias register"}, + {"fe.feat", 0x0e4, 1, -1, -1, "front-end antenna tuning register"}, + {"fe.fepac", 0x0e5, 1, 0xff, -1, "front-end power amplifier control register"}, + {"fe.fevct", 0x0e6, 1, -1, -1, "front-end VCO tuning register"}, + {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, + {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, + {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, + {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, + {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, + {"fe.fealr", 0x0ec, 1, -1, -1, "front-end antenna level detector range register"}, + {"fe.feant", 0x0ed, 1, -1, -1, "front-end antenna register"}, + {"fe.febia", 0x0ee, 1, -1, -1, "front-end IF amplifier BIAS register"}, + {"txm.tmfsm", 0x100, 1, -1, -1, "tx modulator finite state machine register"}, + {"txm.tmcr", 0x101, 2, 0xffff, -1, "tx modulator CRC result register (16 bits)"}, + {"txm.tmcsb", 0x103, 1, 0xff, -1, "tx modulator CRC skip bit number register"}, + {"txm.tmci", 0x104, 2, 0xffff, -1, "tx modulator CRC init value register (16 bits)"}, + {"txm.tmcp", 0x106, 2, 0xffff, -1, "tx modulator CRC polynomial register (16 bits)"}, + {"txm.tmshr", 0x108, 1, 0xff, -1, "tx modulator shift register"}, + {"txm.tmtl", 0x109, 2, 0x0fff, -1, "tx modulator telegram length register (16 bits)"}, + {"txm.tmssc", 0x10b, 1, -1, -1, "tx modulator stop sequence configuration register"}, + {"txm.tmsr", 0x10c, 1, -1, -1, "tx modulator status register"}, + {"txm.tmcr2", 0x10d, 1, -1, -1, "tx modulator control register 2"}, + {"txm.tmcr1", 0x10e, 1, -1, -1, "tx modulator control register 1"}, + {"rxbuf.rxbc1", 0x10f, 1, -1, -1, "rx buffer configuration 1 register"}, + {"rxbuf.rxbc2", 0x110, 1, -1, -1, "rx buffer configuration 2 register"}, + {"rxbuf.rxtllb", 0x111, 1, 0xff, -1, "rx telegram length low byte path B"}, + {"rxbuf.rxtlhb", 0x112, 1, -1, -1, "rx telegram length high byte path B"}, + {"rxbuf.rxcrlb", 0x113, 1, 0xff, -1, "rx CRC result low byte path B"}, + {"rxbuf.rxcrhb", 0x114, 1, 0xff, -1, "rx CRC result high byte path B"}, + {"rxbuf.rxcsbb", 0x115, 1, 0xff, -1, "rx CRC skip bit number path B register"}, + {"rxbuf.rxcilb", 0x116, 1, 0xff, -1, "rx CRC init value low byte path B"}, + {"rxbuf.rxcihb", 0x117, 1, 0xff, -1, "rx CRC init value high byte path B"}, + {"rxbuf.rxcplb", 0x118, 1, 0xfe, -1, "rx CRC polynomial low byte path B"}, + {"rxbuf.rxcphb", 0x119, 1, 0xff, -1, "rx CRC polynomial high byte path B"}, + {"rxbuf.rxdsb", 0x11a, 1, 0xff, -1, "receive data shift register path B"}, + {"rxbuf.rxtlla", 0x11b, 1, 0xff, -1, "rx telegram length low byte path A"}, + {"rxbuf.rxtlha", 0x11c, 1, -1, -1, "rx telegram length high byte path A"}, + {"rxbuf.rxcrla", 0x11d, 1, 0xff, -1, "rx CRC result low byte path A"}, + {"rxbuf.rxcrha", 0x11e, 1, 0xff, -1, "rx CRC result high byte path A"}, + {"rxbuf.rxcsba", 0x11f, 1, 0xff, -1, "rx CRC skip bit number path A register"}, + {"rxbuf.rxcila", 0x120, 1, 0xff, -1, "rx CRC init value low byte path A"}, + {"rxbuf.rxciha", 0x121, 1, 0xff, -1, "rx CRC init value high byte path A"}, + {"rxbuf.rxcpla", 0x122, 1, 0xfe, -1, "rx CRC polynomial low byte path A"}, + {"rxbuf.rxcpha", 0x123, 1, 0xff, -1, "rx CRC polynomial high byte path A"}, + {"rxbuf.rxdsa", 0x124, 1, 0xff, -1, "receive data shift register path A"}, + {"crc.crccr", 0x125, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x126, 1, 0xff, -1, "CRC data output register"}, + {"idscan.idb0", 0x127, 1, 0xff, -1, "ID byte 0"}, + {"idscan.idb1", 0x128, 1, 0xff, -1, "ID byte 1"}, + {"idscan.idb2", 0x129, 1, 0xff, -1, "ID byte 2"}, + {"idscan.idb3", 0x12a, 1, 0xff, -1, "ID byte 3"}, + {"idscan.idc", 0x12b, 1, -1, -1, "ID configuration register"}, + {"idscan.ids", 0x12c, 1, -1, -1, "ID status register"}, + {"rssib.rssav", 0x12d, 1, 0xff, -1, "RSSI average register"}, + {"rssib.rsspk", 0x12e, 1, 0xff, -1, "RSSI peak register"}, + {"rssib.rssl", 0x12f, 1, 0xff, -1, "RSSI low threshold register"}, + {"rssib.rssh", 0x130, 1, 0xff, -1, "RSSI high threshold register"}, + {"rssib.rssc", 0x131, 1, -1, -1, "RSSI configuration register"}, + {"debounce.dbcr", 0x132, 1, -1, -1, "debounce control register"}, + {"debounce.dbtc", 0x133, 1, 0xff, -1, "debounce timer compare register"}, + {"debounce.dbenb", 0x134, 1, 0xff, -1, "debounce enable port B register"}, + {"debounce.dbenc", 0x135, 1, 0x3f, -1, "debounce enable port C register"}, + {"debug.dbgsw", 0x136, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x137, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x138, 1, -1, -1, "SPI FIFO interrupt register"}, + {"eeprom.eecr2", 0x139, 1, -1, -1, "EEPROM control register 2"}, + {"mem.pgmst", 0x13a, 1, -1, -1, "program memory status register"}, + {"mem.eest", 0x13b, 1, -1, -1, "EEPROM status register"}, + {"rssib.rsifg", 0x13c, 1, 0xff, -1, "RSSI IF amplifier gain register"}, + {"rssib.rsldv", 0x13d, 1, 0xff, -1, "RSSI low band damping value register"}, + {"rssib.rshdv", 0x13e, 1, 0xff, -1, "RSSI high band damping value register"}, + {"rssib.rscom", 0x13f, 1, -1, -1, "RSSI compensation register"}, +}; + +// ATA5835 +const Register_file_t rgftab_ata5835[307] = { // I/O memory [0, 479] + 32 + {"clk.prr0", 0x001, 1, -1, -1, "power reduction register 0"}, + {"clk.prr1", 0x002, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x003, 1, -1, -1, "power reduction register 2"}, + {"rxdsp.rdpr", 0x004, 1, -1, -1, "rx DSP power reduction register"}, + {"portb.pinb", 0x005, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x006, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x007, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x008, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x009, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x00a, 1, 0x3f, -1, "port C data register"}, + {"freqs.fscr", 0x00b, 1, -1, -1, "frequency synthesizer control register"}, + {"rxdsp.rdsifr", 0x00d, 1, -1, -1, "rx DSP status interrupt flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"int.pcifr", 0x00f, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x010, 1, -1, -1, "timer 0 control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"timer1.t1ifr", 0x015, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer2.t2ifr", 0x016, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer3.t3ifr", 0x017, 1, -1, -1, "timer 3 interrupt flag register"}, + {"timer4.t4ifr", 0x018, 1, -1, -1, "timer 4 interrupt flag register"}, + {"timer5.t5ifr", 0x019, 1, -1, -1, "timer 5 interrupt flag register"}, + {"gpioregs.gpior0", 0x01a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"gpioregs.gpior3", 0x01b, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs.gpior4", 0x01c, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs.gpior5", 0x01d, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs.gpior6", 0x01e, 1, 0xff, -1, "general purpose I/O register 6"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"crc.crcdir", 0x029, 1, 0xff, -1, "CRC data input register"}, + {"vmon.vmcsr", 0x02a, 1, -1, -1, "voltage monitor control and status register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"timer0_wdt.t0ifr", 0x02f, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"rxdsp.rdcr", 0x032, 1, -1, -1, "rx DSP control register"}, + {"rxdsp.eotsa", 0x033, 1, -1, -1, "end of telegram status path A register"}, + {"rxdsp.eotca", 0x034, 1, -1, -1, "end of telegram conditions path A register"}, + {"rxdsp.eotsb", 0x035, 1, -1, -1, "end of telegram status path B register"}, + {"rxdsp.eotcb", 0x036, 1, -1, -1, "end of telegram conditions path B register"}, + {"cpu.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"clk.smcr", 0x039, 1, -1, -1, "sleep mode control register"}, + {"clk.cmcr", 0x03a, 1, -1, -1, "clock management control register"}, + {"clk.cmimr", 0x03b, 1, -1, -1, "clock management interrupt mask register"}, + {"clk.clpr", 0x03c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"freqs.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, + {"freqs.fsfcr", 0x041, 1, -1, -1, "frequency synthesizer filter control register"}, + {"freqs.gacdiv", 0x042, 2, 0x1fff, -1, "Gauss clock divider register (16 bits)"}, + {"freqs.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, + {"freqs.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, + {"freqs.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, + {"freqs.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, + {"freqs.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, + {"freqs.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"timer5.gtccr", 0x070, 1, -1, -1, "general T/C control register"}, + {"rxdsp.sotsb", 0x071, 1, -1, -1, "start of telegram status path B register"}, + {"rxdsp.sotsa", 0x072, 1, -1, -1, "start of telegram status path A register"}, + {"rxdsp.sotcb", 0x073, 1, -1, -1, "start of telegram conditions path B register"}, + {"rxdsp.sotca", 0x074, 1, -1, -1, "start of telegram conditions path A register"}, + {"rxdsp.tesrb", 0x075, 1, -1, -1, "telegram status register path B"}, + {"rxdsp.tesra", 0x076, 1, -1, -1, "telegram status register path A"}, + {"rxdsp.rdsimr", 0x078, 1, -1, -1, "rx DSP status interrupt mask register"}, + {"rxdsp.rdocr", 0x079, 1, -1, -1, "rx DSP output control register"}, + {"rxdsp.temp", 0x07b, 2, 0xffff, -1, "temperature register (16 bits)"}, + {"demod.sycb", 0x07d, 1, -1, -1, "symbol check configuration path B register"}, + {"demod.syca", 0x07e, 1, -1, -1, "symbol check configuration path A register"}, + {"demod.rxfob", 0x07f, 1, 0xff, -1, "received frequency offset vs intermediate frequency path B register"}, + {"demod.rxfoa", 0x080, 1, 0xff, -1, "received frequency offset vs intermediate frequency path A register"}, + {"demod.dmpatb", 0x081, 1, 0xff, -1, "demodulator signal check pattern path B register"}, + {"demod.dmpata", 0x082, 1, 0xff, -1, "demodulator signal check pattern path A register"}, + {"demod.dmpc", 0x083, 1, -1, -1, "demodulator pattern check control register"}, + {"demod.dmpcb", 0x084, 1, -1, -1, "demodulator pattern check control path B register"}, + {"demod.dmpca", 0x085, 1, -1, -1, "demodulator pattern check control path A register"}, + {"demod.dmsrb", 0x086, 1, 0xff, -1, "demodulator symbol rate path B register"}, + {"demod.dmsra", 0x087, 1, 0xff, -1, "demodulator symbol rate path A register"}, + {"demod.dmmb", 0x088, 1, -1, -1, "demodulator mode path B register"}, + {"demod.dmma", 0x089, 1, -1, -1, "demodulator mode path A register"}, + {"demod.dmcdb", 0x08a, 1, -1, -1, "demodulator carrier detect path B register"}, + {"demod.dmcda", 0x08b, 1, -1, -1, "demodulator carrier detect path A register"}, + {"demod.dmcrb", 0x08c, 1, -1, -1, "demodulator control path B register"}, + {"demod.dmcra", 0x08d, 1, -1, -1, "demodulator control path A register"}, + {"demod.dmdn", 0x08e, 1, -1, -1, "demodulator down sampling register"}, + {"chflt.chcr", 0x08f, 1, -1, -1, "channel filter configuration register"}, + {"chflt.chdn", 0x090, 1, -1, -1, "channel filter down sampling register"}, + {"frsync.sfidcb", 0x091, 1, -1, -1, "start frame ID configuration path B register"}, + {"frsync.sfidlb", 0x092, 1, 0x3f, -1, "start frame ID length path B register"}, + {"frsync.wuptb", 0x093, 1, 0x1f, -1, "wake-up pattern threshold path B register"}, + {"frsync.wuplb", 0x094, 1, 0x3f, -1, "wake-up pattern length path B register"}, + {"frsync.sfid1b", 0x095, 1, 0xff, -1, "start frame ID byte 1 path B"}, + {"frsync.sfid2b", 0x096, 1, 0xff, -1, "start frame ID byte 2 path B"}, + {"frsync.sfid3b", 0x097, 1, 0xff, -1, "start frame ID byte 3 path B"}, + {"frsync.sfid4b", 0x098, 1, 0xff, -1, "start frame ID byte 4 path B"}, + {"frsync.wup1b", 0x099, 1, 0xff, -1, "wake-up pattern byte 1 path B"}, + {"frsync.wup2b", 0x09a, 1, 0xff, -1, "wake-up pattern byte 2 path B"}, + {"frsync.wup3b", 0x09b, 1, 0xff, -1, "wake-up pattern byte 3 path B"}, + {"frsync.wup4b", 0x09c, 1, 0xff, -1, "wake-up pattern byte 4 path B"}, + {"frsync.sfidca", 0x09d, 1, -1, -1, "start frame ID configuration path A register"}, + {"frsync.sfidla", 0x09e, 1, 0x3f, -1, "start frame ID length path A register"}, + {"frsync.wupta", 0x09f, 1, 0x1f, -1, "wake-up pattern threshold path A register"}, + {"frsync.wupla", 0x0a0, 1, 0x3f, -1, "wake-up pattern length path A register"}, + {"frsync.sfid1a", 0x0a1, 1, 0xff, -1, "start frame ID byte 1 path A"}, + {"frsync.sfid2a", 0x0a2, 1, 0xff, -1, "start frame ID byte 2 path A"}, + {"frsync.sfid3a", 0x0a3, 1, 0xff, -1, "start frame ID byte 3 path A"}, + {"frsync.sfid4a", 0x0a4, 1, 0xff, -1, "start frame ID byte 4 path A"}, + {"frsync.wup1a", 0x0a5, 1, 0xff, -1, "wake-up pattern byte 1 path A"}, + {"frsync.wup2a", 0x0a6, 1, 0xff, -1, "wake-up pattern byte 2 path A"}, + {"frsync.wup3a", 0x0a7, 1, 0xff, -1, "wake-up pattern byte 3 path A"}, + {"frsync.wup4a", 0x0a8, 1, 0xff, -1, "wake-up pattern byte 4 path A"}, + {"clk.clkod", 0x0a9, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0aa, 1, -1, -1, "clock output control register"}, + {"calib.xfuse", 0x0ab, 1, -1, -1, "XROW fuse register"}, + {"calib.srccal", 0x0ac, 1, -1, -1, "slow RC oscillator calibration register"}, + {"calib.frccal", 0x0ad, 1, -1, -1, "fast RC oscillator calibration register"}, + {"clk.cmsr", 0x0ae, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0af, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0b0, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0b1, 1, -1, -1, "supply control register"}, + {"calib.supca1", 0x0b2, 1, -1, -1, "supply calibration register 1"}, + {"calib.supca2", 0x0b3, 1, -1, -1, "supply calibration register 2"}, + {"calib.supca3", 0x0b4, 1, -1, -1, "supply calibration register 3"}, + {"calib.supca4", 0x0b5, 1, -1, -1, "supply calibration register 4"}, + {"sup.dccal1", 0x0b6, 1, -1, -1, "DCDC converter calibration register 1"}, + {"sup.dccal2", 0x0b7, 1, -1, -1, "DCDC converter calibration register 2"}, + {"sup.dccal3", 0x0b8, 1, -1, -1, "DCDC converter calibration register 3"}, + {"sup.dctst", 0x0b9, 1, -1, -1, "DCDC converter test mode register"}, + {"calib.calrdy", 0x0ba, 1, 0xff, -1, "calibration ready signature register"}, + {"sup.rctune4", 0x0bc, 1, -1, -1, "resistor capacitor 4 bit tuning register"}, + {"sup.dcc1", 0x0bd, 1, -1, -1, "DCDC converter control register 1"}, + {"sup.dcc2", 0x0be, 1, -1, -1, "DCDC converter control register 2"}, + {"dfifo.dfs", 0x0bf, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dftl", 0x0c0, 2, 0x0fff, -1, "data FIFO telegram length register (16 bits)"}, + {"dfifo.dfl", 0x0c2, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0c3, 1, 0x1f, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0c4, 1, 0x3f, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0c5, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0c6, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0c7, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0c8, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0c9, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0ca, 1, 0x1f, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0cb, 1, 0x1f, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0cc, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0cd, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0ce, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0cf, 1, -1, -1, "sequencer state machine control register"}, + {"ssm.ssmrcr", 0x0d0, 1, -1, -1, "sequencer state machine rx control register"}, + {"ssm.ssmfbr", 0x0d1, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0d2, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0d3, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0d4, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0d5, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0d6, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0d7, 1, -1, -1, "sequencer state machine state register"}, + {"ssm.ssmxsr", 0x0d8, 1, -1, -1, "sequencer state machine extended state register"}, + {"ssm.msmcr1", 0x0d9, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0da, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0db, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0dc, 1, -1, -1, "master state machine control register 4"}, + {"ssm.gtcr", 0x0dd, 1, -1, -1, "get telegram control register"}, + {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, + {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, + {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, + {"fe.felna", 0x0e3, 1, -1, -1, "front-end LNA bias register"}, + {"fe.feas", 0x0e4, 1, -1, -1, "RF front-end antenna switch register"}, + {"fe.fepac", 0x0e5, 1, -1, -1, "front-end power amplifier control register"}, + {"fe.fevct", 0x0e6, 1, 0x0f, -1, "front-end VCO tuning register"}, + {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, + {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, + {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, + {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, + {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, + {"fe.febia", 0x0ec, 1, -1, -1, "front-end amplifier bias register"}, + {"fe.spare1", 0x0ed, 1, -1, -1, "RF front-end spare register 1"}, + {"ssm.sotc1a", 0x100, 1, -1, -1, "start of telegram conditions 1 path A register"}, + {"ssm.sotc2a", 0x101, 1, -1, -1, "start of telegram conditions 2 path A register"}, + {"ssm.sotc1b", 0x102, 1, -1, -1, "start of telegram conditions 1 path B register"}, + {"ssm.sotc2b", 0x103, 1, -1, -1, "start of telegram conditions 2 path B register"}, + {"ssm.eotc1a", 0x104, 1, -1, -1, "end of telegram conditions 1 path A register"}, + {"ssm.eotc2a", 0x105, 1, -1, -1, "end of telegram conditions 2 path A register"}, + {"ssm.eotc3a", 0x106, 1, -1, -1, "end of telegram conditions 3 path A register"}, + {"ssm.eotc1b", 0x107, 1, -1, -1, "end of telegram conditions 1 path B register"}, + {"ssm.eotc2b", 0x108, 1, -1, -1, "end of telegram conditions 2 path B register"}, + {"ssm.eotc3b", 0x109, 1, -1, -1, "end of telegram conditions 3 path B register"}, + {"ssm.wcotoa", 0x10a, 1, 0xff, -1, "wake check ok timeout path A register"}, + {"ssm.wcotob", 0x10b, 1, 0xff, -1, "wake check ok timeout path B register"}, + {"ssm.sottoa", 0x10c, 1, 0xff, -1, "start of telegram time out path A register"}, + {"ssm.sottob", 0x10d, 1, 0xff, -1, "start of telegram time out path B register"}, + {"ssm.ssmfcr", 0x10e, 1, -1, -1, "sequencer state machine flow control register"}, + {"txm.tmfsm", 0x10f, 1, -1, -1, "tx modulator finite state machine register"}, + {"txm.tmcr", 0x110, 2, 0xffff, -1, "tx modulator CRC result register (16 bits)"}, + {"txm.tmcsb", 0x112, 1, 0xff, -1, "tx modulator CRC skip bit number register"}, + {"txm.tmci", 0x113, 2, 0xffff, -1, "tx modulator CRC init value register (16 bits)"}, + {"txm.tmcp", 0x115, 2, 0xffff, -1, "tx modulator CRC polynomial register (16 bits)"}, + {"txm.tmshr", 0x117, 1, 0xff, -1, "tx modulator shift register"}, + {"txm.tmtl", 0x118, 2, 0x0fff, -1, "tx modulator telegram length register (16 bits)"}, + {"txm.tmssc", 0x11a, 1, -1, -1, "tx modulator stop sequence configuration register"}, + {"txm.tmsr", 0x11b, 1, -1, -1, "tx modulator status register"}, + {"txm.tmcr2", 0x11c, 1, -1, -1, "tx modulator control register 2"}, + {"txm.tmcr1", 0x11d, 1, -1, -1, "tx modulator control register 1"}, + {"rxbuf.rxbc1", 0x11e, 1, -1, -1, "rx buffer configuration 1 register"}, + {"rxbuf.rxbc2", 0x11f, 1, -1, -1, "rx buffer configuration 2 register"}, + {"rxbuf.rxtllb", 0x120, 1, 0xff, -1, "rx telegram length low byte path B"}, + {"rxbuf.rxtlhb", 0x121, 1, 0x0f, -1, "rx telegram length high byte path B"}, + {"rxbuf.rxcrlb", 0x122, 1, 0xff, -1, "rx CRC result low byte path B"}, + {"rxbuf.rxcrhb", 0x123, 1, 0xff, -1, "rx CRC result high byte path B"}, + {"rxbuf.rxcsbb", 0x124, 1, 0xff, -1, "rx CRC skip bit number path B register"}, + {"rxbuf.rxcilb", 0x125, 1, 0xff, -1, "rx CRC init value low byte path B"}, + {"rxbuf.rxcihb", 0x126, 1, 0xff, -1, "rx CRC init value high byte path B"}, + {"rxbuf.rxcplb", 0x127, 1, 0xff, -1, "rx CRC polynomial low byte path B"}, + {"rxbuf.rxcphb", 0x128, 1, 0xff, -1, "rx CRC polynomial high byte path B"}, + {"rxbuf.rxdsb", 0x129, 1, 0xff, -1, "receive data shift register path B"}, + {"rxbuf.rxtlla", 0x12a, 1, 0xff, -1, "rx telegram length low byte path A"}, + {"rxbuf.rxtlha", 0x12b, 1, 0x0f, -1, "rx telegram length high byte path A"}, + {"rxbuf.rxcrla", 0x12c, 1, 0xff, -1, "rx CRC result low byte path A"}, + {"rxbuf.rxcrha", 0x12d, 1, 0xff, -1, "rx CRC result high byte path A"}, + {"rxbuf.rxcsba", 0x12e, 1, 0xff, -1, "rx CRC skip bit number path A register"}, + {"rxbuf.rxcila", 0x12f, 1, 0xff, -1, "rx CRC init value low byte path A"}, + {"rxbuf.rxciha", 0x130, 1, 0xff, -1, "rx CRC init value high byte path A"}, + {"rxbuf.rxcpla", 0x131, 1, 0xff, -1, "rx CRC polynomial low byte path A"}, + {"rxbuf.rxcpha", 0x132, 1, 0xff, -1, "rx CRC polynomial high byte path A"}, + {"rxbuf.rxdsa", 0x133, 1, 0xff, -1, "receive data shift register path A"}, + {"crc.crccr", 0x134, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x135, 1, 0xff, -1, "CRC data output register"}, + {"idchk.idb0", 0x136, 1, 0xff, -1, "ID byte 0"}, + {"idchk.idb1", 0x137, 1, 0xff, -1, "ID byte 1"}, + {"idchk.idb2", 0x138, 1, 0xff, -1, "ID byte 2"}, + {"idchk.idb3", 0x139, 1, 0xff, -1, "ID byte 3"}, + {"idchk.idc", 0x13a, 1, -1, -1, "ID configuration register"}, + {"idchk.ids", 0x13b, 1, -1, -1, "ID status register"}, + {"rssib.rssav", 0x13c, 1, 0xff, -1, "RSSI average register"}, + {"rssib.rsspk", 0x13d, 1, 0xff, -1, "RSSI peak register"}, + {"rssib.rssl", 0x13e, 1, 0xff, -1, "RSSI low threshold register"}, + {"rssib.rssh", 0x13f, 1, 0xff, -1, "RSSI high threshold register"}, + {"rssib.rssc", 0x140, 1, -1, -1, "RSSI configuration register"}, + {"ports.dbcr", 0x141, 1, -1, -1, "debounce control register"}, + {"ports.dbtc", 0x142, 1, 0xff, -1, "debounce timer compare register"}, + {"ports.dbenb", 0x143, 1, 0xff, -1, "debounce enable port B register"}, + {"ports.dbenc", 0x144, 1, 0x3f, -1, "debounce enable port C register"}, + {"ports.dbgsw", 0x145, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x146, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x147, 1, -1, -1, "SPI FIFO interrupt register"}, + {"eeprom.eecr2", 0x148, 1, -1, -1, "EEPROM control register 2"}, + {"eeprom.pgmst", 0x149, 1, -1, -1, "program memory status register"}, + {"eeprom.eest", 0x14a, 1, -1, -1, "EEPROM status register"}, + {"rssib.rshsg", 0x14b, 1, 0xff, -1, "RSSI LNA high sensitivity gain register"}, + {"rssib.rsifg", 0x14c, 1, 0xff, -1, "RSSI IF amplifier gain register"}, + {"rssib.rsldv", 0x14d, 1, 0xff, -1, "RSSI low band damping value register"}, + {"rssib.rshdv", 0x14e, 1, 0xff, -1, "RSSI high band damping value register"}, + {"rssib.rscom", 0x14f, 1, -1, -1, "RSSI compensation register"}, + {"occount.occr", 0x150, 1, -1, -1, "oscillator calibration counter configuration register"}, + {"occount.occnt", 0x151, 1, 0xff, -1, "oscillator calibration counter register"}, + {"occount.ocgate", 0x152, 1, 0xff, -1, "oscillator calibration counter gate register"}, + {"lin_uart.lincr", 0x153, 1, -1, -1, "LIN control register"}, + {"lin_uart.linsir", 0x154, 1, -1, -1, "LIN status and interrupt register"}, + {"lin_uart.linenir", 0x155, 1, -1, -1, "LIN enable interrupt register"}, + {"lin_uart.linerr", 0x156, 1, -1, -1, "LIN error register"}, + {"lin_uart.linbtr", 0x157, 1, -1, -1, "LIN bit timing register"}, + {"lin_uart.linbrrl", 0x158, 1, -1, -1, "LIN baud rate low register low byte"}, + {"lin_uart.linbrrh", 0x159, 1, -1, -1, "LIN baud rate high register high byte"}, + {"lin_uart.lindlr", 0x15a, 1, -1, -1, "LIN data length register"}, + {"lin_uart.linidr", 0x15b, 1, -1, -1, "LIN identifier register"}, + {"lin_uart.linsel", 0x15c, 1, -1, -1, "LIN data buffer selection register"}, + {"lin_uart.lindat", 0x15d, 1, -1, -1, "LIN data register"}, + {"trace.trccr", 0x15e, 1, -1, -1, "trace unit control register"}, + {"trace.trcdr", 0x15f, 1, 0xff, -1, "trace unit data register"}, + {"trace.trcid", 0x160, 2, 0xffff, -1, "trace ID register (16 bits)"}, +}; + +// ATA6612C ATA6613C +const Register_file_t rgftab_ata6612c[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, -1, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, -1, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"timer_counter_0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"timer_counter_1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"timer_counter_2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"external_interrupt.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"external_interrupt.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"external_interrupt.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"timer_counter_0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"timer_counter_0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"timer_counter_0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"timer_counter_0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"analog_comparator.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"external_interrupt.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"external_interrupt.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"timer_counter_0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"timer_counter_1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"timer_counter_2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"ad_converter.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"ad_converter.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ad_converter.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"ad_converter.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"ad_converter.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"analog_comparator.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"timer_counter_1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"timer_counter_1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"timer_counter_1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"timer_counter_1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"timer_counter_1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"timer_counter_1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"timer_counter_1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"timer_counter_2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"timer_counter_2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"timer_counter_2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"timer_counter_2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"timer_counter_2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"timer_counter_2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATA6614Q +const Register_file_t rgftab_ata6614q[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, -1, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, -1, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"timer_counter_0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"timer_counter_1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"timer_counter_2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"external_interrupt.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"external_interrupt.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"external_interrupt.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"timer_counter_0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"timer_counter_0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"timer_counter_0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"timer_counter_0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"analog_comparator.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"external_interrupt.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"external_interrupt.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"timer_counter_0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"timer_counter_1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"timer_counter_2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"ad_converter.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"ad_converter.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ad_converter.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"ad_converter.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"ad_converter.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"analog_comparator.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"timer_counter_1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"timer_counter_1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"timer_counter_1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"timer_counter_1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"timer_counter_1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"timer_counter_1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"timer_counter_1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"timer_counter_2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"timer_counter_2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"timer_counter_2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"timer_counter_2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"timer_counter_2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"timer_counter_2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATA6616C ATA6617C ATA664251 +const Register_file_t rgftab_ata6616c[81] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, -1, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, -1, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"timer_counter_0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"timer_counter_1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"external_interrupt.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"external_interrupt.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"external_interrupt.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"timer_counter_0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"timer_counter_0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, + {"timer_counter_0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"analog_comparator.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"external_interrupt.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer_counter_0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"timer_counter_1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ad_converter.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, + {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, + {"ad_converter.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"ad_converter.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ad_converter.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, + {"analog_comparator.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, + {"ad_converter.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"ad_converter.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ad_converter.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"timer_counter_1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"timer_counter_1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"timer_counter_1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"timer_counter_1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, + {"timer_counter_1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"timer_counter_1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"timer_counter_1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"timer_counter_1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"timer_counter_0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, +}; + +// ATxmega16A4 ATxmega32A4 +const Register_file_t rgftab_atxmega16a4[553] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega16A4U ATxmega32A4U +const Register_file_t rgftab_atxmega16a4u[630] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega16C4 ATxmega32C4 +const Register_file_t rgftab_atxmega16c4[482] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega16D4 ATxmega32D4 +const Register_file_t rgftab_atxmega16d4[460] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 +const Register_file_t rgftab_atxmega32c3[569] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 +const Register_file_t rgftab_atxmega32d3[567] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega64A1 ATxmega128A1 +const Register_file_t rgftab_atxmega64a1[814] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"daca.ctrla", 0x300, 1, -1, -1, "control register A"}, + {"daca.ctrlb", 0x301, 1, -1, -1, "control register B"}, + {"daca.ctrlc", 0x302, 1, -1, -1, "control register C"}, + {"daca.evctrl", 0x303, 1, -1, -1, "event control register"}, + {"daca.timctrl", 0x304, 1, -1, -1, "timing control register"}, + {"daca.status", 0x305, 1, -1, -1, "status register"}, + {"daca.gaincal", 0x308, 1, -1, -1, "gain calibration register"}, + {"daca.offsetcal", 0x309, 1, -1, -1, "offset calibration register"}, + {"daca.ch0data", 0x318, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"daca.ch1data", 0x31a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"ebi.ctrl", 0x440, 1, -1, -1, "control register"}, + {"ebi.sdramctrla", 0x441, 1, -1, -1, "SDRAM control register A"}, + {"ebi.refresh", 0x444, 2, -1, -1, "SDRAM refresh period register (16 bits)"}, + {"ebi.initdly", 0x446, 2, -1, -1, "SDRAM initialization delay register (16 bits)"}, + {"ebi.sdramctrlb", 0x448, 1, -1, -1, "SDRAM control register B"}, + {"ebi.sdramctrlc", 0x449, 1, -1, -1, "SDRAM control register C"}, + {"ebi.cs0.ctrla", 0x450, 1, -1, -1, "chip select control register A"}, + {"ebi.cs0.ctrlb", 0x451, 1, -1, -1, "chip select control register B"}, + {"ebi.cs0.baseaddr", 0x452, 2, -1, -1, "base address register (16 bits)"}, + {"ebi.cs1.ctrla", 0x454, 1, -1, -1, "chip select control register A"}, + {"ebi.cs1.ctrlb", 0x455, 1, -1, -1, "chip select control register B"}, + {"ebi.cs1.baseaddr", 0x456, 2, -1, -1, "base address register (16 bits)"}, + {"ebi.cs2.ctrla", 0x458, 1, -1, -1, "chip select control register A"}, + {"ebi.cs2.ctrlb", 0x459, 1, -1, -1, "chip select control register B"}, + {"ebi.cs2.baseaddr", 0x45a, 2, -1, -1, "base address register (16 bits)"}, + {"ebi.cs3.ctrla", 0x45c, 1, -1, -1, "chip select control register A"}, + {"ebi.cs3.ctrlb", 0x45d, 1, -1, -1, "chip select control register B"}, + {"ebi.cs3.baseaddr", 0x45e, 2, -1, -1, "base address register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twid.ctrl", 0x490, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twif.ctrl", 0x4b0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4b1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4b2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4b3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4b4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4b5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4b6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4b7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4b8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4b9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4ba, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4bb, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4bc, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4bd, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"porth.dir", 0x6e0, 1, -1, -1, "data direction register"}, + {"porth.dirset", 0x6e1, 1, -1, -1, "data direction set register"}, + {"porth.dirclr", 0x6e2, 1, -1, -1, "data direction clear register"}, + {"porth.dirtgl", 0x6e3, 1, -1, -1, "data direction toggle register"}, + {"porth.out", 0x6e4, 1, -1, -1, "I/O port output register"}, + {"porth.outset", 0x6e5, 1, -1, -1, "I/O port output set register"}, + {"porth.outclr", 0x6e6, 1, -1, -1, "I/O port output clear register"}, + {"porth.outtgl", 0x6e7, 1, -1, -1, "I/O port output toggle register"}, + {"porth.in", 0x6e8, 1, -1, -1, "I/O port input register"}, + {"porth.intctrl", 0x6e9, 1, -1, -1, "interrupt control register"}, + {"porth.int0mask", 0x6ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"porth.int1mask", 0x6eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"porth.intflags", 0x6ec, 1, -1, -1, "interrupt flags register"}, + {"porth.pin0ctrl", 0x6f0, 1, -1, -1, "pin 0 control register"}, + {"porth.pin1ctrl", 0x6f1, 1, -1, -1, "pin 1 control register"}, + {"porth.pin2ctrl", 0x6f2, 1, -1, -1, "pin 2 control register"}, + {"porth.pin3ctrl", 0x6f3, 1, -1, -1, "pin 3 control register"}, + {"porth.pin4ctrl", 0x6f4, 1, -1, -1, "pin 4 control register"}, + {"porth.pin5ctrl", 0x6f5, 1, -1, -1, "pin 5 control register"}, + {"porth.pin6ctrl", 0x6f6, 1, -1, -1, "pin 6 control register"}, + {"porth.pin7ctrl", 0x6f7, 1, -1, -1, "pin 7 control register"}, + {"portj.dir", 0x700, 1, -1, -1, "data direction register"}, + {"portj.dirset", 0x701, 1, -1, -1, "data direction set register"}, + {"portj.dirclr", 0x702, 1, -1, -1, "data direction clear register"}, + {"portj.dirtgl", 0x703, 1, -1, -1, "data direction toggle register"}, + {"portj.out", 0x704, 1, -1, -1, "I/O port output register"}, + {"portj.outset", 0x705, 1, -1, -1, "I/O port output set register"}, + {"portj.outclr", 0x706, 1, -1, -1, "I/O port output clear register"}, + {"portj.outtgl", 0x707, 1, -1, -1, "I/O port output toggle register"}, + {"portj.in", 0x708, 1, -1, -1, "I/O port input register"}, + {"portj.intctrl", 0x709, 1, -1, -1, "interrupt control register"}, + {"portj.int0mask", 0x70a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portj.int1mask", 0x70b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portj.intflags", 0x70c, 1, -1, -1, "interrupt flags register"}, + {"portj.pin0ctrl", 0x710, 1, -1, -1, "pin 0 control register"}, + {"portj.pin1ctrl", 0x711, 1, -1, -1, "pin 1 control register"}, + {"portj.pin2ctrl", 0x712, 1, -1, -1, "pin 2 control register"}, + {"portj.pin3ctrl", 0x713, 1, -1, -1, "pin 3 control register"}, + {"portj.pin4ctrl", 0x714, 1, -1, -1, "pin 4 control register"}, + {"portj.pin5ctrl", 0x715, 1, -1, -1, "pin 5 control register"}, + {"portj.pin6ctrl", 0x716, 1, -1, -1, "pin 6 control register"}, + {"portj.pin7ctrl", 0x717, 1, -1, -1, "pin 7 control register"}, + {"portk.dir", 0x720, 1, -1, -1, "data direction register"}, + {"portk.dirset", 0x721, 1, -1, -1, "data direction set register"}, + {"portk.dirclr", 0x722, 1, -1, -1, "data direction clear register"}, + {"portk.dirtgl", 0x723, 1, -1, -1, "data direction toggle register"}, + {"portk.out", 0x724, 1, -1, -1, "I/O port output register"}, + {"portk.outset", 0x725, 1, -1, -1, "I/O port output set register"}, + {"portk.outclr", 0x726, 1, -1, -1, "I/O port output clear register"}, + {"portk.outtgl", 0x727, 1, -1, -1, "I/O port output toggle register"}, + {"portk.in", 0x728, 1, -1, -1, "I/O port input register"}, + {"portk.intctrl", 0x729, 1, -1, -1, "interrupt control register"}, + {"portk.int0mask", 0x72a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portk.int1mask", 0x72b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portk.intflags", 0x72c, 1, -1, -1, "interrupt flags register"}, + {"portk.pin0ctrl", 0x730, 1, -1, -1, "pin 0 control register"}, + {"portk.pin1ctrl", 0x731, 1, -1, -1, "pin 1 control register"}, + {"portk.pin2ctrl", 0x732, 1, -1, -1, "pin 2 control register"}, + {"portk.pin3ctrl", 0x733, 1, -1, -1, "pin 3 control register"}, + {"portk.pin4ctrl", 0x734, 1, -1, -1, "pin 4 control register"}, + {"portk.pin5ctrl", 0x735, 1, -1, -1, "pin 5 control register"}, + {"portk.pin6ctrl", 0x736, 1, -1, -1, "pin 6 control register"}, + {"portk.pin7ctrl", 0x737, 1, -1, -1, "pin 7 control register"}, + {"portq.dir", 0x7c0, 1, -1, -1, "data direction register"}, + {"portq.dirset", 0x7c1, 1, -1, -1, "data direction set register"}, + {"portq.dirclr", 0x7c2, 1, -1, -1, "data direction clear register"}, + {"portq.dirtgl", 0x7c3, 1, -1, -1, "data direction toggle register"}, + {"portq.out", 0x7c4, 1, -1, -1, "I/O port output register"}, + {"portq.outset", 0x7c5, 1, -1, -1, "I/O port output set register"}, + {"portq.outclr", 0x7c6, 1, -1, -1, "I/O port output clear register"}, + {"portq.outtgl", 0x7c7, 1, -1, -1, "I/O port output toggle register"}, + {"portq.in", 0x7c8, 1, -1, -1, "I/O port input register"}, + {"portq.intctrl", 0x7c9, 1, -1, -1, "interrupt control register"}, + {"portq.int0mask", 0x7ca, 1, -1, -1, "port interrupt 0 mask register"}, + {"portq.int1mask", 0x7cb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portq.intflags", 0x7cc, 1, -1, -1, "interrupt flags register"}, + {"portq.pin0ctrl", 0x7d0, 1, -1, -1, "pin 0 control register"}, + {"portq.pin1ctrl", 0x7d1, 1, -1, -1, "pin 1 control register"}, + {"portq.pin2ctrl", 0x7d2, 1, -1, -1, "pin 2 control register"}, + {"portq.pin3ctrl", 0x7d3, 1, -1, -1, "pin 3 control register"}, + {"portq.pin4ctrl", 0x7d4, 1, -1, -1, "pin 4 control register"}, + {"portq.pin5ctrl", 0x7d5, 1, -1, -1, "pin 5 control register"}, + {"portq.pin6ctrl", 0x7d6, 1, -1, -1, "pin 6 control register"}, + {"portq.pin7ctrl", 0x7d7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, + {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, + {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, + {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, + {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, + {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, + {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcf1.ctrla", 0xb40, 1, -1, -1, "control register A"}, + {"tcf1.ctrlb", 0xb41, 1, -1, -1, "control register B"}, + {"tcf1.ctrlc", 0xb42, 1, -1, -1, "control register C"}, + {"tcf1.ctrld", 0xb43, 1, -1, -1, "control register D"}, + {"tcf1.ctrle", 0xb44, 1, -1, -1, "control register E"}, + {"tcf1.intctrla", 0xb46, 1, -1, -1, "interrupt control register A"}, + {"tcf1.intctrlb", 0xb47, 1, -1, -1, "interrupt control register B"}, + {"tcf1.ctrlfclr", 0xb48, 1, -1, -1, "control register F clear"}, + {"tcf1.ctrlfset", 0xb49, 1, -1, -1, "control register F set"}, + {"tcf1.ctrlgclr", 0xb4a, 1, -1, -1, "control register G clear"}, + {"tcf1.ctrlgset", 0xb4b, 1, -1, -1, "control register G set"}, + {"tcf1.intflags", 0xb4c, 1, -1, -1, "interrupt flags register"}, + {"tcf1.temp", 0xb4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf1.cnt", 0xb60, 2, -1, -1, "counter (16 bits)"}, + {"tcf1.per", 0xb66, 2, -1, -1, "period register (16 bits)"}, + {"tcf1.cca", 0xb68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf1.ccb", 0xb6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf1.perbuf", 0xb76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf1.ccabuf", 0xb78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf1.ccbbuf", 0xb7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, + {"usartf1.data", 0xbb0, 1, -1, -1, "data register"}, + {"usartf1.status", 0xbb1, 1, -1, -1, "status register"}, + {"usartf1.ctrla", 0xbb3, 1, -1, -1, "control register A"}, + {"usartf1.ctrlb", 0xbb4, 1, -1, -1, "control register B"}, + {"usartf1.ctrlc", 0xbb5, 1, -1, -1, "control register C"}, + {"usartf1.baudctrla", 0xbb6, 1, -1, -1, "baud rate control register A"}, + {"usartf1.baudctrlb", 0xbb7, 1, -1, -1, "baud rate control register B"}, + {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, + {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, + {"spif.status", 0xbc2, 1, -1, -1, "status register"}, + {"spif.data", 0xbc3, 1, -1, -1, "data register"}, +}; + +// ATxmega64A1U ATxmega128A1U +const Register_file_t rgftab_atxmega64a1u[943] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.ebiout", 0x0b5, 1, -1, -1, "EBI output register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, + {"daca.ctrla", 0x300, 1, -1, -1, "control register A"}, + {"daca.ctrlb", 0x301, 1, -1, -1, "control register B"}, + {"daca.ctrlc", 0x302, 1, -1, -1, "control register C"}, + {"daca.evctrl", 0x303, 1, -1, -1, "event control register"}, + {"daca.status", 0x305, 1, -1, -1, "status register"}, + {"daca.ch0gaincal", 0x308, 1, -1, -1, "gain calibration register"}, + {"daca.ch0offsetcal", 0x309, 1, -1, -1, "offset calibration register"}, + {"daca.ch1gaincal", 0x30a, 1, -1, -1, "gain calibration register"}, + {"daca.ch1offsetcal", 0x30b, 1, -1, -1, "offset calibration register"}, + {"daca.ch0data", 0x318, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"daca.ch1data", 0x31a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"acb.currctrl", 0x398, 1, -1, -1, "current source control register"}, + {"acb.currcalib", 0x399, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"ebi.ctrl", 0x440, 1, -1, -1, "control register"}, + {"ebi.sdramctrla", 0x441, 1, -1, -1, "SDRAM control register A"}, + {"ebi.refresh", 0x444, 2, -1, -1, "SDRAM refresh period register (16 bits)"}, + {"ebi.initdly", 0x446, 2, -1, -1, "SDRAM initialization delay register (16 bits)"}, + {"ebi.sdramctrlb", 0x448, 1, -1, -1, "SDRAM control register B"}, + {"ebi.sdramctrlc", 0x449, 1, -1, -1, "SDRAM control register C"}, + {"ebi.cs0.ctrla", 0x450, 1, -1, -1, "chip select control register A"}, + {"ebi.cs0.ctrlb", 0x451, 1, -1, -1, "chip select control register B"}, + {"ebi.cs0.baseaddr", 0x452, 2, -1, -1, "base address register (16 bits)"}, + {"ebi.cs1.ctrla", 0x454, 1, -1, -1, "chip select control register A"}, + {"ebi.cs1.ctrlb", 0x455, 1, -1, -1, "chip select control register B"}, + {"ebi.cs1.baseaddr", 0x456, 2, -1, -1, "base address register (16 bits)"}, + {"ebi.cs2.ctrla", 0x458, 1, -1, -1, "chip select control register A"}, + {"ebi.cs2.ctrlb", 0x459, 1, -1, -1, "chip select control register B"}, + {"ebi.cs2.baseaddr", 0x45a, 2, -1, -1, "base address register (16 bits)"}, + {"ebi.cs3.ctrla", 0x45c, 1, -1, -1, "chip select control register A"}, + {"ebi.cs3.ctrlb", 0x45d, 1, -1, -1, "chip select control register B"}, + {"ebi.cs3.baseaddr", 0x45e, 2, -1, -1, "base address register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twid.ctrl", 0x490, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twif.ctrl", 0x4b0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4b1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4b2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4b3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4b4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4b5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4b6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4b7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4b8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4b9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4ba, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4bb, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4bc, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4bd, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"porth.dir", 0x6e0, 1, -1, -1, "data direction register"}, + {"porth.dirset", 0x6e1, 1, -1, -1, "data direction set register"}, + {"porth.dirclr", 0x6e2, 1, -1, -1, "data direction clear register"}, + {"porth.dirtgl", 0x6e3, 1, -1, -1, "data direction toggle register"}, + {"porth.out", 0x6e4, 1, -1, -1, "I/O port output register"}, + {"porth.outset", 0x6e5, 1, -1, -1, "I/O port output set register"}, + {"porth.outclr", 0x6e6, 1, -1, -1, "I/O port output clear register"}, + {"porth.outtgl", 0x6e7, 1, -1, -1, "I/O port output toggle register"}, + {"porth.in", 0x6e8, 1, -1, -1, "I/O port input register"}, + {"porth.intctrl", 0x6e9, 1, -1, -1, "interrupt control register"}, + {"porth.int0mask", 0x6ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"porth.int1mask", 0x6eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"porth.intflags", 0x6ec, 1, -1, -1, "interrupt flags register"}, + {"porth.remap", 0x6ee, 1, -1, -1, "I/O port pins remap register"}, + {"porth.pin0ctrl", 0x6f0, 1, -1, -1, "pin 0 control register"}, + {"porth.pin1ctrl", 0x6f1, 1, -1, -1, "pin 1 control register"}, + {"porth.pin2ctrl", 0x6f2, 1, -1, -1, "pin 2 control register"}, + {"porth.pin3ctrl", 0x6f3, 1, -1, -1, "pin 3 control register"}, + {"porth.pin4ctrl", 0x6f4, 1, -1, -1, "pin 4 control register"}, + {"porth.pin5ctrl", 0x6f5, 1, -1, -1, "pin 5 control register"}, + {"porth.pin6ctrl", 0x6f6, 1, -1, -1, "pin 6 control register"}, + {"porth.pin7ctrl", 0x6f7, 1, -1, -1, "pin 7 control register"}, + {"portj.dir", 0x700, 1, -1, -1, "data direction register"}, + {"portj.dirset", 0x701, 1, -1, -1, "data direction set register"}, + {"portj.dirclr", 0x702, 1, -1, -1, "data direction clear register"}, + {"portj.dirtgl", 0x703, 1, -1, -1, "data direction toggle register"}, + {"portj.out", 0x704, 1, -1, -1, "I/O port output register"}, + {"portj.outset", 0x705, 1, -1, -1, "I/O port output set register"}, + {"portj.outclr", 0x706, 1, -1, -1, "I/O port output clear register"}, + {"portj.outtgl", 0x707, 1, -1, -1, "I/O port output toggle register"}, + {"portj.in", 0x708, 1, -1, -1, "I/O port input register"}, + {"portj.intctrl", 0x709, 1, -1, -1, "interrupt control register"}, + {"portj.int0mask", 0x70a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portj.int1mask", 0x70b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portj.intflags", 0x70c, 1, -1, -1, "interrupt flags register"}, + {"portj.remap", 0x70e, 1, -1, -1, "I/O port pins remap register"}, + {"portj.pin0ctrl", 0x710, 1, -1, -1, "pin 0 control register"}, + {"portj.pin1ctrl", 0x711, 1, -1, -1, "pin 1 control register"}, + {"portj.pin2ctrl", 0x712, 1, -1, -1, "pin 2 control register"}, + {"portj.pin3ctrl", 0x713, 1, -1, -1, "pin 3 control register"}, + {"portj.pin4ctrl", 0x714, 1, -1, -1, "pin 4 control register"}, + {"portj.pin5ctrl", 0x715, 1, -1, -1, "pin 5 control register"}, + {"portj.pin6ctrl", 0x716, 1, -1, -1, "pin 6 control register"}, + {"portj.pin7ctrl", 0x717, 1, -1, -1, "pin 7 control register"}, + {"portk.dir", 0x720, 1, -1, -1, "data direction register"}, + {"portk.dirset", 0x721, 1, -1, -1, "data direction set register"}, + {"portk.dirclr", 0x722, 1, -1, -1, "data direction clear register"}, + {"portk.dirtgl", 0x723, 1, -1, -1, "data direction toggle register"}, + {"portk.out", 0x724, 1, -1, -1, "I/O port output register"}, + {"portk.outset", 0x725, 1, -1, -1, "I/O port output set register"}, + {"portk.outclr", 0x726, 1, -1, -1, "I/O port output clear register"}, + {"portk.outtgl", 0x727, 1, -1, -1, "I/O port output toggle register"}, + {"portk.in", 0x728, 1, -1, -1, "I/O port input register"}, + {"portk.intctrl", 0x729, 1, -1, -1, "interrupt control register"}, + {"portk.int0mask", 0x72a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portk.int1mask", 0x72b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portk.intflags", 0x72c, 1, -1, -1, "interrupt flags register"}, + {"portk.remap", 0x72e, 1, -1, -1, "I/O port pins remap register"}, + {"portk.pin0ctrl", 0x730, 1, -1, -1, "pin 0 control register"}, + {"portk.pin1ctrl", 0x731, 1, -1, -1, "pin 1 control register"}, + {"portk.pin2ctrl", 0x732, 1, -1, -1, "pin 2 control register"}, + {"portk.pin3ctrl", 0x733, 1, -1, -1, "pin 3 control register"}, + {"portk.pin4ctrl", 0x734, 1, -1, -1, "pin 4 control register"}, + {"portk.pin5ctrl", 0x735, 1, -1, -1, "pin 5 control register"}, + {"portk.pin6ctrl", 0x736, 1, -1, -1, "pin 6 control register"}, + {"portk.pin7ctrl", 0x737, 1, -1, -1, "pin 7 control register"}, + {"portq.dir", 0x7c0, 1, -1, -1, "data direction register"}, + {"portq.dirset", 0x7c1, 1, -1, -1, "data direction set register"}, + {"portq.dirclr", 0x7c2, 1, -1, -1, "data direction clear register"}, + {"portq.dirtgl", 0x7c3, 1, -1, -1, "data direction toggle register"}, + {"portq.out", 0x7c4, 1, -1, -1, "I/O port output register"}, + {"portq.outset", 0x7c5, 1, -1, -1, "I/O port output set register"}, + {"portq.outclr", 0x7c6, 1, -1, -1, "I/O port output clear register"}, + {"portq.outtgl", 0x7c7, 1, -1, -1, "I/O port output toggle register"}, + {"portq.in", 0x7c8, 1, -1, -1, "I/O port input register"}, + {"portq.intctrl", 0x7c9, 1, -1, -1, "interrupt control register"}, + {"portq.int0mask", 0x7ca, 1, -1, -1, "port interrupt 0 mask register"}, + {"portq.int1mask", 0x7cb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portq.intflags", 0x7cc, 1, -1, -1, "interrupt flags register"}, + {"portq.remap", 0x7ce, 1, -1, -1, "I/O port pins remap register"}, + {"portq.pin0ctrl", 0x7d0, 1, -1, -1, "pin 0 control register"}, + {"portq.pin1ctrl", 0x7d1, 1, -1, -1, "pin 1 control register"}, + {"portq.pin2ctrl", 0x7d2, 1, -1, -1, "pin 2 control register"}, + {"portq.pin3ctrl", 0x7d3, 1, -1, -1, "pin 3 control register"}, + {"portq.pin4ctrl", 0x7d4, 1, -1, -1, "pin 4 control register"}, + {"portq.pin5ctrl", 0x7d5, 1, -1, -1, "pin 5 control register"}, + {"portq.pin6ctrl", 0x7d6, 1, -1, -1, "pin 6 control register"}, + {"portq.pin7ctrl", 0x7d7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, + {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, + {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, + {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, + {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, + {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, + {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcf1.ctrla", 0xb40, 1, -1, -1, "control register A"}, + {"tcf1.ctrlb", 0xb41, 1, -1, -1, "control register B"}, + {"tcf1.ctrlc", 0xb42, 1, -1, -1, "control register C"}, + {"tcf1.ctrld", 0xb43, 1, -1, -1, "control register D"}, + {"tcf1.ctrle", 0xb44, 1, -1, -1, "control register E"}, + {"tcf1.intctrla", 0xb46, 1, -1, -1, "interrupt control register A"}, + {"tcf1.intctrlb", 0xb47, 1, -1, -1, "interrupt control register B"}, + {"tcf1.ctrlfclr", 0xb48, 1, -1, -1, "control register F clear"}, + {"tcf1.ctrlfset", 0xb49, 1, -1, -1, "control register F set"}, + {"tcf1.ctrlgclr", 0xb4a, 1, -1, -1, "control register G clear"}, + {"tcf1.ctrlgset", 0xb4b, 1, -1, -1, "control register G set"}, + {"tcf1.intflags", 0xb4c, 1, -1, -1, "interrupt flags register"}, + {"tcf1.temp", 0xb4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf1.cnt", 0xb60, 2, -1, -1, "counter (16 bits)"}, + {"tcf1.per", 0xb66, 2, -1, -1, "period register (16 bits)"}, + {"tcf1.cca", 0xb68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf1.ccb", 0xb6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf1.perbuf", 0xb76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf1.ccabuf", 0xb78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf1.ccbbuf", 0xb7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, + {"usartf1.data", 0xbb0, 1, -1, -1, "data register"}, + {"usartf1.status", 0xbb1, 1, -1, -1, "status register"}, + {"usartf1.ctrla", 0xbb3, 1, -1, -1, "control register A"}, + {"usartf1.ctrlb", 0xbb4, 1, -1, -1, "control register B"}, + {"usartf1.ctrlc", 0xbb5, 1, -1, -1, "control register C"}, + {"usartf1.baudctrla", 0xbb6, 1, -1, -1, "baud rate control register A"}, + {"usartf1.baudctrlb", 0xbb7, 1, -1, -1, "baud rate control register B"}, + {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, + {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, + {"spif.status", 0xbc2, 1, -1, -1, "status register"}, + {"spif.data", 0xbc3, 1, -1, -1, "data register"}, +}; + +// ATxmega64B1 ATxmega128B1 +const Register_file_t rgftab_atxmega64b1[574] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.sampctrl", 0x248, 1, -1, -1, "ADC sampling time control register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"acb.currctrl", 0x398, 1, -1, -1, "current source control register"}, + {"acb.currcalib", 0x399, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x481, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x482, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x483, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x484, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x485, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x486, 1, -1, -1, "address register"}, + {"twi.host.data", 0x487, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x488, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x489, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x48a, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x48b, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x48c, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x48d, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portg.dir", 0x6c0, 1, -1, -1, "data direction register"}, + {"portg.dirset", 0x6c1, 1, -1, -1, "data direction set register"}, + {"portg.dirclr", 0x6c2, 1, -1, -1, "data direction clear register"}, + {"portg.dirtgl", 0x6c3, 1, -1, -1, "data direction toggle register"}, + {"portg.out", 0x6c4, 1, -1, -1, "I/O port output register"}, + {"portg.outset", 0x6c5, 1, -1, -1, "I/O port output set register"}, + {"portg.outclr", 0x6c6, 1, -1, -1, "I/O port output clear register"}, + {"portg.outtgl", 0x6c7, 1, -1, -1, "I/O port output toggle register"}, + {"portg.in", 0x6c8, 1, -1, -1, "I/O port input register"}, + {"portg.intctrl", 0x6c9, 1, -1, -1, "interrupt control register"}, + {"portg.int0mask", 0x6ca, 1, -1, -1, "port interrupt 0 mask register"}, + {"portg.int1mask", 0x6cb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portg.intflags", 0x6cc, 1, -1, -1, "interrupt flags register"}, + {"portg.remap", 0x6ce, 1, -1, -1, "I/O port pins remap register"}, + {"portg.pin0ctrl", 0x6d0, 1, -1, -1, "pin 0 control register"}, + {"portg.pin1ctrl", 0x6d1, 1, -1, -1, "pin 1 control register"}, + {"portg.pin2ctrl", 0x6d2, 1, -1, -1, "pin 2 control register"}, + {"portg.pin3ctrl", 0x6d3, 1, -1, -1, "pin 3 control register"}, + {"portg.pin4ctrl", 0x6d4, 1, -1, -1, "pin 4 control register"}, + {"portg.pin5ctrl", 0x6d5, 1, -1, -1, "pin 5 control register"}, + {"portg.pin6ctrl", 0x6d6, 1, -1, -1, "pin 6 control register"}, + {"portg.pin7ctrl", 0x6d7, 1, -1, -1, "pin 7 control register"}, + {"portm.dir", 0x760, 1, -1, -1, "data direction register"}, + {"portm.dirset", 0x761, 1, -1, -1, "data direction set register"}, + {"portm.dirclr", 0x762, 1, -1, -1, "data direction clear register"}, + {"portm.dirtgl", 0x763, 1, -1, -1, "data direction toggle register"}, + {"portm.out", 0x764, 1, -1, -1, "I/O port output register"}, + {"portm.outset", 0x765, 1, -1, -1, "I/O port output set register"}, + {"portm.outclr", 0x766, 1, -1, -1, "I/O port output clear register"}, + {"portm.outtgl", 0x767, 1, -1, -1, "I/O port output toggle register"}, + {"portm.in", 0x768, 1, -1, -1, "I/O port input register"}, + {"portm.intctrl", 0x769, 1, -1, -1, "interrupt control register"}, + {"portm.int0mask", 0x76a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portm.int1mask", 0x76b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portm.intflags", 0x76c, 1, -1, -1, "interrupt flags register"}, + {"portm.remap", 0x76e, 1, -1, -1, "I/O port pins remap register"}, + {"portm.pin0ctrl", 0x770, 1, -1, -1, "pin 0 control register"}, + {"portm.pin1ctrl", 0x771, 1, -1, -1, "pin 1 control register"}, + {"portm.pin2ctrl", 0x772, 1, -1, -1, "pin 2 control register"}, + {"portm.pin3ctrl", 0x773, 1, -1, -1, "pin 3 control register"}, + {"portm.pin4ctrl", 0x774, 1, -1, -1, "pin 4 control register"}, + {"portm.pin5ctrl", 0x775, 1, -1, -1, "pin 5 control register"}, + {"portm.pin6ctrl", 0x776, 1, -1, -1, "pin 6 control register"}, + {"portm.pin7ctrl", 0x777, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"lcd.ctrla", 0xd00, 1, -1, -1, "control register A"}, + {"lcd.ctrlb", 0xd01, 1, -1, -1, "control register B"}, + {"lcd.ctrlc", 0xd02, 1, -1, -1, "control register C"}, + {"lcd.intctrl", 0xd03, 1, -1, -1, "interrupt control register"}, + {"lcd.intflag", 0xd04, 1, -1, -1, "interrupt flag register"}, + {"lcd.ctrld", 0xd05, 1, -1, -1, "control register D"}, + {"lcd.ctrle", 0xd06, 1, -1, -1, "control register E"}, + {"lcd.ctrlf", 0xd07, 1, -1, -1, "control register F"}, + {"lcd.ctrlg", 0xd08, 1, -1, -1, "control register G"}, + {"lcd.ctrlh", 0xd09, 1, -1, -1, "control register H"}, + {"lcd.data0", 0xd10, 1, -1, -1, "data register 0"}, + {"lcd.data1", 0xd11, 1, -1, -1, "data register 1"}, + {"lcd.data2", 0xd12, 1, -1, -1, "data register 2"}, + {"lcd.data3", 0xd13, 1, -1, -1, "LCD data register 3"}, + {"lcd.data4", 0xd14, 1, -1, -1, "LCD data register 4"}, + {"lcd.data5", 0xd15, 1, -1, -1, "LCD data register 5"}, + {"lcd.data6", 0xd16, 1, -1, -1, "LCD data register 6"}, + {"lcd.data7", 0xd17, 1, -1, -1, "LCD data register 7"}, + {"lcd.data8", 0xd18, 1, -1, -1, "LCD data register 8"}, + {"lcd.data9", 0xd19, 1, -1, -1, "LCD data register 9"}, + {"lcd.data10", 0xd1a, 1, -1, -1, "LCD data register 10"}, + {"lcd.data11", 0xd1b, 1, -1, -1, "LCD data register 11"}, + {"lcd.data12", 0xd1c, 1, -1, -1, "LCD data register 12"}, + {"lcd.data13", 0xd1d, 1, -1, -1, "LCD data register 13"}, + {"lcd.data14", 0xd1e, 1, -1, -1, "LCD data register 14"}, + {"lcd.data15", 0xd1f, 1, -1, -1, "LCD data register 15"}, + {"lcd.data16", 0xd20, 1, -1, -1, "LCD data register 16"}, + {"lcd.data17", 0xd21, 1, -1, -1, "LCD data register 17"}, + {"lcd.data18", 0xd22, 1, -1, -1, "LCD data register 18"}, + {"lcd.data19", 0xd23, 1, -1, -1, "LCD data register 19"}, +}; + +// ATxmega64B3 ATxmega128B3 +const Register_file_t rgftab_atxmega64b3[458] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.sampctrl", 0x248, 1, -1, -1, "ADC sampling time control register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"acb.currctrl", 0x398, 1, -1, -1, "current source control register"}, + {"acb.currcalib", 0x399, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x481, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x482, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x483, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x484, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x485, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x486, 1, -1, -1, "address register"}, + {"twi.host.data", 0x487, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x488, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x489, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x48a, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x48b, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x48c, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x48d, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"portg.dir", 0x6c0, 1, -1, -1, "data direction register"}, + {"portg.dirset", 0x6c1, 1, -1, -1, "data direction set register"}, + {"portg.dirclr", 0x6c2, 1, -1, -1, "data direction clear register"}, + {"portg.dirtgl", 0x6c3, 1, -1, -1, "data direction toggle register"}, + {"portg.out", 0x6c4, 1, -1, -1, "I/O port output register"}, + {"portg.outset", 0x6c5, 1, -1, -1, "I/O port output set register"}, + {"portg.outclr", 0x6c6, 1, -1, -1, "I/O port output clear register"}, + {"portg.outtgl", 0x6c7, 1, -1, -1, "I/O port output toggle register"}, + {"portg.in", 0x6c8, 1, -1, -1, "I/O port input register"}, + {"portg.intctrl", 0x6c9, 1, -1, -1, "interrupt control register"}, + {"portg.int0mask", 0x6ca, 1, -1, -1, "port interrupt 0 mask register"}, + {"portg.int1mask", 0x6cb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portg.intflags", 0x6cc, 1, -1, -1, "interrupt flags register"}, + {"portg.remap", 0x6ce, 1, -1, -1, "I/O port pins remap register"}, + {"portg.pin0ctrl", 0x6d0, 1, -1, -1, "pin 0 control register"}, + {"portg.pin1ctrl", 0x6d1, 1, -1, -1, "pin 1 control register"}, + {"portg.pin2ctrl", 0x6d2, 1, -1, -1, "pin 2 control register"}, + {"portg.pin3ctrl", 0x6d3, 1, -1, -1, "pin 3 control register"}, + {"portg.pin4ctrl", 0x6d4, 1, -1, -1, "pin 4 control register"}, + {"portg.pin5ctrl", 0x6d5, 1, -1, -1, "pin 5 control register"}, + {"portg.pin6ctrl", 0x6d6, 1, -1, -1, "pin 6 control register"}, + {"portg.pin7ctrl", 0x6d7, 1, -1, -1, "pin 7 control register"}, + {"portm.dir", 0x760, 1, -1, -1, "data direction register"}, + {"portm.dirset", 0x761, 1, -1, -1, "data direction set register"}, + {"portm.dirclr", 0x762, 1, -1, -1, "data direction clear register"}, + {"portm.dirtgl", 0x763, 1, -1, -1, "data direction toggle register"}, + {"portm.out", 0x764, 1, -1, -1, "I/O port output register"}, + {"portm.outset", 0x765, 1, -1, -1, "I/O port output set register"}, + {"portm.outclr", 0x766, 1, -1, -1, "I/O port output clear register"}, + {"portm.outtgl", 0x767, 1, -1, -1, "I/O port output toggle register"}, + {"portm.in", 0x768, 1, -1, -1, "I/O port input register"}, + {"portm.intctrl", 0x769, 1, -1, -1, "interrupt control register"}, + {"portm.int0mask", 0x76a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portm.int1mask", 0x76b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portm.intflags", 0x76c, 1, -1, -1, "interrupt flags register"}, + {"portm.remap", 0x76e, 1, -1, -1, "I/O port pins remap register"}, + {"portm.pin0ctrl", 0x770, 1, -1, -1, "pin 0 control register"}, + {"portm.pin1ctrl", 0x771, 1, -1, -1, "pin 1 control register"}, + {"portm.pin2ctrl", 0x772, 1, -1, -1, "pin 2 control register"}, + {"portm.pin3ctrl", 0x773, 1, -1, -1, "pin 3 control register"}, + {"portm.pin4ctrl", 0x774, 1, -1, -1, "pin 4 control register"}, + {"portm.pin5ctrl", 0x775, 1, -1, -1, "pin 5 control register"}, + {"portm.pin6ctrl", 0x776, 1, -1, -1, "pin 6 control register"}, + {"portm.pin7ctrl", 0x777, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"lcd.ctrla", 0xd00, 1, -1, -1, "control register A"}, + {"lcd.ctrlb", 0xd01, 1, -1, -1, "control register B"}, + {"lcd.ctrlc", 0xd02, 1, -1, -1, "control register C"}, + {"lcd.intctrl", 0xd03, 1, -1, -1, "interrupt control register"}, + {"lcd.intflag", 0xd04, 1, -1, -1, "interrupt flag register"}, + {"lcd.ctrld", 0xd05, 1, -1, -1, "control register D"}, + {"lcd.ctrle", 0xd06, 1, -1, -1, "control register E"}, + {"lcd.ctrlf", 0xd07, 1, -1, -1, "control register F"}, + {"lcd.ctrlg", 0xd08, 1, -1, -1, "control register G"}, + {"lcd.ctrlh", 0xd09, 1, -1, -1, "control register H"}, + {"lcd.data0", 0xd10, 1, -1, -1, "data register 0"}, + {"lcd.data1", 0xd11, 1, -1, -1, "data register 1"}, + {"lcd.data2", 0xd12, 1, -1, -1, "data register 2"}, + {"lcd.data3", 0xd13, 1, -1, -1, "LCD data register 3"}, + {"lcd.data4", 0xd14, 1, -1, -1, "LCD data register 4"}, + {"lcd.data5", 0xd15, 1, -1, -1, "LCD data register 5"}, + {"lcd.data6", 0xd16, 1, -1, -1, "LCD data register 6"}, + {"lcd.data7", 0xd17, 1, -1, -1, "LCD data register 7"}, + {"lcd.data8", 0xd18, 1, -1, -1, "LCD data register 8"}, + {"lcd.data9", 0xd19, 1, -1, -1, "LCD data register 9"}, + {"lcd.data10", 0xd1a, 1, -1, -1, "LCD data register 10"}, + {"lcd.data11", 0xd1b, 1, -1, -1, "LCD data register 11"}, + {"lcd.data12", 0xd1c, 1, -1, -1, "LCD data register 12"}, + {"lcd.data13", 0xd1d, 1, -1, -1, "LCD data register 13"}, + {"lcd.data14", 0xd1e, 1, -1, -1, "LCD data register 14"}, + {"lcd.data15", 0xd1f, 1, -1, -1, "LCD data register 15"}, + {"lcd.data16", 0xd20, 1, -1, -1, "LCD data register 16"}, + {"lcd.data17", 0xd21, 1, -1, -1, "LCD data register 17"}, + {"lcd.data18", 0xd22, 1, -1, -1, "LCD data register 18"}, + {"lcd.data19", 0xd23, 1, -1, -1, "LCD data register 19"}, +}; + +// ATxmega64A4U ATxmega128A4U +const Register_file_t rgftab_atxmega64a4u[632] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega64D4 ATxmega128D4 +const Register_file_t rgftab_atxmega64d4[460] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega256A3B +const Register_file_t rgftab_atxmega256a3b[665] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"vbat.ctrl", 0x0f0, 1, -1, -1, "control register"}, + {"vbat.status", 0x0f1, 1, -1, -1, "status register"}, + {"vbat.backup0", 0x0f2, 1, -1, -1, "backup register 0"}, + {"vbat.backup1", 0x0f3, 1, -1, -1, "backup register 1"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc32.ctrl", 0x420, 1, -1, -1, "control register"}, + {"rtc32.syncctrl", 0x421, 1, -1, -1, "synchronization control/status register"}, + {"rtc32.intctrl", 0x422, 1, -1, -1, "interrupt control register"}, + {"rtc32.intflags", 0x423, 1, -1, -1, "interrupt flags register"}, + {"rtc32.cnt", 0x424, 4, -1, -1, "counter (32 bits)"}, + {"rtc32.per", 0x428, 4, -1, -1, "period register (32 bits)"}, + {"rtc32.comp", 0x42c, 4, -1, -1, "compare register (32 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, + {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, + {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, + {"spif.status", 0xbc2, 1, -1, -1, "status register"}, + {"spif.data", 0xbc3, 1, -1, -1, "data register"}, +}; + +// ATxmega256A3BU +const Register_file_t rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"vbat.ctrl", 0x0f0, 1, -1, -1, "control register"}, + {"vbat.status", 0x0f1, 1, -1, -1, "status register"}, + {"vbat.backup0", 0x0f2, 1, -1, -1, "backup register 0"}, + {"vbat.backup1", 0x0f3, 1, -1, -1, "backup register 1"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc32.ctrl", 0x420, 1, -1, -1, "control register"}, + {"rtc32.syncctrl", 0x421, 1, -1, -1, "synchronization control/status register"}, + {"rtc32.intctrl", 0x422, 1, -1, -1, "interrupt control register"}, + {"rtc32.intflags", 0x423, 1, -1, -1, "interrupt flags register"}, + {"rtc32.cnt", 0x424, 4, -1, -1, "counter (32 bits)"}, + {"rtc32.per", 0x428, 4, -1, -1, "period register (32 bits)"}, + {"rtc32.comp", 0x42c, 4, -1, -1, "compare register (32 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega384C3 +const Register_file_t rgftab_atxmega384c3[603] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega384D3 +const Register_file_t rgftab_atxmega384d3[560] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATtiny202 ATtiny402 +const Register_file_t rgftab_attiny202[217] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, -1, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny212 ATtiny412 +const Register_file_t rgftab_attiny212[247] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x0681, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, -1, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny214 ATtiny414 +const Register_file_t rgftab_attiny214[265] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x0681, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, -1, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny406 +const Register_file_t rgftab_attiny406[253] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny416 +const Register_file_t rgftab_attiny416[283] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x0681, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny416auto +const Register_file_t rgftab_attiny416auto[283] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x00, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x0681, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny417 ATtiny816 ATtiny817 +const Register_file_t rgftab_attiny417[283] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, -1, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, -1, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x0681, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny426 ATtiny427 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 ATtiny3226 ATtiny3227 +const Register_file_t rgftab_attiny426[308] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.sweventa", 0x0180, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x01a8, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userusart0irda", 0x01ac, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x01ad, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x01ae, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x01af, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x01b0, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x01b1, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x01b2, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x01b3, 1, -1, 0x00, "user TCB 1 event register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e3, 1, -1, 0x00, "SPI route A register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, -1, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, -1, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny804 ATtiny806 ATtiny807 ATtiny1604 ATtiny1606 ATtiny1607 +const Register_file_t rgftab_attiny804[255] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.asyncuser11", 0x019d, 1, -1, 0x00, "asynchronous user ch 11 input selection - TCB 1 register"}, + {"evsys.asyncuser12", 0x019e, 1, -1, 0x00, "asynchronous user ch 12 input selection - ADC 1 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny814 +const Register_file_t rgftab_attiny814[265] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, -1, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, -1, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x0681, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny1614 +const Register_file_t rgftab_attiny1614[308] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"vref.ctrlc", 0x00a2, 1, -1, 0x00, "control register C"}, + {"vref.ctrld", 0x00a3, 1, -1, 0x00, "control register D"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.asyncuser11", 0x019d, 1, -1, 0x00, "asynchronous user ch 11 input selection - TCB 1 register"}, + {"evsys.asyncuser12", 0x019e, 1, -1, 0x00, "asynchronous user ch 12 input selection - ADC 1 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, -1, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, -1, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, + {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, + {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, + {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, + {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, + {"adc1.sampctrl", 0x0645, 1, -1, 0x00, "sample control register"}, + {"adc1.muxpos", 0x0646, 1, -1, 0x00, "positive mux input register"}, + {"adc1.command", 0x0648, 1, -1, 0x00, "command register"}, + {"adc1.evctrl", 0x0649, 1, -1, 0x00, "event control register"}, + {"adc1.intctrl", 0x064a, 1, -1, 0x00, "interrupt control register"}, + {"adc1.intflags", 0x064b, 1, -1, 0x00, "interrupt flags register"}, + {"adc1.dbgctrl", 0x064c, 1, -1, 0x00, "debug control register"}, + {"adc1.temp", 0x064d, 1, -1, 0x00, "temporary data register"}, + {"adc1.res", 0x0650, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc1.winlt", 0x0652, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc1.winht", 0x0654, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc1.calib", 0x0656, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.muxctrla", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.muxctrla", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a1, 1, -1, -1, "data register"}, + {"dac1.ctrla", 0x06a8, 1, -1, 0x00, "control register A"}, + {"dac1.data", 0x06a9, 1, -1, -1, "data register"}, + {"dac2.ctrla", 0x06b0, 1, -1, 0x00, "control register A"}, + {"dac2.data", 0x06b1, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a50, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a51, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a54, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a55, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a56, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a57, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a58, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a59, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a5a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a5c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny1616 ATtiny1617 +const Register_file_t rgftab_attiny1616[326] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"vref.ctrlc", 0x00a2, 1, -1, 0x00, "control register C"}, + {"vref.ctrld", 0x00a3, 1, -1, 0x00, "control register D"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.asyncuser11", 0x019d, 1, -1, 0x00, "asynchronous user ch 11 input selection - TCB 1 register"}, + {"evsys.asyncuser12", 0x019e, 1, -1, 0x00, "asynchronous user ch 12 input selection - ADC 1 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, -1, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, -1, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, + {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, + {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, + {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, + {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, + {"adc1.sampctrl", 0x0645, 1, -1, 0x00, "sample control register"}, + {"adc1.muxpos", 0x0646, 1, -1, 0x00, "positive mux input register"}, + {"adc1.command", 0x0648, 1, -1, 0x00, "command register"}, + {"adc1.evctrl", 0x0649, 1, -1, 0x00, "event control register"}, + {"adc1.intctrl", 0x064a, 1, -1, 0x00, "interrupt control register"}, + {"adc1.intflags", 0x064b, 1, -1, 0x00, "interrupt flags register"}, + {"adc1.dbgctrl", 0x064c, 1, -1, 0x00, "debug control register"}, + {"adc1.temp", 0x064d, 1, -1, 0x00, "temporary data register"}, + {"adc1.res", 0x0650, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc1.winlt", 0x0652, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc1.winht", 0x0654, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc1.calib", 0x0656, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.muxctrla", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.muxctrla", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a1, 1, -1, -1, "data register"}, + {"dac1.ctrla", 0x06a8, 1, -1, 0x00, "control register A"}, + {"dac1.data", 0x06a9, 1, -1, -1, "data register"}, + {"dac2.ctrla", 0x06b0, 1, -1, 0x00, "control register A"}, + {"dac2.data", 0x06b1, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a50, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a51, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a54, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a55, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a56, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a57, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a58, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a59, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a5a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a5c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny3216 ATtiny3217 +const Register_file_t rgftab_attiny3216[326] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"vref.ctrlc", 0x00a2, 1, -1, 0x00, "control register C"}, + {"vref.ctrld", 0x00a3, 1, -1, 0x00, "control register D"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.asyncch2", 0x0184, 1, -1, 0x00, "asynchronous channel 2 generator selection register"}, + {"evsys.asyncch3", 0x0185, 1, -1, 0x00, "asynchronous channel 3 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.asyncuser11", 0x019d, 1, -1, 0x00, "asynchronous user ch 11 input selection - TCB 1 register"}, + {"evsys.asyncuser12", 0x019e, 1, -1, 0x00, "asynchronous user ch 12 input selection - ADC 1 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, -1, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, -1, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, + {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, + {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, + {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, + {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, + {"adc1.sampctrl", 0x0645, 1, -1, 0x00, "sample control register"}, + {"adc1.muxpos", 0x0646, 1, -1, 0x00, "positive mux input register"}, + {"adc1.command", 0x0648, 1, -1, 0x00, "command register"}, + {"adc1.evctrl", 0x0649, 1, -1, 0x00, "event control register"}, + {"adc1.intctrl", 0x064a, 1, -1, 0x00, "interrupt control register"}, + {"adc1.intflags", 0x064b, 1, -1, 0x00, "interrupt flags register"}, + {"adc1.dbgctrl", 0x064c, 1, -1, 0x00, "debug control register"}, + {"adc1.temp", 0x064d, 1, -1, 0x00, "temporary data register"}, + {"adc1.res", 0x0650, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc1.winlt", 0x0652, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc1.winht", 0x0654, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc1.calib", 0x0656, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.muxctrla", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.muxctrla", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a1, 1, -1, -1, "data register"}, + {"dac1.ctrla", 0x06a8, 1, -1, 0x00, "control register A"}, + {"dac1.data", 0x06a9, 1, -1, -1, "data register"}, + {"dac2.ctrla", 0x06b0, 1, -1, 0x00, "control register A"}, + {"dac2.data", 0x06b1, 1, -1, -1, "data register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a50, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a51, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a54, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a55, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a56, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a57, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a58, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a59, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a5a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a5c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0a82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0a83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0a84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0a88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0a89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0a8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0a8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0a8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0a90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0a91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0a92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0a94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0a95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0a98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0a99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0a9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0aa2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0aa4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0aa8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0aaa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0aac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0aae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATmega808 ATmega1608 +const Register_file_t rgftab_atmega808[406] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.strobe", 0x0180, 1, -1, 0x00, "event strobe register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0", 0x01a8, 1, -1, 0x00, "user ADC 0 register"}, + {"evsys.userevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevoutd", 0x01ac, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevoute", 0x01ad, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevoutf", 0x01ae, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0", 0x01af, 1, -1, 0x00, "user USART 0 register"}, + {"evsys.userusart1", 0x01b0, 1, -1, 0x00, "user USART 1 register"}, + {"evsys.userusart2", 0x01b1, 1, -1, 0x00, "user USART 2 register"}, + {"evsys.userusart3", 0x01b2, 1, -1, 0x00, "user USART 3 register"}, + {"evsys.usertca0", 0x01b3, 1, -1, 0x00, "user TCA 0 register"}, + {"evsys.usertcb0", 0x01b4, 1, -1, 0x00, "user TCB 0 register"}, + {"evsys.usertcb1", 0x01b5, 1, -1, 0x00, "user TCB 1 register"}, + {"evsys.usertcb2", 0x01b6, 1, -1, 0x00, "user TCB 2 register"}, + {"evsys.usertcb3", 0x01b7, 1, -1, 0x00, "user TCB 3 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.twispiroutea", 0x05e3, 1, -1, 0x00, "port multiplexer TWI and SPI register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x01, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x08a1, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0aa0, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0aa1, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0aa4, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0aa5, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0aa6, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0aa7, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0aa8, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0aa9, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0aaa, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0aac, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"syscfg.ocdm", 0x0f18, 1, -1, -1, "OCD message register"}, + {"syscfg.ocdms", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATmega809 ATmega1609 +const Register_file_t rgftab_atmega809[432] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.strobe", 0x0180, 1, -1, 0x00, "event strobe register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0196, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0197, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0", 0x01a8, 1, -1, 0x00, "user ADC 0 register"}, + {"evsys.userevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevoutd", 0x01ac, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevoute", 0x01ad, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevoutf", 0x01ae, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0", 0x01af, 1, -1, 0x00, "user USART 0 register"}, + {"evsys.userusart1", 0x01b0, 1, -1, 0x00, "user USART 1 register"}, + {"evsys.userusart2", 0x01b1, 1, -1, 0x00, "user USART 2 register"}, + {"evsys.userusart3", 0x01b2, 1, -1, 0x00, "user USART 3 register"}, + {"evsys.usertca0", 0x01b3, 1, -1, 0x00, "user TCA 0 register"}, + {"evsys.usertcb0", 0x01b4, 1, -1, 0x00, "user TCB 0 register"}, + {"evsys.usertcb1", 0x01b5, 1, -1, 0x00, "user TCB 1 register"}, + {"evsys.usertcb2", 0x01b6, 1, -1, 0x00, "user TCB 2 register"}, + {"evsys.usertcb3", 0x01b7, 1, -1, 0x00, "user TCB 3 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.twispiroutea", 0x05e3, 1, -1, 0x00, "port multiplexer TWI and SPI register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x01, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x08a1, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0aa0, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0aa1, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0aa4, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0aa5, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0aa6, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0aa7, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0aa8, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0aa9, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0aaa, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0aac, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0ab0, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0ab1, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0ab4, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0ab5, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0ab6, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0ab7, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0ab8, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0ab9, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0aba, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0abc, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"syscfg.ocdm", 0x0f18, 1, -1, -1, "OCD message register"}, + {"syscfg.ocdms", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATmega3208 ATmega4808 +const Register_file_t rgftab_atmega3208[406] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, -1, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.strobe", 0x0180, 1, -1, 0x00, "event strobe register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0", 0x01a8, 1, -1, 0x00, "user ADC 0 register"}, + {"evsys.userevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevoutd", 0x01ac, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevoute", 0x01ad, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevoutf", 0x01ae, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0", 0x01af, 1, -1, 0x00, "user USART 0 register"}, + {"evsys.userusart1", 0x01b0, 1, -1, 0x00, "user USART 1 register"}, + {"evsys.userusart2", 0x01b1, 1, -1, 0x00, "user USART 2 register"}, + {"evsys.userusart3", 0x01b2, 1, -1, 0x00, "user USART 3 register"}, + {"evsys.usertca0", 0x01b3, 1, -1, 0x00, "user TCA 0 register"}, + {"evsys.usertcb0", 0x01b4, 1, -1, 0x00, "user TCB 0 register"}, + {"evsys.usertcb1", 0x01b5, 1, -1, 0x00, "user TCB 1 register"}, + {"evsys.usertcb2", 0x01b6, 1, -1, 0x00, "user TCB 2 register"}, + {"evsys.usertcb3", 0x01b7, 1, -1, 0x00, "user TCB 3 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.twispiroutea", 0x05e3, 1, -1, 0x00, "port multiplexer TWI and SPI register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x01, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x08a1, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0aa0, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0aa1, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0aa4, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0aa5, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0aa6, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0aa7, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0aa8, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0aa9, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0aaa, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0aac, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"syscfg.ocdm", 0x0f18, 1, -1, -1, "OCD message register"}, + {"syscfg.ocdms", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATmega3209 ATmega4809 +const Register_file_t rgftab_atmega3209[432] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, -1, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.strobe", 0x0180, 1, -1, 0x00, "event strobe register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0196, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0197, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0", 0x01a8, 1, -1, 0x00, "user ADC 0 register"}, + {"evsys.userevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevoutd", 0x01ac, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevoute", 0x01ad, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevoutf", 0x01ae, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0", 0x01af, 1, -1, 0x00, "user USART 0 register"}, + {"evsys.userusart1", 0x01b0, 1, -1, 0x00, "user USART 1 register"}, + {"evsys.userusart2", 0x01b1, 1, -1, 0x00, "user USART 2 register"}, + {"evsys.userusart3", 0x01b2, 1, -1, 0x00, "user USART 3 register"}, + {"evsys.usertca0", 0x01b3, 1, -1, 0x00, "user TCA 0 register"}, + {"evsys.usertcb0", 0x01b4, 1, -1, 0x00, "user TCB 0 register"}, + {"evsys.usertcb1", 0x01b5, 1, -1, 0x00, "user TCB 1 register"}, + {"evsys.usertcb2", 0x01b6, 1, -1, 0x00, "user TCB 2 register"}, + {"evsys.usertcb3", 0x01b7, 1, -1, 0x00, "user TCB 3 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.twispiroutea", 0x05e3, 1, -1, 0x00, "port multiplexer TWI and SPI register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x01, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x08a1, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0aa0, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0aa1, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0aa4, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0aa5, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0aa6, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0aa7, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0aa8, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0aa9, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0aaa, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0aac, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0ab0, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0ab1, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0ab4, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0ab5, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0ab6, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0ab7, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0ab8, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0ab9, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0aba, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0abc, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"syscfg.ocdm", 0x0f18, 1, -1, -1, "OCD message register"}, + {"syscfg.ocdms", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// AVR16EB14 +const Register_file_t rgftab_avr16eb14[390] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.pllctrlb", 0x0071, 1, -1, 0x00, "PLL control B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.usertce0cnta", 0x022e, 1, -1, 0x00, "user TCE 0 event A register"}, + {"evsys.usertce0cntb", 0x022f, 1, -1, 0x00, "user TCE 0 event B register"}, + {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcf0cnt", 0x0234, 1, -1, 0x00, "user TCF 0 clock event register"}, + {"evsys.usertcf0act", 0x0235, 1, -1, 0x00, "user TCF 0 action event register"}, + {"evsys.userwexa", 0x0236, 1, -1, 0x00, "user WEX event A register"}, + {"evsys.userwexb", 0x0237, 1, -1, 0x00, "user WEX event B register"}, + {"evsys.userwexc", 0x0238, 1, -1, 0x00, "user WEX event C register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, + {"portmux.tcfroutea", 0x05ec, 1, -1, 0x00, "TCF route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tce0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, + {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, + {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, + {"tce0.amp", 0x0a22, 2, -1, 0x0000, "amplitude register (16 bits)"}, + {"tce0.offset", 0x0a24, 2, -1, 0x0000, "offset register (16 bits)"}, + {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, + {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, + {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tce0.cmp3", 0x0a2e, 2, -1, 0x0000, "compare 3 register (16 bits)"}, + {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, + {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, + {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tce0.cmp3buf", 0x0a3e, 2, -1, 0x0000, "compare 3 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcf0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, + {"tcf0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, + {"tcf0.ctrlc", 0x0c02, 1, -1, 0x00, "control register C"}, + {"tcf0.ctrld", 0x0c03, 1, -1, 0x00, "control register D"}, + {"tcf0.evctrl", 0x0c04, 1, -1, 0x00, "event control register"}, + {"tcf0.intctrl", 0x0c05, 1, -1, 0x00, "interrupt control register"}, + {"tcf0.intflags", 0x0c06, 1, -1, 0x00, "interrupt flags register"}, + {"tcf0.status", 0x0c07, 1, -1, 0x00, "status register"}, + {"tcf0.dbgctrl", 0x0c0d, 1, -1, 0x00, "debug control register"}, + {"tcf0.cnt", 0x0c10, 4, -1, 0x00000000, "counter (32 bits)"}, + {"tcf0.cmp", 0x0c14, 4, -1, 0x00000000, "compare register (32 bits)"}, + {"wex0.ctrla", 0x0c80, 1, -1, 0x00, "control register A"}, + {"wex0.ctrlb", 0x0c81, 1, -1, 0x00, "control register B"}, + {"wex0.ctrlc", 0x0c82, 1, -1, 0x00, "control register C"}, + {"wex0.evctrla", 0x0c84, 1, -1, 0x00, "event control register A"}, + {"wex0.evctrlb", 0x0c85, 1, -1, 0x00, "event control register B"}, + {"wex0.evctrlc", 0x0c86, 1, -1, 0x00, "event control register C"}, + {"wex0.bufctrl", 0x0c87, 1, -1, 0x00, "buffer valid control register"}, + {"wex0.blankctrl", 0x0c88, 1, -1, 0x00, "blanking control register"}, + {"wex0.blanktime", 0x0c89, 1, -1, 0x00, "blanking time register"}, + {"wex0.faultctrl", 0x0c8a, 1, -1, 0x00, "fault control register"}, + {"wex0.faultdrv", 0x0c8b, 1, -1, 0x00, "fault drive register"}, + {"wex0.faultout", 0x0c8c, 1, -1, 0x00, "fault output register"}, + {"wex0.intctrl", 0x0c8d, 1, -1, 0x00, "interrupt control register"}, + {"wex0.intflags", 0x0c8e, 1, -1, 0x00, "interrupt flags register"}, + {"wex0.status", 0x0c8f, 1, -1, 0x00, "status register"}, + {"wex0.dtls", 0x0c90, 1, -1, 0x00, "dead-time low side register"}, + {"wex0.dths", 0x0c91, 1, -1, 0x00, "dead-time high side register"}, + {"wex0.dtboth", 0x0c92, 1, -1, 0x00, "dead-time both sides register"}, + {"wex0.swap", 0x0c93, 1, -1, 0x00, "DTI swap register"}, + {"wex0.pgmovr", 0x0c94, 1, -1, 0x00, "pattern generation override register"}, + {"wex0.pgmout", 0x0c95, 1, -1, 0x00, "pattern generation output register"}, + {"wex0.outoven", 0x0c97, 1, -1, 0x00, "output override enable register"}, + {"wex0.dtlsbuf", 0x0c98, 1, -1, 0x00, "dead-time low side buffer register"}, + {"wex0.dthsbuf", 0x0c99, 1, -1, 0x00, "dead-time high side buffer register"}, + {"wex0.dtbothbuf", 0x0c9a, 1, -1, 0x00, "dead-time both sides buffer register"}, + {"wex0.swapbuf", 0x0c9b, 1, -1, 0x00, "DTI swap buffer register"}, + {"wex0.pgmovrbuf", 0x0c9c, 1, -1, 0x00, "pattern generation override buffer register"}, + {"wex0.pgmoutbuf", 0x0c9d, 1, -1, 0x00, "pattern generation output buffer register"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16EB20 AVR16EB28 AVR16EB32 +const Register_file_t rgftab_avr16eb20[391] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.pllctrlb", 0x0071, 1, -1, 0x00, "PLL control B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.usertce0cnta", 0x022e, 1, -1, 0x00, "user TCE 0 event A register"}, + {"evsys.usertce0cntb", 0x022f, 1, -1, 0x00, "user TCE 0 event B register"}, + {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcf0cnt", 0x0234, 1, -1, 0x00, "user TCF 0 clock event register"}, + {"evsys.usertcf0act", 0x0235, 1, -1, 0x00, "user TCF 0 action event register"}, + {"evsys.userwexa", 0x0236, 1, -1, 0x00, "user WEX event A register"}, + {"evsys.userwexb", 0x0237, 1, -1, 0x00, "user WEX event B register"}, + {"evsys.userwexc", 0x0238, 1, -1, 0x00, "user WEX event C register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcfroutea", 0x05ec, 1, -1, 0x00, "TCF route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tce0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, + {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, + {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, + {"tce0.amp", 0x0a22, 2, -1, 0x0000, "amplitude register (16 bits)"}, + {"tce0.offset", 0x0a24, 2, -1, 0x0000, "offset register (16 bits)"}, + {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, + {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, + {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tce0.cmp3", 0x0a2e, 2, -1, 0x0000, "compare 3 register (16 bits)"}, + {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, + {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, + {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tce0.cmp3buf", 0x0a3e, 2, -1, 0x0000, "compare 3 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcf0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, + {"tcf0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, + {"tcf0.ctrlc", 0x0c02, 1, -1, 0x00, "control register C"}, + {"tcf0.ctrld", 0x0c03, 1, -1, 0x00, "control register D"}, + {"tcf0.evctrl", 0x0c04, 1, -1, 0x00, "event control register"}, + {"tcf0.intctrl", 0x0c05, 1, -1, 0x00, "interrupt control register"}, + {"tcf0.intflags", 0x0c06, 1, -1, 0x00, "interrupt flags register"}, + {"tcf0.status", 0x0c07, 1, -1, 0x00, "status register"}, + {"tcf0.dbgctrl", 0x0c0d, 1, -1, 0x00, "debug control register"}, + {"tcf0.cnt", 0x0c10, 4, -1, 0x00000000, "counter (32 bits)"}, + {"tcf0.cmp", 0x0c14, 4, -1, 0x00000000, "compare register (32 bits)"}, + {"wex0.ctrla", 0x0c80, 1, -1, 0x00, "control register A"}, + {"wex0.ctrlb", 0x0c81, 1, -1, 0x00, "control register B"}, + {"wex0.ctrlc", 0x0c82, 1, -1, 0x00, "control register C"}, + {"wex0.evctrla", 0x0c84, 1, -1, 0x00, "event control register A"}, + {"wex0.evctrlb", 0x0c85, 1, -1, 0x00, "event control register B"}, + {"wex0.evctrlc", 0x0c86, 1, -1, 0x00, "event control register C"}, + {"wex0.bufctrl", 0x0c87, 1, -1, 0x00, "buffer valid control register"}, + {"wex0.blankctrl", 0x0c88, 1, -1, 0x00, "blanking control register"}, + {"wex0.blanktime", 0x0c89, 1, -1, 0x00, "blanking time register"}, + {"wex0.faultctrl", 0x0c8a, 1, -1, 0x00, "fault control register"}, + {"wex0.faultdrv", 0x0c8b, 1, -1, 0x00, "fault drive register"}, + {"wex0.faultout", 0x0c8c, 1, -1, 0x00, "fault output register"}, + {"wex0.intctrl", 0x0c8d, 1, -1, 0x00, "interrupt control register"}, + {"wex0.intflags", 0x0c8e, 1, -1, 0x00, "interrupt flags register"}, + {"wex0.status", 0x0c8f, 1, -1, 0x00, "status register"}, + {"wex0.dtls", 0x0c90, 1, -1, 0x00, "dead-time low side register"}, + {"wex0.dths", 0x0c91, 1, -1, 0x00, "dead-time high side register"}, + {"wex0.dtboth", 0x0c92, 1, -1, 0x00, "dead-time both sides register"}, + {"wex0.swap", 0x0c93, 1, -1, 0x00, "DTI swap register"}, + {"wex0.pgmovr", 0x0c94, 1, -1, 0x00, "pattern generation override register"}, + {"wex0.pgmout", 0x0c95, 1, -1, 0x00, "pattern generation output register"}, + {"wex0.outoven", 0x0c97, 1, -1, 0x00, "output override enable register"}, + {"wex0.dtlsbuf", 0x0c98, 1, -1, 0x00, "dead-time low side buffer register"}, + {"wex0.dthsbuf", 0x0c99, 1, -1, 0x00, "dead-time high side buffer register"}, + {"wex0.dtbothbuf", 0x0c9a, 1, -1, 0x00, "dead-time both sides buffer register"}, + {"wex0.swapbuf", 0x0c9b, 1, -1, 0x00, "DTI swap buffer register"}, + {"wex0.pgmovrbuf", 0x0c9c, 1, -1, 0x00, "pattern generation override buffer register"}, + {"wex0.pgmoutbuf", 0x0c9d, 1, -1, 0x00, "pattern generation output buffer register"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16EA28 AVR16EA32 AVR32EA28 AVR32EA32 AVR64EA28 AVR64EA32 +const Register_file_t rgftab_avr16ea28[402] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022b, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022c, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022e, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022f, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0230, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0231, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x0232, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0233, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x0234, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x0235, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x0236, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0237, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0238, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0239, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023a, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023b, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023c, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023d, 1, -1, 0x00, "user TCB 3 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrl", 0x0418, 1, -1, 0x00, "event generation control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrl", 0x0458, 1, -1, 0x00, "event generation control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrl", 0x0478, 1, -1, 0x00, "event generation control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrl", 0x04b8, 1, -1, 0x00, "event generation control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR32DA28 +const Register_file_t rgftab_avr32da28[432] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DB28 AVR64DB28 AVR128DB28 +const Register_file_t rgftab_avr32db28[462] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DA32 +const Register_file_t rgftab_avr32da32[447] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DB32 AVR64DB32 AVR128DB32 +const Register_file_t rgftab_avr32db32[477] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DA48 +const Register_file_t rgftab_avr32da48[600] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, 0x00, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, 0x00, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, 0x00, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, 0x00, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, 0x00, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, 0x00, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022f, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0232, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0238, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0239, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023d, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023e, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0245, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0246, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, 0x00, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, 0x00, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, 0x00, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, 0x00, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, 0x00, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, 0x00, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, 0x00, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, 0x00, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, 0x00, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, 0x00, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, 0x00, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, 0x00, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, 0x00, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, 0x00, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, 0x00, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, 0x00, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, 0x00, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, 0x00, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x00, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, -1, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, -1, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, -1, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DB48 AVR64DB48 AVR128DB48 +const Register_file_t rgftab_avr32db48[643] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, + {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, + {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, + {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, + {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, + {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, + {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, + {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, + {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, + {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, + {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x00, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, -1, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, -1, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, -1, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64DA28 AVR128DA28 +const Register_file_t rgftab_avr64da28[433] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64DA32 AVR128DA32 +const Register_file_t rgftab_avr64da32[448] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64DA48 AVR128DA48 +const Register_file_t rgftab_avr64da48[601] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, 0x00, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, 0x00, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, 0x00, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, 0x00, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, 0x00, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, 0x00, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022f, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0232, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0238, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0239, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023d, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023e, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0245, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0246, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, 0x00, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, 0x00, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, 0x00, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, 0x00, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, 0x00, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, 0x00, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, 0x00, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, 0x00, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, 0x00, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, 0x00, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, 0x00, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, 0x00, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, 0x00, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, 0x00, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, 0x00, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, 0x00, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, 0x00, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, 0x00, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x00, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, -1, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, -1, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, -1, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64DA64 AVR128DA64 +const Register_file_t rgftab_avr64da64[659] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, 0x00, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, 0x00, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, 0x00, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, 0x00, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, 0x00, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, 0x00, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"vportg.dir", 0x0018, 1, -1, 0x00, "data direction register"}, + {"vportg.out", 0x0019, 1, -1, 0x00, "I/O port output register"}, + {"vportg.in", 0x001a, 1, -1, 0x00, "I/O port input register"}, + {"vportg.intflags", 0x001b, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00a0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00a2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00a4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userptcstart", 0x022d, 1, -1, 0x00, "user PTC register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022f, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x0230, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0231, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0232, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0233, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userevsysevoutg", 0x0234, 1, -1, 0x00, "user EVOUT port G register"}, + {"evsys.userusart0irda", 0x0235, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0236, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0237, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0238, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0239, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.userusart5irda", 0x023a, 1, -1, 0x00, "user USART 5 IrDA event register"}, + {"evsys.usertca0cnta", 0x023b, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023c, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023d, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023e, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023f, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0240, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0241, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0242, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0243, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0244, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0245, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0246, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcb4capt", 0x0247, 1, -1, 0x00, "user TCB 4 capture register"}, + {"evsys.usertcb4count", 0x0248, 1, -1, 0x00, "user TCB 4 event register"}, + {"evsys.usertcd0inputa", 0x0249, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x024a, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, 0x00, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, 0x00, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, 0x00, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, 0x00, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, 0x00, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, 0x00, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, 0x00, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, 0x00, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, 0x00, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, 0x00, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, 0x00, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, 0x00, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, 0x00, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, 0x00, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, 0x00, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, 0x00, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, 0x00, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, 0x00, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portg.dir", 0x04c0, 1, -1, 0x00, "data direction register"}, + {"portg.dirset", 0x04c1, 1, -1, 0x00, "data direction set register"}, + {"portg.dirclr", 0x04c2, 1, -1, 0x00, "data direction clear register"}, + {"portg.dirtgl", 0x04c3, 1, -1, 0x00, "data direction toggle register"}, + {"portg.out", 0x04c4, 1, -1, 0x00, "I/O port output register"}, + {"portg.outset", 0x04c5, 1, -1, 0x00, "I/O port output set register"}, + {"portg.outclr", 0x04c6, 1, -1, 0x00, "I/O port output clear register"}, + {"portg.outtgl", 0x04c7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portg.in", 0x04c8, 1, -1, 0x00, "I/O port input register"}, + {"portg.intflags", 0x04c9, 1, -1, 0x00, "interrupt flags register"}, + {"portg.portctrl", 0x04ca, 1, -1, 0x00, "port control register"}, + {"portg.pinconfig", 0x04cb, 1, -1, 0x00, "pin control config register"}, + {"portg.pinctrlupd", 0x04cc, 1, -1, 0x00, "pin control update register"}, + {"portg.pinctrlset", 0x04cd, 1, -1, 0x00, "pin control set register"}, + {"portg.pinctrlclr", 0x04ce, 1, -1, 0x00, "pin control clear register"}, + {"portg.pin0ctrl", 0x04d0, 1, -1, 0x00, "pin 0 control register"}, + {"portg.pin1ctrl", 0x04d1, 1, -1, 0x00, "pin 1 control register"}, + {"portg.pin2ctrl", 0x04d2, 1, -1, 0x00, "pin 2 control register"}, + {"portg.pin3ctrl", 0x04d3, 1, -1, 0x00, "pin 3 control register"}, + {"portg.pin4ctrl", 0x04d4, 1, -1, 0x00, "pin 4 control register"}, + {"portg.pin5ctrl", 0x04d5, 1, -1, 0x00, "pin 5 control register"}, + {"portg.pin6ctrl", 0x04d6, 1, -1, 0x00, "pin 6 control register"}, + {"portg.pin7ctrl", 0x04d7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, + {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, + {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x00, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart5.rxdatal", 0x08a0, 1, -1, 0x00, "receive data low byte"}, + {"usart5.rxdatah", 0x08a1, 1, -1, 0x00, "receive data high byte"}, + {"usart5.txdatal", 0x08a2, 1, -1, 0x00, "transmit data low byte"}, + {"usart5.txdatah", 0x08a3, 1, -1, 0x00, "transmit data high byte"}, + {"usart5.status", 0x08a4, 1, -1, 0x00, "status register"}, + {"usart5.ctrla", 0x08a5, 1, -1, 0x00, "control register A"}, + {"usart5.ctrlb", 0x08a6, 1, -1, 0x00, "control register B"}, + {"usart5.ctrlc", 0x08a7, 1, -1, 0x03, "control register C"}, + {"usart5.baud", 0x08a8, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart5.ctrld", 0x08aa, 1, -1, 0x00, "control register D"}, + {"usart5.dbgctrl", 0x08ab, 1, -1, 0x00, "debug control register"}, + {"usart5.evctrl", 0x08ac, 1, -1, 0x00, "event control register"}, + {"usart5.txplctrl", 0x08ad, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart5.rxplctrl", 0x08ae, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, -1, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, -1, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, -1, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb4.ctrla", 0x0b40, 1, -1, 0x00, "control register A"}, + {"tcb4.ctrlb", 0x0b41, 1, -1, 0x00, "control register B"}, + {"tcb4.evctrl", 0x0b44, 1, -1, 0x00, "event control register"}, + {"tcb4.intctrl", 0x0b45, 1, -1, 0x00, "interrupt control register"}, + {"tcb4.intflags", 0x0b46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb4.status", 0x0b47, 1, -1, 0x00, "status register"}, + {"tcb4.dbgctrl", 0x0b48, 1, -1, 0x00, "debug control register"}, + {"tcb4.temp", 0x0b49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb4.cnt", 0x0b4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb4.ccmp", 0x0b4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64DB64 AVR128DB64 +const Register_file_t rgftab_avr64db64[698] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"vportg.dir", 0x0018, 1, -1, -1, "data direction register"}, + {"vportg.out", 0x0019, 1, -1, -1, "I/O port output register"}, + {"vportg.in", 0x001a, 1, -1, -1, "I/O port input register"}, + {"vportg.intflags", 0x001b, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userevsysevoutg", 0x0233, 1, -1, 0x00, "user EVOUT port G register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.userusart5irda", 0x0239, 1, -1, 0x00, "user USART 5 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcb4capt", 0x0246, 1, -1, 0x00, "user TCB 4 capture register"}, + {"evsys.usertcb4count", 0x0247, 1, -1, 0x00, "user TCB 4 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, + {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, + {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, + {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portg.dir", 0x04c0, 1, -1, -1, "data direction register"}, + {"portg.dirset", 0x04c1, 1, -1, -1, "data direction set register"}, + {"portg.dirclr", 0x04c2, 1, -1, -1, "data direction clear register"}, + {"portg.dirtgl", 0x04c3, 1, -1, -1, "data direction toggle register"}, + {"portg.out", 0x04c4, 1, -1, -1, "I/O port output register"}, + {"portg.outset", 0x04c5, 1, -1, -1, "I/O port output set register"}, + {"portg.outclr", 0x04c6, 1, -1, -1, "I/O port output clear register"}, + {"portg.outtgl", 0x04c7, 1, -1, -1, "I/O port output toggle register"}, + {"portg.in", 0x04c8, 1, -1, -1, "I/O port input register"}, + {"portg.intflags", 0x04c9, 1, -1, 0x00, "interrupt flags register"}, + {"portg.portctrl", 0x04ca, 1, -1, 0x00, "port control register"}, + {"portg.pinconfig", 0x04cb, 1, -1, 0x00, "pin control config register"}, + {"portg.pinctrlupd", 0x04cc, 1, -1, 0x00, "pin control update register"}, + {"portg.pinctrlset", 0x04cd, 1, -1, 0x00, "pin control set register"}, + {"portg.pinctrlclr", 0x04ce, 1, -1, 0x00, "pin control clear register"}, + {"portg.pin0ctrl", 0x04d0, 1, -1, 0x00, "pin 0 control register"}, + {"portg.pin1ctrl", 0x04d1, 1, -1, 0x00, "pin 1 control register"}, + {"portg.pin2ctrl", 0x04d2, 1, -1, 0x00, "pin 2 control register"}, + {"portg.pin3ctrl", 0x04d3, 1, -1, 0x00, "pin 3 control register"}, + {"portg.pin4ctrl", 0x04d4, 1, -1, 0x00, "pin 4 control register"}, + {"portg.pin5ctrl", 0x04d5, 1, -1, 0x00, "pin 5 control register"}, + {"portg.pin6ctrl", 0x04d6, 1, -1, 0x00, "pin 6 control register"}, + {"portg.pin7ctrl", 0x04d7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, + {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, + {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, + {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, + {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, + {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, + {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, + {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x00, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x00, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x00, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart5.rxdatal", 0x08a0, 1, -1, 0x00, "receive data low byte"}, + {"usart5.rxdatah", 0x08a1, 1, -1, 0x00, "receive data high byte"}, + {"usart5.txdatal", 0x08a2, 1, -1, 0x00, "transmit data low byte"}, + {"usart5.txdatah", 0x08a3, 1, -1, 0x00, "transmit data high byte"}, + {"usart5.status", 0x08a4, 1, -1, 0x00, "status register"}, + {"usart5.ctrla", 0x08a5, 1, -1, 0x00, "control register A"}, + {"usart5.ctrlb", 0x08a6, 1, -1, 0x00, "control register B"}, + {"usart5.ctrlc", 0x08a7, 1, -1, 0x03, "control register C"}, + {"usart5.baud", 0x08a8, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart5.ctrld", 0x08aa, 1, -1, 0x00, "control register D"}, + {"usart5.dbgctrl", 0x08ab, 1, -1, 0x00, "debug control register"}, + {"usart5.evctrl", 0x08ac, 1, -1, 0x00, "event control register"}, + {"usart5.txplctrl", 0x08ad, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart5.rxplctrl", 0x08ae, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, -1, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, -1, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, -1, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, -1, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, -1, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, -1, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, -1, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, -1, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, -1, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb4.ctrla", 0x0b40, 1, -1, 0x00, "control register A"}, + {"tcb4.ctrlb", 0x0b41, 1, -1, 0x00, "control register B"}, + {"tcb4.evctrl", 0x0b44, 1, -1, 0x00, "event control register"}, + {"tcb4.intctrl", 0x0b45, 1, -1, 0x00, "interrupt control register"}, + {"tcb4.intflags", 0x0b46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb4.status", 0x0b47, 1, -1, 0x00, "status register"}, + {"tcb4.dbgctrl", 0x0b48, 1, -1, 0x00, "debug control register"}, + {"tcb4.temp", 0x0b49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb4.cnt", 0x0b4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb4.ccmp", 0x0b4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, -1, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, -1, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, -1, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, -1, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, -1, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, -1, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; diff --git a/src/avrintel.h b/src/avrintel.h index fd749c7c..3df9f8bd 100644 --- a/src/avrintel.h +++ b/src/avrintel.h @@ -9,7 +9,7 @@ * Meta-author Stefan Rueger * * v 1.3 - * 15.08.2023 + * 27.11.2023 * */ @@ -34,6 +34,15 @@ typedef struct { const char *ccomment; // Expanded semantic name for this configuration item } Configitem_t; +typedef struct { + const char *reg; // Name of I/O register + int addr; // Address of register in IO memory + int size; // Size of register (1, 2 or 4 bytes) + int mask; // Bit mask for register, if any (-1 means none/unknown) + int initval; // Reset value, if any (-1 means none/unknown) + const char *caption; // Expanded semantic name +} Register_file_t; + typedef struct { // Value of -1 typically means unknown const char *name; // Name of part uint16_t mcuid; // ID of MCU in 0..2039 @@ -55,6 +64,8 @@ typedef struct { // Value of -1 typically means unknown const char * const *isrtable; // Interrupt vector table vector names uint8_t nconfigs; // Number of configuration bitfields in fuses/locks const Configitem_t *cfgtable; // Configuration bitfield table + uint16_t nregisters; // Number of I/O registers + const Register_file_t *regf; // Register file } uPcore_t; #define F_AVR8L 1 // TPI programming, ATtiny(4|5|9|10|20|40|102|104) @@ -2169,6 +2180,507 @@ extern const Configitem_t cfgtab_avr32db28[16]; #define cfgtab_avr128db48 cfgtab_avr32db28 #define cfgtab_avr128db64 cfgtab_avr32db28 +// I/O Register files + +extern const Register_file_t rgftab_atmega328[81]; +#define rgftab_atmega328p rgftab_atmega328 + +extern const Register_file_t rgftab_atmega16m1[136]; +#define rgftab_atmega32m1 rgftab_atmega16m1 + +extern const Register_file_t rgftab_atmega32hvbrevb[91]; +#define rgftab_atmega16hvb rgftab_atmega32hvbrevb +#define rgftab_atmega16hvbrevb rgftab_atmega32hvbrevb +#define rgftab_atmega32hvb rgftab_atmega32hvbrevb + +extern const Register_file_t rgftab_atmega328pb[123]; + +extern const Register_file_t rgftab_atmega8515[52]; + +extern const Register_file_t rgftab_attiny102[55]; +#define rgftab_attiny104 rgftab_attiny102 + +extern const Register_file_t rgftab_attiny28[20]; + +extern const Register_file_t rgftab_attiny441[101]; +#define rgftab_attiny841 rgftab_attiny441 + +extern const Register_file_t rgftab_at90pwm81[84]; + +extern const Register_file_t rgftab_at90can128[137]; +#define rgftab_at90can32 rgftab_at90can128 +#define rgftab_at90can64 rgftab_at90can128 + +extern const Register_file_t rgftab_at90usb162[92]; +#define rgftab_at90usb82 rgftab_at90usb162 + +extern const Register_file_t rgftab_ata5700m322[337]; + +extern const Register_file_t rgftab_ata5781[262]; +#define rgftab_ata5782 rgftab_ata5781 +#define rgftab_ata5783 rgftab_ata5781 +#define rgftab_ata8210 rgftab_ata5781 +#define rgftab_ata8215 rgftab_ata5781 + +extern const Register_file_t rgftab_ata5790[112]; + +extern const Register_file_t rgftab_ata6285[79]; +#define rgftab_ata6286 rgftab_ata6285 + +extern const Register_file_t rgftab_atxmega16e5[438]; +#define rgftab_atxmega8e5 rgftab_atxmega16e5 +#define rgftab_atxmega32e5 rgftab_atxmega16e5 + +extern const Register_file_t rgftab_atxmega128a3[680]; +#define rgftab_atxmega64a3 rgftab_atxmega128a3 +#define rgftab_atxmega192a3 rgftab_atxmega128a3 +#define rgftab_atxmega256a3 rgftab_atxmega128a3 + +extern const Register_file_t rgftab_atxmega128a3u[792]; +#define rgftab_atxmega64a3u rgftab_atxmega128a3u +#define rgftab_atxmega192a3u rgftab_atxmega128a3u +#define rgftab_atxmega256a3u rgftab_atxmega128a3u + +extern const Register_file_t rgftab_attiny204[235]; +#define rgftab_attiny404 rgftab_attiny204 + +extern const Register_file_t rgftab_attiny1624[307]; +#define rgftab_attiny424 rgftab_attiny1624 +#define rgftab_attiny824 rgftab_attiny1624 +#define rgftab_attiny3224 rgftab_attiny1624 + +extern const Register_file_t rgftab_avr32dd14[401]; +#define rgftab_avr16dd14 rgftab_avr32dd14 +#define rgftab_avr16dd20 rgftab_avr32dd14 +#define rgftab_avr16dd28 rgftab_avr32dd14 +#define rgftab_avr16dd32 rgftab_avr32dd14 +#define rgftab_avr32dd20 rgftab_avr32dd14 +#define rgftab_avr32dd28 rgftab_avr32dd14 +#define rgftab_avr32dd32 rgftab_avr32dd14 +#define rgftab_avr64dd14 rgftab_avr32dd14 +#define rgftab_avr64dd20 rgftab_avr32dd14 +#define rgftab_avr64dd28 rgftab_avr32dd14 +#define rgftab_avr64dd32 rgftab_avr32dd14 + +extern const Register_file_t rgftab_avr64ea48[502]; +#define rgftab_avr16ea48 rgftab_avr64ea48 +#define rgftab_avr32ea48 rgftab_avr64ea48 + +extern const Register_file_t rgftab_attiny4[36]; +#define rgftab_attiny9 rgftab_attiny4 + +extern const Register_file_t rgftab_attiny5[41]; +#define rgftab_attiny10 rgftab_attiny5 + +extern const Register_file_t rgftab_attiny20[61]; + +extern const Register_file_t rgftab_attiny40[63]; + +extern const Register_file_t rgftab_attiny11[14]; + +extern const Register_file_t rgftab_attiny12[18]; + +extern const Register_file_t rgftab_attiny13[35]; + +extern const Register_file_t rgftab_attiny13a[37]; + +extern const Register_file_t rgftab_attiny15[28]; + +extern const Register_file_t rgftab_attiny24[55]; +#define rgftab_attiny24a rgftab_attiny24 + +extern const Register_file_t rgftab_attiny25[55]; + +extern const Register_file_t rgftab_attiny26[37]; + +extern const Register_file_t rgftab_attiny43u[54]; + +extern const Register_file_t rgftab_attiny44[55]; +#define rgftab_attiny44a rgftab_attiny44 + +extern const Register_file_t rgftab_attiny45[55]; +#define rgftab_attiny85 rgftab_attiny45 + +extern const Register_file_t rgftab_attiny48[74]; + +extern const Register_file_t rgftab_attiny84[55]; +#define rgftab_attiny84a rgftab_attiny84 + +extern const Register_file_t rgftab_attiny87[80]; +#define rgftab_attiny167 rgftab_attiny87 + +extern const Register_file_t rgftab_attiny88[74]; + +extern const Register_file_t rgftab_attiny261[63]; +#define rgftab_attiny261a rgftab_attiny261 + +extern const Register_file_t rgftab_attiny461[63]; +#define rgftab_attiny461a rgftab_attiny461 + +extern const Register_file_t rgftab_attiny828[94]; + +extern const Register_file_t rgftab_attiny861[63]; +#define rgftab_attiny861a rgftab_attiny861 + +extern const Register_file_t rgftab_attiny1634[89]; + +extern const Register_file_t rgftab_attiny2313[54]; + +extern const Register_file_t rgftab_attiny2313a[58]; + +extern const Register_file_t rgftab_attiny4313[58]; + +extern const Register_file_t rgftab_atmega8[61]; +#define rgftab_atmega8a rgftab_atmega8 + +extern const Register_file_t rgftab_atmega8hva[74]; +#define rgftab_atmega16hva rgftab_atmega8hva + +extern const Register_file_t rgftab_atmega8u2[92]; +#define rgftab_atmega16u2 rgftab_atmega8u2 +#define rgftab_atmega32u2 rgftab_atmega8u2 + +extern const Register_file_t rgftab_atmega16[70]; + +extern const Register_file_t rgftab_atmega16a[70]; + +extern const Register_file_t rgftab_atmega16u4[139]; +#define rgftab_atmega32u4 rgftab_atmega16u4 + +extern const Register_file_t rgftab_atmega32[68]; + +extern const Register_file_t rgftab_atmega32a[66]; + +extern const Register_file_t rgftab_atmega32c1[117]; + +extern const Register_file_t rgftab_atmega48[81]; +#define rgftab_atmega48p rgftab_atmega48 + +extern const Register_file_t rgftab_atmega48a[82]; +#define rgftab_atmega48pa rgftab_atmega48a + +extern const Register_file_t rgftab_atmega48pb[95]; + +extern const Register_file_t rgftab_atmega64[103]; +#define rgftab_atmega64a rgftab_atmega64 + +extern const Register_file_t rgftab_atmega64c1[122]; + +extern const Register_file_t rgftab_atmega64m1[136]; + +extern const Register_file_t rgftab_atmega64hve2[89]; + +extern const Register_file_t rgftab_atmega64rfr2[269]; +#define rgftab_atmega644rfr2 rgftab_atmega64rfr2 + +extern const Register_file_t rgftab_atmega88[81]; +#define rgftab_atmega88a rgftab_atmega88 +#define rgftab_atmega88p rgftab_atmega88 +#define rgftab_atmega88pa rgftab_atmega88 +#define rgftab_atmega168 rgftab_atmega88 +#define rgftab_atmega168a rgftab_atmega88 +#define rgftab_atmega168p rgftab_atmega88 +#define rgftab_atmega168pa rgftab_atmega88 + +extern const Register_file_t rgftab_atmega88pb[95]; +#define rgftab_atmega168pb rgftab_atmega88pb + +extern const Register_file_t rgftab_atmega128[103]; + +extern const Register_file_t rgftab_atmega128a[103]; + +extern const Register_file_t rgftab_atmega128rfa1[237]; + +extern const Register_file_t rgftab_atmega128rfr2[270]; +#define rgftab_atmega1284rfr2 rgftab_atmega128rfr2 + +extern const Register_file_t rgftab_atmega162[79]; + +extern const Register_file_t rgftab_atmega164a[96]; +#define rgftab_atmega164p rgftab_atmega164a +#define rgftab_atmega164pa rgftab_atmega164a +#define rgftab_atmega324a rgftab_atmega164a +#define rgftab_atmega324p rgftab_atmega164a +#define rgftab_atmega324pa rgftab_atmega164a + +extern const Register_file_t rgftab_atmega165a[86]; +#define rgftab_atmega165p rgftab_atmega165a +#define rgftab_atmega165pa rgftab_atmega165a + +extern const Register_file_t rgftab_atmega169a[106]; +#define rgftab_atmega169p rgftab_atmega169a +#define rgftab_atmega169pa rgftab_atmega169a + +extern const Register_file_t rgftab_atmega256rfr2[271]; + +extern const Register_file_t rgftab_atmega324pb[134]; + +extern const Register_file_t rgftab_atmega325[86]; +#define rgftab_atmega325a rgftab_atmega325 +#define rgftab_atmega325p rgftab_atmega325 +#define rgftab_atmega325pa rgftab_atmega325 + +extern const Register_file_t rgftab_atmega329[106]; + +extern const Register_file_t rgftab_atmega329a[106]; +#define rgftab_atmega329pa rgftab_atmega329a + +extern const Register_file_t rgftab_atmega329p[106]; + +extern const Register_file_t rgftab_atmega406[79]; + +extern const Register_file_t rgftab_atmega640[160]; + +extern const Register_file_t rgftab_atmega644[88]; + +extern const Register_file_t rgftab_atmega644a[93]; +#define rgftab_atmega644p rgftab_atmega644a +#define rgftab_atmega644pa rgftab_atmega644a + +extern const Register_file_t rgftab_atmega645[86]; +#define rgftab_atmega645a rgftab_atmega645 +#define rgftab_atmega645p rgftab_atmega645 + +extern const Register_file_t rgftab_atmega649[106]; +#define rgftab_atmega649a rgftab_atmega649 +#define rgftab_atmega649p rgftab_atmega649 + +extern const Register_file_t rgftab_atmega1280[161]; +#define rgftab_atmega2560 rgftab_atmega1280 + +extern const Register_file_t rgftab_atmega1281[138]; + +extern const Register_file_t rgftab_atmega1284[104]; +#define rgftab_atmega1284p rgftab_atmega1284 + +extern const Register_file_t rgftab_atmega2561[139]; + +extern const Register_file_t rgftab_atmega2564rfr2[271]; + +extern const Register_file_t rgftab_atmega3250[94]; +#define rgftab_atmega3250a rgftab_atmega3250 +#define rgftab_atmega3250p rgftab_atmega3250 +#define rgftab_atmega3250pa rgftab_atmega3250 + +extern const Register_file_t rgftab_atmega3290[118]; +#define rgftab_atmega3290a rgftab_atmega3290 + +extern const Register_file_t rgftab_atmega3290p[118]; + +extern const Register_file_t rgftab_atmega3290pa[118]; + +extern const Register_file_t rgftab_atmega6450[94]; +#define rgftab_atmega6450a rgftab_atmega6450 +#define rgftab_atmega6450p rgftab_atmega6450 + +extern const Register_file_t rgftab_atmega6490[118]; +#define rgftab_atmega6490a rgftab_atmega6490 +#define rgftab_atmega6490p rgftab_atmega6490 + +extern const Register_file_t rgftab_atmega8535[67]; + +extern const Register_file_t rgftab_at90pwm1[92]; + +extern const Register_file_t rgftab_at90pwm2b[100]; + +extern const Register_file_t rgftab_at90pwm3[115]; + +extern const Register_file_t rgftab_at90pwm3b[115]; + +extern const Register_file_t rgftab_at90pwm161[86]; + +extern const Register_file_t rgftab_at90pwm216[102]; + +extern const Register_file_t rgftab_at90pwm316[117]; + +extern const Register_file_t rgftab_at90usb646[157]; +#define rgftab_at90usb647 rgftab_at90usb646 +#define rgftab_at90usb1287 rgftab_at90usb646 + +extern const Register_file_t rgftab_at90usb1286[132]; + +extern const Register_file_t rgftab_ata5272[80]; +#define rgftab_ata5505 rgftab_ata5272 + +extern const Register_file_t rgftab_ata5702m322[378]; + +extern const Register_file_t rgftab_ata5787[292]; + +extern const Register_file_t rgftab_ata5790n[117]; +#define rgftab_ata5791 rgftab_ata5790n + +extern const Register_file_t rgftab_ata5795[84]; + +extern const Register_file_t rgftab_ata5831[279]; +#define rgftab_ata5832 rgftab_ata5831 +#define rgftab_ata5833 rgftab_ata5831 +#define rgftab_ata8510 rgftab_ata5831 +#define rgftab_ata8515 rgftab_ata5831 + +extern const Register_file_t rgftab_ata5835[307]; + +extern const Register_file_t rgftab_ata6612c[81]; +#define rgftab_ata6613c rgftab_ata6612c + +extern const Register_file_t rgftab_ata6614q[81]; + +extern const Register_file_t rgftab_ata6616c[81]; +#define rgftab_ata6617c rgftab_ata6616c +#define rgftab_ata664251 rgftab_ata6616c + +extern const Register_file_t rgftab_atxmega16a4[553]; +#define rgftab_atxmega32a4 rgftab_atxmega16a4 + +extern const Register_file_t rgftab_atxmega16a4u[630]; +#define rgftab_atxmega32a4u rgftab_atxmega16a4u + +extern const Register_file_t rgftab_atxmega16c4[482]; +#define rgftab_atxmega32c4 rgftab_atxmega16c4 + +extern const Register_file_t rgftab_atxmega16d4[460]; +#define rgftab_atxmega32d4 rgftab_atxmega16d4 + +extern const Register_file_t rgftab_atxmega32c3[569]; +#define rgftab_atxmega64c3 rgftab_atxmega32c3 +#define rgftab_atxmega128c3 rgftab_atxmega32c3 +#define rgftab_atxmega192c3 rgftab_atxmega32c3 +#define rgftab_atxmega256c3 rgftab_atxmega32c3 + +extern const Register_file_t rgftab_atxmega32d3[567]; +#define rgftab_atxmega64d3 rgftab_atxmega32d3 +#define rgftab_atxmega128d3 rgftab_atxmega32d3 +#define rgftab_atxmega192d3 rgftab_atxmega32d3 +#define rgftab_atxmega256d3 rgftab_atxmega32d3 + +extern const Register_file_t rgftab_atxmega64a1[814]; +#define rgftab_atxmega128a1 rgftab_atxmega64a1 + +extern const Register_file_t rgftab_atxmega64a1u[943]; +#define rgftab_atxmega128a1u rgftab_atxmega64a1u + +extern const Register_file_t rgftab_atxmega64b1[574]; +#define rgftab_atxmega128b1 rgftab_atxmega64b1 + +extern const Register_file_t rgftab_atxmega64b3[458]; +#define rgftab_atxmega128b3 rgftab_atxmega64b3 + +extern const Register_file_t rgftab_atxmega64a4u[632]; +#define rgftab_atxmega128a4u rgftab_atxmega64a4u + +extern const Register_file_t rgftab_atxmega64d4[460]; +#define rgftab_atxmega128d4 rgftab_atxmega64d4 + +extern const Register_file_t rgftab_atxmega256a3b[665]; + +extern const Register_file_t rgftab_atxmega256a3bu[780]; + +extern const Register_file_t rgftab_atxmega384c3[603]; + +extern const Register_file_t rgftab_atxmega384d3[560]; + +extern const Register_file_t rgftab_attiny202[217]; +#define rgftab_attiny402 rgftab_attiny202 + +extern const Register_file_t rgftab_attiny212[247]; +#define rgftab_attiny412 rgftab_attiny212 + +extern const Register_file_t rgftab_attiny214[265]; +#define rgftab_attiny414 rgftab_attiny214 + +extern const Register_file_t rgftab_attiny406[253]; + +extern const Register_file_t rgftab_attiny416[283]; + +extern const Register_file_t rgftab_attiny416auto[283]; + +extern const Register_file_t rgftab_attiny417[283]; +#define rgftab_attiny816 rgftab_attiny417 +#define rgftab_attiny817 rgftab_attiny417 + +extern const Register_file_t rgftab_attiny426[308]; +#define rgftab_attiny427 rgftab_attiny426 +#define rgftab_attiny826 rgftab_attiny426 +#define rgftab_attiny827 rgftab_attiny426 +#define rgftab_attiny1626 rgftab_attiny426 +#define rgftab_attiny1627 rgftab_attiny426 +#define rgftab_attiny3226 rgftab_attiny426 +#define rgftab_attiny3227 rgftab_attiny426 + +extern const Register_file_t rgftab_attiny804[255]; +#define rgftab_attiny806 rgftab_attiny804 +#define rgftab_attiny807 rgftab_attiny804 +#define rgftab_attiny1604 rgftab_attiny804 +#define rgftab_attiny1606 rgftab_attiny804 +#define rgftab_attiny1607 rgftab_attiny804 + +extern const Register_file_t rgftab_attiny814[265]; + +extern const Register_file_t rgftab_attiny1614[308]; + +extern const Register_file_t rgftab_attiny1616[326]; +#define rgftab_attiny1617 rgftab_attiny1616 + +extern const Register_file_t rgftab_attiny3216[326]; +#define rgftab_attiny3217 rgftab_attiny3216 + +extern const Register_file_t rgftab_atmega808[406]; +#define rgftab_atmega1608 rgftab_atmega808 + +extern const Register_file_t rgftab_atmega809[432]; +#define rgftab_atmega1609 rgftab_atmega809 + +extern const Register_file_t rgftab_atmega3208[406]; +#define rgftab_atmega4808 rgftab_atmega3208 + +extern const Register_file_t rgftab_atmega3209[432]; +#define rgftab_atmega4809 rgftab_atmega3209 + +extern const Register_file_t rgftab_avr16eb14[390]; + +extern const Register_file_t rgftab_avr16eb20[391]; +#define rgftab_avr16eb28 rgftab_avr16eb20 +#define rgftab_avr16eb32 rgftab_avr16eb20 + +extern const Register_file_t rgftab_avr16ea28[402]; +#define rgftab_avr16ea32 rgftab_avr16ea28 +#define rgftab_avr32ea28 rgftab_avr16ea28 +#define rgftab_avr32ea32 rgftab_avr16ea28 +#define rgftab_avr64ea28 rgftab_avr16ea28 +#define rgftab_avr64ea32 rgftab_avr16ea28 + +extern const Register_file_t rgftab_avr32da28[432]; + +extern const Register_file_t rgftab_avr32db28[462]; +#define rgftab_avr64db28 rgftab_avr32db28 +#define rgftab_avr128db28 rgftab_avr32db28 + +extern const Register_file_t rgftab_avr32da32[447]; + +extern const Register_file_t rgftab_avr32db32[477]; +#define rgftab_avr64db32 rgftab_avr32db32 +#define rgftab_avr128db32 rgftab_avr32db32 + +extern const Register_file_t rgftab_avr32da48[600]; + +extern const Register_file_t rgftab_avr32db48[643]; +#define rgftab_avr64db48 rgftab_avr32db48 +#define rgftab_avr128db48 rgftab_avr32db48 + +extern const Register_file_t rgftab_avr64da28[433]; +#define rgftab_avr128da28 rgftab_avr64da28 + +extern const Register_file_t rgftab_avr64da32[448]; +#define rgftab_avr128da32 rgftab_avr64da32 + +extern const Register_file_t rgftab_avr64da48[601]; +#define rgftab_avr128da48 rgftab_avr64da48 + +extern const Register_file_t rgftab_avr64da64[659]; +#define rgftab_avr128da64 rgftab_avr64da64 + +extern const Register_file_t rgftab_avr64db64[698]; +#define rgftab_avr128db64 rgftab_avr64db64 + int upidxmcuid(int mcuid); int upidxsig(const uint8_t *sigs); int upidxname(const char *name);