diff --git a/src/avrintel.c b/src/avrintel.c index efa83bd5..80f9c582 100644 --- a/src/avrintel.c +++ b/src/avrintel.c @@ -8,8 +8,8 @@ * Published under GNU General Public License, version 3 (GPL-3.0) * Meta-author Stefan Rueger * - * v 1.46 - * 15.04.2026 + * v 1.50 + * 17.04.2026 * */ @@ -143,28 +143,28 @@ const Avrintel uP_table[422] = { // Value of -1 typically means unknown //ATtiny4 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny4", 0, F_AVR8L, {0x1E, 0x8F, 0x0A}, // ID /*ATtiny4*/ 0, 0x00200, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny4*/ 1, 1, 10, vtab_attiny9, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny4*/ 1, 1, 10, vtab_attiny4, 4, cfgtab_attiny4, // ISRs, Config /*ATtiny4*/ 36, rgftab_attiny4, 0, UART_NONE, -1, NULL, // Register file, UART /*ATtiny4*/ 1, ports_attiny4, WDT_CLASSIC4}, // Ports, WDT //ATtiny5 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny5", 1, F_AVR8L, {0x1E, 0x8F, 0x09}, // ID /*ATtiny5*/ 0, 0x00200, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny5*/ 1, 1, 11, vtab_attiny10, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny5*/ 1, 1, 11, vtab_attiny5, 4, cfgtab_attiny4, // ISRs, Config /*ATtiny5*/ 41, rgftab_attiny5, 0, UART_NONE, -1, NULL, // Register file, UART /*ATtiny5*/ 1, ports_attiny4, WDT_CLASSIC4}, // Ports, WDT //ATtiny9 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny9", 2, F_AVR8L, {0x1E, 0x90, 0x08}, // ID /*ATtiny9*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny9*/ 1, 1, 10, vtab_attiny9, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny9*/ 1, 1, 10, vtab_attiny4, 4, cfgtab_attiny4, // ISRs, Config /*ATtiny9*/ 36, rgftab_attiny4, 0, UART_NONE, -1, NULL, // Register file, UART /*ATtiny9*/ 1, ports_attiny4, WDT_CLASSIC4}, // Ports, WDT //ATtiny10 atdf, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"ATtiny10", 3, F_AVR8L, {0x1E, 0x90, 0x03}, // ID /*ATtiny10*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny10*/ 1, 1, 11, vtab_attiny10, 4, cfgtab_attiny4, // ISRs, Config + /*ATtiny10*/ 1, 1, 11, vtab_attiny5, 4, cfgtab_attiny4, // ISRs, Config /*ATtiny10*/ 41, rgftab_attiny5, 0, UART_NONE, -1, NULL, // Register file, UART /*ATtiny10*/ 1, ports_attiny4, WDT_CLASSIC4}, // Ports, WDT @@ -185,1285 +185,18 @@ const Avrintel uP_table[422] = { // Value of -1 typically means unknown //ATtiny102 atdf, avrdude, boot size (manual) // Sources {"ATtiny102", 6, F_AVR8L, {0x1E, 0x90, 0x0C}, // ID /*ATtiny102*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny102*/ 1, 1, 16, vtab_attiny104, 5, cfgtab_attiny102, // ISRs, Config + /*ATtiny102*/ 1, 1, 16, vtab_attiny102, 5, cfgtab_attiny102, // ISRs, Config /*ATtiny102*/ 55, rgftab_attiny102, 1, UART_CLASSIC_2x12, 1, uarts_attiny102, // Register file, UART /*ATtiny102*/ 2, ports_attiny102, WDT_CLASSIC4}, // Ports, WDT //ATtiny104 atdf, avrdude, boot size (manual) // Sources {"ATtiny104", 7, F_AVR8L, {0x1E, 0x90, 0x0B}, // ID /*ATtiny104*/ 0, 0x00400, 0x010, 0, 0, 0, 0, 0, 0x0040, 0x0020, // Mem - /*ATtiny104*/ 1, 1, 16, vtab_attiny104, 5, cfgtab_attiny102, // ISRs, Config + /*ATtiny104*/ 1, 1, 16, vtab_attiny102, 5, cfgtab_attiny102, // ISRs, Config /*ATtiny104*/ 55, rgftab_attiny102, 1, UART_CLASSIC_2x12, 1, uarts_attiny102, // Register file, UART /*ATtiny104*/ 2, ports_attiny20, WDT_CLASSIC4}, // Ports, WDT - //ATtiny11 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny11", 8, F_AVR8, {0x1E, 0x90, 0x04}, // ID - /*ATtiny11*/ 0, 0x00400, 0x001, 0, 0, 0, 0, 0, 0x0060, 0x0020, // Mem - /*ATtiny11*/ 1, 1, 5, vtab_attiny11, 4, cfgtab_attiny11, // ISRs, Config - /*ATtiny11*/ 14, rgftab_attiny11, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny11*/ 1, ports_attiny11, WDT_CLASSIC3}, // Ports, WDT - - //ATtiny12 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny12", 9, F_AVR8, {0x1E, 0x90, 0x05}, // ID - /*ATtiny12*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, // Mem - /*ATtiny12*/ 1, 1, 6, vtab_attiny12, 6, cfgtab_attiny12, // ISRs, Config - /*ATtiny12*/ 18, rgftab_attiny12, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny12*/ 1, ports_attiny11, WDT_CLASSIC3}, // Ports, WDT - - //ATtiny13 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny13", 10, F_AVR8, {0x1E, 0x90, 0x07}, // ID - /*ATtiny13*/ 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, // Mem - /*ATtiny13*/ 2, 1, 10, vtab_attiny13a, 10, cfgtab_attiny13, // ISRs, Config - /*ATtiny13*/ 35, rgftab_attiny13, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny13*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny13A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny13A", 11, F_AVR8, {0x1E, 0x90, 0x07}, // ID - /*ATtiny13A*/ 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, // Mem - /*ATtiny13A*/ 2, 1, 10, vtab_attiny13a, 10, cfgtab_attiny13, // ISRs, Config - /*ATtiny13A*/ 37, rgftab_attiny13a, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny13A*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny15 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny15", 12, F_AVR8, {0x1E, 0x90, 0x06}, // ID - /*ATtiny15*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, // Mem - /*ATtiny15*/ 1, 1, 9, vtab_attiny15, 6, cfgtab_attiny15, // ISRs, Config - /*ATtiny15*/ 28, rgftab_attiny15, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny15*/ 1, ports_attiny11, WDT_CLASSIC3}, // Ports, WDT - - //ATtiny22 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"ATtiny22", 13, F_AVR8, {0x1E, 0x91, 0x06}, // ID - /*ATtiny22*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*ATtiny22*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_attiny22, // ISRs, Config - /*ATtiny22*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny22*/ 1, ports_attiny22, WDT_CLASSIC3}, // Ports, WDT - - //ATtiny24 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny24", 14, F_AVR8, {0x1E, 0x91, 0x0B}, // ID - /*ATtiny24*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny24*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config - /*ATtiny24*/ 55, rgftab_attiny24, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny24*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny24A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny24A", 15, F_AVR8, {0x1E, 0x91, 0x0B}, // ID - /*ATtiny24A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny24A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config - /*ATtiny24A*/ 55, rgftab_attiny24, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny24A*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny25 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny25", 16, F_AVR8, {0x1E, 0x91, 0x08}, // ID - /*ATtiny25*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny25*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25, // ISRs, Config - /*ATtiny25*/ 55, rgftab_attiny25, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny25*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny26 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny26", 17, F_AVR8, {0x1E, 0x91, 0x09}, // ID - /*ATtiny26*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny26*/ 2, 1, 12, vtab_attiny26, 8, cfgtab_attiny26, // ISRs, Config - /*ATtiny26*/ 37, rgftab_attiny26, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny26*/ 2, ports_attiny26, WDT_CLASSIC3}, // Ports, WDT - - //ATtiny28 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny28", 18, F_AVR8, {0x1E, 0x91, 0x07}, // ID - /*ATtiny28*/ 0, 0x00800, 0x002, 0, 0, 0, 0, 0, 0x0060, 0x0020, // Mem - /*ATtiny28*/ 1, 1, 6, vtab_attiny28, 3, cfgtab_attiny28, // ISRs, Config - /*ATtiny28*/ 20, rgftab_attiny28, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny28*/ 3, ports_attiny28, WDT_CLASSIC3}, // Ports, WDT - - //ATtiny43U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny43U", 19, F_AVR8, {0x1E, 0x92, 0x0C}, // ID - /*ATtiny43U*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0060, 0x0100, // Mem - /*ATtiny43U*/ 3, 1, 16, vtab_attiny43u, 11, cfgtab_attiny43u, // ISRs, Config - /*ATtiny43U*/ 54, rgftab_attiny43u, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny43U*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny44 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny44", 20, F_AVR8, {0x1E, 0x92, 0x07}, // ID - /*ATtiny44*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny44*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config - /*ATtiny44*/ 55, rgftab_attiny44, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny44*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny44A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny44A", 21, F_AVR8, {0x1E, 0x92, 0x07}, // ID - /*ATtiny44A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny44A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config - /*ATtiny44A*/ 55, rgftab_attiny44, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny44A*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny45 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny45", 22, F_AVR8, {0x1E, 0x92, 0x06}, // ID - /*ATtiny45*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny45*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25, // ISRs, Config - /*ATtiny45*/ 55, rgftab_attiny45, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny45*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny48 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny48", 23, F_AVR8, {0x1E, 0x92, 0x09}, // ID - /*ATtiny48*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0100, // Mem - /*ATtiny48*/ 3, 1, 20, vtab_attiny88, 11, cfgtab_attiny48, // ISRs, Config - /*ATtiny48*/ 74, rgftab_attiny48, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny48*/ 4, ports_attiny48, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny84 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny84", 24, F_AVR8, {0x1E, 0x93, 0x0C}, // ID - /*ATtiny84*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny84*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config - /*ATtiny84*/ 55, rgftab_attiny84, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny84*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny84A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny84A", 25, F_AVR8, {0x1E, 0x93, 0x0C}, // ID - /*ATtiny84A*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny84A*/ 3, 1, 17, vtab_attiny84a, 11, cfgtab_attiny24, // ISRs, Config - /*ATtiny84A*/ 55, rgftab_attiny84, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny84A*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny85 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny85", 26, F_AVR8, {0x1E, 0x93, 0x0B}, // ID - /*ATtiny85*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny85*/ 3, 1, 15, vtab_attiny85, 11, cfgtab_attiny25, // ISRs, Config - /*ATtiny85*/ 55, rgftab_attiny45, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny85*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny87 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny87", 27, F_AVR8, {0x1E, 0x93, 0x87}, // ID - /*ATtiny87*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATtiny87*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config - /*ATtiny87*/ 80, rgftab_attiny87, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART - /*ATtiny87*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny88 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny88", 28, F_AVR8, {0x1E, 0x93, 0x11}, // ID - /*ATtiny88*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0200, // Mem - /*ATtiny88*/ 3, 1, 20, vtab_attiny88, 11, cfgtab_attiny48, // ISRs, Config - /*ATtiny88*/ 74, rgftab_attiny88, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny88*/ 4, ports_attiny48, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny167 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny167", 29, F_AVR8, {0x1E, 0x94, 0x87}, // ID - /*ATtiny167*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATtiny167*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config - /*ATtiny167*/ 80, rgftab_attiny87, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART - /*ATtiny167*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny261 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny261", 30, F_AVR8, {0x1E, 0x91, 0x0C}, // ID - /*ATtiny261*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny261*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny261, // ISRs, Config - /*ATtiny261*/ 63, rgftab_attiny261, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny261*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny261A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny261A", 31, F_AVR8, {0x1E, 0x91, 0x0C}, // ID - /*ATtiny261A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny261A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny261, // ISRs, Config - /*ATtiny261A*/ 63, rgftab_attiny261, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny261A*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny441 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny441", 32, F_AVR8, {0x1E, 0x92, 0x15}, // ID - /*ATtiny441*/ 0, 0x01000, 0x010, 0, 0, 0, 0x0100, 4, 0x0100, 0x0100, // Mem - /*ATtiny441*/ 3, 1, 30, vtab_attiny841, 14, cfgtab_attiny441, // ISRs, Config - /*ATtiny441*/ 101, rgftab_attiny441, 2, UART_CLASSIC_2x12, 3, uarts_attiny441, // Register file, UART - /*ATtiny441*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny461 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny461", 33, F_AVR8, {0x1E, 0x92, 0x08}, // ID - /*ATtiny461*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny461*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny261, // ISRs, Config - /*ATtiny461*/ 63, rgftab_attiny461, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny461*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny461A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny461A", 34, F_AVR8, {0x1E, 0x92, 0x08}, // ID - /*ATtiny461A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny461A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny261, // ISRs, Config - /*ATtiny461A*/ 63, rgftab_attiny461, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny461A*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny828 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny828", 35, F_AVR8, {0x1E, 0x93, 0x14}, // ID - /*ATtiny828*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATtiny828*/ 3, 1, 26, vtab_attiny828r, 16, cfgtab_attiny828, // ISRs, Config - /*ATtiny828*/ 94, rgftab_attiny828, 1, UART_CLASSIC_2x12, 1, uarts_attiny828, // Register file, UART - /*ATtiny828*/ 4, ports_attiny828, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny828R avrdude, from ATtiny828 // Sources - {"ATtiny828R", 36, F_AVR8, {0x1E, 0x93, 0x14}, // ID - /*ATtiny828R*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATtiny828R*/ 3, 1, 26, vtab_attiny828r, 16, cfgtab_attiny828, // ISRs, Config - /*ATtiny828R*/ 94, rgftab_attiny828, 1, UART_CLASSIC_2x12, 1, uarts_attiny828, // Register file, UART - /*ATtiny828R*/ 4, ports_attiny828, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny841 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny841", 37, F_AVR8, {0x1E, 0x93, 0x15}, // ID - /*ATtiny841*/ 0, 0x02000, 0x010, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATtiny841*/ 3, 1, 30, vtab_attiny841, 14, cfgtab_attiny441, // ISRs, Config - /*ATtiny841*/ 101, rgftab_attiny441, 2, UART_CLASSIC_2x12, 3, uarts_attiny441, // Register file, UART - /*ATtiny841*/ 2, ports_attiny441, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny861 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny861", 38, F_AVR8, {0x1E, 0x93, 0x0D}, // ID - /*ATtiny861*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny861*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny261, // ISRs, Config - /*ATtiny861*/ 63, rgftab_attiny861, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny861*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny861A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny861A", 39, F_AVR8, {0x1E, 0x93, 0x0D}, // ID - /*ATtiny861A*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATtiny861A*/ 3, 1, 19, vtab_attiny861a, 11, cfgtab_attiny261, // ISRs, Config - /*ATtiny861A*/ 63, rgftab_attiny861, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATtiny861A*/ 2, ports_attiny26, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny1634 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1634", 40, F_AVR8, {0x1E, 0x94, 0x12}, // ID - /*ATtiny1634*/ 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, // Mem - /*ATtiny1634*/ 3, 1, 28, vtab_attiny1634r, 13, cfgtab_attiny1634, // ISRs, Config - /*ATtiny1634*/ 89, rgftab_attiny1634, 2, UART_CLASSIC_2x12, 2, uarts_attiny1634, // Register file, UART - /*ATtiny1634*/ 3, ports_attiny1634, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny1634R avrdude, from ATtiny1634 // Sources - {"ATtiny1634R", 41, F_AVR8, {0x1E, 0x94, 0x12}, // ID - /*ATtiny1634R*/ 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, // Mem - /*ATtiny1634R*/ 3, 1, 28, vtab_attiny1634r, 13, cfgtab_attiny1634, // ISRs, Config - /*ATtiny1634R*/ 89, rgftab_attiny1634, 2, UART_CLASSIC_2x12, 2, uarts_attiny1634, // Register file, UART - /*ATtiny1634R*/ 3, ports_attiny1634, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny2313 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny2313", 42, F_AVR8, {0x1E, 0x91, 0x0A}, // ID - /*ATtiny2313*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny2313*/ 3, 1, 19, vtab_attiny2313, 11, cfgtab_attiny2313, // ISRs, Config - /*ATtiny2313*/ 54, rgftab_attiny2313, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*ATtiny2313*/ 3, ports_attiny2313, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny2313A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny2313A", 43, F_AVR8, {0x1E, 0x91, 0x0A}, // ID - /*ATtiny2313A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem - /*ATtiny2313A*/ 3, 1, 21, vtab_attiny4313, 11, cfgtab_attiny2313a, // ISRs, Config - /*ATtiny2313A*/ 58, rgftab_attiny2313a, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*ATtiny2313A*/ 3, ports_attiny2313, WDT_CLASSIC4}, // Ports, WDT - - //ATtiny4313 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny4313", 44, F_AVR8, {0x1E, 0x92, 0x0D}, // ID - /*ATtiny4313*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem - /*ATtiny4313*/ 3, 1, 21, vtab_attiny4313, 11, cfgtab_attiny2313a, // ISRs, Config - /*ATtiny4313*/ 58, rgftab_attiny4313, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*ATtiny4313*/ 3, ports_attiny2313, WDT_CLASSIC4}, // Ports, WDT - - //ATmega8 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega8", 45, F_AVR8, {0x1E, 0x93, 0x07}, // ID - /*ATmega8*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega8*/ 2, 1, 19, vtab_atmega8a, 13, cfgtab_atmega8, // ISRs, Config - /*ATmega8*/ 61, rgftab_atmega8, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega8*/ 3, ports_atmega8, WDT_CLASSIC3}, // Ports, WDT - - //ATmega8A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega8A", 46, F_AVR8, {0x1E, 0x93, 0x07}, // ID - /*ATmega8A*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega8A*/ 2, 1, 19, vtab_atmega8a, 13, cfgtab_atmega8, // ISRs, Config - /*ATmega8A*/ 61, rgftab_atmega8, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega8A*/ 3, ports_atmega8, WDT_CLASSIC3}, // Ports, WDT - - //ATmega8HVA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega8HVA", 47, F_AVR8, {0x1E, 0x93, 0x10}, // ID - /*ATmega8HVA*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega8HVA*/ 1, 1, 21, vtab_atmega16hva, 7, cfgtab_atmega8hva, // ISRs, Config - /*ATmega8HVA*/ 74, rgftab_atmega8hva, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega8HVA*/ 3, ports_atmega16hva2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega8U2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega8U2", 48, F_AVR8, {0x1E, 0x93, 0x89}, // ID - /*ATmega8U2*/ 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATmega8U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_atmega8u2, // ISRs, Config - /*ATmega8U2*/ 92, rgftab_atmega8u2, 1, UART_CLASSIC_2x12, 1, uarts_atmega8u2, // Register file, UART - /*ATmega8U2*/ 3, ports_at90usb162, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16", 49, F_AVR8, {0x1E, 0x94, 0x03}, // ID - /*ATmega16*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega16*/ 2, 1, 21, vtab_atmega16a, 13, cfgtab_atmega16, // ISRs, Config - /*ATmega16*/ 70, rgftab_atmega16, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART - /*ATmega16*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //ATmega16A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16A", 50, F_AVR8, {0x1E, 0x94, 0x03}, // ID - /*ATmega16A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem - /*ATmega16A*/ 2, 1, 21, vtab_atmega16a, 13, cfgtab_atmega16, // ISRs, Config - /*ATmega16A*/ 70, rgftab_atmega16a, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART - /*ATmega16A*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //ATmega16HVA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16HVA", 51, F_AVR8, {0x1E, 0x94, 0x0C}, // ID - /*ATmega16HVA*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega16HVA*/ 1, 1, 21, vtab_atmega16hva, 7, cfgtab_atmega8hva, // ISRs, Config - /*ATmega16HVA*/ 74, rgftab_atmega8hva, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega16HVA*/ 3, ports_atmega16hva2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16HVB atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16HVB", 52, F_AVR8, {0x1E, 0x94, 0x0D}, // ID - /*ATmega16HVB*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega16HVB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega16hvb, // ISRs, Config - /*ATmega16HVB*/ 91, rgftab_atmega32hvbrevb, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega16HVB*/ 3, ports_atmega32hvbrevb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16HVBrevB atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16HVBrevB", 53, F_AVR8, {0x1E, 0x94, 0x0D}, // ID - /*ATmega16HVBrevB*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega16HVBrevB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega16hvbrevb, // ISRs, Config - /*ATmega16HVBrevB*/ 91, rgftab_atmega32hvbrevb, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega16HVBrevB*/ 3, ports_atmega32hvbrevb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16M1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16M1", 54, F_AVR8, {0x1E, 0x94, 0x84}, // ID - /*ATmega16M1*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega16M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega16m1, // ISRs, Config - /*ATmega16M1*/ 136, rgftab_atmega16m1, 1, UART_LIN, 1, uarts_atmega16m1, // Register file, UART - /*ATmega16M1*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16HVA2 xml, avr-gcc 12.2.0 // Sources - {"ATmega16HVA2", 55, F_AVR8, {0x1E, 0x94, 0x0E}, // ID - /*ATmega16HVA2*/ 0, 0x04000, 0x080, -1, -1, 0, 0x0100, -1, 0x0100, 0x0400, // Mem - /*ATmega16HVA2*/ 2, 1, 22, vtab_atmega16hva2, 9, cfgtab_atmega16hva2, // ISRs, Config - /*ATmega16HVA2*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega16HVA2*/ 3, ports_atmega16hva2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16U2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16U2", 56, F_AVR8, {0x1E, 0x94, 0x89}, // ID - /*ATmega16U2*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATmega16U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162, // ISRs, Config - /*ATmega16U2*/ 92, rgftab_atmega8u2, 1, UART_CLASSIC_2x12, 1, uarts_atmega8u2, // Register file, UART - /*ATmega16U2*/ 3, ports_at90usb162, WDT_CLASSIC4}, // Ports, WDT - - //ATmega16U4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega16U4", 57, F_AVR8, {0x1E, 0x94, 0x88}, // ID - /*ATmega16U4*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0500, // Mem - /*ATmega16U4*/ 3, 1, 43, vtab_atmega32u4, 15, cfgtab_atmega16u4, // ISRs, Config - /*ATmega16U4*/ 139, rgftab_atmega16u4, 1, UART_CLASSIC_2x12, 1, uarts_atmega16u4, // Register file, UART - /*ATmega16U4*/ 5, ports_atmega16u4, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32", 58, F_AVR8, {0x1E, 0x95, 0x02}, // ID - /*ATmega32*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, // Mem - /*ATmega32*/ 2, 1, 21, vtab_atmega323, 13, cfgtab_atmega32, // ISRs, Config - /*ATmega32*/ 68, rgftab_atmega32, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART - /*ATmega32*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //ATmega32A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32A", 59, F_AVR8, {0x1E, 0x95, 0x02}, // ID - /*ATmega32A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, // Mem - /*ATmega32A*/ 2, 1, 21, vtab_atmega323, 13, cfgtab_atmega32, // ISRs, Config - /*ATmega32A*/ 66, rgftab_atmega32a, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART - /*ATmega32A*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //ATmega32HVB atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32HVB", 60, F_AVR8, {0x1E, 0x95, 0x10}, // ID - /*ATmega32HVB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32HVB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega32hvb, // ISRs, Config - /*ATmega32HVB*/ 91, rgftab_atmega32hvbrevb, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega32HVB*/ 3, ports_atmega32hvbrevb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32HVBrevB atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32HVBrevB", 61, F_AVR8, {0x1E, 0x95, 0x10}, // ID - /*ATmega32HVBrevB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32HVBrevB*/ 2, 1, 29, vtab_atmega32hvbrevb, 12, cfgtab_atmega32hvbrevb, // ISRs, Config - /*ATmega32HVBrevB*/ 91, rgftab_atmega32hvbrevb, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega32HVBrevB*/ 3, ports_atmega32hvbrevb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32C1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32C1", 62, F_AVR8, {0x1E, 0x95, 0x86}, // ID - /*ATmega32C1*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32C1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega32c1, // ISRs, Config - /*ATmega32C1*/ 117, rgftab_atmega32c1, 1, UART_LIN, 1, uarts_atmega16m1, // Register file, UART - /*ATmega32C1*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32M1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32M1", 63, F_AVR8, {0x1E, 0x95, 0x84}, // ID - /*ATmega32M1*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega32M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega32c1, // ISRs, Config - /*ATmega32M1*/ 136, rgftab_atmega16m1, 1, UART_LIN, 1, uarts_atmega16m1, // Register file, UART - /*ATmega32M1*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32HVE2 avrdude, boot size (manual) // Sources - {"ATmega32HVE2", 379, F_AVR8, {0x1E, 0x95, 0x13}, // ID - /*ATmega32HVE2*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, -1, -1, // Mem - /*ATmega32HVE2*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve2, // ISRs, Config - /*ATmega32HVE2*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*ATmega32HVE2*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATmega32U2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32U2", 64, F_AVR8, {0x1E, 0x95, 0x8A}, // ID - /*ATmega32U2*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0400, // Mem - /*ATmega32U2*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_atmega32u2, // ISRs, Config - /*ATmega32U2*/ 92, rgftab_atmega8u2, 1, UART_CLASSIC_2x12, 1, uarts_atmega8u2, // Register file, UART - /*ATmega32U2*/ 3, ports_at90usb162, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32U4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega32U4", 65, F_AVR8, {0x1E, 0x95, 0x87}, // ID - /*ATmega32U4*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0a00, // Mem - /*ATmega32U4*/ 3, 1, 43, vtab_atmega32u4, 15, cfgtab_atmega32u4, // ISRs, Config - /*ATmega32U4*/ 139, rgftab_atmega16u4, 1, UART_CLASSIC_2x12, 1, uarts_atmega16u4, // Register file, UART - /*ATmega32U4*/ 5, ports_atmega16u4, WDT_CLASSIC4}, // Ports, WDT - - //ATmega32U6 xml, avr-gcc 12.2.0, boot size (manual) // Sources - {"ATmega32U6", 66, F_AVR8, {0x1E, 0x95, 0x88}, // ID - /*ATmega32U6*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, -1, 0x0100, 0x0a00, // Mem - /*ATmega32U6*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_atmega32u6, // ISRs, Config - /*ATmega32U6*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*ATmega32U6*/ 6, ports_atmega32u6, WDT_CLASSIC4}, // Ports, WDT - - //ATmega48 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega48", 67, F_AVR8, {0x1E, 0x92, 0x05}, // ID - /*ATmega48*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config - /*ATmega48*/ 81, rgftab_atmega48, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega48*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega48A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega48A", 68, F_AVR8, {0x1E, 0x92, 0x05}, // ID - /*ATmega48A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48A*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config - /*ATmega48A*/ 82, rgftab_atmega48a, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega48A*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega48P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega48P", 69, F_AVR8, {0x1E, 0x92, 0x0A}, // ID - /*ATmega48P*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48P*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config - /*ATmega48P*/ 81, rgftab_atmega48, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega48P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega48PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega48PA", 70, F_AVR8, {0x1E, 0x92, 0x0A}, // ID - /*ATmega48PA*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48PA*/ 3, 1, 26, vtab_atmega328p, 11, cfgtab_atmega48, // ISRs, Config - /*ATmega48PA*/ 82, rgftab_atmega48a, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega48PA*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega48PB atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega48PB", 71, F_AVR8, {0x1E, 0x92, 0x10}, // ID - /*ATmega48PB*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem - /*ATmega48PB*/ 3, 1, 27, vtab_atmega168pb, 11, cfgtab_atmega48pb, // ISRs, Config - /*ATmega48PB*/ 95, rgftab_atmega48pb, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega48PB*/ 4, ports_atmega328pb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega64 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega64", 72, F_AVR8, {0x1E, 0x96, 0x02}, // ID - /*ATmega64*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega64, // ISRs, Config - /*ATmega64*/ 103, rgftab_atmega64, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmega64*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT - - //ATmega64A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega64A", 73, F_AVR8, {0x1E, 0x96, 0x02}, // ID - /*ATmega64A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64A*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega64, // ISRs, Config - /*ATmega64A*/ 103, rgftab_atmega64, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmega64A*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT - - //ATmega64HVE xml, avr-gcc 12.2.0, boot size (manual) // Sources - {"ATmega64HVE", 74, F_AVR8, {0x1E, 0x96, 0x10}, // ID - /*ATmega64HVE*/ 0, 0x10000, 0x080, 4, 0x0400, 0, 0x0400, -1, 0x0100, 0x1000, // Mem - /*ATmega64HVE*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve, // ISRs, Config - /*ATmega64HVE*/ 0, NULL, 1, UART_LIN, 1, uarts_atmega64hve, // Register file, UART - /*ATmega64HVE*/ 2, ports_atmega64hve, WDT_CLASSIC4}, // Ports, WDT - - //ATmega64C1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega64C1", 75, F_AVR8, {0x1E, 0x96, 0x86}, // ID - /*ATmega64C1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64C1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1, // ISRs, Config - /*ATmega64C1*/ 122, rgftab_atmega64c1, 1, UART_LIN, 1, uarts_atmega16m1, // Register file, UART - /*ATmega64C1*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //ATmegaS64M1 atdf, avrdude, from ATmega64M1 // Sources - {"ATmegaS64M1", 412, F_AVR8, {0x1E, 0x96, 0x84}, // ID - /*ATmegaS64M1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmegaS64M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1, // ISRs, Config - /*ATmegaS64M1*/ 136, rgftab_atmegas64m1, 1, UART_LIN, 1, uarts_atmega16m1, // Register file, UART - /*ATmegaS64M1*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //ATmega64M1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega64M1", 76, F_AVR8, {0x1E, 0x96, 0x84}, // ID - /*ATmega64M1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega64M1*/ 3, 1, 31, vtab_atmega64m1, 17, cfgtab_atmega64c1, // ISRs, Config - /*ATmega64M1*/ 136, rgftab_atmegas64m1, 1, UART_LIN, 1, uarts_atmega16m1, // Register file, UART - /*ATmega64M1*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //ATmega64HVE2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega64HVE2", 77, F_AVR8, {0x1E, 0x96, 0x10}, // ID - /*ATmega64HVE2*/ 0, 0x10000, 0x080, 4, 0x0400, 0, 0x0400, 4, 0x0100, 0x1000, // Mem - /*ATmega64HVE2*/ 2, 1, 25, vtab_atmega64hve2, 13, cfgtab_atmega64hve2, // ISRs, Config - /*ATmega64HVE2*/ 89, rgftab_atmega64hve2, 1, UART_LIN, 1, uarts_atmega64hve, // Register file, UART - /*ATmega64HVE2*/ 2, ports_atmega64hve, WDT_CLASSIC4}, // Ports, WDT - - //ATmega64RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega64RFR2", 78, F_AVR8, {0x1E, 0xA6, 0x02}, // ID - /*ATmega64RFR2*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, // Mem - /*ATmega64RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega64rfr2, // ISRs, Config - /*ATmega64RFR2*/ 269, rgftab_atmega64rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega64RFR2*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega88 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega88", 79, F_AVR8, {0x1E, 0x93, 0x0A}, // ID - /*ATmega88*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config - /*ATmega88*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega88*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega88A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega88A", 80, F_AVR8, {0x1E, 0x93, 0x0A}, // ID - /*ATmega88A*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88A*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config - /*ATmega88A*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega88A*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega88P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega88P", 81, F_AVR8, {0x1E, 0x93, 0x0F}, // ID - /*ATmega88P*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config - /*ATmega88P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega88P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega88PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega88PA", 82, F_AVR8, {0x1E, 0x93, 0x0F}, // ID - /*ATmega88PA*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88PA*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config - /*ATmega88PA*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega88PA*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega88PB atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega88PB", 83, F_AVR8, {0x1E, 0x93, 0x16}, // ID - /*ATmega88PB*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega88PB*/ 3, 1, 27, vtab_atmega168pb, 14, cfgtab_atmega88pb, // ISRs, Config - /*ATmega88PB*/ 95, rgftab_atmega88pb, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega88PB*/ 4, ports_atmega328pb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega103 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"ATmega103", 84, F_AVR8, {0x1E, 0x97, 0x01}, // ID - /*ATmega103*/ 0, 0x20000, 0x100, 0, 0, 0, 0x1000, 1, 0x0060, 0x0fa0, // Mem - /*ATmega103*/ 1, 1, 24, vtab_atmega103, 4, cfgtab_atmega103, // ISRs, Config - /*ATmega103*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_atmega103, // Register file, UART - /*ATmega103*/ 6, ports_atmega103, WDT_CLASSIC3}, // Ports, WDT - - //ATmega103comp xml // Sources - {"ATmega103comp", 374, F_AVR8, {0x1E, 0x97, 0x01}, // ID - /*ATmega103comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*ATmega103comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega103comp, // ISRs, Config - /*ATmega103comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*ATmega103comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATmega128 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega128", 85, F_AVR8, {0x1E, 0x97, 0x02}, // ID - /*ATmega128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*ATmega128*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128, // ISRs, Config - /*ATmega128*/ 103, rgftab_atmega128, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmega128*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT - - //ATmegaS128 atdf, avrdude, from ATmega128 // Sources - {"ATmegaS128", 413, F_AVR8, {0x1E, 0x97, 0x02}, // ID - /*ATmegaS128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*ATmegaS128*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128, // ISRs, Config - /*ATmegaS128*/ 103, rgftab_atmega128, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmegaS128*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT - - //ATmega128A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega128A", 86, F_AVR8, {0x1E, 0x97, 0x02}, // ID - /*ATmega128A*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*ATmega128A*/ 3, 1, 35, vtab_atmega128a, 15, cfgtab_atmega128, // ISRs, Config - /*ATmega128A*/ 103, rgftab_atmega128a, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmega128A*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT - - //ATmega128RFA1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega128RFA1", 87, F_AVR8, {0x1E, 0xA7, 0x01}, // ID - /*ATmega128RFA1*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem - /*ATmega128RFA1*/ 3, 1, 72, vtab_atmega128rfa1, 14, cfgtab_atmega128rfa1, // ISRs, Config - /*ATmega128RFA1*/ 237, rgftab_atmega128rfa1, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega128RFA1*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega128RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega128RFR2", 88, F_AVR8, {0x1E, 0xA7, 0x02}, // ID - /*ATmega128RFR2*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem - /*ATmega128RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega128rfr2, // ISRs, Config - /*ATmega128RFR2*/ 270, rgftab_atmega128rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega128RFR2*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega161 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"ATmega161", 89, F_AVR8, {0x1E, 0x94, 0x01}, // ID - /*ATmega161*/ 0, 0x04000, 0x080, 1, 0x0400, 0, 0x0200, 1, 0x0060, 0x0400, // Mem - /*ATmega161*/ 1, 1, 21, vtab_atmega161, 7, cfgtab_atmega161, // ISRs, Config - /*ATmega161*/ 0, NULL, 2, UART_CLASSIC_2x12, 2, uarts_atmega161, // Register file, UART - /*ATmega161*/ 5, ports_atmega8515, WDT_CLASSIC3}, // Ports, WDT - - //ATmega161comp xml // Sources - {"ATmega161comp", 375, F_AVR8, {0x1E, 0x94, 0x01}, // ID - /*ATmega161comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*ATmega161comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega161comp, // ISRs, Config - /*ATmega161comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*ATmega161comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATmega162 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega162", 90, F_AVR8, {0x1E, 0x94, 0x04}, // ID - /*ATmega162*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega162*/ 3, 1, 28, vtab_atmega162, 15, cfgtab_atmega162, // ISRs, Config - /*ATmega162*/ 79, rgftab_atmega162, 2, UART_CLASSIC_2x12, 2, uarts_atmega161, // Register file, UART - /*ATmega162*/ 5, ports_atmega8515, WDT_CLASSIC3}, // Ports, WDT - - //ATmega163 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"ATmega163", 91, F_AVR8, {0x1E, 0x94, 0x02}, // ID - /*ATmega163*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 1, 0x0060, 0x0400, // Mem - /*ATmega163*/ 2, 1, 18, vtab_atmega163, 9, cfgtab_atmega163, // ISRs, Config - /*ATmega163*/ 0, NULL, 1, UART_CLASSIC_2x08, 1, uarts_attiny2313, // Register file, UART - /*ATmega163*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //ATmega164A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega164A", 92, F_AVR8, {0x1E, 0x94, 0x0F}, // ID - /*ATmega164A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega164A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a, // ISRs, Config - /*ATmega164A*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega164A*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega164P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega164P", 93, F_AVR8, {0x1E, 0x94, 0x0A}, // ID - /*ATmega164P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega164P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a, // ISRs, Config - /*ATmega164P*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega164P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega164PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega164PA", 94, F_AVR8, {0x1E, 0x94, 0x0A}, // ID - /*ATmega164PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega164PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega164a, // ISRs, Config - /*ATmega164PA*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega164PA*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega165 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"ATmega165", 95, F_AVR8, {0x1E, 0x94, 0x07}, // ID - /*ATmega165*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165, // ISRs, Config - /*ATmega165*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega165*/ 7, ports_at90can128, WDT_CLASSIC3}, // Ports, WDT - - //ATmega165A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega165A", 96, F_AVR8, {0x1E, 0x94, 0x10}, // ID - /*ATmega165A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165a, // ISRs, Config - /*ATmega165A*/ 86, rgftab_atmega165a, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega165A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega165P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega165P", 97, F_AVR8, {0x1E, 0x94, 0x07}, // ID - /*ATmega165P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165a, // ISRs, Config - /*ATmega165P*/ 86, rgftab_atmega165a, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega165P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega165PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega165PA", 98, F_AVR8, {0x1E, 0x94, 0x07}, // ID - /*ATmega165PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega165PA*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega165a, // ISRs, Config - /*ATmega165PA*/ 86, rgftab_atmega165a, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega165PA*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega168 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega168", 99, F_AVR8, {0x1E, 0x94, 0x06}, // ID - /*ATmega168*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168*/ 3, 1, 26, vtab_atmega328, 14, cfgtab_atmega168, // ISRs, Config - /*ATmega168*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega168*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega168A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega168A", 100, F_AVR8, {0x1E, 0x94, 0x06}, // ID - /*ATmega168A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168A*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config - /*ATmega168A*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega168A*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega168P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega168P", 101, F_AVR8, {0x1E, 0x94, 0x0B}, // ID - /*ATmega168P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config - /*ATmega168P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega168P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega168PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega168PA", 102, F_AVR8, {0x1E, 0x94, 0x0B}, // ID - /*ATmega168PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168PA*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config - /*ATmega168PA*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega168PA*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega168PB atdf, avr-gcc 7.3.0, avrdude // Sources - {"ATmega168PB", 103, F_AVR8, {0x1E, 0x94, 0x15}, // ID - /*ATmega168PB*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega168PB*/ 3, 1, 27, vtab_atmega168pb, 14, cfgtab_atmega168pb, // ISRs, Config - /*ATmega168PB*/ 95, rgftab_atmega88pb, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega168PB*/ 4, ports_atmega328pb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega169 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"ATmega169", 104, F_AVR8, {0x1E, 0x94, 0x05}, // ID - /*ATmega169*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165, // ISRs, Config - /*ATmega169*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega169*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega169A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega169A", 105, F_AVR8, {0x1E, 0x94, 0x11}, // ID - /*ATmega169A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165a, // ISRs, Config - /*ATmega169A*/ 106, rgftab_atmega169a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega169A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega169P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega169P", 106, F_AVR8, {0x1E, 0x94, 0x05}, // ID - /*ATmega169P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165a, // ISRs, Config - /*ATmega169P*/ 106, rgftab_atmega169a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega169P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega169PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega169PA", 107, F_AVR8, {0x1E, 0x94, 0x05}, // ID - /*ATmega169PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATmega169PA*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega165a, // ISRs, Config - /*ATmega169PA*/ 106, rgftab_atmega169a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega169PA*/ 7, ports_atmega64rfr2, WDT_CLASSIC3}, // Ports, WDT - - //ATmega256RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega256RFR2", 108, F_AVR8, {0x1E, 0xA8, 0x02}, // ID - /*ATmega256RFR2*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, // Mem - /*ATmega256RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega256rfr2, // ISRs, Config - /*ATmega256RFR2*/ 271, rgftab_atmega256rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega256RFR2*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega323 xml, avr-gcc 12.2.0, boot size (manual) // Sources - {"ATmega323", 109, F_AVR8, {0x1E, 0x95, 0x01}, // ID - /*ATmega323*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, -1, 0x0060, 0x0800, // Mem - /*ATmega323*/ 2, 1, 21, vtab_atmega323, 12, cfgtab_atmega323, // ISRs, Config - /*ATmega323*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*ATmega323*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //ATmega324A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega324A", 110, F_AVR8, {0x1E, 0x95, 0x15}, // ID - /*ATmega324A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a, // ISRs, Config - /*ATmega324A*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega324A*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega324P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega324P", 111, F_AVR8, {0x1E, 0x95, 0x08}, // ID - /*ATmega324P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a, // ISRs, Config - /*ATmega324P*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega324P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega324PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega324PA", 112, F_AVR8, {0x1E, 0x95, 0x11}, // ID - /*ATmega324PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega324a, // ISRs, Config - /*ATmega324PA*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega324PA*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega324PB atdf, avrdude // Sources - {"ATmega324PB", 113, F_AVR8, {0x1E, 0x95, 0x17}, // ID - /*ATmega324PB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega324PB*/ 3, 1, 51, vtab_atmega324pb, 15, cfgtab_atmega324pb, // ISRs, Config - /*ATmega324PB*/ 134, rgftab_atmega324pb, 3, UART_CLASSIC_2x12, 3, uarts_atmega324pb, // Register file, UART - /*ATmega324PB*/ 5, ports_atmega324pb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega325 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega325", 114, F_AVR8, {0x1E, 0x95, 0x05}, // ID - /*ATmega325*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega325*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega325*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega325A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega325A", 115, F_AVR8, {0x1E, 0x95, 0x05}, // ID - /*ATmega325A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega325A*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega325A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega325P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega325P", 116, F_AVR8, {0x1E, 0x95, 0x0D}, // ID - /*ATmega325P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega325P*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega325P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega325PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega325PA", 117, F_AVR8, {0x1E, 0x95, 0x0D}, // ID - /*ATmega325PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega325PA*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega325PA*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega325PA*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega328 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega328", 118, F_AVR8, {0x1E, 0x95, 0x14}, // ID - /*ATmega328*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega328*/ 3, 1, 26, vtab_atmega328, 14, cfgtab_atmega328, // ISRs, Config - /*ATmega328*/ 81, rgftab_atmega328, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega328*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega328P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega328P", 119, F_AVR8, {0x1E, 0x95, 0x0F}, // ID - /*ATmega328P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega328P*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega328, // ISRs, Config - /*ATmega328P*/ 81, rgftab_atmega328, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATmega328P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATmega328PB atdf, avr-gcc 7.3.0, avrdude // Sources - {"ATmega328PB", 120, F_AVR8, {0x1E, 0x95, 0x16}, // ID - /*ATmega328PB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega328PB*/ 3, 1, 45, vtab_atmega328pb, 15, cfgtab_atmega328pb, // ISRs, Config - /*ATmega328PB*/ 125, rgftab_atmega328pb, 2, UART_CLASSIC_2x12, 2, uarts_atmega328pb, // Register file, UART - /*ATmega328PB*/ 4, ports_atmega328pb, WDT_CLASSIC4}, // Ports, WDT - - //ATmega329 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega329", 121, F_AVR8, {0x1E, 0x95, 0x03}, // ID - /*ATmega329*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega329*/ 106, rgftab_atmega329, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega329*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega329A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega329A", 122, F_AVR8, {0x1E, 0x95, 0x03}, // ID - /*ATmega329A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega329A*/ 106, rgftab_atmega329a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega329A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega329P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega329P", 123, F_AVR8, {0x1E, 0x95, 0x0B}, // ID - /*ATmega329P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega329P*/ 106, rgftab_atmega329p, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega329P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega329PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega329PA", 124, F_AVR8, {0x1E, 0x95, 0x0B}, // ID - /*ATmega329PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega329PA*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega329PA*/ 106, rgftab_atmega329a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega329PA*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega406 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega406", 125, F_AVR8, {0x1E, 0x95, 0x07}, // ID - /*ATmega406*/ 0, 0x0a000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0800, // Mem - /*ATmega406*/ 2, 1, 23, vtab_atmega406, 10, cfgtab_atmega406, // ISRs, Config - /*ATmega406*/ 79, rgftab_atmega406, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATmega406*/ 4, ports_atmega406, WDT_CLASSIC4}, // Ports, WDT - - //ATmega640 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega640", 126, F_AVR8, {0x1E, 0x96, 0x08}, // ID - /*ATmega640*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega640*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega640, // ISRs, Config - /*ATmega640*/ 160, rgftab_atmega640, 4, UART_CLASSIC_2x12, 4, uarts_atmega640, // Register file, UART - /*ATmega640*/ 11, ports_atmega640, WDT_CLASSIC4}, // Ports, WDT - - //ATmega644 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega644", 127, F_AVR8, {0x1E, 0x96, 0x09}, // ID - /*ATmega644*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644*/ 3, 1, 28, vtab_atmega644, 14, cfgtab_atmega644, // ISRs, Config - /*ATmega644*/ 88, rgftab_atmega644, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART - /*ATmega644*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega644A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega644A", 128, F_AVR8, {0x1E, 0x96, 0x09}, // ID - /*ATmega644A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644A*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644, // ISRs, Config - /*ATmega644A*/ 93, rgftab_atmega644a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega644A*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega644P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega644P", 129, F_AVR8, {0x1E, 0x96, 0x0A}, // ID - /*ATmega644P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644P*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644, // ISRs, Config - /*ATmega644P*/ 93, rgftab_atmega644a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega644P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega644PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega644PA", 130, F_AVR8, {0x1E, 0x96, 0x0A}, // ID - /*ATmega644PA*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega644PA*/ 3, 1, 31, vtab_atmega644pa, 14, cfgtab_atmega644, // ISRs, Config - /*ATmega644PA*/ 93, rgftab_atmega644a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega644PA*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega644RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega644RFR2", 131, F_AVR8, {0x1E, 0xA6, 0x03}, // ID - /*ATmega644RFR2*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, // Mem - /*ATmega644RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega64rfr2, // ISRs, Config - /*ATmega644RFR2*/ 269, rgftab_atmega64rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega644RFR2*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega645 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega645", 132, F_AVR8, {0x1E, 0x96, 0x05}, // ID - /*ATmega645*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega645*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega645*/ 86, rgftab_atmega645, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega645*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega645A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega645A", 133, F_AVR8, {0x1E, 0x96, 0x05}, // ID - /*ATmega645A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega645A*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega645A*/ 86, rgftab_atmega645, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega645A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega645P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega645P", 134, F_AVR8, {0x1E, 0x96, 0x0D}, // ID - /*ATmega645P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega645P*/ 3, 1, 22, vtab_atmega645p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega645P*/ 86, rgftab_atmega645, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega645P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega649 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega649", 135, F_AVR8, {0x1E, 0x96, 0x03}, // ID - /*ATmega649*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega649*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega649*/ 106, rgftab_atmega649, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega649*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega649A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega649A", 136, F_AVR8, {0x1E, 0x96, 0x03}, // ID - /*ATmega649A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega649A*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega649A*/ 106, rgftab_atmega649, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega649A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega649P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega649P", 137, F_AVR8, {0x1E, 0x96, 0x0B}, // ID - /*ATmega649P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega649P*/ 3, 1, 23, vtab_atmega649p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega649P*/ 106, rgftab_atmega649, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART - /*ATmega649P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT - - //ATmega1280 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1280", 138, F_AVR8, {0x1E, 0x97, 0x03}, // ID - /*ATmega1280*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega1280*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega1280, // ISRs, Config - /*ATmega1280*/ 161, rgftab_atmega1280, 4, UART_CLASSIC_2x12, 4, uarts_atmega640, // Register file, UART - /*ATmega1280*/ 11, ports_atmega640, WDT_CLASSIC4}, // Ports, WDT - - //ATmega1281 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1281", 139, F_AVR8, {0x1E, 0x97, 0x04}, // ID - /*ATmega1281*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega1281*/ 3, 1, 57, vtab_atmega2561, 14, cfgtab_atmega1280, // ISRs, Config - /*ATmega1281*/ 138, rgftab_atmega1281, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmega1281*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega1284 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1284", 140, F_AVR8, {0x1E, 0x97, 0x06}, // ID - /*ATmega1284*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, // Mem - /*ATmega1284*/ 3, 1, 35, vtab_atmega1284p, 14, cfgtab_atmega1284, // ISRs, Config - /*ATmega1284*/ 104, rgftab_atmega1284, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega1284*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega1284P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1284P", 141, F_AVR8, {0x1E, 0x97, 0x05}, // ID - /*ATmega1284P*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, // Mem - /*ATmega1284P*/ 3, 1, 35, vtab_atmega1284p, 14, cfgtab_atmega1284, // ISRs, Config - /*ATmega1284P*/ 104, rgftab_atmega1284, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART - /*ATmega1284P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT - - //ATmega1284RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1284RFR2", 142, F_AVR8, {0x1E, 0xA7, 0x03}, // ID - /*ATmega1284RFR2*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem - /*ATmega1284RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega128rfr2, // ISRs, Config - /*ATmega1284RFR2*/ 270, rgftab_atmega128rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega1284RFR2*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega2560 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega2560", 143, F_AVR8, {0x1E, 0x98, 0x01}, // ID - /*ATmega2560*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega2560*/ 3, 1, 57, vtab_atmega2560, 14, cfgtab_atmega2560, // ISRs, Config - /*ATmega2560*/ 161, rgftab_atmega1280, 4, UART_CLASSIC_2x12, 4, uarts_atmega640, // Register file, UART - /*ATmega2560*/ 11, ports_atmega640, WDT_CLASSIC4}, // Ports, WDT - - //ATmega2561 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega2561", 144, F_AVR8, {0x1E, 0x98, 0x02}, // ID - /*ATmega2561*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem - /*ATmega2561*/ 3, 1, 57, vtab_atmega2561, 14, cfgtab_atmega2560, // ISRs, Config - /*ATmega2561*/ 139, rgftab_atmega2561, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*ATmega2561*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega2564RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega2564RFR2", 145, F_AVR8, {0x1E, 0xA8, 0x03}, // ID - /*ATmega2564RFR2*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, // Mem - /*ATmega2564RFR2*/ 3, 1, 77, vtab_atmega2564rfr2, 14, cfgtab_atmega256rfr2, // ISRs, Config - /*ATmega2564RFR2*/ 271, rgftab_atmega2564rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega64rfr2, // Register file, UART - /*ATmega2564RFR2*/ 7, ports_atmega64rfr2, WDT_CLASSIC4}, // Ports, WDT - - //ATmega3250 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3250", 146, F_AVR8, {0x1E, 0x95, 0x06}, // ID - /*ATmega3250*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3250*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3250*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3250A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3250A", 147, F_AVR8, {0x1E, 0x95, 0x06}, // ID - /*ATmega3250A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250A*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3250A*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3250A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3250P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3250P", 148, F_AVR8, {0x1E, 0x95, 0x0E}, // ID - /*ATmega3250P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250P*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3250P*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3250P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3250PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3250PA", 149, F_AVR8, {0x1E, 0x95, 0x0E}, // ID - /*ATmega3250PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3250PA*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3250PA*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3250PA*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3290 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3290", 150, F_AVR8, {0x1E, 0x95, 0x04}, // ID - /*ATmega3290*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3290*/ 118, rgftab_atmega3290, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3290*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3290A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3290A", 151, F_AVR8, {0x1E, 0x95, 0x04}, // ID - /*ATmega3290A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290A*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3290A*/ 118, rgftab_atmega3290, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3290A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3290P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3290P", 152, F_AVR8, {0x1E, 0x95, 0x0C}, // ID - /*ATmega3290P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290P*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3290P*/ 118, rgftab_atmega3290p, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3290P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega3290PA atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3290PA", 153, F_AVR8, {0x1E, 0x95, 0x0C}, // ID - /*ATmega3290PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATmega3290PA*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega325, // ISRs, Config - /*ATmega3290PA*/ 118, rgftab_atmega3290pa, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega3290PA*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega6450 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega6450", 154, F_AVR8, {0x1E, 0x96, 0x06}, // ID - /*ATmega6450*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6450*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega6450*/ 94, rgftab_atmega6450, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega6450*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega6450A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega6450A", 155, F_AVR8, {0x1E, 0x96, 0x06}, // ID - /*ATmega6450A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6450A*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega6450A*/ 94, rgftab_atmega6450, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega6450A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega6450P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega6450P", 156, F_AVR8, {0x1E, 0x96, 0x0E}, // ID - /*ATmega6450P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6450P*/ 3, 1, 25, vtab_atmega6450p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega6450P*/ 94, rgftab_atmega6450, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega6450P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega6490 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega6490", 157, F_AVR8, {0x1E, 0x96, 0x04}, // ID - /*ATmega6490*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6490*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega6490*/ 118, rgftab_atmega6490, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega6490*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega6490A atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega6490A", 158, F_AVR8, {0x1E, 0x96, 0x04}, // ID - /*ATmega6490A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6490A*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega6490A*/ 118, rgftab_atmega6490, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega6490A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega6490P atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega6490P", 159, F_AVR8, {0x1E, 0x96, 0x0C}, // ID - /*ATmega6490P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*ATmega6490P*/ 3, 1, 25, vtab_atmega6490p, 15, cfgtab_atmega645, // ISRs, Config - /*ATmega6490P*/ 118, rgftab_atmega6490, 1, UART_CLASSIC_2x12, 1, uarts_atmega103, // Register file, UART - /*ATmega6490P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT - - //ATmega8515 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega8515", 160, F_AVR8, {0x1E, 0x93, 0x06}, // ID - /*ATmega8515*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATmega8515*/ 2, 1, 17, vtab_atmega8515, 13, cfgtab_atmega8515, // ISRs, Config - /*ATmega8515*/ 52, rgftab_atmega8515, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*ATmega8515*/ 5, ports_atmega8515, WDT_CLASSIC3}, // Ports, WDT - - //ATmega8535 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega8535", 161, F_AVR8, {0x1E, 0x93, 0x08}, // ID - /*ATmega8535*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, // Mem - /*ATmega8535*/ 2, 1, 21, vtab_atmega8535, 13, cfgtab_atmega8535, // ISRs, Config - /*ATmega8535*/ 67, rgftab_atmega8535, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*ATmega8535*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //AT43USB320 avr-gcc 12.2.0 // Sources - {"AT43USB320", 162, F_AVR8, {0xff, -1, -1}, // ID - /*AT43USB320*/ 0, 0x10000, -1, -1, -1, 0, 0, -1, 0x0060, 0x0200, // Mem - /*AT43USB320*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*AT43USB320*/ 0, NULL, 1, UART_CLASSIC_1x08, -1, NULL, // Register file, UART - /*AT43USB320*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT - - //AT43USB355 avr-gcc 12.2.0 // Sources - {"AT43USB355", 163, F_AVR8, {0xff, -1, -1}, // ID - /*AT43USB355*/ 0, 0x06000, -1, -1, -1, 0, 0, -1, 0x0060, 0x0400, // Mem - /*AT43USB355*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*AT43USB355*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*AT43USB355*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT - - //AT76C711 avr-gcc 12.2.0 // Sources - {"AT76C711", 164, F_AVR8, {0xff, -1, -1}, // ID - /*AT76C711*/ 0, 0x04000, -1, -1, -1, 0, 0, -1, 0x0060, 0x07a0, // Mem - /*AT76C711*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*AT76C711*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*AT76C711*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT - - //AT86RF401 avr-gcc 12.2.0 // Sources - {"AT86RF401", 165, F_AVR8, {0x1E, 0x91, 0x81}, // ID - /*AT86RF401*/ 0, 0x00800, -1, -1, -1, 0, 0x0080, -1, 0x0060, 0x0080, // Mem - /*AT86RF401*/ 0, 1, 3, vtab_at86rf401, 0, NULL, // ISRs, Config - /*AT86RF401*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART - /*AT86RF401*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT - - //AT90PWM1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM1", 166, F_AVR8, {0x1E, 0x93, 0x83}, // ID - /*AT90PWM1*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM1*/ 3, 1, 32, vtab_at90pwm1, 17, cfgtab_at90pwm1, // ISRs, Config - /*AT90PWM1*/ 92, rgftab_at90pwm1, 0, UART_NONE, -1, NULL, // Register file, UART - /*AT90PWM1*/ 3, ports_at90pwm81, WDT_CLASSIC4}, // Ports, WDT - - //AT90PWM2 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"AT90PWM2", 167, F_AVR8, {0x1E, 0x93, 0x81}, // ID - /*AT90PWM2*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM2*/ 3, 1, 32, vtab_at90pwm2, 18, cfgtab_at90pwm2, // ISRs, Config - /*AT90PWM2*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART - /*AT90PWM2*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //AT90PWM2B atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM2B", 168, F_AVR8, {0x1E, 0x93, 0x83}, // ID - /*AT90PWM2B*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM2B*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2b, // ISRs, Config - /*AT90PWM2B*/ 100, rgftab_at90pwm2b, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART - /*AT90PWM2B*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //AT90PWM3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM3", 169, F_AVR8, {0x1E, 0x93, 0x81}, // ID - /*AT90PWM3*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM3*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2, // ISRs, Config - /*AT90PWM3*/ 115, rgftab_at90pwm3, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART - /*AT90PWM3*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //AT90PWM3B atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM3B", 170, F_AVR8, {0x1E, 0x93, 0x83}, // ID - /*AT90PWM3B*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90PWM3B*/ 3, 1, 32, vtab_at90pwm3b, 18, cfgtab_at90pwm2b, // ISRs, Config - /*AT90PWM3B*/ 115, rgftab_at90pwm3b, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART - /*AT90PWM3B*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //AT90CAN32 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90CAN32", 171, F_AVR8, {0x1E, 0x95, 0x81}, // ID - /*AT90CAN32*/ 0, 0x08000, 0x100, 4, 0x0400, 0, 0x0400, 8, 0x0100, 0x0800, // Mem - /*AT90CAN32*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can32, // ISRs, Config - /*AT90CAN32*/ 137, rgftab_at90can128, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*AT90CAN32*/ 7, ports_at90can128, WDT_CLASSIC3}, // Ports, WDT - - //AT90CAN64 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90CAN64", 172, F_AVR8, {0x1E, 0x96, 0x81}, // ID - /*AT90CAN64*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*AT90CAN64*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can64, // ISRs, Config - /*AT90CAN64*/ 137, rgftab_at90can128, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*AT90CAN64*/ 7, ports_at90can128, WDT_CLASSIC3}, // Ports, WDT - - //AT90PWM81 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM81", 173, F_AVR8, {0x1E, 0x93, 0x88}, // ID - /*AT90PWM81*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0100, // Mem - /*AT90PWM81*/ 3, 1, 20, vtab_at90pwm161, 19, cfgtab_at90pwm81, // ISRs, Config - /*AT90PWM81*/ 84, rgftab_at90pwm81, 0, UART_NONE, -1, NULL, // Register file, UART - /*AT90PWM81*/ 3, ports_at90pwm81, WDT_CLASSIC4}, // Ports, WDT - - //AT90USB82 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90USB82", 174, F_AVR8, {0x1E, 0x93, 0x82}, // ID - /*AT90USB82*/ 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90USB82*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162, // ISRs, Config - /*AT90USB82*/ 92, rgftab_at90usb162, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*AT90USB82*/ 3, ports_at90usb162, WDT_CLASSIC4}, // Ports, WDT - - //AT90SCR100 avr-gcc 12.2.0, boot size (manual) // Sources - {"AT90SCR100", 175, F_AVR8, {0x1E, 0x96, 0xC1}, // ID - /*AT90SCR100*/ 0, 0x10000, 0x100, 4, 0x0200, 0, 0x0800, -1, 0x0100, 0x1000, // Mem - /*AT90SCR100*/ 3, 1, 38, vtab_at90scr100h, 13, cfgtab_at90scr100h, // ISRs, Config - /*AT90SCR100*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*AT90SCR100*/ 5, ports_at90scr100, WDT_CLASSIC4}, // Ports, WDT - - //AT90SCR100H xml, from AT90SCR100 // Sources - {"AT90SCR100H", 376, F_AVR8, {0x1E, 0x96, 0xC1}, // ID - /*AT90SCR100H*/ -1, 0x10000, 0x100, 4, 0x0200, 0, 0x0800, -1, 0x0100, 0x1000, // Mem - /*AT90SCR100H*/ 3, 1, 38, vtab_at90scr100h, 13, cfgtab_at90scr100h, // ISRs, Config - /*AT90SCR100H*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_attiny2313, // Register file, UART - /*AT90SCR100H*/ 5, ports_at90scr100, WDT_CLASSIC4}, // Ports, WDT - - //AT90CAN128 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90CAN128", 176, F_AVR8, {0x1E, 0x97, 0x81}, // ID - /*AT90CAN128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem - /*AT90CAN128*/ 3, 1, 37, vtab_at90can128, 15, cfgtab_at90can128, // ISRs, Config - /*AT90CAN128*/ 137, rgftab_at90can128, 2, UART_CLASSIC_2x12, 2, uarts_atmega64, // Register file, UART - /*AT90CAN128*/ 7, ports_at90can128, WDT_CLASSIC3}, // Ports, WDT - - //AT90PWM161 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM161", 177, F_AVR8, {0x1E, 0x94, 0x8B}, // ID - /*AT90PWM161*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*AT90PWM161*/ 3, 1, 20, vtab_at90pwm161, 19, cfgtab_at90pwm81, // ISRs, Config - /*AT90PWM161*/ 86, rgftab_at90pwm161, 0, UART_NONE, -1, NULL, // Register file, UART - /*AT90PWM161*/ 3, ports_at90pwm81, WDT_CLASSIC4}, // Ports, WDT - - //AT90USB162 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90USB162", 178, F_AVR8, {0x1E, 0x94, 0x82}, // ID - /*AT90USB162*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*AT90USB162*/ 3, 1, 29, vtab_atmega32u2, 15, cfgtab_at90usb162, // ISRs, Config - /*AT90USB162*/ 92, rgftab_at90usb162, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*AT90USB162*/ 3, ports_at90usb162, WDT_CLASSIC4}, // Ports, WDT - - //AT90PWM216 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM216", 179, F_AVR8, {0x1E, 0x94, 0x83}, // ID - /*AT90PWM216*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*AT90PWM216*/ 3, 1, 32, vtab_at90pwm316, 18, cfgtab_at90pwm216, // ISRs, Config - /*AT90PWM216*/ 102, rgftab_at90pwm216, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART - /*AT90PWM216*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //AT90PWM316 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90PWM316", 180, F_AVR8, {0x1E, 0x94, 0x83}, // ID - /*AT90PWM316*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*AT90PWM316*/ 3, 1, 32, vtab_at90pwm316, 18, cfgtab_at90pwm316, // ISRs, Config - /*AT90PWM316*/ 117, rgftab_at90pwm316, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART - /*AT90PWM316*/ 4, ports_atmega16m1, WDT_CLASSIC4}, // Ports, WDT - - //AT90USB646 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90USB646", 181, F_AVR8, {0x1E, 0x96, 0x82}, // ID - /*AT90USB646*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*AT90USB646*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb646, // ISRs, Config - /*AT90USB646*/ 157, rgftab_at90usb646, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*AT90USB646*/ 6, ports_atmega32u6, WDT_CLASSIC4}, // Ports, WDT - - //AT90USB647 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90USB647", 182, F_AVR8, {0x1E, 0x96, 0x82}, // ID - /*AT90USB647*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem - /*AT90USB647*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb646, // ISRs, Config - /*AT90USB647*/ 157, rgftab_at90usb646, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*AT90USB647*/ 6, ports_atmega32u6, WDT_CLASSIC4}, // Ports, WDT - //AT90S1200 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S1200", 183, F_AVR8, {0x1E, 0x90, 0x01}, // ID /*AT90S1200*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 1, 0x0060, 0x0020, // Mem @@ -1471,82 +204,54 @@ const Avrintel uP_table[422] = { // Value of -1 typically means unknown /*AT90S1200*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART /*AT90S1200*/ 2, ports_at90s1200, WDT_CLASSIC3}, // Ports, WDT - //AT90USB1286 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90USB1286", 184, F_AVR8, {0x1E, 0x97, 0x82}, // ID - /*AT90USB1286*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, // Mem - /*AT90USB1286*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb1286, // ISRs, Config - /*AT90USB1286*/ 132, rgftab_at90usb1286, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*AT90USB1286*/ 6, ports_atmega32u6, WDT_CLASSIC4}, // Ports, WDT - - //AT90USB1287 atdf, avr-gcc 12.2.0, avrdude // Sources - {"AT90USB1287", 185, F_AVR8, {0x1E, 0x97, 0x82}, // ID - /*AT90USB1287*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, // Mem - /*AT90USB1287*/ 3, 1, 38, vtab_atmega32u6, 15, cfgtab_at90usb1286, // ISRs, Config - /*AT90USB1287*/ 157, rgftab_at90usb646, 1, UART_CLASSIC_2x12, 1, uarts_atmega32u6, // Register file, UART - /*AT90USB1287*/ 6, ports_atmega32u6, WDT_CLASSIC4}, // Ports, WDT - //AT90S2313 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2313", 186, F_AVR8, {0x1E, 0x91, 0x01}, // ID /*AT90S2313*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem /*AT90S2313*/ 1, 1, 11, vtab_at90s2313, 3, cfgtab_at90s2313, // ISRs, Config - /*AT90S2313*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_attiny2313, // Register file, UART + /*AT90S2313*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_at90s2313, // Register file, UART /*AT90S2313*/ 2, ports_at90s1200, WDT_CLASSIC3}, // Ports, WDT //AT90S2323 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2323", 187, F_AVR8, {0x1E, 0x91, 0x02}, // ID /*AT90S2323*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2323*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_at90s2323, // ISRs, Config + /*AT90S2323*/ 1, 1, 3, vtab_at90s2323, 3, cfgtab_at90s2323, // ISRs, Config /*AT90S2323*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART /*AT90S2323*/ 1, ports_at90s2323, WDT_CLASSIC3}, // Ports, WDT //AT90S2333 avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2333", 188, F_AVR8, {0x1E, 0x91, 0x05}, // ID /*AT90S2333*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2333*/ 1, 1, 14, vtab_at90s4433, 5, cfgtab_at90s2333, // ISRs, Config - /*AT90S2333*/ 0, NULL, 1, UART_CLASSIC_1x12, 1, uarts_attiny2313, // Register file, UART + /*AT90S2333*/ 1, 1, 14, vtab_at90s2333, 5, cfgtab_at90s2333, // ISRs, Config + /*AT90S2333*/ 0, NULL, 1, UART_CLASSIC_1x12, 1, uarts_at90s2313, // Register file, UART /*AT90S2333*/ 3, ports_at90s2333, WDT_CLASSIC3}, // Ports, WDT //AT90S2343 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S2343", 189, F_AVR8, {0x1E, 0x91, 0x03}, // ID /*AT90S2343*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem - /*AT90S2343*/ 1, 1, 3, vtab_attiny22, 3, cfgtab_at90s2343, // ISRs, Config + /*AT90S2343*/ 1, 1, 3, vtab_at90s2323, 3, cfgtab_at90s2343, // ISRs, Config /*AT90S2343*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART - /*AT90S2343*/ 1, ports_attiny22, WDT_CLASSIC3}, // Ports, WDT + /*AT90S2343*/ 1, ports_at90s2343, WDT_CLASSIC3}, // Ports, WDT //AT90S4414 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S4414", 190, F_AVR8, {0x1E, 0x92, 0x01}, // ID /*AT90S4414*/ 0, 0x01000, 0x001, 0, 0, 0, 0x0100, 1, 0x0060, 0x0100, // Mem - /*AT90S4414*/ 1, 1, 13, vtab_at90s8515, 3, cfgtab_at90s2313, // ISRs, Config - /*AT90S4414*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_attiny2313, // Register file, UART - /*AT90S4414*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT + /*AT90S4414*/ 1, 1, 13, vtab_at90s4414, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S4414*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_at90s2313, // Register file, UART + /*AT90S4414*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT //AT90S4433 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S4433", 191, F_AVR8, {0x1E, 0x92, 0x03}, // ID /*AT90S4433*/ 0, 0x01000, 0x001, 0, 0, 0, 0x0100, 1, 0x0060, 0x0080, // Mem - /*AT90S4433*/ 1, 1, 14, vtab_at90s4433, 5, cfgtab_at90s4433, // ISRs, Config - /*AT90S4433*/ 0, NULL, 1, UART_CLASSIC_1x12, 1, uarts_attiny2313, // Register file, UART + /*AT90S4433*/ 1, 1, 14, vtab_at90s2333, 5, cfgtab_at90s4433, // ISRs, Config + /*AT90S4433*/ 0, NULL, 1, UART_CLASSIC_1x12, 1, uarts_at90s2313, // Register file, UART /*AT90S4433*/ 3, ports_at90s2333, WDT_CLASSIC3}, // Ports, WDT //AT90S4434 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S4434", 192, F_AVR8, {0x1E, 0x92, 0x02}, // ID /*AT90S4434*/ 0, 0x01000, 0x001, 0, 0, 0, 0x0100, 1, 0x0060, 0x0100, // Mem - /*AT90S4434*/ 1, 1, 17, vtab_at90s8535, 3, cfgtab_at90s2313, // ISRs, Config - /*AT90S4434*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_attiny2313, // Register file, UART - /*AT90S4434*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //AT90S8515 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources - {"AT90S8515", 193, F_AVR8, {0x1E, 0x93, 0x01}, // ID - /*AT90S8515*/ 0, 0x02000, 0x001, 0, 0, 0, 0x0200, 1, 0x0060, 0x0200, // Mem - /*AT90S8515*/ 1, 1, 13, vtab_at90s8515, 3, cfgtab_at90s2313, // ISRs, Config - /*AT90S8515*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_attiny2313, // Register file, UART - /*AT90S8515*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT - - //AT90S8515comp xml // Sources - {"AT90S8515comp", 377, F_AVR8, {0x1E, 0x93, 0x01}, // ID - /*AT90S8515comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem - /*AT90S8515comp*/ -1, -1, 0, NULL, 13, cfgtab_at90s8515comp, // ISRs, Config - /*AT90S8515comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*AT90S8515comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + /*AT90S4434*/ 1, 1, 17, vtab_at90s4434, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S4434*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_at90s2313, // Register file, UART + /*AT90S4434*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT //AT90C8534 avr-gcc 12.2.0 // Sources {"AT90C8534", 194, F_AVR8, {0xff, -1, -1}, // ID @@ -1555,12 +260,26 @@ const Avrintel uP_table[422] = { // Value of -1 typically means unknown /*AT90C8534*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART /*AT90C8534*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT + //AT90S8515 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"AT90S8515", 193, F_AVR8, {0x1E, 0x93, 0x01}, // ID + /*AT90S8515*/ 0, 0x02000, 0x001, 0, 0, 0, 0x0200, 1, 0x0060, 0x0200, // Mem + /*AT90S8515*/ 1, 1, 13, vtab_at90s4414, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S8515*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_at90s2313, // Register file, UART + /*AT90S8515*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //AT90S8515comp xml // Sources + {"AT90S8515comp", 377, F_AVR8, {0x1E, 0x93, 0x01}, // ID + /*AT90S8515comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem + /*AT90S8515comp*/ -1, -1, 0, NULL, 13, cfgtab_at90s8515comp, // ISRs, Config + /*AT90S8515comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*AT90S8515comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + //AT90S8535 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources {"AT90S8535", 195, F_AVR8, {0x1E, 0x93, 0x03}, // ID /*AT90S8535*/ 0, 0x02000, 0x001, 0, 0, 0, 0x0200, 1, 0x0060, 0x0200, // Mem - /*AT90S8535*/ 1, 1, 17, vtab_at90s8535, 3, cfgtab_at90s2313, // ISRs, Config - /*AT90S8535*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_attiny2313, // Register file, UART - /*AT90S8535*/ 4, ports_atmega16, WDT_CLASSIC3}, // Ports, WDT + /*AT90S8535*/ 1, 1, 17, vtab_at90s4434, 3, cfgtab_at90s2313, // ISRs, Config + /*AT90S8535*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_at90s2313, // Register file, UART + /*AT90S8535*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT //AT90S8535comp xml // Sources {"AT90S8535comp", 378, F_AVR8, {0x1E, 0x93, 0x03}, // ID @@ -1569,1519 +288,152 @@ const Avrintel uP_table[422] = { // Value of -1 typically means unknown /*AT90S8535comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART /*AT90S8535comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - //AT94K avr-gcc 12.2.0 // Sources - {"AT94K", 196, F_AVR8, {0xff, -1, -1}, // ID - /*AT94K*/ 0, 0x08000, -1, -1, -1, 0, 0, -1, 0x0060, 0x0fa0, // Mem - /*AT94K*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*AT94K*/ 0, NULL, 2, UART_CLASSIC_2x12, -1, NULL, // Register file, UART - /*AT94K*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT - - //ATA5272 atdf, avr-gcc 12.2.0 // Sources - {"ATA5272", 197, F_AVR8, {0x1E, 0x93, 0x87}, // ID - /*ATA5272*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA5272*/ 3, 1, 37, vtab_ata5272, 11, cfgtab_attiny87, // ISRs, Config - /*ATA5272*/ 80, rgftab_ata5272, 1, UART_LIN, -1, NULL, // Register file, UART - /*ATA5272*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //ATA5505 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA5505", 198, F_AVR8, {0x1E, 0x94, 0x87}, // ID - /*ATA5505*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA5505*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config - /*ATA5505*/ 80, rgftab_ata5272, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART - /*ATA5505*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //ATA5700M322 atdf // Sources - {"ATA5700M322", 199, F_AVR8, {0x1E, 0x95, 0x67}, // ID - /*ATA5700M322*/ 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, // Mem - /*ATA5700M322*/ 1, 1, 51, vtab_ata5702m322, 9, cfgtab_ata5700m322, // ISRs, Config - /*ATA5700M322*/ 337, rgftab_ata5700m322, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5700M322*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA5702M322 atdf, avr-gcc 12.2.0 // Sources - {"ATA5702M322", 200, F_AVR8, {0x1E, 0x95, 0x69}, // ID - /*ATA5702M322*/ 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, // Mem - /*ATA5702M322*/ 1, 1, 51, vtab_ata5702m322, 9, cfgtab_ata5700m322, // ISRs, Config - /*ATA5702M322*/ 378, rgftab_ata5702m322, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5702M322*/ 3, ports_ata6285, WDT_UNKNOWN}, // Ports, WDT - - //ATA5781 atdf // Sources - {"ATA5781", 201, F_AVR8, {0x1E, 0x95, 0x64}, // ID - /*ATA5781*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5781*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config - /*ATA5781*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5781*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA5782 atdf, avr-gcc 12.2.0 // Sources - {"ATA5782", 202, F_AVR8, {0x1E, 0x95, 0x65}, // ID - /*ATA5782*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5782*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config - /*ATA5782*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5782*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT - - //ATA5783 atdf // Sources - {"ATA5783", 203, F_AVR8, {0x1E, 0x95, 0x66}, // ID - /*ATA5783*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5783*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config - /*ATA5783*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5783*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA5787 atdf // Sources - {"ATA5787", 204, F_AVR8, {0x1E, 0x94, 0x6C}, // ID - /*ATA5787*/ 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, // Mem - /*ATA5787*/ 1, 1, 44, vtab_ata5835, 11, cfgtab_ata5787, // ISRs, Config - /*ATA5787*/ 292, rgftab_ata5787, 1, UART_LIN, -1, NULL, // Register file, UART - /*ATA5787*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA5790 atdf, avr-gcc 12.2.0 // Sources - {"ATA5790", 205, F_AVR8, {0x1E, 0x94, 0x61}, // ID - /*ATA5790*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5790*/ 1, 1, 30, vtab_ata5790, 11, cfgtab_ata5790, // ISRs, Config - /*ATA5790*/ 112, rgftab_ata5790, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5790*/ 3, ports_ata5790, WDT_UNKNOWN}, // Ports, WDT - - //ATA5790N atdf, avr-gcc 12.2.0 // Sources - {"ATA5790N", 206, F_AVR8, {0x1E, 0x94, 0x62}, // ID - /*ATA5790N*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5790N*/ 1, 1, 31, vtab_ata5791, 10, cfgtab_ata5790n, // ISRs, Config - /*ATA5790N*/ 117, rgftab_ata5790n, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5790N*/ 3, ports_ata5790, WDT_UNKNOWN}, // Ports, WDT - - //ATA5791 atdf, avr-gcc 7.3.0 // Sources - {"ATA5791", 207, F_AVR8, {0x1E, 0x94, 0x62}, // ID - /*ATA5791*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5791*/ 1, 1, 31, vtab_ata5791, 11, cfgtab_ata5790, // ISRs, Config - /*ATA5791*/ 117, rgftab_ata5790n, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5791*/ 3, ports_ata5790, WDT_UNKNOWN}, // Ports, WDT - - //ATA5795 atdf, avr-gcc 12.2.0 // Sources - {"ATA5795", 208, F_AVR8, {0x1E, 0x93, 0x61}, // ID - /*ATA5795*/ 0, 0x02000, 0x040, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem - /*ATA5795*/ 1, 1, 23, vtab_ata5795, 10, cfgtab_ata5790n, // ISRs, Config - /*ATA5795*/ 84, rgftab_ata5795, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5795*/ 3, ports_ata5795, WDT_UNKNOWN}, // Ports, WDT - - //ATA5831 atdf, avr-gcc 12.2.0 // Sources - {"ATA5831", 209, F_AVR8, {0x1E, 0x95, 0x61}, // ID - /*ATA5831*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5831*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config - /*ATA5831*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5831*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT - - //ATA5832 atdf // Sources - {"ATA5832", 210, F_AVR8, {0x1E, 0x95, 0x62}, // ID - /*ATA5832*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5832*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config - /*ATA5832*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5832*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA5833 atdf // Sources - {"ATA5833", 211, F_AVR8, {0x1E, 0x95, 0x63}, // ID - /*ATA5833*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA5833*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata5781, // ISRs, Config - /*ATA5833*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA5833*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA5835 atdf // Sources - {"ATA5835", 212, F_AVR8, {0x1E, 0x94, 0x6B}, // ID - /*ATA5835*/ 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, // Mem - /*ATA5835*/ 1, 1, 44, vtab_ata5835, 11, cfgtab_ata5835, // ISRs, Config - /*ATA5835*/ 307, rgftab_ata5835, 1, UART_LIN, -1, NULL, // Register file, UART - /*ATA5835*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA6285 atdf, avr-gcc 12.2.0 // Sources - {"ATA6285", 213, F_AVR8, {0x1E, 0x93, 0x82}, // ID - /*ATA6285*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, // Mem - /*ATA6285*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6285, // ISRs, Config - /*ATA6285*/ 79, rgftab_ata6285, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA6285*/ 3, ports_ata6285, WDT_UNKNOWN}, // Ports, WDT - - //ATA6286 atdf, avr-gcc 12.2.0 // Sources - {"ATA6286", 214, F_AVR8, {0x1E, 0x93, 0x82}, // ID - /*ATA6286*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, // Mem - /*ATA6286*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6285, // ISRs, Config - /*ATA6286*/ 79, rgftab_ata6285, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA6286*/ 3, ports_ata6285, WDT_UNKNOWN}, // Ports, WDT - - //ATA6289 xml, avr-gcc 12.2.0, boot size (manual) // Sources - {"ATA6289", 215, F_AVR8, {0x1E, 0x93, 0x82}, // ID - /*ATA6289*/ 0, 0x02000, 0x040, 4, 0x0100, 0x00040, 0x0100, -1, 0x0100, 0x0200, // Mem - /*ATA6289*/ 2, 1, 27, vtab_ata6289, 17, cfgtab_ata6289, // ISRs, Config - /*ATA6289*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART - /*ATA6289*/ 3, ports_ata6289, WDT_UNKNOWN}, // Ports, WDT - - //ATA6612C atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA6612C", 216, F_AVR8, {0x1E, 0x93, 0x0A}, // ID - /*ATA6612C*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATA6612C*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega88, // ISRs, Config - /*ATA6612C*/ 81, rgftab_ata6612c, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATA6612C*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATA6613C atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA6613C", 217, F_AVR8, {0x1E, 0x94, 0x06}, // ID - /*ATA6613C*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*ATA6613C*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega168, // ISRs, Config - /*ATA6613C*/ 81, rgftab_ata6612c, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATA6613C*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATA6614Q atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA6614Q", 218, F_AVR8, {0x1E, 0x95, 0x0F}, // ID - /*ATA6614Q*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*ATA6614Q*/ 3, 1, 26, vtab_atmega328p, 14, cfgtab_atmega328, // ISRs, Config - /*ATA6614Q*/ 81, rgftab_ata6614q, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*ATA6614Q*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //ATA6616C atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA6616C", 219, F_AVR8, {0x1E, 0x93, 0x87}, // ID - /*ATA6616C*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA6616C*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config - /*ATA6616C*/ 81, rgftab_ata6616c, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART - /*ATA6616C*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //ATA6617C atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA6617C", 220, F_AVR8, {0x1E, 0x94, 0x87}, // ID - /*ATA6617C*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA6617C*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config - /*ATA6617C*/ 81, rgftab_ata6616c, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART - /*ATA6617C*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //ATA8210 atdf, avr-gcc 7.3.0 // Sources - {"ATA8210", 221, F_AVR8, {0x1E, 0x95, 0x65}, // ID - /*ATA8210*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8210*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata8210, // ISRs, Config - /*ATA8210*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA8210*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT - - //ATA8215 atdf // Sources - {"ATA8215", 222, F_AVR8, {0x1E, 0x95, 0x64}, // ID - /*ATA8215*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8215*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata8210, // ISRs, Config - /*ATA8215*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA8215*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA8510 atdf, avr-gcc 7.3.0 // Sources - {"ATA8510", 223, F_AVR8, {0x1E, 0x95, 0x61}, // ID - /*ATA8510*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8510*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata8210, // ISRs, Config - /*ATA8510*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA8510*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT - - //ATA8515 atdf // Sources - {"ATA8515", 224, F_AVR8, {0x1E, 0x95, 0x63}, // ID - /*ATA8515*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem - /*ATA8515*/ 1, 1, 42, vtab_ata8515, 11, cfgtab_ata8210, // ISRs, Config - /*ATA8515*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART - /*ATA8515*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATA664251 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATA664251", 225, F_AVR8, {0x1E, 0x94, 0x87}, // ID - /*ATA664251*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem - /*ATA664251*/ 3, 1, 20, vtab_attiny167, 11, cfgtab_attiny87, // ISRs, Config - /*ATA664251*/ 81, rgftab_ata6616c, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART - /*ATA664251*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT - - //M3000 avr-gcc 12.2.0 // Sources - {"M3000", 226, F_AVR8, {0xff, -1, -1}, // ID - /*M3000*/ 0, 0x10000, -1, -1, -1, 0, 0, -1, 0x1000, 0x1000, // Mem - /*M3000*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*M3000*/ 0, NULL, 1, UART_CLASSIC_2x12, -1, NULL, // Register file, UART - /*M3000*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT - - //LGT8F88P avrdude, from ATmega88 // Sources - {"LGT8F88P", 227, F_AVR8, {0x1E, 0x93, 0x0F}, // ID - /*LGT8F88P*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*LGT8F88P*/ -1, -1, 26, vtab_atmega328p, 0, NULL, // ISRs, Config - /*LGT8F88P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*LGT8F88P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //LGT8F168P avrdude, from ATmega168P // Sources - {"LGT8F168P", 228, F_AVR8, {0x1E, 0x94, 0x0B}, // ID - /*LGT8F168P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem - /*LGT8F168P*/ -1, -1, 26, vtab_atmega328p, 0, NULL, // ISRs, Config - /*LGT8F168P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*LGT8F168P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - //LGT8F328P avrdude, from ATmega328P // Sources - {"LGT8F328P", 229, F_AVR8, {0x1E, 0x95, 0x0F}, // ID - /*LGT8F328P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem - /*LGT8F328P*/ -1, -1, 26, vtab_atmega328p, 0, NULL, // ISRs, Config - /*LGT8F328P*/ 81, rgftab_atmega328, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART - /*LGT8F328P*/ 3, ports_atmega328, WDT_CLASSIC4}, // Ports, WDT - - - //ATxmega8E5 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega8E5", 230, F_XMEGA, {0x1E, 0x93, 0x41}, // ID - /*ATxmega8E5*/ 0, 0x02800, 0x080, 1, 0x0800, 0, 0x0200, 32, 0x2000, 0x0400, // Mem - /*ATxmega8E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5, // ISRs, Config - /*ATxmega8E5*/ 438, rgftab_atxmega16e5, 2, UART_XMEGA, 4, uarts_atxmega8e5, // Register file, UART - /*ATxmega8E5*/ 4, ports_atxmega16e5, WDT_XMEGA}, // Ports, WDT - - //ATxmega16A4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega16A4", 231, F_XMEGA, {0x1E, 0x94, 0x41}, // ID - /*ATxmega16A4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16A4*/ 6, 1, 94, vtab_atxmega32a4, 16, cfgtab_atxmega64a4, // ISRs, Config - /*ATxmega16A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega16A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega16A4U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega16A4U", 232, F_XMEGA, {0x1E, 0x94, 0x41}, // ID - /*ATxmega16A4U*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega16A4U*/ 630, rgftab_atxmega16a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega16A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega16C4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega16C4", 233, F_XMEGA, {0x1E, 0x94, 0x43}, // ID - /*ATxmega16C4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16C4*/ 6, 1, 127, vtab_atxmega32c4, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega16C4*/ 482, rgftab_atxmega16c4, 3, UART_XMEGA, 4, uarts_atxmega16c4, // Register file, UART - /*ATxmega16C4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega16D4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega16D4", 234, F_XMEGA, {0x1E, 0x94, 0x42}, // ID - /*ATxmega16D4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem - /*ATxmega16D4*/ 6, 1, 91, vtab_atxmega32d4, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega16D4*/ 460, rgftab_atxmega16d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART - /*ATxmega16D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega16E5 atdf, avr-gcc 7.3.0, avrdude // Sources - {"ATxmega16E5", 235, F_XMEGA, {0x1E, 0x94, 0x45}, // ID - /*ATxmega16E5*/ 0, 0x05000, 0x080, 1, 0x1000, 0, 0x0200, 32, 0x2000, 0x0800, // Mem - /*ATxmega16E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5, // ISRs, Config - /*ATxmega16E5*/ 438, rgftab_atxmega16e5, 2, UART_XMEGA, 4, uarts_atxmega8e5, // Register file, UART - /*ATxmega16E5*/ 4, ports_atxmega16e5, WDT_XMEGA}, // Ports, WDT - - //ATxmega32C3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32C3", 236, F_XMEGA, {0x1E, 0x95, 0x49}, // ID - /*ATxmega32C3*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega32C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega32C3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega32D3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32D3", 237, F_XMEGA, {0x1E, 0x95, 0x4A}, // ID - /*ATxmega32D3*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega32D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega32D3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega32A4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32A4", 238, F_XMEGA, {0x1E, 0x95, 0x41}, // ID - /*ATxmega32A4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32A4*/ 6, 1, 94, vtab_atxmega32a4, 16, cfgtab_atxmega64a4, // ISRs, Config - /*ATxmega32A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega32A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega32A4U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32A4U", 239, F_XMEGA, {0x1E, 0x95, 0x41}, // ID - /*ATxmega32A4U*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega32A4U*/ 630, rgftab_atxmega16a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega32A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega32C4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32C4", 240, F_XMEGA, {0x1E, 0x95, 0x44}, // ID - /*ATxmega32C4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32C4*/ 6, 1, 127, vtab_atxmega32c4, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega32C4*/ 482, rgftab_atxmega16c4, 3, UART_XMEGA, 4, uarts_atxmega16c4, // Register file, UART - /*ATxmega32C4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega32D4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32D4", 241, F_XMEGA, {0x1E, 0x95, 0x42}, // ID - /*ATxmega32D4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32D4*/ 6, 1, 91, vtab_atxmega32d4, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega32D4*/ 460, rgftab_atxmega16d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART - /*ATxmega32D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega32E5 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega32E5", 242, F_XMEGA, {0x1E, 0x95, 0x4C}, // ID - /*ATxmega32E5*/ 0, 0x09000, 0x080, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem - /*ATxmega32E5*/ 7, 1, 43, vtab_atxmega32e5, 17, cfgtab_atxmega16e5, // ISRs, Config - /*ATxmega32E5*/ 438, rgftab_atxmega16e5, 2, UART_XMEGA, 4, uarts_atxmega8e5, // Register file, UART - /*ATxmega32E5*/ 4, ports_atxmega16e5, WDT_XMEGA}, // Ports, WDT - - //ATxmega64A1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64A1", 243, F_XMEGA, {0x1E, 0x96, 0x4E}, // ID - /*ATxmega64A1*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A1*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega64A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART - /*ATxmega64A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega64A1U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64A1U", 244, F_XMEGA, {0x1E, 0x96, 0x4E}, // ID - /*ATxmega64A1U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A1U*/ 6, 1, 127, vtab_atxmega128a1u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega64A1U*/ 943, rgftab_atxmega64a1u, 8, UART_XMEGA, 9, uarts_atxmega64a1u, // Register file, UART - /*ATxmega64A1U*/ 11, ports_atxmega64a1u, WDT_XMEGA}, // Ports, WDT - - //ATxmega64B1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64B1", 245, F_XMEGA, {0x1E, 0x96, 0x52}, // ID - /*ATxmega64B1*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64B1*/ 6, 1, 81, vtab_atxmega128b1, 17, cfgtab_atxmega64b1, // ISRs, Config - /*ATxmega64B1*/ 574, rgftab_atxmega64b1, 2, UART_XMEGA, 4, uarts_atxmega64b1, // Register file, UART - /*ATxmega64B1*/ 8, ports_atxmega64b1, WDT_XMEGA}, // Ports, WDT - - //ATxmega64A3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64A3", 246, F_XMEGA, {0x1E, 0x96, 0x42}, // ID - /*ATxmega64A3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega64A3*/ 680, rgftab_atxmega128a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART - /*ATxmega64A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega64A3U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64A3U", 247, F_XMEGA, {0x1E, 0x96, 0x42}, // ID - /*ATxmega64A3U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega64A3U*/ 792, rgftab_atxmega128a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART - /*ATxmega64A3U*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega64B3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64B3", 248, F_XMEGA, {0x1E, 0x96, 0x51}, // ID - /*ATxmega64B3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64B3*/ 6, 1, 54, vtab_atxmega128b3, 17, cfgtab_atxmega64b1, // ISRs, Config - /*ATxmega64B3*/ 458, rgftab_atxmega64b3, 1, UART_XMEGA, 2, uarts_atxmega64b3, // Register file, UART - /*ATxmega64B3*/ 6, ports_atxmega64b3, WDT_XMEGA}, // Ports, WDT - - //ATxmega64C3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64C3", 249, F_XMEGA, {0x1E, 0x96, 0x49}, // ID - /*ATxmega64C3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega64C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega64C3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega64D3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64D3", 250, F_XMEGA, {0x1E, 0x96, 0x4A}, // ID - /*ATxmega64D3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega64D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega64D3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega64A4 avrdude, from ATxmega32A4 // Sources - {"ATxmega64A4", 251, F_XMEGA, {0x1E, 0x96, 0x46}, // ID - /*ATxmega64A4*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A4*/ 6, 1, 0, NULL, 16, cfgtab_atxmega64a4, // ISRs, Config - /*ATxmega64A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega64A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega64A4U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64A4U", 252, F_XMEGA, {0x1E, 0x96, 0x46}, // ID - /*ATxmega64A4U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega64A4U*/ 632, rgftab_atxmega64a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega64A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega64D4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega64D4", 253, F_XMEGA, {0x1E, 0x96, 0x47}, // ID - /*ATxmega64D4*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem - /*ATxmega64D4*/ 6, 1, 91, vtab_atxmega128d4, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega64D4*/ 460, rgftab_atxmega64d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART - /*ATxmega64D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128A1", 254, F_XMEGA, {0x1E, 0x97, 0x4C}, // ID - /*ATxmega128A1*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A1*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega128A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART - /*ATxmega128A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A1revD avrdude, from ATxmega128A1 // Sources - {"ATxmega128A1revD", 255, F_XMEGA, {0x1E, 0x97, 0x41}, // ID - /*ATxmega128A1revD*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A1revD*/ 6, 1, 125, vtab_atxmega128a1revd, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega128A1revD*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART - /*ATxmega128A1revD*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A1U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128A1U", 256, F_XMEGA, {0x1E, 0x97, 0x4C}, // ID - /*ATxmega128A1U*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A1U*/ 6, 1, 127, vtab_atxmega128a1u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega128A1U*/ 943, rgftab_atxmega64a1u, 8, UART_XMEGA, 9, uarts_atxmega64a1u, // Register file, UART - /*ATxmega128A1U*/ 11, ports_atxmega64a1u, WDT_XMEGA}, // Ports, WDT - - //ATxmega128B1 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128B1", 257, F_XMEGA, {0x1E, 0x97, 0x4D}, // ID - /*ATxmega128B1*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128B1*/ 6, 1, 81, vtab_atxmega128b1, 17, cfgtab_atxmega64b1, // ISRs, Config - /*ATxmega128B1*/ 574, rgftab_atxmega64b1, 2, UART_XMEGA, 4, uarts_atxmega64b1, // Register file, UART - /*ATxmega128B1*/ 8, ports_atxmega64b1, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128A3", 258, F_XMEGA, {0x1E, 0x97, 0x42}, // ID - /*ATxmega128A3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega128A3*/ 680, rgftab_atxmega128a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART - /*ATxmega128A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A3U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128A3U", 259, F_XMEGA, {0x1E, 0x97, 0x42}, // ID - /*ATxmega128A3U*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega128A3U*/ 792, rgftab_atxmega128a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART - /*ATxmega128A3U*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega128B3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128B3", 260, F_XMEGA, {0x1E, 0x97, 0x4B}, // ID - /*ATxmega128B3*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128B3*/ 6, 1, 54, vtab_atxmega128b3, 17, cfgtab_atxmega64b1, // ISRs, Config - /*ATxmega128B3*/ 458, rgftab_atxmega64b3, 1, UART_XMEGA, 2, uarts_atxmega64b3, // Register file, UART - /*ATxmega128B3*/ 6, ports_atxmega64b3, WDT_XMEGA}, // Ports, WDT - - //ATxmega128C3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128C3", 261, F_XMEGA, {0x1E, 0x97, 0x52}, // ID - /*ATxmega128C3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega128C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega128C3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega128D3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128D3", 262, F_XMEGA, {0x1E, 0x97, 0x48}, // ID - /*ATxmega128D3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega128D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega128D3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A4 avrdude, from ATxmega32A4 // Sources - {"ATxmega128A4", 263, F_XMEGA, {0x1E, 0x97, 0x46}, // ID - /*ATxmega128A4*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A4*/ 6, 1, 0, NULL, 16, cfgtab_atxmega64a4, // ISRs, Config - /*ATxmega128A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega128A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega128A4U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128A4U", 264, F_XMEGA, {0x1E, 0x97, 0x46}, // ID - /*ATxmega128A4U*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128A4U*/ 6, 1, 127, vtab_atxmega128a4u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega128A4U*/ 632, rgftab_atxmega64a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART - /*ATxmega128A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega128D4 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega128D4", 265, F_XMEGA, {0x1E, 0x97, 0x47}, // ID - /*ATxmega128D4*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem - /*ATxmega128D4*/ 6, 1, 91, vtab_atxmega128d4, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega128D4*/ 460, rgftab_atxmega64d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART - /*ATxmega128D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT - - //ATxmega192A1 avrdude, from ATxmega128A1 // Sources - {"ATxmega192A1", 266, F_XMEGA, {0x1E, 0x97, 0x4E}, // ID - /*ATxmega192A1*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192A1*/ 6, 1, 0, NULL, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega192A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART - /*ATxmega192A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega192A3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega192A3", 267, F_XMEGA, {0x1E, 0x97, 0x44}, // ID - /*ATxmega192A3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega192A3*/ 680, rgftab_atxmega128a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART - /*ATxmega192A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega192A3U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega192A3U", 268, F_XMEGA, {0x1E, 0x97, 0x44}, // ID - /*ATxmega192A3U*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega192A3U*/ 792, rgftab_atxmega128a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART - /*ATxmega192A3U*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega192C3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega192C3", 269, F_XMEGA, {0x1E, 0x97, 0x51}, // ID - /*ATxmega192C3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega192C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega192C3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega192D3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega192D3", 270, F_XMEGA, {0x1E, 0x97, 0x49}, // ID - /*ATxmega192D3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem - /*ATxmega192D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega192D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega192D3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega256A1 avrdude, from ATxmega128A1 // Sources - {"ATxmega256A1", 271, F_XMEGA, {0x1E, 0x98, 0x46}, // ID - /*ATxmega256A1*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A1*/ 6, 1, 0, NULL, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega256A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART - /*ATxmega256A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega256A3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega256A3", 272, F_XMEGA, {0x1E, 0x98, 0x42}, // ID - /*ATxmega256A3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3*/ 6, 1, 122, vtab_atxmega256a3, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega256A3*/ 680, rgftab_atxmega128a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART - /*ATxmega256A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega256A3B atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega256A3B", 273, F_XMEGA, {0x1E, 0x98, 0x43}, // ID - /*ATxmega256A3B*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3B*/ 6, 1, 122, vtab_atxmega256a3b, 16, cfgtab_atxmega192a1, // ISRs, Config - /*ATxmega256A3B*/ 665, rgftab_atxmega256a3b, 6, UART_XMEGA, 6, uarts_atxmega256a3b, // Register file, UART - /*ATxmega256A3B*/ 0, NULL, WDT_XMEGA}, // Ports, WDT - - //ATxmega256A3BU atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega256A3BU", 274, F_XMEGA, {0x1E, 0x98, 0x43}, // ID - /*ATxmega256A3BU*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3BU*/ 6, 1, 127, vtab_atxmega256a3bu, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega256A3BU*/ 780, rgftab_atxmega256a3bu, 6, UART_XMEGA, 8, uarts_atxmega256a3bu, // Register file, UART - /*ATxmega256A3BU*/ 7, ports_atxmega256a3bu, WDT_XMEGA}, // Ports, WDT - - //ATxmega256A3U atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega256A3U", 275, F_XMEGA, {0x1E, 0x98, 0x42}, // ID - /*ATxmega256A3U*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256A3U*/ 6, 1, 127, vtab_atxmega256a3u, 17, cfgtab_atxmega128a3u, // ISRs, Config - /*ATxmega256A3U*/ 792, rgftab_atxmega128a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART - /*ATxmega256A3U*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega256C3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega256C3", 276, F_XMEGA, {0x1E, 0x98, 0x46}, // ID - /*ATxmega256C3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256C3*/ 6, 1, 127, vtab_atxmega256c3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega256C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega256C3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega256D3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega256D3", 277, F_XMEGA, {0x1E, 0x98, 0x44}, // ID - /*ATxmega256D3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem - /*ATxmega256D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega256D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega256D3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega384C3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega384C3", 278, F_XMEGA, {0x1E, 0x98, 0x45}, // ID - /*ATxmega384C3*/ 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, // Mem - /*ATxmega384C3*/ 6, 1, 127, vtab_atxmega384c3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega384C3*/ 603, rgftab_atxmega384c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega384C3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - //ATxmega384D3 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATxmega384D3", 279, F_XMEGA, {0x1E, 0x98, 0x47}, // ID - /*ATxmega384D3*/ 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, // Mem - /*ATxmega384D3*/ 6, 1, 114, vtab_atxmega384d3, 15, cfgtab_atxmega16c4, // ISRs, Config - /*ATxmega384D3*/ 560, rgftab_atxmega384d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART - /*ATxmega384D3*/ 7, ports_atxmega128a3u, WDT_XMEGA}, // Ports, WDT - - - //ATtiny202 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny202", 280, F_AVR8X, {0x1E, 0x91, 0x23}, // ID - /*ATtiny202*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny202*/ 10, 1, 26, vtab_attiny402, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny202*/ 217, rgftab_attiny202, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART - /*ATtiny202*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT - - //ATtiny204 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny204", 281, F_AVR8X, {0x1E, 0x91, 0x22}, // ID - /*ATtiny204*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny204*/ 10, 1, 26, vtab_attiny404, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny204*/ 235, rgftab_attiny204, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny204*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny212 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny212", 282, F_AVR8X, {0x1E, 0x91, 0x21}, // ID - /*ATtiny212*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny212*/ 10, 1, 26, vtab_attiny412, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny212*/ 247, rgftab_attiny212, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART - /*ATtiny212*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT - - //ATtiny214 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny214", 283, F_AVR8X, {0x1E, 0x91, 0x20}, // ID - /*ATtiny214*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem - /*ATtiny214*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny214*/ 265, rgftab_attiny214, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny214*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny402 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny402", 284, F_AVR8X, {0x1E, 0x92, 0x27}, // ID - /*ATtiny402*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny402*/ 10, 1, 26, vtab_attiny402, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny402*/ 217, rgftab_attiny202, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART - /*ATtiny402*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT - - //ATtiny404 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny404", 285, F_AVR8X, {0x1E, 0x92, 0x26}, // ID - /*ATtiny404*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny404*/ 10, 1, 26, vtab_attiny404, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny404*/ 235, rgftab_attiny204, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny404*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny406 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny406", 286, F_AVR8X, {0x1E, 0x92, 0x25}, // ID - /*ATtiny406*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny406*/ 10, 1, 26, vtab_attiny406, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny406*/ 253, rgftab_attiny406, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny406*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny412 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny412", 287, F_AVR8X, {0x1E, 0x92, 0x23}, // ID - /*ATtiny412*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny412*/ 10, 1, 26, vtab_attiny412, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny412*/ 247, rgftab_attiny212, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART - /*ATtiny412*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT - - //ATtiny414 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny414", 288, F_AVR8X, {0x1E, 0x92, 0x22}, // ID - /*ATtiny414*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny414*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny414*/ 265, rgftab_attiny214, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny414*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny416 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny416", 289, F_AVR8X, {0x1E, 0x92, 0x21}, // ID - /*ATtiny416*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny416*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny416*/ 283, rgftab_attiny416, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny416*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny416auto atdf, avrdude // Sources - {"ATtiny416auto", 290, F_AVR8X, {0x1E, 0x92, 0x28}, // ID - /*ATtiny416auto*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny416auto*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny416auto, // ISRs, Config - /*ATtiny416auto*/ 283, rgftab_attiny416auto, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny416auto*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny417 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny417", 291, F_AVR8X, {0x1E, 0x92, 0x20}, // ID - /*ATtiny417*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem - /*ATtiny417*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny417*/ 283, rgftab_attiny417, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny417*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny424 atdf, avrdude // Sources - {"ATtiny424", 292, F_AVR8X, {0x1E, 0x92, 0x2C}, // ID - /*ATtiny424*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny424*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny424*/ 307, rgftab_attiny1624, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART - /*ATtiny424*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny426 atdf, avrdude // Sources - {"ATtiny426", 293, F_AVR8X, {0x1E, 0x92, 0x2B}, // ID - /*ATtiny426*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny426*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny426*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny426*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny427 atdf, avrdude // Sources - {"ATtiny427", 294, F_AVR8X, {0x1E, 0x92, 0x2A}, // ID - /*ATtiny427*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny427*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny427*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny427*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny804 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny804", 295, F_AVR8X, {0x1E, 0x93, 0x25}, // ID - /*ATtiny804*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny804*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config - /*ATtiny804*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny804*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny806 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny806", 296, F_AVR8X, {0x1E, 0x93, 0x24}, // ID - /*ATtiny806*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny806*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config - /*ATtiny806*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny806*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny807 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny807", 297, F_AVR8X, {0x1E, 0x93, 0x23}, // ID - /*ATtiny807*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny807*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config - /*ATtiny807*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny807*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny814 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny814", 298, F_AVR8X, {0x1E, 0x93, 0x22}, // ID - /*ATtiny814*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny814*/ 10, 1, 26, vtab_attiny814, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny814*/ 265, rgftab_attiny814, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny814*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny816 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny816", 299, F_AVR8X, {0x1E, 0x93, 0x21}, // ID - /*ATtiny816*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny816*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny816*/ 283, rgftab_attiny417, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny816*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny817 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny817", 300, F_AVR8X, {0x1E, 0x93, 0x20}, // ID - /*ATtiny817*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem - /*ATtiny817*/ 10, 1, 26, vtab_attiny817, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny817*/ 283, rgftab_attiny417, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny817*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny824 atdf, avrdude // Sources - {"ATtiny824", 301, F_AVR8X, {0x1E, 0x93, 0x29}, // ID - /*ATtiny824*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem - /*ATtiny824*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny824*/ 307, rgftab_attiny1624, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART - /*ATtiny824*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny826 atdf, avrdude // Sources - {"ATtiny826", 302, F_AVR8X, {0x1E, 0x93, 0x28}, // ID - /*ATtiny826*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem - /*ATtiny826*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny826*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny826*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny827 atdf, avrdude // Sources - {"ATtiny827", 303, F_AVR8X, {0x1E, 0x93, 0x27}, // ID - /*ATtiny827*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem - /*ATtiny827*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny827*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny827*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny1604 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1604", 304, F_AVR8X, {0x1E, 0x94, 0x25}, // ID - /*ATtiny1604*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATtiny1604*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config - /*ATtiny1604*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny1604*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny1606 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1606", 305, F_AVR8X, {0x1E, 0x94, 0x24}, // ID - /*ATtiny1606*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATtiny1606*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config - /*ATtiny1606*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny1606*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny1607 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1607", 306, F_AVR8X, {0x1E, 0x94, 0x23}, // ID - /*ATtiny1607*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATtiny1607*/ 10, 1, 31, vtab_attiny1607, 15, cfgtab_attiny804, // ISRs, Config - /*ATtiny1607*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny1607*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny1614 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1614", 307, F_AVR8X, {0x1E, 0x94, 0x22}, // ID - /*ATtiny1614*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1614*/ 10, 1, 31, vtab_attiny1614, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny1614*/ 308, rgftab_attiny1614, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny1614*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny1616 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1616", 308, F_AVR8X, {0x1E, 0x94, 0x21}, // ID - /*ATtiny1616*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1616*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny1616*/ 326, rgftab_attiny1616, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny1616*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny1617 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny1617", 309, F_AVR8X, {0x1E, 0x94, 0x20}, // ID - /*ATtiny1617*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1617*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny1617*/ 326, rgftab_attiny1616, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny1617*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny1624 atdf, avrdude // Sources - {"ATtiny1624", 310, F_AVR8X, {0x1E, 0x94, 0x2A}, // ID - /*ATtiny1624*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1624*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny1624*/ 307, rgftab_attiny1624, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART - /*ATtiny1624*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny1626 atdf, avrdude // Sources - {"ATtiny1626", 311, F_AVR8X, {0x1E, 0x94, 0x29}, // ID - /*ATtiny1626*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1626*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny1626*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny1626*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny1627 atdf, avrdude // Sources - {"ATtiny1627", 312, F_AVR8X, {0x1E, 0x94, 0x28}, // ID - /*ATtiny1627*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATtiny1627*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny1627*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny1627*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny3214 avr-gcc 12.2.0 // Sources - {"ATtiny3214", 313, F_AVR8X, {0x1E, 0x95, 0x20}, // ID - /*ATtiny3214*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem - /*ATtiny3214*/ 10, 1, 31, vtab_attiny3214, 0, NULL, // ISRs, Config - /*ATtiny3214*/ 0, NULL, 1, UART_AVR8X, -1, NULL, // Register file, UART - /*ATtiny3214*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT - - //ATtiny3216 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny3216", 314, F_AVR8X, {0x1E, 0x95, 0x21}, // ID - /*ATtiny3216*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem - /*ATtiny3216*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny3216*/ 326, rgftab_attiny3216, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny3216*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny3217 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATtiny3217", 315, F_AVR8X, {0x1E, 0x95, 0x22}, // ID - /*ATtiny3217*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem - /*ATtiny3217*/ 10, 1, 31, vtab_attiny3217, 23, cfgtab_attiny204, // ISRs, Config - /*ATtiny3217*/ 326, rgftab_attiny3216, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART - /*ATtiny3217*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATtiny3224 atdf, avrdude // Sources - {"ATtiny3224", 316, F_AVR8X, {0x1E, 0x95, 0x28}, // ID - /*ATtiny3224*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem - /*ATtiny3224*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny3224*/ 307, rgftab_attiny1624, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART - /*ATtiny3224*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT - - //ATtiny3226 atdf, avrdude // Sources - {"ATtiny3226", 317, F_AVR8X, {0x1E, 0x95, 0x27}, // ID - /*ATtiny3226*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem - /*ATtiny3226*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny3226*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny3226*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT - - //ATtiny3227 atdf, avrdude // Sources - {"ATtiny3227", 318, F_AVR8X, {0x1E, 0x95, 0x26}, // ID - /*ATtiny3227*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem - /*ATtiny3227*/ 10, 1, 30, vtab_attiny3227, 16, cfgtab_attiny1624, // ISRs, Config - /*ATtiny3227*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART - /*ATtiny3227*/ 3, ports_attiny417, WDT_AVR8X}, // Ports, WDT - - //ATmega808 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega808", 319, F_AVR8X, {0x1E, 0x93, 0x26}, // ID - /*ATmega808*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATmega808*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega808*/ 406, rgftab_atmega808, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART - /*ATmega808*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //ATmega809 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega809", 320, F_AVR8X, {0x1E, 0x93, 0x2A}, // ID - /*ATmega809*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem - /*ATmega809*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega809*/ 432, rgftab_atmega809, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART - /*ATmega809*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //ATmega1608 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1608", 321, F_AVR8X, {0x1E, 0x94, 0x27}, // ID - /*ATmega1608*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATmega1608*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega1608*/ 406, rgftab_atmega808, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART - /*ATmega1608*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //ATmega1609 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega1609", 322, F_AVR8X, {0x1E, 0x94, 0x26}, // ID - /*ATmega1609*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem - /*ATmega1609*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega1609*/ 432, rgftab_atmega809, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART - /*ATmega1609*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //ATmega3208 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3208", 323, F_AVR8X, {0x1E, 0x95, 0x30}, // ID - /*ATmega3208*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3000, 0x1000, // Mem - /*ATmega3208*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega3208*/ 406, rgftab_atmega3208, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART - /*ATmega3208*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //ATmega3209 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega3209", 324, F_AVR8X, {0x1E, 0x95, 0x31}, // ID - /*ATmega3209*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3000, 0x1000, // Mem - /*ATmega3209*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega3209*/ 432, rgftab_atmega3209, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART - /*ATmega3209*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //ATmega4808 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega4808", 325, F_AVR8X, {0x1E, 0x96, 0x50}, // ID - /*ATmega4808*/ 0, 0x0c000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x2800, 0x1800, // Mem - /*ATmega4808*/ 10, 1, 36, vtab_atmega4808, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega4808*/ 406, rgftab_atmega3208, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART - /*ATmega4808*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //ATmega4809 atdf, avr-gcc 12.2.0, avrdude // Sources - {"ATmega4809", 326, F_AVR8X, {0x1E, 0x96, 0x51}, // ID - /*ATmega4809*/ 0, 0x0c000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x2800, 0x1800, // Mem - /*ATmega4809*/ 10, 1, 40, vtab_atmega4809, 15, cfgtab_atmega808, // ISRs, Config - /*ATmega4809*/ 432, rgftab_atmega3209, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART - /*ATmega4809*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR8EA28 avrdude // Sources - {"AVR8EA28", 327, F_AVR8X, {0x1E, 0x93, 0x2C}, // ID - /*AVR8EA28*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, -1, -1, // Mem - /*AVR8EA28*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*AVR8EA28*/ 0, NULL, 0, UART_AVR8X, -1, NULL, // Register file, UART - /*AVR8EA28*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT - - //AVR8EA32 avrdude // Sources - {"AVR8EA32", 328, F_AVR8X, {0x1E, 0x93, 0x2B}, // ID - /*AVR8EA32*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, -1, -1, // Mem - /*AVR8EA32*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config - /*AVR8EA32*/ 0, NULL, 0, UART_AVR8X, -1, NULL, // Register file, UART - /*AVR8EA32*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT - - //AVR16DD14 atdf, avrdude // Sources - {"AVR16DD14", 329, F_AVR8X, {0x1E, 0x94, 0x34}, // ID - /*AVR16DD14*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD14*/ 16, 4, 36, vtab_avr64dd20, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR16DD14*/ 390, rgftab_avr32dd14, 2, UART_AVR8X, 5, uarts_avr16dd14, // Register file, UART - /*AVR16DD14*/ 4, ports_avr32dd14, WDT_AVR8X}, // Ports, WDT - - //AVR16DU14 atdf, avrdude // Sources - {"AVR16DU14", 386, F_AVR8X, {0x1E, 0x94, 0x3B}, // ID - /*AVR16DU14*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DU14*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR16DU14*/ 370, rgftab_avr16du14, 2, UART_AVR8X, 3, uarts_avr16du14, // Register file, UART - /*AVR16DU14*/ 4, ports_avr16du14, WDT_AVR8X}, // Ports, WDT - - //AVR16EB14 atdf, avrdude // Sources - {"AVR16EB14", 380, F_AVR8X, {0x1E, 0x94, 0x49}, // ID - /*AVR16EB14*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB14*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR16EB14*/ 390, rgftab_avr16eb14, 1, UART_AVR8X, 4, uarts_avr16eb14, // Register file, UART - /*AVR16EB14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT - - //AVR16LA14 atdf // Sources - {"AVR16LA14", 414, F_AVR8X, {0x1E, 0x94, 0x54}, // ID - /*AVR16LA14*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16LA14*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR16LA14*/ 339, rgftab_avr16la14, 1, UART_AVR8X, 3, uarts_avr16la14, // Register file, UART - /*AVR16LA14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT - - //AVR16DD20 atdf, avrdude // Sources - {"AVR16DD20", 330, F_AVR8X, {0x1E, 0x94, 0x33}, // ID - /*AVR16DD20*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD20*/ 16, 4, 36, vtab_avr64dd20, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR16DD20*/ 391, rgftab_avr16dd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART - /*AVR16DD20*/ 4, ports_avr16dd20, WDT_AVR8X}, // Ports, WDT - - //AVR16DU20 atdf, avrdude // Sources - {"AVR16DU20", 387, F_AVR8X, {0x1E, 0x94, 0x3A}, // ID - /*AVR16DU20*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DU20*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR16DU20*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR16DU20*/ 4, ports_avr16du20, WDT_AVR8X}, // Ports, WDT - - //AVR16EB20 atdf, avrdude // Sources - {"AVR16EB20", 381, F_AVR8X, {0x1E, 0x94, 0x40}, // ID - /*AVR16EB20*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB20*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR16EB20*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART - /*AVR16EB20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT - - //AVR16LA20 atdf // Sources - {"AVR16LA20", 415, F_AVR8X, {0x1E, 0x94, 0x53}, // ID - /*AVR16LA20*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16LA20*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR16LA20*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART - /*AVR16LA20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT - - //AVR16DD28 atdf, avrdude // Sources - {"AVR16DD28", 331, F_AVR8X, {0x1E, 0x94, 0x32}, // ID - /*AVR16DD28*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR16DD28*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART - /*AVR16DD28*/ 4, ports_avr16dd28, WDT_AVR8X}, // Ports, WDT - - //AVR16DU28 atdf, avrdude // Sources - {"AVR16DU28", 388, F_AVR8X, {0x1E, 0x94, 0x39}, // ID - /*AVR16DU28*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DU28*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR16DU28*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR16DU28*/ 4, ports_avr16du28, WDT_AVR8X}, // Ports, WDT - - //AVR16EA28 atdf, avrdude // Sources - {"AVR16EA28", 332, F_AVR8X, {0x1E, 0x94, 0x37}, // ID - /*AVR16EA28*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EA28*/ 16, 4, 43, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR16EA28*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART - /*AVR16EA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR16EB28 atdf, avrdude // Sources - {"AVR16EB28", 382, F_AVR8X, {0x1E, 0x94, 0x3F}, // ID - /*AVR16EB28*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB28*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR16EB28*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART - /*AVR16EB28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR16LA28 atdf // Sources - {"AVR16LA28", 416, F_AVR8X, {0x1E, 0x94, 0x52}, // ID - /*AVR16LA28*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16LA28*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR16LA28*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART - /*AVR16LA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR16DD32 atdf, avrdude // Sources - {"AVR16DD32", 333, F_AVR8X, {0x1E, 0x94, 0x31}, // ID - /*AVR16DD32*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR16DD32*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART - /*AVR16DD32*/ 4, ports_avr16dd32, WDT_AVR8X}, // Ports, WDT - - //AVR16DU32 atdf, avrdude // Sources - {"AVR16DU32", 389, F_AVR8X, {0x1E, 0x94, 0x38}, // ID - /*AVR16DU32*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem - /*AVR16DU32*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR16DU32*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR16DU32*/ 4, ports_avr16du32, WDT_AVR8X}, // Ports, WDT - - //AVR16EA32 atdf, avrdude // Sources - {"AVR16EA32", 334, F_AVR8X, {0x1E, 0x94, 0x36}, // ID - /*AVR16EA32*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EA32*/ 16, 4, 43, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR16EA32*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART - /*AVR16EA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR16EB32 atdf, avrdude // Sources - {"AVR16EB32", 383, F_AVR8X, {0x1E, 0x94, 0x3E}, // ID - /*AVR16EB32*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EB32*/ 16, 4, 31, vtab_avr16eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR16EB32*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART - /*AVR16EB32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR16LA32 atdf // Sources - {"AVR16LA32", 417, F_AVR8X, {0x1E, 0x94, 0x51}, // ID - /*AVR16LA32*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16LA32*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR16LA32*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART - /*AVR16LA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR16EA48 atdf, avrdude // Sources - {"AVR16EA48", 335, F_AVR8X, {0x1E, 0x94, 0x35}, // ID - /*AVR16EA48*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR16EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR16EA48*/ 502, rgftab_avr64ea48, 3, UART_AVR8X, 10, uarts_avr16ea48, // Register file, UART - /*AVR16EA48*/ 6, ports_avr64ea48, WDT_AVR8X}, // Ports, WDT - - //AVR32DD14 atdf, avrdude // Sources - {"AVR32DD14", 336, F_AVR8X, {0x1E, 0x95, 0x3B}, // ID - /*AVR32DD14*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD14*/ 16, 4, 36, vtab_avr64dd20, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR32DD14*/ 390, rgftab_avr32dd14, 2, UART_AVR8X, 5, uarts_avr16dd14, // Register file, UART - /*AVR32DD14*/ 4, ports_avr32dd14, WDT_AVR8X}, // Ports, WDT - - //AVR32DU14 atdf, avrdude // Sources - {"AVR32DU14", 390, F_AVR8X, {0x1E, 0x95, 0x4F}, // ID - /*AVR32DU14*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DU14*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR32DU14*/ 370, rgftab_avr16du14, 2, UART_AVR8X, 3, uarts_avr16du14, // Register file, UART - /*AVR32DU14*/ 4, ports_avr16du14, WDT_AVR8X}, // Ports, WDT - - //AVR32EB14 atdf, avrdude // Sources - {"AVR32EB14", 398, F_AVR8X, {0x1E, 0x95, 0x2D}, // ID - /*AVR32EB14*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem - /*AVR32EB14*/ 16, 4, 31, vtab_avr32eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR32EB14*/ 390, rgftab_avr16eb14, 1, UART_AVR8X, 4, uarts_avr16eb14, // Register file, UART - /*AVR32EB14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT - - //AVR32LA14 atdf // Sources - {"AVR32LA14", 418, F_AVR8X, {0x1E, 0x95, 0x29}, // ID - /*AVR32LA14*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR32LA14*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR32LA14*/ 339, rgftab_avr16la14, 1, UART_AVR8X, 3, uarts_avr16la14, // Register file, UART - /*AVR32LA14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT - - //AVR32DD20 atdf, avrdude // Sources - {"AVR32DD20", 337, F_AVR8X, {0x1E, 0x95, 0x3A}, // ID - /*AVR32DD20*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD20*/ 16, 4, 36, vtab_avr64dd20, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR32DD20*/ 391, rgftab_avr16dd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART - /*AVR32DD20*/ 4, ports_avr16dd20, WDT_AVR8X}, // Ports, WDT - - //AVR32DU20 atdf, avrdude // Sources - {"AVR32DU20", 391, F_AVR8X, {0x1E, 0x95, 0x4E}, // ID - /*AVR32DU20*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DU20*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR32DU20*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR32DU20*/ 4, ports_avr16du20, WDT_AVR8X}, // Ports, WDT - - //AVR32EB20 atdf, avrdude // Sources - {"AVR32EB20", 399, F_AVR8X, {0x1E, 0x95, 0x2C}, // ID - /*AVR32EB20*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem - /*AVR32EB20*/ 16, 4, 31, vtab_avr32eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR32EB20*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART - /*AVR32EB20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT - - //AVR32LA20 atdf // Sources - {"AVR32LA20", 419, F_AVR8X, {0x1E, 0x95, 0x60}, // ID - /*AVR32LA20*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR32LA20*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR32LA20*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART - /*AVR32LA20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT - - //AVR32SD20 atdf, avrdude // Sources - {"AVR32SD20", 402, F_AVR8X, {0x1E, 0x95, 0x54}, // ID - /*AVR32SD20*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32SD20*/ 16, 4, 50, vtab_avr32sd20, 18, cfgtab_avr32sd20, // ISRs, Config - /*AVR32SD20*/ 540, rgftab_avr32sd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART - /*AVR32SD20*/ 4, ports_avr16dd20, WDT_AVR8X_DUAL}, // Ports, WDT - - //AVR32DA28 atdf, avrdude // Sources - {"AVR32DA28", 338, F_AVR8X, {0x1E, 0x95, 0x34}, // ID - /*AVR32DA28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA28*/ 16, 4, 41, vtab_avr128da28s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR32DA28*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR32DA28*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT - - //AVR32DA28S atdf, avrdude // Sources - {"AVR32DA28S", 405, F_AVR8X, {0x1E, 0x95, 0x72}, // ID - /*AVR32DA28S*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA28S*/ 16, 4, 41, vtab_avr128da28s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR32DA28S*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR32DA28S*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT - - //AVR32DB28 atdf, avrdude // Sources - {"AVR32DB28", 339, F_AVR8X, {0x1E, 0x95, 0x37}, // ID - /*AVR32DB28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR32DB28*/ 461, rgftab_avr32db28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR32DB28*/ 4, ports_avr32db28, WDT_AVR8X}, // Ports, WDT - - //AVR32DD28 atdf, avrdude // Sources - {"AVR32DD28", 340, F_AVR8X, {0x1E, 0x95, 0x39}, // ID - /*AVR32DD28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR32DD28*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART - /*AVR32DD28*/ 4, ports_avr16dd28, WDT_AVR8X}, // Ports, WDT - - //AVR32DU28 atdf, avrdude // Sources - {"AVR32DU28", 392, F_AVR8X, {0x1E, 0x95, 0x40}, // ID - /*AVR32DU28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DU28*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR32DU28*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR32DU28*/ 4, ports_avr16du28, WDT_AVR8X}, // Ports, WDT - - //AVR32EA28 atdf, avrdude // Sources - {"AVR32EA28", 341, F_AVR8X, {0x1E, 0x95, 0x3E}, // ID - /*AVR32EA28*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem - /*AVR32EA28*/ 16, 4, 43, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR32EA28*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART - /*AVR32EA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR32EB28 atdf, avrdude // Sources - {"AVR32EB28", 400, F_AVR8X, {0x1E, 0x95, 0x2B}, // ID - /*AVR32EB28*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem - /*AVR32EB28*/ 16, 4, 31, vtab_avr32eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR32EB28*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART - /*AVR32EB28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR32LA28 atdf // Sources - {"AVR32LA28", 420, F_AVR8X, {0x1E, 0x95, 0x59}, // ID - /*AVR32LA28*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR32LA28*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR32LA28*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART - /*AVR32LA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR32SD28 atdf, avrdude // Sources - {"AVR32SD28", 403, F_AVR8X, {0x1E, 0x95, 0x53}, // ID - /*AVR32SD28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32SD28*/ 16, 4, 54, vtab_avr32sd28, 18, cfgtab_avr32sd20, // ISRs, Config - /*AVR32SD28*/ 559, rgftab_avr32sd28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART - /*AVR32SD28*/ 4, ports_avr16dd28, WDT_AVR8X_DUAL}, // Ports, WDT - - //AVR32DA32 atdf, avrdude // Sources - {"AVR32DA32", 342, F_AVR8X, {0x1E, 0x95, 0x33}, // ID - /*AVR32DA32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA32*/ 16, 4, 44, vtab_avr128da32s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR32DA32*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR32DA32*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //AVR32DA32S atdf, avrdude // Sources - {"AVR32DA32S", 406, F_AVR8X, {0x1E, 0x95, 0x71}, // ID - /*AVR32DA32S*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA32S*/ 16, 4, 44, vtab_avr128da32s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR32DA32S*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR32DA32S*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //AVR32DB32 atdf, avrdude // Sources - {"AVR32DB32", 343, F_AVR8X, {0x1E, 0x95, 0x36}, // ID - /*AVR32DB32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR32DB32*/ 476, rgftab_avr32db32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR32DB32*/ 4, ports_avr32db32, WDT_AVR8X}, // Ports, WDT - - //AVR32DD32 atdf, avrdude // Sources - {"AVR32DD32", 344, F_AVR8X, {0x1E, 0x95, 0x38}, // ID - /*AVR32DD32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR32DD32*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART - /*AVR32DD32*/ 4, ports_avr16dd32, WDT_AVR8X}, // Ports, WDT - - //AVR32DU32 atdf, avrdude // Sources - {"AVR32DU32", 393, F_AVR8X, {0x1E, 0x95, 0x3F}, // ID - /*AVR32DU32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32DU32*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR32DU32*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR32DU32*/ 4, ports_avr16du32, WDT_AVR8X}, // Ports, WDT - - //AVR32EA32 atdf, avrdude // Sources - {"AVR32EA32", 345, F_AVR8X, {0x1E, 0x95, 0x3D}, // ID - /*AVR32EA32*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem - /*AVR32EA32*/ 16, 4, 43, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR32EA32*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART - /*AVR32EA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR32EB32 atdf, avrdude // Sources - {"AVR32EB32", 401, F_AVR8X, {0x1E, 0x95, 0x2A}, // ID - /*AVR32EB32*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem - /*AVR32EB32*/ 16, 4, 31, vtab_avr32eb32, 18, cfgtab_avr16eb14, // ISRs, Config - /*AVR32EB32*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART - /*AVR32EB32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR32LA32 atdf // Sources - {"AVR32LA32", 421, F_AVR8X, {0x1E, 0x95, 0x58}, // ID - /*AVR32LA32*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem - /*AVR32LA32*/ 12, 4, 29, vtab_avr32la32, 20, cfgtab_avr16la14, // ISRs, Config - /*AVR32LA32*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART - /*AVR32LA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR32SD32 atdf, avrdude // Sources - {"AVR32SD32", 404, F_AVR8X, {0x1E, 0x95, 0x52}, // ID - /*AVR32SD32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem - /*AVR32SD32*/ 16, 4, 56, vtab_avr32sd32, 18, cfgtab_avr32sd20, // ISRs, Config - /*AVR32SD32*/ 575, rgftab_avr32sd32, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART - /*AVR32SD32*/ 4, ports_avr16dd32, WDT_AVR8X_DUAL}, // Ports, WDT - - //AVR32DA48 atdf, avrdude // Sources - {"AVR32DA48", 346, F_AVR8X, {0x1E, 0x95, 0x32}, // ID - /*AVR32DA48*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA48*/ 16, 4, 61, vtab_avr32da48s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR32DA48*/ 610, rgftab_avr32da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR32DA48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR32DA48S atdf, avrdude // Sources - {"AVR32DA48S", 407, F_AVR8X, {0x1E, 0x95, 0x70}, // ID - /*AVR32DA48S*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DA48S*/ 16, 4, 61, vtab_avr32da48s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR32DA48S*/ 610, rgftab_avr32da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR32DA48S*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR32DB48 atdf, avrdude // Sources - {"AVR32DB48", 347, F_AVR8X, {0x1E, 0x95, 0x35}, // ID - /*AVR32DB48*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem - /*AVR32DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR32DB48*/ 642, rgftab_avr32db48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR32DB48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR32EA48 atdf, avrdude // Sources - {"AVR32EA48", 348, F_AVR8X, {0x1E, 0x95, 0x3C}, // ID - /*AVR32EA48*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem - /*AVR32EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR32EA48*/ 502, rgftab_avr64ea48, 3, UART_AVR8X, 10, uarts_avr16ea48, // Register file, UART - /*AVR32EA48*/ 6, ports_avr64ea48, WDT_AVR8X}, // Ports, WDT - - //AVR64DD14 atdf, avrdude // Sources - {"AVR64DD14", 349, F_AVR8X, {0x1E, 0x96, 0x1D}, // ID - /*AVR64DD14*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD14*/ 16, 4, 36, vtab_avr64dd20, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR64DD14*/ 390, rgftab_avr32dd14, 2, UART_AVR8X, 5, uarts_avr16dd14, // Register file, UART - /*AVR64DD14*/ 4, ports_avr32dd14, WDT_AVR8X}, // Ports, WDT - - //AVR64DD20 atdf, avrdude // Sources - {"AVR64DD20", 350, F_AVR8X, {0x1E, 0x96, 0x1C}, // ID - /*AVR64DD20*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD20*/ 16, 4, 36, vtab_avr64dd20, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR64DD20*/ 391, rgftab_avr16dd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART - /*AVR64DD20*/ 4, ports_avr16dd20, WDT_AVR8X}, // Ports, WDT - - //AVR64DA28 atdf, avrdude // Sources - {"AVR64DA28", 351, F_AVR8X, {0x1E, 0x96, 0x15}, // ID - /*AVR64DA28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA28*/ 16, 4, 41, vtab_avr128da28s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR64DA28*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR64DA28*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT - - //AVR64DA28S atdf, avrdude // Sources - {"AVR64DA28S", 408, F_AVR8X, {0x1E, 0x96, 0x2E}, // ID - /*AVR64DA28S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA28S*/ 16, 4, 41, vtab_avr128da28s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR64DA28S*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR64DA28S*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT - - //AVR64DB28 atdf, avrdude // Sources - {"AVR64DB28", 352, F_AVR8X, {0x1E, 0x96, 0x19}, // ID - /*AVR64DB28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR64DB28*/ 461, rgftab_avr32db28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR64DB28*/ 4, ports_avr32db28, WDT_AVR8X}, // Ports, WDT - - //AVR64DD28 atdf, avrdude // Sources - {"AVR64DD28", 353, F_AVR8X, {0x1E, 0x96, 0x1B}, // ID - /*AVR64DD28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD28*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR64DD28*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART - /*AVR64DD28*/ 4, ports_avr16dd28, WDT_AVR8X}, // Ports, WDT - - //AVR64DU28 atdf, avrdude // Sources - {"AVR64DU28", 384, F_AVR8X, {0x1E, 0x96, 0x22}, // ID - /*AVR64DU28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DU28*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR64DU28*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR64DU28*/ 4, ports_avr16du28, WDT_AVR8X}, // Ports, WDT - - //AVR64EA28 atdf, avrdude // Sources - {"AVR64EA28", 354, F_AVR8X, {0x1E, 0x96, 0x20}, // ID - /*AVR64EA28*/ 0, 0x10000, 0x080, 1, 0x0100, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem - /*AVR64EA28*/ 16, 4, 43, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR64EA28*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART - /*AVR64EA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT - - //AVR64DA32 atdf, avrdude // Sources - {"AVR64DA32", 355, F_AVR8X, {0x1E, 0x96, 0x14}, // ID - /*AVR64DA32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA32*/ 16, 4, 44, vtab_avr128da32s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR64DA32*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR64DA32*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //AVR64DA32S atdf, avrdude // Sources - {"AVR64DA32S", 409, F_AVR8X, {0x1E, 0x96, 0x2D}, // ID - /*AVR64DA32S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA32S*/ 16, 4, 44, vtab_avr128da32s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR64DA32S*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR64DA32S*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //AVR64DB32 atdf, avrdude // Sources - {"AVR64DB32", 356, F_AVR8X, {0x1E, 0x96, 0x18}, // ID - /*AVR64DB32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR64DB32*/ 476, rgftab_avr32db32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR64DB32*/ 4, ports_avr32db32, WDT_AVR8X}, // Ports, WDT - - //AVR64DD32 atdf, avrdude // Sources - {"AVR64DD32", 357, F_AVR8X, {0x1E, 0x96, 0x1A}, // ID - /*AVR64DD32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DD32*/ 16, 4, 36, vtab_avr64dd32, 17, cfgtab_avr32dd14, // ISRs, Config - /*AVR64DD32*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART - /*AVR64DD32*/ 4, ports_avr16dd32, WDT_AVR8X}, // Ports, WDT - - //AVR64DU32 atdf, avrdude // Sources - {"AVR64DU32", 385, F_AVR8X, {0x1E, 0x96, 0x21}, // ID - /*AVR64DU32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem - /*AVR64DU32*/ 16, 4, 34, vtab_avr64du32, 20, cfgtab_avr16du14, // ISRs, Config - /*AVR64DU32*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART - /*AVR64DU32*/ 4, ports_avr16du32, WDT_AVR8X}, // Ports, WDT - - //AVR64EA32 atdf, avrdude // Sources - {"AVR64EA32", 358, F_AVR8X, {0x1E, 0x96, 0x1F}, // ID - /*AVR64EA32*/ 0, 0x10000, 0x080, 1, 0x0100, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem - /*AVR64EA32*/ 16, 4, 43, vtab_avr64ea32, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR64EA32*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART - /*AVR64EA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT - - //AVR64DA48 atdf, avrdude // Sources - {"AVR64DA48", 359, F_AVR8X, {0x1E, 0x96, 0x13}, // ID - /*AVR64DA48*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA48*/ 16, 4, 58, vtab_avr128da48s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR64DA48*/ 600, rgftab_avr64da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR64DA48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR64DA48S atdf, avrdude // Sources - {"AVR64DA48S", 410, F_AVR8X, {0x1E, 0x96, 0x2C}, // ID - /*AVR64DA48S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA48S*/ 16, 4, 58, vtab_avr128da48s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR64DA48S*/ 600, rgftab_avr64da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR64DA48S*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR64DB48 atdf, avrdude // Sources - {"AVR64DB48", 360, F_AVR8X, {0x1E, 0x96, 0x17}, // ID - /*AVR64DB48*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR64DB48*/ 642, rgftab_avr32db48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR64DB48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR64EA48 atdf, avrdude // Sources - {"AVR64EA48", 361, F_AVR8X, {0x1E, 0x96, 0x1E}, // ID - /*AVR64EA48*/ 0, 0x10000, 0x080, 1, 0x0100, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem - /*AVR64EA48*/ 16, 4, 45, vtab_avr64ea48, 16, cfgtab_avr64ea48, // ISRs, Config - /*AVR64EA48*/ 502, rgftab_avr64ea48, 3, UART_AVR8X, 10, uarts_avr16ea48, // Register file, UART - /*AVR64EA48*/ 6, ports_avr64ea48, WDT_AVR8X}, // Ports, WDT - - //AVR64DA64 atdf, avrdude // Sources - {"AVR64DA64", 362, F_AVR8X, {0x1E, 0x96, 0x12}, // ID - /*AVR64DA64*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA64*/ 16, 4, 64, vtab_avr128da64s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR64DA64*/ 658, rgftab_avr64da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART - /*AVR64DA64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT - - //AVR64DA64S atdf, avrdude // Sources - {"AVR64DA64S", 411, F_AVR8X, {0x1E, 0x96, 0x2B}, // ID - /*AVR64DA64S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DA64S*/ 16, 4, 64, vtab_avr128da64s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR64DA64S*/ 658, rgftab_avr64da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART - /*AVR64DA64S*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT - - //AVR64DB64 atdf, avrdude // Sources - {"AVR64DB64", 363, F_AVR8X, {0x1E, 0x96, 0x16}, // ID - /*AVR64DB64*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem - /*AVR64DB64*/ 16, 4, 65, vtab_avr128db64, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR64DB64*/ 697, rgftab_avr64db64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART - /*AVR64DB64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT - - //AVR128DA28 atdf, avrdude // Sources - {"AVR128DA28", 364, F_AVR8X, {0x1E, 0x97, 0x0A}, // ID - /*AVR128DA28*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA28*/ 16, 4, 41, vtab_avr128da28s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR128DA28*/ 433, rgftab_avr128da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR128DA28*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT - - //AVR128DA28S atdf, avrdude // Sources - {"AVR128DA28S", 394, F_AVR8X, {0x1E, 0x97, 0x12}, // ID - /*AVR128DA28S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA28S*/ 16, 4, 41, vtab_avr128da28s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR128DA28S*/ 433, rgftab_avr128da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR128DA28S*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT - - //AVR128DB28 atdf, avrdude // Sources - {"AVR128DB28", 365, F_AVR8X, {0x1E, 0x97, 0x0E}, // ID - /*AVR128DB28*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB28*/ 16, 4, 42, vtab_avr128db28, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR128DB28*/ 462, rgftab_avr128db28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART - /*AVR128DB28*/ 4, ports_avr32db28, WDT_AVR8X}, // Ports, WDT - - //AVR128DA32 atdf, avrdude // Sources - {"AVR128DA32", 366, F_AVR8X, {0x1E, 0x97, 0x09}, // ID - /*AVR128DA32*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA32*/ 16, 4, 44, vtab_avr128da32s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR128DA32*/ 448, rgftab_avr128da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR128DA32*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //AVR128DA32S atdf, avrdude // Sources - {"AVR128DA32S", 395, F_AVR8X, {0x1E, 0x97, 0x11}, // ID - /*AVR128DA32S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA32S*/ 16, 4, 44, vtab_avr128da32s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR128DA32S*/ 448, rgftab_avr128da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR128DA32S*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT - - //AVR128DB32 atdf, avrdude // Sources - {"AVR128DB32", 367, F_AVR8X, {0x1E, 0x97, 0x0D}, // ID - /*AVR128DB32*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB32*/ 16, 4, 44, vtab_avr128db32, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR128DB32*/ 477, rgftab_avr128db32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART - /*AVR128DB32*/ 4, ports_avr32db32, WDT_AVR8X}, // Ports, WDT - - //AVR128DA48 atdf, avrdude // Sources - {"AVR128DA48", 368, F_AVR8X, {0x1E, 0x97, 0x08}, // ID - /*AVR128DA48*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA48*/ 16, 4, 58, vtab_avr128da48s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR128DA48*/ 601, rgftab_avr128da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR128DA48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR128DA48S atdf, avrdude // Sources - {"AVR128DA48S", 396, F_AVR8X, {0x1E, 0x97, 0x10}, // ID - /*AVR128DA48S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA48S*/ 16, 4, 58, vtab_avr128da48s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR128DA48S*/ 601, rgftab_avr128da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR128DA48S*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR128DB48 atdf, avrdude // Sources - {"AVR128DB48", 369, F_AVR8X, {0x1E, 0x97, 0x0C}, // ID - /*AVR128DB48*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB48*/ 16, 4, 61, vtab_avr128db48, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR128DB48*/ 643, rgftab_avr128db48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART - /*AVR128DB48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT - - //AVR128DA64 atdf, avrdude // Sources - {"AVR128DA64", 370, F_AVR8X, {0x1E, 0x97, 0x07}, // ID - /*AVR128DA64*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA64*/ 16, 4, 64, vtab_avr128da64s, 15, cfgtab_avr32da28, // ISRs, Config - /*AVR128DA64*/ 659, rgftab_avr128da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART - /*AVR128DA64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT - - //AVR128DA64S atdf, avrdude // Sources - {"AVR128DA64S", 397, F_AVR8X, {0x1E, 0x97, 0x0F}, // ID - /*AVR128DA64S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DA64S*/ 16, 4, 64, vtab_avr128da64s, 17, cfgtab_avr32da28s, // ISRs, Config - /*AVR128DA64S*/ 659, rgftab_avr128da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART - /*AVR128DA64S*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT - - //AVR128DB64 atdf, avrdude // Sources - {"AVR128DB64", 371, F_AVR8X, {0x1E, 0x97, 0x0B}, // ID - /*AVR128DB64*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem - /*AVR128DB64*/ 16, 4, 65, vtab_avr128db64, 16, cfgtab_avr32db28, // ISRs, Config - /*AVR128DB64*/ 698, rgftab_avr128db64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART - /*AVR128DB64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + //AT90CAN32 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90CAN32", 171, F_AVR8, {0x1E, 0x95, 0x81}, // ID + /*AT90CAN32*/ 0, 0x08000, 0x100, 4, 0x0400, 0, 0x0400, 8, 0x0100, 0x0800, // Mem + /*AT90CAN32*/ 3, 1, 37, vtab_at90can32, 15, cfgtab_at90can32, // ISRs, Config + /*AT90CAN32*/ 137, rgftab_at90can32, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*AT90CAN32*/ 7, ports_at90can32, WDT_CLASSIC3}, // Ports, WDT + + //AT90CAN64 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90CAN64", 172, F_AVR8, {0x1E, 0x96, 0x81}, // ID + /*AT90CAN64*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*AT90CAN64*/ 3, 1, 37, vtab_at90can32, 15, cfgtab_at90can64, // ISRs, Config + /*AT90CAN64*/ 137, rgftab_at90can32, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*AT90CAN64*/ 7, ports_at90can32, WDT_CLASSIC3}, // Ports, WDT + + //AT90CAN128 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90CAN128", 176, F_AVR8, {0x1E, 0x97, 0x81}, // ID + /*AT90CAN128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem + /*AT90CAN128*/ 3, 1, 37, vtab_at90can32, 15, cfgtab_at90can128, // ISRs, Config + /*AT90CAN128*/ 137, rgftab_at90can32, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*AT90CAN128*/ 7, ports_at90can32, WDT_CLASSIC3}, // Ports, WDT + + //AT90PWM1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM1", 166, F_AVR8, {0x1E, 0x93, 0x83}, // ID + /*AT90PWM1*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90PWM1*/ 3, 1, 32, vtab_at90pwm1, 17, cfgtab_at90pwm1, // ISRs, Config + /*AT90PWM1*/ 92, rgftab_at90pwm1, 0, UART_NONE, -1, NULL, // Register file, UART + /*AT90PWM1*/ 3, ports_at90pwm1, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM81 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM81", 173, F_AVR8, {0x1E, 0x93, 0x88}, // ID + /*AT90PWM81*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0100, // Mem + /*AT90PWM81*/ 3, 1, 20, vtab_at90pwm81, 19, cfgtab_at90pwm81, // ISRs, Config + /*AT90PWM81*/ 84, rgftab_at90pwm81, 0, UART_NONE, -1, NULL, // Register file, UART + /*AT90PWM81*/ 3, ports_at90pwm1, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM161 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM161", 177, F_AVR8, {0x1E, 0x94, 0x8B}, // ID + /*AT90PWM161*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*AT90PWM161*/ 3, 1, 20, vtab_at90pwm81, 19, cfgtab_at90pwm81, // ISRs, Config + /*AT90PWM161*/ 86, rgftab_at90pwm161, 0, UART_NONE, -1, NULL, // Register file, UART + /*AT90PWM161*/ 3, ports_at90pwm1, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM2 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"AT90PWM2", 167, F_AVR8, {0x1E, 0x93, 0x81}, // ID + /*AT90PWM2*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90PWM2*/ 3, 1, 32, vtab_at90pwm2, 18, cfgtab_at90pwm2, // ISRs, Config + /*AT90PWM2*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART + /*AT90PWM2*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM2B atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM2B", 168, F_AVR8, {0x1E, 0x93, 0x83}, // ID + /*AT90PWM2B*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90PWM2B*/ 3, 1, 32, vtab_at90pwm2b, 18, cfgtab_at90pwm2b, // ISRs, Config + /*AT90PWM2B*/ 100, rgftab_at90pwm2b, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART + /*AT90PWM2B*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM216 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM216", 179, F_AVR8, {0x1E, 0x94, 0x83}, // ID + /*AT90PWM216*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*AT90PWM216*/ 3, 1, 32, vtab_at90pwm216, 18, cfgtab_at90pwm216, // ISRs, Config + /*AT90PWM216*/ 102, rgftab_at90pwm216, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART + /*AT90PWM216*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM3", 169, F_AVR8, {0x1E, 0x93, 0x81}, // ID + /*AT90PWM3*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90PWM3*/ 3, 1, 32, vtab_at90pwm2b, 18, cfgtab_at90pwm2, // ISRs, Config + /*AT90PWM3*/ 115, rgftab_at90pwm3, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART + /*AT90PWM3*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM3B atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM3B", 170, F_AVR8, {0x1E, 0x93, 0x83}, // ID + /*AT90PWM3B*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90PWM3B*/ 3, 1, 32, vtab_at90pwm2b, 18, cfgtab_at90pwm2b, // ISRs, Config + /*AT90PWM3B*/ 115, rgftab_at90pwm3b, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART + /*AT90PWM3B*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //AT90PWM316 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90PWM316", 180, F_AVR8, {0x1E, 0x94, 0x83}, // ID + /*AT90PWM316*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*AT90PWM316*/ 3, 1, 32, vtab_at90pwm216, 18, cfgtab_at90pwm316, // ISRs, Config + /*AT90PWM316*/ 117, rgftab_at90pwm316, 1, UART_CLASSIC_2x12, 1, uarts_at90pwm2, // Register file, UART + /*AT90PWM316*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //AT90USB82 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90USB82", 174, F_AVR8, {0x1E, 0x93, 0x82}, // ID + /*AT90USB82*/ 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90USB82*/ 3, 1, 29, vtab_at90usb82, 15, cfgtab_at90usb82, // ISRs, Config + /*AT90USB82*/ 92, rgftab_at90usb82, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*AT90USB82*/ 3, ports_at90usb82, WDT_CLASSIC4}, // Ports, WDT + + //AT90USB162 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90USB162", 178, F_AVR8, {0x1E, 0x94, 0x82}, // ID + /*AT90USB162*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*AT90USB162*/ 3, 1, 29, vtab_at90usb82, 15, cfgtab_at90usb82, // ISRs, Config + /*AT90USB162*/ 92, rgftab_at90usb82, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*AT90USB162*/ 3, ports_at90usb82, WDT_CLASSIC4}, // Ports, WDT + + //AT90USB646 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90USB646", 181, F_AVR8, {0x1E, 0x96, 0x82}, // ID + /*AT90USB646*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*AT90USB646*/ 3, 1, 38, vtab_at90usb646, 15, cfgtab_at90usb646, // ISRs, Config + /*AT90USB646*/ 157, rgftab_at90usb646, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*AT90USB646*/ 6, ports_at90usb646, WDT_CLASSIC4}, // Ports, WDT + + //AT90USB1286 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90USB1286", 184, F_AVR8, {0x1E, 0x97, 0x82}, // ID + /*AT90USB1286*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, // Mem + /*AT90USB1286*/ 3, 1, 38, vtab_at90usb646, 15, cfgtab_at90usb1286, // ISRs, Config + /*AT90USB1286*/ 132, rgftab_at90usb1286, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*AT90USB1286*/ 6, ports_at90usb646, WDT_CLASSIC4}, // Ports, WDT + + //AT90USB647 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90USB647", 182, F_AVR8, {0x1E, 0x96, 0x82}, // ID + /*AT90USB647*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*AT90USB647*/ 3, 1, 38, vtab_at90usb646, 15, cfgtab_at90usb646, // ISRs, Config + /*AT90USB647*/ 157, rgftab_at90usb646, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*AT90USB647*/ 6, ports_at90usb646, WDT_CLASSIC4}, // Ports, WDT + + //AT90USB1287 atdf, avr-gcc 12.2.0, avrdude // Sources + {"AT90USB1287", 185, F_AVR8, {0x1E, 0x97, 0x82}, // ID + /*AT90USB1287*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x2000, // Mem + /*AT90USB1287*/ 3, 1, 38, vtab_at90usb646, 15, cfgtab_at90usb1286, // ISRs, Config + /*AT90USB1287*/ 157, rgftab_at90usb646, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*AT90USB1287*/ 6, ports_at90usb646, WDT_CLASSIC4}, // Ports, WDT + + //AT90SCR100 avr-gcc 12.2.0, boot size (manual) // Sources + {"AT90SCR100", 175, F_AVR8, {0x1E, 0x96, 0xC1}, // ID + /*AT90SCR100*/ 0, 0x10000, 0x100, 4, 0x0200, 0, 0x0800, -1, 0x0100, 0x1000, // Mem + /*AT90SCR100*/ 3, 1, 38, vtab_at90scr100, 13, cfgtab_at90scr100, // ISRs, Config + /*AT90SCR100*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*AT90SCR100*/ 5, ports_at90scr100, WDT_CLASSIC4}, // Ports, WDT + + //AT90SCR100H xml, from AT90SCR100 // Sources + {"AT90SCR100H", 376, F_AVR8, {0x1E, 0x96, 0xC1}, // ID + /*AT90SCR100H*/ -1, 0x10000, 0x100, 4, 0x0200, 0, 0x0800, -1, 0x0100, 0x1000, // Mem + /*AT90SCR100H*/ 3, 1, 38, vtab_at90scr100, 13, cfgtab_at90scr100, // ISRs, Config + /*AT90SCR100H*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*AT90SCR100H*/ 5, ports_at90scr100, WDT_CLASSIC4}, // Ports, WDT + + //AT86RF401 avr-gcc 12.2.0 // Sources + {"AT86RF401", 165, F_AVR8, {0x1E, 0x91, 0x81}, // ID + /*AT86RF401*/ 0, 0x00800, -1, -1, -1, 0, 0x0080, -1, 0x0060, 0x0080, // Mem + /*AT86RF401*/ 0, 1, 3, vtab_at86rf401, 0, NULL, // ISRs, Config + /*AT86RF401*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART + /*AT86RF401*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT //AT89S51 avrdude // Sources @@ -3097,13 +449,2662 @@ const Avrintel uP_table[422] = { // Value of -1 typically means unknown /*AT89S52*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config /*AT89S52*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART /*AT89S52*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT + + + //AT76C711 avr-gcc 12.2.0 // Sources + {"AT76C711", 164, F_AVR8, {0xff, -1, -1}, // ID + /*AT76C711*/ 0, 0x04000, -1, -1, -1, 0, 0, -1, 0x0060, 0x07a0, // Mem + /*AT76C711*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT76C711*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*AT76C711*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT + + //AT43USB355 avr-gcc 12.2.0 // Sources + {"AT43USB355", 163, F_AVR8, {0xff, -1, -1}, // ID + /*AT43USB355*/ 0, 0x06000, -1, -1, -1, 0, 0, -1, 0x0060, 0x0400, // Mem + /*AT43USB355*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT43USB355*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*AT43USB355*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT + + //AT94K avr-gcc 12.2.0 // Sources + {"AT94K", 196, F_AVR8, {0xff, -1, -1}, // ID + /*AT94K*/ 0, 0x08000, -1, -1, -1, 0, 0, -1, 0x0060, 0x0fa0, // Mem + /*AT94K*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT94K*/ 0, NULL, 2, UART_CLASSIC_2x12, -1, NULL, // Register file, UART + /*AT94K*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT + + //AT43USB320 avr-gcc 12.2.0 // Sources + {"AT43USB320", 162, F_AVR8, {0xff, -1, -1}, // ID + /*AT43USB320*/ 0, 0x10000, -1, -1, -1, 0, 0, -1, 0x0060, 0x0200, // Mem + /*AT43USB320*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AT43USB320*/ 0, NULL, 1, UART_CLASSIC_1x08, -1, NULL, // Register file, UART + /*AT43USB320*/ -1, NULL, WDT_CLASSIC3}, // Ports, WDT + + //M3000 avr-gcc 12.2.0 // Sources + {"M3000", 226, F_AVR8, {0xff, -1, -1}, // ID + /*M3000*/ 0, 0x10000, -1, -1, -1, 0, 0, -1, 0x1000, 0x1000, // Mem + /*M3000*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*M3000*/ 0, NULL, 1, UART_CLASSIC_2x12, -1, NULL, // Register file, UART + /*M3000*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATtiny11 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny11", 8, F_AVR8, {0x1E, 0x90, 0x04}, // ID + /*ATtiny11*/ 0, 0x00400, 0x001, 0, 0, 0, 0, 0, 0x0060, 0x0020, // Mem + /*ATtiny11*/ 1, 1, 5, vtab_attiny11, 4, cfgtab_attiny11, // ISRs, Config + /*ATtiny11*/ 14, rgftab_attiny11, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny11*/ 1, ports_attiny11, WDT_CLASSIC3}, // Ports, WDT + + //ATtiny12 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny12", 9, F_AVR8, {0x1E, 0x90, 0x05}, // ID + /*ATtiny12*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, // Mem + /*ATtiny12*/ 1, 1, 6, vtab_attiny12, 6, cfgtab_attiny12, // ISRs, Config + /*ATtiny12*/ 18, rgftab_attiny12, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny12*/ 1, ports_attiny11, WDT_CLASSIC3}, // Ports, WDT + + //ATtiny22 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"ATtiny22", 13, F_AVR8, {0x1E, 0x91, 0x06}, // ID + /*ATtiny22*/ 0, 0x00800, 0x001, 0, 0, 0, 0x0080, 1, 0x0060, 0x0080, // Mem + /*ATtiny22*/ 1, 1, 3, vtab_at90s2323, 3, cfgtab_attiny22, // ISRs, Config + /*ATtiny22*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny22*/ 1, ports_at90s2343, WDT_CLASSIC3}, // Ports, WDT + + //ATtiny13 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny13", 10, F_AVR8, {0x1E, 0x90, 0x07}, // ID + /*ATtiny13*/ 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, // Mem + /*ATtiny13*/ 2, 1, 10, vtab_attiny13, 10, cfgtab_attiny13, // ISRs, Config + /*ATtiny13*/ 35, rgftab_attiny13, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny13*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny13A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny13A", 11, F_AVR8, {0x1E, 0x90, 0x07}, // ID + /*ATtiny13A*/ 0, 0x00400, 0x020, 0, 0, 0, 0x0040, 4, 0x0060, 0x0040, // Mem + /*ATtiny13A*/ 2, 1, 10, vtab_attiny13, 10, cfgtab_attiny13, // ISRs, Config + /*ATtiny13A*/ 37, rgftab_attiny13a, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny13A*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny43U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny43U", 19, F_AVR8, {0x1E, 0x92, 0x0C}, // ID + /*ATtiny43U*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0060, 0x0100, // Mem + /*ATtiny43U*/ 3, 1, 16, vtab_attiny43u, 11, cfgtab_attiny43u, // ISRs, Config + /*ATtiny43U*/ 54, rgftab_attiny43u, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny43U*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny24 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny24", 14, F_AVR8, {0x1E, 0x91, 0x0B}, // ID + /*ATtiny24*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny24*/ 3, 1, 17, vtab_attiny24, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny24*/ 55, rgftab_attiny24, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny24*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny24A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny24A", 15, F_AVR8, {0x1E, 0x91, 0x0B}, // ID + /*ATtiny24A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny24A*/ 3, 1, 17, vtab_attiny24, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny24A*/ 55, rgftab_attiny24, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny24A*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny44 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny44", 20, F_AVR8, {0x1E, 0x92, 0x07}, // ID + /*ATtiny44*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem + /*ATtiny44*/ 3, 1, 17, vtab_attiny24, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny44*/ 55, rgftab_attiny44, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny44*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny44A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny44A", 21, F_AVR8, {0x1E, 0x92, 0x07}, // ID + /*ATtiny44A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem + /*ATtiny44A*/ 3, 1, 17, vtab_attiny24, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny44A*/ 55, rgftab_attiny44, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny44A*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny84 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny84", 24, F_AVR8, {0x1E, 0x93, 0x0C}, // ID + /*ATtiny84*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATtiny84*/ 3, 1, 17, vtab_attiny24, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny84*/ 55, rgftab_attiny84, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny84*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny84A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny84A", 25, F_AVR8, {0x1E, 0x93, 0x0C}, // ID + /*ATtiny84A*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATtiny84A*/ 3, 1, 17, vtab_attiny24, 11, cfgtab_attiny24, // ISRs, Config + /*ATtiny84A*/ 55, rgftab_attiny84, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny84A*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny15 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny15", 12, F_AVR8, {0x1E, 0x90, 0x06}, // ID + /*ATtiny15*/ 0, 0x00400, 0x001, 0, 0, 0, 0x0040, 2, 0x0060, 0x0020, // Mem + /*ATtiny15*/ 1, 1, 9, vtab_attiny15, 6, cfgtab_attiny15, // ISRs, Config + /*ATtiny15*/ 28, rgftab_attiny15, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny15*/ 1, ports_attiny11, WDT_CLASSIC3}, // Ports, WDT + + //ATtiny25 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny25", 16, F_AVR8, {0x1E, 0x91, 0x08}, // ID + /*ATtiny25*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny25*/ 3, 1, 15, vtab_attiny25, 11, cfgtab_attiny25, // ISRs, Config + /*ATtiny25*/ 55, rgftab_attiny25, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny25*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny45 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny45", 22, F_AVR8, {0x1E, 0x92, 0x06}, // ID + /*ATtiny45*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem + /*ATtiny45*/ 3, 1, 15, vtab_attiny25, 11, cfgtab_attiny25, // ISRs, Config + /*ATtiny45*/ 55, rgftab_attiny45, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny45*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny85 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny85", 26, F_AVR8, {0x1E, 0x93, 0x0B}, // ID + /*ATtiny85*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATtiny85*/ 3, 1, 15, vtab_attiny25, 11, cfgtab_attiny25, // ISRs, Config + /*ATtiny85*/ 55, rgftab_attiny45, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny85*/ 1, ports_attiny13, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny26 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny26", 17, F_AVR8, {0x1E, 0x91, 0x09}, // ID + /*ATtiny26*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny26*/ 2, 1, 12, vtab_attiny26, 8, cfgtab_attiny26, // ISRs, Config + /*ATtiny26*/ 37, rgftab_attiny26, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny26*/ 2, ports_attiny43u, WDT_CLASSIC3}, // Ports, WDT + + //ATtiny87 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny87", 27, F_AVR8, {0x1E, 0x93, 0x87}, // ID + /*ATtiny87*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATtiny87*/ 3, 1, 20, vtab_attiny87, 11, cfgtab_attiny87, // ISRs, Config + /*ATtiny87*/ 80, rgftab_attiny87, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART + /*ATtiny87*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny167 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny167", 29, F_AVR8, {0x1E, 0x94, 0x87}, // ID + /*ATtiny167*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATtiny167*/ 3, 1, 20, vtab_attiny87, 11, cfgtab_attiny87, // ISRs, Config + /*ATtiny167*/ 80, rgftab_attiny87, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART + /*ATtiny167*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny28 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny28", 18, F_AVR8, {0x1E, 0x91, 0x07}, // ID + /*ATtiny28*/ 0, 0x00800, 0x002, 0, 0, 0, 0, 0, 0x0060, 0x0020, // Mem + /*ATtiny28*/ 1, 1, 6, vtab_attiny28, 3, cfgtab_attiny28, // ISRs, Config + /*ATtiny28*/ 20, rgftab_attiny28, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny28*/ 3, ports_attiny28, WDT_CLASSIC3}, // Ports, WDT + + //ATtiny48 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny48", 23, F_AVR8, {0x1E, 0x92, 0x09}, // ID + /*ATtiny48*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0100, // Mem + /*ATtiny48*/ 3, 1, 20, vtab_attiny48, 11, cfgtab_attiny48, // ISRs, Config + /*ATtiny48*/ 74, rgftab_attiny48, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny48*/ 4, ports_attiny48, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny88 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny88", 28, F_AVR8, {0x1E, 0x93, 0x11}, // ID + /*ATtiny88*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0040, 4, 0x0100, 0x0200, // Mem + /*ATtiny88*/ 3, 1, 20, vtab_attiny48, 11, cfgtab_attiny48, // ISRs, Config + /*ATtiny88*/ 74, rgftab_attiny88, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny88*/ 4, ports_attiny48, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny828 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny828", 35, F_AVR8, {0x1E, 0x93, 0x14}, // ID + /*ATtiny828*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATtiny828*/ 3, 1, 26, vtab_attiny828, 16, cfgtab_attiny828, // ISRs, Config + /*ATtiny828*/ 94, rgftab_attiny828, 1, UART_CLASSIC_2x12, 1, uarts_attiny828, // Register file, UART + /*ATtiny828*/ 4, ports_attiny828, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny828R avrdude, from ATtiny828 // Sources + {"ATtiny828R", 36, F_AVR8, {0x1E, 0x93, 0x14}, // ID + /*ATtiny828R*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATtiny828R*/ 3, 1, 26, vtab_attiny828, 16, cfgtab_attiny828, // ISRs, Config + /*ATtiny828R*/ 94, rgftab_attiny828, 1, UART_CLASSIC_2x12, 1, uarts_attiny828, // Register file, UART + /*ATtiny828R*/ 4, ports_attiny828, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny1634 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1634", 40, F_AVR8, {0x1E, 0x94, 0x12}, // ID + /*ATtiny1634*/ 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, // Mem + /*ATtiny1634*/ 3, 1, 28, vtab_attiny1634, 13, cfgtab_attiny1634, // ISRs, Config + /*ATtiny1634*/ 89, rgftab_attiny1634, 2, UART_CLASSIC_2x12, 2, uarts_attiny1634, // Register file, UART + /*ATtiny1634*/ 3, ports_attiny1634, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny1634R avrdude, from ATtiny1634 // Sources + {"ATtiny1634R", 41, F_AVR8, {0x1E, 0x94, 0x12}, // ID + /*ATtiny1634R*/ 0, 0x04000, 0x020, 0, 0, 0, 0x0100, 4, 0x0100, 0x0400, // Mem + /*ATtiny1634R*/ 3, 1, 28, vtab_attiny1634, 13, cfgtab_attiny1634, // ISRs, Config + /*ATtiny1634R*/ 89, rgftab_attiny1634, 2, UART_CLASSIC_2x12, 2, uarts_attiny1634, // Register file, UART + /*ATtiny1634R*/ 3, ports_attiny1634, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny441 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny441", 32, F_AVR8, {0x1E, 0x92, 0x15}, // ID + /*ATtiny441*/ 0, 0x01000, 0x010, 0, 0, 0, 0x0100, 4, 0x0100, 0x0100, // Mem + /*ATtiny441*/ 3, 1, 30, vtab_attiny441, 14, cfgtab_attiny441, // ISRs, Config + /*ATtiny441*/ 101, rgftab_attiny441, 2, UART_CLASSIC_2x12, 3, uarts_attiny441, // Register file, UART + /*ATtiny441*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny841 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny841", 37, F_AVR8, {0x1E, 0x93, 0x15}, // ID + /*ATtiny841*/ 0, 0x02000, 0x010, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATtiny841*/ 3, 1, 30, vtab_attiny441, 14, cfgtab_attiny441, // ISRs, Config + /*ATtiny841*/ 101, rgftab_attiny441, 2, UART_CLASSIC_2x12, 3, uarts_attiny441, // Register file, UART + /*ATtiny841*/ 2, ports_attiny24, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny261 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny261", 30, F_AVR8, {0x1E, 0x91, 0x0C}, // ID + /*ATtiny261*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny261*/ 3, 1, 19, vtab_attiny261, 11, cfgtab_attiny261, // ISRs, Config + /*ATtiny261*/ 63, rgftab_attiny261, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny261*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny261A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny261A", 31, F_AVR8, {0x1E, 0x91, 0x0C}, // ID + /*ATtiny261A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny261A*/ 3, 1, 19, vtab_attiny261, 11, cfgtab_attiny261, // ISRs, Config + /*ATtiny261A*/ 63, rgftab_attiny261, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny261A*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny461 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny461", 33, F_AVR8, {0x1E, 0x92, 0x08}, // ID + /*ATtiny461*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem + /*ATtiny461*/ 3, 1, 19, vtab_attiny261, 11, cfgtab_attiny261, // ISRs, Config + /*ATtiny461*/ 63, rgftab_attiny461, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny461*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny461A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny461A", 34, F_AVR8, {0x1E, 0x92, 0x08}, // ID + /*ATtiny461A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem + /*ATtiny461A*/ 3, 1, 19, vtab_attiny261, 11, cfgtab_attiny261, // ISRs, Config + /*ATtiny461A*/ 63, rgftab_attiny461, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny461A*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny861 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny861", 38, F_AVR8, {0x1E, 0x93, 0x0D}, // ID + /*ATtiny861*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATtiny861*/ 3, 1, 19, vtab_attiny261, 11, cfgtab_attiny261, // ISRs, Config + /*ATtiny861*/ 63, rgftab_attiny861, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny861*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny861A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny861A", 39, F_AVR8, {0x1E, 0x93, 0x0D}, // ID + /*ATtiny861A*/ 0, 0x02000, 0x040, 0, 0, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATtiny861A*/ 3, 1, 19, vtab_attiny261, 11, cfgtab_attiny261, // ISRs, Config + /*ATtiny861A*/ 63, rgftab_attiny861, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATtiny861A*/ 2, ports_attiny43u, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny2313 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny2313", 42, F_AVR8, {0x1E, 0x91, 0x0A}, // ID + /*ATtiny2313*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny2313*/ 3, 1, 19, vtab_attiny2313, 11, cfgtab_attiny2313, // ISRs, Config + /*ATtiny2313*/ 54, rgftab_attiny2313, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*ATtiny2313*/ 3, ports_attiny2313, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny2313A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny2313A", 43, F_AVR8, {0x1E, 0x91, 0x0A}, // ID + /*ATtiny2313A*/ 0, 0x00800, 0x020, 0, 0, 0, 0x0080, 4, 0x0060, 0x0080, // Mem + /*ATtiny2313A*/ 3, 1, 21, vtab_attiny2313a, 11, cfgtab_attiny2313a, // ISRs, Config + /*ATtiny2313A*/ 58, rgftab_attiny2313a, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*ATtiny2313A*/ 3, ports_attiny2313, WDT_CLASSIC4}, // Ports, WDT + + //ATtiny4313 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny4313", 44, F_AVR8, {0x1E, 0x92, 0x0D}, // ID + /*ATtiny4313*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0060, 0x0100, // Mem + /*ATtiny4313*/ 3, 1, 21, vtab_attiny2313a, 11, cfgtab_attiny2313a, // ISRs, Config + /*ATtiny4313*/ 58, rgftab_attiny4313, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*ATtiny4313*/ 3, ports_attiny2313, WDT_CLASSIC4}, // Ports, WDT + + //ATmega8 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega8", 45, F_AVR8, {0x1E, 0x93, 0x07}, // ID + /*ATmega8*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem + /*ATmega8*/ 2, 1, 19, vtab_atmega8, 13, cfgtab_atmega8, // ISRs, Config + /*ATmega8*/ 61, rgftab_atmega8, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega8*/ 3, ports_atmega8, WDT_CLASSIC3}, // Ports, WDT + + //ATmega8A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega8A", 46, F_AVR8, {0x1E, 0x93, 0x07}, // ID + /*ATmega8A*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem + /*ATmega8A*/ 2, 1, 19, vtab_atmega8, 13, cfgtab_atmega8, // ISRs, Config + /*ATmega8A*/ 61, rgftab_atmega8, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega8A*/ 3, ports_atmega8, WDT_CLASSIC3}, // Ports, WDT + + //ATmega16 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16", 49, F_AVR8, {0x1E, 0x94, 0x03}, // ID + /*ATmega16*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem + /*ATmega16*/ 2, 1, 21, vtab_atmega16, 13, cfgtab_atmega16, // ISRs, Config + /*ATmega16*/ 70, rgftab_atmega16, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART + /*ATmega16*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega16A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16A", 50, F_AVR8, {0x1E, 0x94, 0x03}, // ID + /*ATmega16A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0400, // Mem + /*ATmega16A*/ 2, 1, 21, vtab_atmega16, 13, cfgtab_atmega16, // ISRs, Config + /*ATmega16A*/ 70, rgftab_atmega16a, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART + /*ATmega16A*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega32 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32", 58, F_AVR8, {0x1E, 0x95, 0x02}, // ID + /*ATmega32*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, // Mem + /*ATmega32*/ 2, 1, 21, vtab_atmega32, 13, cfgtab_atmega32, // ISRs, Config + /*ATmega32*/ 68, rgftab_atmega32, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART + /*ATmega32*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega32A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32A", 59, F_AVR8, {0x1E, 0x95, 0x02}, // ID + /*ATmega32A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0060, 0x0800, // Mem + /*ATmega32A*/ 2, 1, 21, vtab_atmega32, 13, cfgtab_atmega32, // ISRs, Config + /*ATmega32A*/ 66, rgftab_atmega32a, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART + /*ATmega32A*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega64 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega64", 72, F_AVR8, {0x1E, 0x96, 0x02}, // ID + /*ATmega64*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega64*/ 3, 1, 35, vtab_atmega64, 15, cfgtab_atmega64, // ISRs, Config + /*ATmega64*/ 103, rgftab_atmega64, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmega64*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT + + //ATmega64A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega64A", 73, F_AVR8, {0x1E, 0x96, 0x02}, // ID + /*ATmega64A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega64A*/ 3, 1, 35, vtab_atmega64, 15, cfgtab_atmega64, // ISRs, Config + /*ATmega64A*/ 103, rgftab_atmega64, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmega64A*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT + + //ATmega128 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega128", 85, F_AVR8, {0x1E, 0x97, 0x02}, // ID + /*ATmega128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem + /*ATmega128*/ 3, 1, 35, vtab_atmega64, 15, cfgtab_atmega128, // ISRs, Config + /*ATmega128*/ 103, rgftab_atmega128, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmega128*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT + + //ATmega128A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega128A", 86, F_AVR8, {0x1E, 0x97, 0x02}, // ID + /*ATmega128A*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem + /*ATmega128A*/ 3, 1, 35, vtab_atmega64, 15, cfgtab_atmega128, // ISRs, Config + /*ATmega128A*/ 103, rgftab_atmega128a, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmega128A*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT + + //ATmegaS128 atdf, avrdude, from ATmega128 // Sources + {"ATmegaS128", 413, F_AVR8, {0x1E, 0x97, 0x02}, // ID + /*ATmegaS128*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x1000, // Mem + /*ATmegaS128*/ 3, 1, 35, vtab_atmega64, 15, cfgtab_atmega128, // ISRs, Config + /*ATmegaS128*/ 103, rgftab_atmega128, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmegaS128*/ 7, ports_atmega64, WDT_CLASSIC3}, // Ports, WDT + + //ATmega640 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega640", 126, F_AVR8, {0x1E, 0x96, 0x08}, // ID + /*ATmega640*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem + /*ATmega640*/ 3, 1, 57, vtab_atmega640, 14, cfgtab_atmega640, // ISRs, Config + /*ATmega640*/ 160, rgftab_atmega640, 4, UART_CLASSIC_2x12, 4, uarts_atmega640, // Register file, UART + /*ATmega640*/ 11, ports_atmega640, WDT_CLASSIC4}, // Ports, WDT + + //ATmega1280 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1280", 138, F_AVR8, {0x1E, 0x97, 0x03}, // ID + /*ATmega1280*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem + /*ATmega1280*/ 3, 1, 57, vtab_atmega640, 14, cfgtab_atmega1280, // ISRs, Config + /*ATmega1280*/ 161, rgftab_atmega1280, 4, UART_CLASSIC_2x12, 4, uarts_atmega640, // Register file, UART + /*ATmega1280*/ 11, ports_atmega640, WDT_CLASSIC4}, // Ports, WDT + + //ATmega2560 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega2560", 143, F_AVR8, {0x1E, 0x98, 0x01}, // ID + /*ATmega2560*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem + /*ATmega2560*/ 3, 1, 57, vtab_atmega640, 14, cfgtab_atmega2560, // ISRs, Config + /*ATmega2560*/ 161, rgftab_atmega1280, 4, UART_CLASSIC_2x12, 4, uarts_atmega640, // Register file, UART + /*ATmega2560*/ 11, ports_atmega640, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32C1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32C1", 62, F_AVR8, {0x1E, 0x95, 0x86}, // ID + /*ATmega32C1*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega32C1*/ 3, 1, 31, vtab_atmega32c1, 17, cfgtab_atmega32c1, // ISRs, Config + /*ATmega32C1*/ 117, rgftab_atmega32c1, 1, UART_LIN, 1, uarts_atmega32c1, // Register file, UART + /*ATmega32C1*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //ATmega64C1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega64C1", 75, F_AVR8, {0x1E, 0x96, 0x86}, // ID + /*ATmega64C1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega64C1*/ 3, 1, 31, vtab_atmega32c1, 17, cfgtab_atmega64c1, // ISRs, Config + /*ATmega64C1*/ 122, rgftab_atmega64c1, 1, UART_LIN, 1, uarts_atmega32c1, // Register file, UART + /*ATmega64C1*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16M1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16M1", 54, F_AVR8, {0x1E, 0x94, 0x84}, // ID + /*ATmega16M1*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega16M1*/ 3, 1, 31, vtab_atmega32c1, 17, cfgtab_atmega16m1, // ISRs, Config + /*ATmega16M1*/ 136, rgftab_atmega16m1, 1, UART_LIN, 1, uarts_atmega32c1, // Register file, UART + /*ATmega16M1*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32M1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32M1", 63, F_AVR8, {0x1E, 0x95, 0x84}, // ID + /*ATmega32M1*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega32M1*/ 3, 1, 31, vtab_atmega32c1, 17, cfgtab_atmega32c1, // ISRs, Config + /*ATmega32M1*/ 136, rgftab_atmega16m1, 1, UART_LIN, 1, uarts_atmega32c1, // Register file, UART + /*ATmega32M1*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //ATmega64M1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega64M1", 76, F_AVR8, {0x1E, 0x96, 0x84}, // ID + /*ATmega64M1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega64M1*/ 3, 1, 31, vtab_atmega32c1, 17, cfgtab_atmega64c1, // ISRs, Config + /*ATmega64M1*/ 136, rgftab_atmega64m1, 1, UART_LIN, 1, uarts_atmega32c1, // Register file, UART + /*ATmega64M1*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //ATmegaS64M1 atdf, avrdude, from ATmega64M1 // Sources + {"ATmegaS64M1", 412, F_AVR8, {0x1E, 0x96, 0x84}, // ID + /*ATmegaS64M1*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmegaS64M1*/ 3, 1, 31, vtab_atmega32c1, 17, cfgtab_atmega64c1, // ISRs, Config + /*ATmegaS64M1*/ 136, rgftab_atmega64m1, 1, UART_LIN, 1, uarts_atmega32c1, // Register file, UART + /*ATmegaS64M1*/ 4, ports_at90pwm2, WDT_CLASSIC4}, // Ports, WDT + + //ATmega128RFA1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega128RFA1", 87, F_AVR8, {0x1E, 0xA7, 0x01}, // ID + /*ATmega128RFA1*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem + /*ATmega128RFA1*/ 3, 1, 72, vtab_atmega128rfa1, 14, cfgtab_atmega128rfa1, // ISRs, Config + /*ATmega128RFA1*/ 237, rgftab_atmega128rfa1, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega128RFA1*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega64RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega64RFR2", 78, F_AVR8, {0x1E, 0xA6, 0x02}, // ID + /*ATmega64RFR2*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, // Mem + /*ATmega64RFR2*/ 3, 1, 77, vtab_atmega64rfr2, 14, cfgtab_atmega64rfr2, // ISRs, Config + /*ATmega64RFR2*/ 269, rgftab_atmega64rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega64RFR2*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega128RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega128RFR2", 88, F_AVR8, {0x1E, 0xA7, 0x02}, // ID + /*ATmega128RFR2*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem + /*ATmega128RFR2*/ 3, 1, 77, vtab_atmega64rfr2, 14, cfgtab_atmega128rfr2, // ISRs, Config + /*ATmega128RFR2*/ 270, rgftab_atmega128rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega128RFR2*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega256RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega256RFR2", 108, F_AVR8, {0x1E, 0xA8, 0x02}, // ID + /*ATmega256RFR2*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, // Mem + /*ATmega256RFR2*/ 3, 1, 77, vtab_atmega64rfr2, 14, cfgtab_atmega256rfr2, // ISRs, Config + /*ATmega256RFR2*/ 271, rgftab_atmega256rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega256RFR2*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega8U2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega8U2", 48, F_AVR8, {0x1E, 0x93, 0x89}, // ID + /*ATmega8U2*/ 0, 0x02000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATmega8U2*/ 3, 1, 29, vtab_at90usb82, 15, cfgtab_atmega8u2, // ISRs, Config + /*ATmega8U2*/ 92, rgftab_atmega8u2, 1, UART_CLASSIC_2x12, 1, uarts_atmega8u2, // Register file, UART + /*ATmega8U2*/ 3, ports_at90usb82, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16U2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16U2", 56, F_AVR8, {0x1E, 0x94, 0x89}, // ID + /*ATmega16U2*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATmega16U2*/ 3, 1, 29, vtab_at90usb82, 15, cfgtab_at90usb82, // ISRs, Config + /*ATmega16U2*/ 92, rgftab_atmega8u2, 1, UART_CLASSIC_2x12, 1, uarts_atmega8u2, // Register file, UART + /*ATmega16U2*/ 3, ports_at90usb82, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32U2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32U2", 64, F_AVR8, {0x1E, 0x95, 0x8A}, // ID + /*ATmega32U2*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0400, // Mem + /*ATmega32U2*/ 3, 1, 29, vtab_at90usb82, 15, cfgtab_atmega32u2, // ISRs, Config + /*ATmega32U2*/ 92, rgftab_atmega8u2, 1, UART_CLASSIC_2x12, 1, uarts_atmega8u2, // Register file, UART + /*ATmega32U2*/ 3, ports_at90usb82, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16U4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16U4", 57, F_AVR8, {0x1E, 0x94, 0x88}, // ID + /*ATmega16U4*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0500, // Mem + /*ATmega16U4*/ 3, 1, 43, vtab_atmega16u4, 15, cfgtab_atmega16u4, // ISRs, Config + /*ATmega16U4*/ 139, rgftab_atmega16u4, 1, UART_CLASSIC_2x12, 1, uarts_atmega16u4, // Register file, UART + /*ATmega16U4*/ 5, ports_atmega16u4, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32U4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32U4", 65, F_AVR8, {0x1E, 0x95, 0x87}, // ID + /*ATmega32U4*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0a00, // Mem + /*ATmega32U4*/ 3, 1, 43, vtab_atmega16u4, 15, cfgtab_atmega32u4, // ISRs, Config + /*ATmega32U4*/ 139, rgftab_atmega16u4, 1, UART_CLASSIC_2x12, 1, uarts_atmega16u4, // Register file, UART + /*ATmega32U4*/ 5, ports_atmega16u4, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32U6 xml, avr-gcc 12.2.0, boot size (manual) // Sources + {"ATmega32U6", 66, F_AVR8, {0x1E, 0x95, 0x88}, // ID + /*ATmega32U6*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, -1, 0x0100, 0x0a00, // Mem + /*ATmega32U6*/ 3, 1, 38, vtab_at90usb646, 15, cfgtab_atmega32u6, // ISRs, Config + /*ATmega32U6*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_at90usb82, // Register file, UART + /*ATmega32U6*/ 6, ports_at90usb646, WDT_CLASSIC4}, // Ports, WDT + + //ATmega161 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"ATmega161", 89, F_AVR8, {0x1E, 0x94, 0x01}, // ID + /*ATmega161*/ 0, 0x04000, 0x080, 1, 0x0400, 0, 0x0200, 1, 0x0060, 0x0400, // Mem + /*ATmega161*/ 1, 1, 21, vtab_atmega161, 7, cfgtab_atmega161, // ISRs, Config + /*ATmega161*/ 0, NULL, 2, UART_CLASSIC_2x12, 2, uarts_atmega161, // Register file, UART + /*ATmega161*/ 5, ports_atmega161, WDT_CLASSIC3}, // Ports, WDT + + //ATmega161comp xml // Sources + {"ATmega161comp", 375, F_AVR8, {0x1E, 0x94, 0x01}, // ID + /*ATmega161comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem + /*ATmega161comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega161comp, // ISRs, Config + /*ATmega161comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*ATmega161comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATmega1281 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1281", 139, F_AVR8, {0x1E, 0x97, 0x04}, // ID + /*ATmega1281*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem + /*ATmega1281*/ 3, 1, 57, vtab_atmega1281, 14, cfgtab_atmega1280, // ISRs, Config + /*ATmega1281*/ 138, rgftab_atmega1281, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmega1281*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega2561 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega2561", 144, F_AVR8, {0x1E, 0x98, 0x02}, // ID + /*ATmega2561*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x2000, // Mem + /*ATmega2561*/ 3, 1, 57, vtab_atmega1281, 14, cfgtab_atmega2560, // ISRs, Config + /*ATmega2561*/ 139, rgftab_atmega2561, 2, UART_CLASSIC_2x12, 2, uarts_at90can32, // Register file, UART + /*ATmega2561*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega162 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega162", 90, F_AVR8, {0x1E, 0x94, 0x04}, // ID + /*ATmega162*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega162*/ 3, 1, 28, vtab_atmega162, 15, cfgtab_atmega162, // ISRs, Config + /*ATmega162*/ 79, rgftab_atmega162, 2, UART_CLASSIC_2x12, 2, uarts_atmega161, // Register file, UART + /*ATmega162*/ 5, ports_atmega161, WDT_CLASSIC3}, // Ports, WDT + + //ATmega163 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"ATmega163", 91, F_AVR8, {0x1E, 0x94, 0x02}, // ID + /*ATmega163*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 1, 0x0060, 0x0400, // Mem + /*ATmega163*/ 2, 1, 18, vtab_atmega163, 9, cfgtab_atmega163, // ISRs, Config + /*ATmega163*/ 0, NULL, 1, UART_CLASSIC_2x08, 1, uarts_at90s2313, // Register file, UART + /*ATmega163*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega323 xml, avr-gcc 12.2.0, boot size (manual) // Sources + {"ATmega323", 109, F_AVR8, {0x1E, 0x95, 0x01}, // ID + /*ATmega323*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, -1, 0x0060, 0x0800, // Mem + /*ATmega323*/ 2, 1, 21, vtab_atmega32, 12, cfgtab_atmega323, // ISRs, Config + /*ATmega323*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*ATmega323*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega164A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega164A", 92, F_AVR8, {0x1E, 0x94, 0x0F}, // ID + /*ATmega164A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega164A*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega164a, // ISRs, Config + /*ATmega164A*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega164A*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega164P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega164P", 93, F_AVR8, {0x1E, 0x94, 0x0A}, // ID + /*ATmega164P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega164P*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega164a, // ISRs, Config + /*ATmega164P*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega164P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega164PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega164PA", 94, F_AVR8, {0x1E, 0x94, 0x0A}, // ID + /*ATmega164PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega164PA*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega164a, // ISRs, Config + /*ATmega164PA*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega164PA*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega324A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega324A", 110, F_AVR8, {0x1E, 0x95, 0x15}, // ID + /*ATmega324A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega324A*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega324a, // ISRs, Config + /*ATmega324A*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega324A*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega324P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega324P", 111, F_AVR8, {0x1E, 0x95, 0x08}, // ID + /*ATmega324P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega324P*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega324a, // ISRs, Config + /*ATmega324P*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega324P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega324PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega324PA", 112, F_AVR8, {0x1E, 0x95, 0x11}, // ID + /*ATmega324PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega324PA*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega324a, // ISRs, Config + /*ATmega324PA*/ 96, rgftab_atmega164a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega324PA*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega644 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega644", 127, F_AVR8, {0x1E, 0x96, 0x09}, // ID + /*ATmega644*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega644*/ 3, 1, 28, vtab_atmega644, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644*/ 88, rgftab_atmega644, 1, UART_CLASSIC_2x12, 1, uarts_atmega16, // Register file, UART + /*ATmega644*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega644A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega644A", 128, F_AVR8, {0x1E, 0x96, 0x09}, // ID + /*ATmega644A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega644A*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644A*/ 93, rgftab_atmega644a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega644A*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega644P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega644P", 129, F_AVR8, {0x1E, 0x96, 0x0A}, // ID + /*ATmega644P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega644P*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644P*/ 93, rgftab_atmega644a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega644P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega644PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega644PA", 130, F_AVR8, {0x1E, 0x96, 0x0A}, // ID + /*ATmega644PA*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega644PA*/ 3, 1, 31, vtab_atmega164a, 14, cfgtab_atmega644, // ISRs, Config + /*ATmega644PA*/ 93, rgftab_atmega644a, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega644PA*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega1284 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1284", 140, F_AVR8, {0x1E, 0x97, 0x06}, // ID + /*ATmega1284*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, // Mem + /*ATmega1284*/ 3, 1, 35, vtab_atmega1284, 14, cfgtab_atmega1284, // ISRs, Config + /*ATmega1284*/ 104, rgftab_atmega1284, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega1284*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega1284P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1284P", 141, F_AVR8, {0x1E, 0x97, 0x05}, // ID + /*ATmega1284P*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0100, 0x4000, // Mem + /*ATmega1284P*/ 3, 1, 35, vtab_atmega1284, 14, cfgtab_atmega1284, // ISRs, Config + /*ATmega1284P*/ 104, rgftab_atmega1284, 2, UART_CLASSIC_2x12, 2, uarts_atmega164a, // Register file, UART + /*ATmega1284P*/ 4, ports_atmega164a, WDT_CLASSIC4}, // Ports, WDT + + //ATmega324PB atdf, avrdude // Sources + {"ATmega324PB", 113, F_AVR8, {0x1E, 0x95, 0x17}, // ID + /*ATmega324PB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega324PB*/ 3, 1, 51, vtab_atmega324pb, 15, cfgtab_atmega324pb, // ISRs, Config + /*ATmega324PB*/ 134, rgftab_atmega324pb, 3, UART_CLASSIC_2x12, 3, uarts_atmega324pb, // Register file, UART + /*ATmega324PB*/ 5, ports_atmega324pb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega644RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega644RFR2", 131, F_AVR8, {0x1E, 0xA6, 0x03}, // ID + /*ATmega644RFR2*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0200, 0x2000, // Mem + /*ATmega644RFR2*/ 3, 1, 77, vtab_atmega64rfr2, 14, cfgtab_atmega64rfr2, // ISRs, Config + /*ATmega644RFR2*/ 269, rgftab_atmega64rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega644RFR2*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega1284RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1284RFR2", 142, F_AVR8, {0x1E, 0xA7, 0x03}, // ID + /*ATmega1284RFR2*/ 0, 0x20000, 0x100, 4, 0x0400, 0, 0x1000, 8, 0x0200, 0x4000, // Mem + /*ATmega1284RFR2*/ 3, 1, 77, vtab_atmega64rfr2, 14, cfgtab_atmega128rfr2, // ISRs, Config + /*ATmega1284RFR2*/ 270, rgftab_atmega128rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega1284RFR2*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega2564RFR2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega2564RFR2", 145, F_AVR8, {0x1E, 0xA8, 0x03}, // ID + /*ATmega2564RFR2*/ 0, 0x40000, 0x100, 4, 0x0400, 0, 0x2000, 8, 0x0200, 0x8000, // Mem + /*ATmega2564RFR2*/ 3, 1, 77, vtab_atmega64rfr2, 14, cfgtab_atmega256rfr2, // ISRs, Config + /*ATmega2564RFR2*/ 271, rgftab_atmega2564rfr2, 2, UART_CLASSIC_2x12, 2, uarts_atmega128rfa1, // Register file, UART + /*ATmega2564RFR2*/ 7, ports_atmega128rfa1, WDT_CLASSIC4}, // Ports, WDT + + //ATmega165 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"ATmega165", 95, F_AVR8, {0x1E, 0x94, 0x07}, // ID + /*ATmega165*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega165*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega165*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega165*/ 7, ports_at90can32, WDT_CLASSIC3}, // Ports, WDT + + //ATmega165A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega165A", 96, F_AVR8, {0x1E, 0x94, 0x10}, // ID + /*ATmega165A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega165A*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega165a, // ISRs, Config + /*ATmega165A*/ 86, rgftab_atmega165a, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega165A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega165P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega165P", 97, F_AVR8, {0x1E, 0x94, 0x07}, // ID + /*ATmega165P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega165P*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega165a, // ISRs, Config + /*ATmega165P*/ 86, rgftab_atmega165a, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega165P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega165PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega165PA", 98, F_AVR8, {0x1E, 0x94, 0x07}, // ID + /*ATmega165PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega165PA*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega165a, // ISRs, Config + /*ATmega165PA*/ 86, rgftab_atmega165a, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega165PA*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega325 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega325", 114, F_AVR8, {0x1E, 0x95, 0x05}, // ID + /*ATmega325*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega325*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega325*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega325A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega325A", 115, F_AVR8, {0x1E, 0x95, 0x05}, // ID + /*ATmega325A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega325A*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325A*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega325A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega325P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega325P", 116, F_AVR8, {0x1E, 0x95, 0x0D}, // ID + /*ATmega325P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega325P*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325P*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega325P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega325PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega325PA", 117, F_AVR8, {0x1E, 0x95, 0x0D}, // ID + /*ATmega325PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega325PA*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega325PA*/ 86, rgftab_atmega325, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega325PA*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega645 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega645", 132, F_AVR8, {0x1E, 0x96, 0x05}, // ID + /*ATmega645*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega645*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega645*/ 86, rgftab_atmega645, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega645*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega645A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega645A", 133, F_AVR8, {0x1E, 0x96, 0x05}, // ID + /*ATmega645A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega645A*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega645A*/ 86, rgftab_atmega645, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega645A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega645P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega645P", 134, F_AVR8, {0x1E, 0x96, 0x0D}, // ID + /*ATmega645P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega645P*/ 3, 1, 22, vtab_atmega165, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega645P*/ 86, rgftab_atmega645, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega645P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3250 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3250", 146, F_AVR8, {0x1E, 0x95, 0x06}, // ID + /*ATmega3250*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3250*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3250*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3250A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3250A", 147, F_AVR8, {0x1E, 0x95, 0x06}, // ID + /*ATmega3250A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3250A*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250A*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3250A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3250P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3250P", 148, F_AVR8, {0x1E, 0x95, 0x0E}, // ID + /*ATmega3250P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3250P*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250P*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3250P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3250PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3250PA", 149, F_AVR8, {0x1E, 0x95, 0x0E}, // ID + /*ATmega3250PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3250PA*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3250PA*/ 94, rgftab_atmega3250, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3250PA*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega6450 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega6450", 154, F_AVR8, {0x1E, 0x96, 0x06}, // ID + /*ATmega6450*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega6450*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6450*/ 94, rgftab_atmega6450, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega6450*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega6450A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega6450A", 155, F_AVR8, {0x1E, 0x96, 0x06}, // ID + /*ATmega6450A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega6450A*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6450A*/ 94, rgftab_atmega6450, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega6450A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega6450P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega6450P", 156, F_AVR8, {0x1E, 0x96, 0x0E}, // ID + /*ATmega6450P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega6450P*/ 3, 1, 25, vtab_atmega3250, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6450P*/ 94, rgftab_atmega6450, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega6450P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega8515 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega8515", 160, F_AVR8, {0x1E, 0x93, 0x06}, // ID + /*ATmega8515*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATmega8515*/ 2, 1, 17, vtab_atmega8515, 13, cfgtab_atmega8515, // ISRs, Config + /*ATmega8515*/ 52, rgftab_atmega8515, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*ATmega8515*/ 5, ports_atmega161, WDT_CLASSIC3}, // Ports, WDT + + //ATmega8535 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega8535", 161, F_AVR8, {0x1E, 0x93, 0x08}, // ID + /*ATmega8535*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0060, 0x0200, // Mem + /*ATmega8535*/ 2, 1, 21, vtab_atmega8535, 13, cfgtab_atmega8535, // ISRs, Config + /*ATmega8535*/ 67, rgftab_atmega8535, 1, UART_CLASSIC_2x12, 1, uarts_at90s2313, // Register file, UART + /*ATmega8535*/ 4, ports_at90s4414, WDT_CLASSIC3}, // Ports, WDT + + //ATmega48 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega48", 67, F_AVR8, {0x1E, 0x92, 0x05}, // ID + /*ATmega48*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega48*/ 3, 1, 26, vtab_atmega48, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48*/ 81, rgftab_atmega48, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega48*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega48A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega48A", 68, F_AVR8, {0x1E, 0x92, 0x05}, // ID + /*ATmega48A*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega48A*/ 3, 1, 26, vtab_atmega48, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48A*/ 82, rgftab_atmega48a, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega48A*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega48P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega48P", 69, F_AVR8, {0x1E, 0x92, 0x0A}, // ID + /*ATmega48P*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega48P*/ 3, 1, 26, vtab_atmega48, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48P*/ 81, rgftab_atmega48, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega48P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega48PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega48PA", 70, F_AVR8, {0x1E, 0x92, 0x0A}, // ID + /*ATmega48PA*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega48PA*/ 3, 1, 26, vtab_atmega48, 11, cfgtab_atmega48, // ISRs, Config + /*ATmega48PA*/ 82, rgftab_atmega48a, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega48PA*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega88 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega88", 79, F_AVR8, {0x1E, 0x93, 0x0A}, // ID + /*ATmega88*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega88*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega88*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega88A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega88A", 80, F_AVR8, {0x1E, 0x93, 0x0A}, // ID + /*ATmega88A*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega88A*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88A*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega88A*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega88P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega88P", 81, F_AVR8, {0x1E, 0x93, 0x0F}, // ID + /*ATmega88P*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega88P*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega88P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega88PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega88PA", 82, F_AVR8, {0x1E, 0x93, 0x0F}, // ID + /*ATmega88PA*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega88PA*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega88, // ISRs, Config + /*ATmega88PA*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega88PA*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega168 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega168", 99, F_AVR8, {0x1E, 0x94, 0x06}, // ID + /*ATmega168*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega168*/ 3, 1, 26, vtab_atmega168, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega168*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega168A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega168A", 100, F_AVR8, {0x1E, 0x94, 0x06}, // ID + /*ATmega168A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega168A*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168A*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega168A*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega168P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega168P", 101, F_AVR8, {0x1E, 0x94, 0x0B}, // ID + /*ATmega168P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega168P*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega168P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega168PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega168PA", 102, F_AVR8, {0x1E, 0x94, 0x0B}, // ID + /*ATmega168PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega168PA*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega168, // ISRs, Config + /*ATmega168PA*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega168PA*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega328 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega328", 118, F_AVR8, {0x1E, 0x95, 0x14}, // ID + /*ATmega328*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega328*/ 3, 1, 26, vtab_atmega168, 14, cfgtab_atmega328, // ISRs, Config + /*ATmega328*/ 81, rgftab_atmega328, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega328*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega328P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega328P", 119, F_AVR8, {0x1E, 0x95, 0x0F}, // ID + /*ATmega328P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega328P*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega328, // ISRs, Config + /*ATmega328P*/ 81, rgftab_atmega328, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega328P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega48PB atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega48PB", 71, F_AVR8, {0x1E, 0x92, 0x10}, // ID + /*ATmega48PB*/ 0, 0x01000, 0x040, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega48PB*/ 3, 1, 27, vtab_atmega48pb, 11, cfgtab_atmega48pb, // ISRs, Config + /*ATmega48PB*/ 95, rgftab_atmega48pb, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega48PB*/ 4, ports_atmega48pb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega88PB atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega88PB", 83, F_AVR8, {0x1E, 0x93, 0x16}, // ID + /*ATmega88PB*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega88PB*/ 3, 1, 27, vtab_atmega48pb, 14, cfgtab_atmega88pb, // ISRs, Config + /*ATmega88PB*/ 95, rgftab_atmega88pb, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega88PB*/ 4, ports_atmega48pb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega168PB atdf, avr-gcc 7.3.0, avrdude // Sources + {"ATmega168PB", 103, F_AVR8, {0x1E, 0x94, 0x15}, // ID + /*ATmega168PB*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega168PB*/ 3, 1, 27, vtab_atmega48pb, 14, cfgtab_atmega168pb, // ISRs, Config + /*ATmega168PB*/ 95, rgftab_atmega88pb, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATmega168PB*/ 4, ports_atmega48pb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega328PB atdf, avr-gcc 7.3.0, avrdude // Sources + {"ATmega328PB", 120, F_AVR8, {0x1E, 0x95, 0x16}, // ID + /*ATmega328PB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega328PB*/ 3, 1, 45, vtab_atmega328pb, 15, cfgtab_atmega328pb, // ISRs, Config + /*ATmega328PB*/ 125, rgftab_atmega328pb, 2, UART_CLASSIC_2x12, 2, uarts_atmega328pb, // Register file, UART + /*ATmega328PB*/ 4, ports_atmega48pb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega169 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"ATmega169", 104, F_AVR8, {0x1E, 0x94, 0x05}, // ID + /*ATmega169*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega169*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega165, // ISRs, Config + /*ATmega169*/ 0, NULL, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega169*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega169A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega169A", 105, F_AVR8, {0x1E, 0x94, 0x11}, // ID + /*ATmega169A*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega169A*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega165a, // ISRs, Config + /*ATmega169A*/ 106, rgftab_atmega169a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega169A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega169P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega169P", 106, F_AVR8, {0x1E, 0x94, 0x05}, // ID + /*ATmega169P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega169P*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega165a, // ISRs, Config + /*ATmega169P*/ 106, rgftab_atmega169a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega169P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega169PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega169PA", 107, F_AVR8, {0x1E, 0x94, 0x05}, // ID + /*ATmega169PA*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega169PA*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega165a, // ISRs, Config + /*ATmega169PA*/ 106, rgftab_atmega169a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega169PA*/ 7, ports_atmega128rfa1, WDT_CLASSIC3}, // Ports, WDT + + //ATmega329 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega329", 121, F_AVR8, {0x1E, 0x95, 0x03}, // ID + /*ATmega329*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega329*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329*/ 106, rgftab_atmega329, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega329*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega329A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega329A", 122, F_AVR8, {0x1E, 0x95, 0x03}, // ID + /*ATmega329A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega329A*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329A*/ 106, rgftab_atmega329a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega329A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega329P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega329P", 123, F_AVR8, {0x1E, 0x95, 0x0B}, // ID + /*ATmega329P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega329P*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329P*/ 106, rgftab_atmega329p, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega329P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega329PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega329PA", 124, F_AVR8, {0x1E, 0x95, 0x0B}, // ID + /*ATmega329PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega329PA*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega329PA*/ 106, rgftab_atmega329a, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega329PA*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega649 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega649", 135, F_AVR8, {0x1E, 0x96, 0x03}, // ID + /*ATmega649*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega649*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega649*/ 106, rgftab_atmega649, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega649*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega649A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega649A", 136, F_AVR8, {0x1E, 0x96, 0x03}, // ID + /*ATmega649A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega649A*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega649A*/ 106, rgftab_atmega649, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega649A*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega649P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega649P", 137, F_AVR8, {0x1E, 0x96, 0x0B}, // ID + /*ATmega649P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega649P*/ 3, 1, 23, vtab_atmega169, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega649P*/ 106, rgftab_atmega649, 1, UART_CLASSIC_2x12, 1, uarts_atmega169a, // Register file, UART + /*ATmega649P*/ 7, ports_atmega165a, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3290 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3290", 150, F_AVR8, {0x1E, 0x95, 0x04}, // ID + /*ATmega3290*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3290*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290*/ 118, rgftab_atmega3290, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3290*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3290A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3290A", 151, F_AVR8, {0x1E, 0x95, 0x04}, // ID + /*ATmega3290A*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3290A*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290A*/ 118, rgftab_atmega3290, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3290A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3290P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3290P", 152, F_AVR8, {0x1E, 0x95, 0x0C}, // ID + /*ATmega3290P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3290P*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290P*/ 118, rgftab_atmega3290p, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3290P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega3290PA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3290PA", 153, F_AVR8, {0x1E, 0x95, 0x0C}, // ID + /*ATmega3290PA*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega3290PA*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega325, // ISRs, Config + /*ATmega3290PA*/ 118, rgftab_atmega3290pa, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega3290PA*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega6490 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega6490", 157, F_AVR8, {0x1E, 0x96, 0x04}, // ID + /*ATmega6490*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega6490*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6490*/ 118, rgftab_atmega6490, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega6490*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega6490A atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega6490A", 158, F_AVR8, {0x1E, 0x96, 0x04}, // ID + /*ATmega6490A*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega6490A*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6490A*/ 118, rgftab_atmega6490, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega6490A*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //ATmega6490P atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega6490P", 159, F_AVR8, {0x1E, 0x96, 0x0C}, // ID + /*ATmega6490P*/ 0, 0x10000, 0x100, 4, 0x0400, 0, 0x0800, 8, 0x0100, 0x1000, // Mem + /*ATmega6490P*/ 3, 1, 25, vtab_atmega3290, 15, cfgtab_atmega645, // ISRs, Config + /*ATmega6490P*/ 118, rgftab_atmega6490, 1, UART_CLASSIC_2x12, 1, uarts_atmega165, // Register file, UART + /*ATmega6490P*/ 9, ports_atmega3250, WDT_CLASSIC3}, // Ports, WDT + + //LGT8F88P avrdude, from ATmega88 // Sources + {"LGT8F88P", 227, F_AVR8, {0x1E, 0x93, 0x0F}, // ID + /*LGT8F88P*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*LGT8F88P*/ -1, -1, 26, vtab_atmega48, 0, NULL, // ISRs, Config + /*LGT8F88P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*LGT8F88P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //LGT8F168P avrdude, from ATmega168P // Sources + {"LGT8F168P", 228, F_AVR8, {0x1E, 0x94, 0x0B}, // ID + /*LGT8F168P*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*LGT8F168P*/ -1, -1, 26, vtab_atmega48, 0, NULL, // ISRs, Config + /*LGT8F168P*/ 81, rgftab_atmega88, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*LGT8F168P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //LGT8F328P avrdude, from ATmega328P // Sources + {"LGT8F328P", 229, F_AVR8, {0x1E, 0x95, 0x0F}, // ID + /*LGT8F328P*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*LGT8F328P*/ -1, -1, 26, vtab_atmega48, 0, NULL, // ISRs, Config + /*LGT8F328P*/ 81, rgftab_atmega328, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*LGT8F328P*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATmega103 xml, avr-gcc 12.2.0, avrdude, boot size (manual) // Sources + {"ATmega103", 84, F_AVR8, {0x1E, 0x97, 0x01}, // ID + /*ATmega103*/ 0, 0x20000, 0x100, 0, 0, 0, 0x1000, 1, 0x0060, 0x0fa0, // Mem + /*ATmega103*/ 1, 1, 24, vtab_atmega103, 4, cfgtab_atmega103, // ISRs, Config + /*ATmega103*/ 0, NULL, 1, UART_CLASSIC_1x08, 1, uarts_atmega165, // Register file, UART + /*ATmega103*/ 6, ports_atmega103, WDT_CLASSIC3}, // Ports, WDT + + //ATmega103comp xml // Sources + {"ATmega103comp", 374, F_AVR8, {0x1E, 0x97, 0x01}, // ID + /*ATmega103comp*/ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, // Mem + /*ATmega103comp*/ -1, -1, 0, NULL, 15, cfgtab_atmega103comp, // ISRs, Config + /*ATmega103comp*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*ATmega103comp*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATmega8HVA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega8HVA", 47, F_AVR8, {0x1E, 0x93, 0x10}, // ID + /*ATmega8HVA*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega8HVA*/ 1, 1, 21, vtab_atmega8hva, 7, cfgtab_atmega8hva, // ISRs, Config + /*ATmega8HVA*/ 74, rgftab_atmega8hva, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega8HVA*/ 3, ports_atmega8hva, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16HVA atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16HVA", 51, F_AVR8, {0x1E, 0x94, 0x0C}, // ID + /*ATmega16HVA*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0100, 4, 0x0100, 0x0200, // Mem + /*ATmega16HVA*/ 1, 1, 21, vtab_atmega8hva, 7, cfgtab_atmega8hva, // ISRs, Config + /*ATmega16HVA*/ 74, rgftab_atmega8hva, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega16HVA*/ 3, ports_atmega8hva, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16HVA2 xml, avr-gcc 12.2.0 // Sources + {"ATmega16HVA2", 55, F_AVR8, {0x1E, 0x94, 0x0E}, // ID + /*ATmega16HVA2*/ 0, 0x04000, 0x080, -1, -1, 0, 0x0100, -1, 0x0100, 0x0400, // Mem + /*ATmega16HVA2*/ 2, 1, 22, vtab_atmega16hva2, 9, cfgtab_atmega16hva2, // ISRs, Config + /*ATmega16HVA2*/ 0, NULL, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega16HVA2*/ 3, ports_atmega8hva, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16HVB atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16HVB", 52, F_AVR8, {0x1E, 0x94, 0x0D}, // ID + /*ATmega16HVB*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega16HVB*/ 2, 1, 29, vtab_atmega16hvb, 12, cfgtab_atmega16hvb, // ISRs, Config + /*ATmega16HVB*/ 91, rgftab_atmega16hvb, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega16HVB*/ 3, ports_atmega16hvb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega16HVBrevB atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega16HVBrevB", 53, F_AVR8, {0x1E, 0x94, 0x0D}, // ID + /*ATmega16HVBrevB*/ 0, 0x04000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATmega16HVBrevB*/ 2, 1, 29, vtab_atmega16hvb, 12, cfgtab_atmega16hvbrevb, // ISRs, Config + /*ATmega16HVBrevB*/ 91, rgftab_atmega16hvb, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega16HVBrevB*/ 3, ports_atmega16hvb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32HVB atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32HVB", 60, F_AVR8, {0x1E, 0x95, 0x10}, // ID + /*ATmega32HVB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega32HVB*/ 2, 1, 29, vtab_atmega16hvb, 12, cfgtab_atmega32hvb, // ISRs, Config + /*ATmega32HVB*/ 91, rgftab_atmega16hvb, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega32HVB*/ 3, ports_atmega16hvb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32HVBrevB atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega32HVBrevB", 61, F_AVR8, {0x1E, 0x95, 0x10}, // ID + /*ATmega32HVBrevB*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATmega32HVBrevB*/ 2, 1, 29, vtab_atmega16hvb, 12, cfgtab_atmega32hvbrevb, // ISRs, Config + /*ATmega32HVBrevB*/ 91, rgftab_atmega16hvb, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega32HVBrevB*/ 3, ports_atmega16hvb, WDT_CLASSIC4}, // Ports, WDT + + //ATmega64HVE xml, avr-gcc 12.2.0, boot size (manual) // Sources + {"ATmega64HVE", 74, F_AVR8, {0x1E, 0x96, 0x10}, // ID + /*ATmega64HVE*/ 0, 0x10000, 0x080, 4, 0x0400, 0, 0x0400, -1, 0x0100, 0x1000, // Mem + /*ATmega64HVE*/ 2, 1, 25, vtab_atmega64hve, 13, cfgtab_atmega64hve, // ISRs, Config + /*ATmega64HVE*/ 0, NULL, 1, UART_LIN, 1, uarts_atmega64hve, // Register file, UART + /*ATmega64HVE*/ 2, ports_atmega64hve, WDT_CLASSIC4}, // Ports, WDT + + //ATmega32HVE2 avrdude, boot size (manual) // Sources + {"ATmega32HVE2", 379, F_AVR8, {0x1E, 0x95, 0x13}, // ID + /*ATmega32HVE2*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, -1, -1, // Mem + /*ATmega32HVE2*/ 2, 1, 25, vtab_atmega64hve, 13, cfgtab_atmega32hve2, // ISRs, Config + /*ATmega32HVE2*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*ATmega32HVE2*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATmega64HVE2 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega64HVE2", 77, F_AVR8, {0x1E, 0x96, 0x10}, // ID + /*ATmega64HVE2*/ 0, 0x10000, 0x080, 4, 0x0400, 0, 0x0400, 4, 0x0100, 0x1000, // Mem + /*ATmega64HVE2*/ 2, 1, 25, vtab_atmega64hve, 13, cfgtab_atmega32hve2, // ISRs, Config + /*ATmega64HVE2*/ 89, rgftab_atmega64hve2, 1, UART_LIN, 1, uarts_atmega64hve, // Register file, UART + /*ATmega64HVE2*/ 2, ports_atmega64hve, WDT_CLASSIC4}, // Ports, WDT + + //ATmega406 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega406", 125, F_AVR8, {0x1E, 0x95, 0x07}, // ID + /*ATmega406*/ 0, 0x0a000, 0x080, 4, 0x0200, 0, 0x0200, 4, 0x0100, 0x0800, // Mem + /*ATmega406*/ 2, 1, 23, vtab_atmega406, 10, cfgtab_atmega406, // ISRs, Config + /*ATmega406*/ 79, rgftab_atmega406, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATmega406*/ 4, ports_atmega406, WDT_CLASSIC4}, // Ports, WDT + + //ATA5272 atdf, avr-gcc 12.2.0 // Sources + {"ATA5272", 197, F_AVR8, {0x1E, 0x93, 0x87}, // ID + /*ATA5272*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATA5272*/ 3, 1, 37, vtab_ata5272, 11, cfgtab_attiny87, // ISRs, Config + /*ATA5272*/ 80, rgftab_ata5272, 1, UART_LIN, -1, NULL, // Register file, UART + /*ATA5272*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATA5505 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA5505", 198, F_AVR8, {0x1E, 0x94, 0x87}, // ID + /*ATA5505*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATA5505*/ 3, 1, 20, vtab_attiny87, 11, cfgtab_attiny87, // ISRs, Config + /*ATA5505*/ 80, rgftab_ata5272, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART + /*ATA5505*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATA5700M322 atdf // Sources + {"ATA5700M322", 199, F_AVR8, {0x1E, 0x95, 0x67}, // ID + /*ATA5700M322*/ 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, // Mem + /*ATA5700M322*/ 1, 1, 51, vtab_ata5700m322, 9, cfgtab_ata5700m322, // ISRs, Config + /*ATA5700M322*/ 337, rgftab_ata5700m322, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5700M322*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA5702M322 atdf, avr-gcc 12.2.0 // Sources + {"ATA5702M322", 200, F_AVR8, {0x1E, 0x95, 0x69}, // ID + /*ATA5702M322*/ 0x08000, 0x08000, 0x040, 0, 0, 0, 0x0880, 16, 0x0200, 0x0400, // Mem + /*ATA5702M322*/ 1, 1, 51, vtab_ata5700m322, 9, cfgtab_ata5700m322, // ISRs, Config + /*ATA5702M322*/ 378, rgftab_ata5702m322, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5702M322*/ 3, ports_ata5702m322, WDT_UNKNOWN}, // Ports, WDT + + //ATA5781 atdf // Sources + {"ATA5781", 201, F_AVR8, {0x1E, 0x95, 0x64}, // ID + /*ATA5781*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA5781*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5781*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5781*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA5782 atdf, avr-gcc 12.2.0 // Sources + {"ATA5782", 202, F_AVR8, {0x1E, 0x95, 0x65}, // ID + /*ATA5782*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA5782*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5782*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5782*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT + + //ATA5783 atdf // Sources + {"ATA5783", 203, F_AVR8, {0x1E, 0x95, 0x66}, // ID + /*ATA5783*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA5783*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5783*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5783*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA5787 atdf // Sources + {"ATA5787", 204, F_AVR8, {0x1E, 0x94, 0x6C}, // ID + /*ATA5787*/ 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, // Mem + /*ATA5787*/ 1, 1, 44, vtab_ata5787, 11, cfgtab_ata5787, // ISRs, Config + /*ATA5787*/ 292, rgftab_ata5787, 1, UART_LIN, -1, NULL, // Register file, UART + /*ATA5787*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA5790 atdf, avr-gcc 12.2.0 // Sources + {"ATA5790", 205, F_AVR8, {0x1E, 0x94, 0x61}, // ID + /*ATA5790*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem + /*ATA5790*/ 1, 1, 30, vtab_ata5790, 11, cfgtab_ata5790, // ISRs, Config + /*ATA5790*/ 112, rgftab_ata5790, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5790*/ 3, ports_ata5790, WDT_UNKNOWN}, // Ports, WDT + + //ATA5790N atdf, avr-gcc 12.2.0 // Sources + {"ATA5790N", 206, F_AVR8, {0x1E, 0x94, 0x62}, // ID + /*ATA5790N*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem + /*ATA5790N*/ 1, 1, 31, vtab_ata5790n, 10, cfgtab_ata5790n, // ISRs, Config + /*ATA5790N*/ 117, rgftab_ata5790n, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5790N*/ 3, ports_ata5790, WDT_UNKNOWN}, // Ports, WDT + + //ATA5791 atdf, avr-gcc 7.3.0 // Sources + {"ATA5791", 207, F_AVR8, {0x1E, 0x94, 0x62}, // ID + /*ATA5791*/ 0, 0x04000, 0x080, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem + /*ATA5791*/ 1, 1, 31, vtab_ata5790n, 11, cfgtab_ata5790, // ISRs, Config + /*ATA5791*/ 117, rgftab_ata5790n, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5791*/ 3, ports_ata5790, WDT_UNKNOWN}, // Ports, WDT + + //ATA5795 atdf, avr-gcc 12.2.0 // Sources + {"ATA5795", 208, F_AVR8, {0x1E, 0x93, 0x61}, // ID + /*ATA5795*/ 0, 0x02000, 0x040, 1, 0x0800, 0, 0x0800, 16, 0x0100, 0x0200, // Mem + /*ATA5795*/ 1, 1, 23, vtab_ata5795, 10, cfgtab_ata5790n, // ISRs, Config + /*ATA5795*/ 84, rgftab_ata5795, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5795*/ 3, ports_ata5795, WDT_UNKNOWN}, // Ports, WDT + + //ATA5831 atdf, avr-gcc 12.2.0 // Sources + {"ATA5831", 209, F_AVR8, {0x1E, 0x95, 0x61}, // ID + /*ATA5831*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA5831*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5831*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5831*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT + + //ATA5832 atdf // Sources + {"ATA5832", 210, F_AVR8, {0x1E, 0x95, 0x62}, // ID + /*ATA5832*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA5832*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5832*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5832*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA5833 atdf // Sources + {"ATA5833", 211, F_AVR8, {0x1E, 0x95, 0x63}, // ID + /*ATA5833*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA5833*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata5781, // ISRs, Config + /*ATA5833*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA5833*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA5835 atdf // Sources + {"ATA5835", 212, F_AVR8, {0x1E, 0x94, 0x6B}, // ID + /*ATA5835*/ 0x08000, 0x05200, 0x040, 0, 0, 0, 0x0400, 16, 0x0200, 0x0800, // Mem + /*ATA5835*/ 1, 1, 44, vtab_ata5787, 11, cfgtab_ata5835, // ISRs, Config + /*ATA5835*/ 307, rgftab_ata5835, 1, UART_LIN, -1, NULL, // Register file, UART + /*ATA5835*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA6285 atdf, avr-gcc 12.2.0 // Sources + {"ATA6285", 213, F_AVR8, {0x1E, 0x93, 0x82}, // ID + /*ATA6285*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, // Mem + /*ATA6285*/ 2, 1, 27, vtab_ata6285, 17, cfgtab_ata6285, // ISRs, Config + /*ATA6285*/ 79, rgftab_ata6285, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA6285*/ 3, ports_ata5702m322, WDT_UNKNOWN}, // Ports, WDT + + //ATA6286 atdf, avr-gcc 12.2.0 // Sources + {"ATA6286", 214, F_AVR8, {0x1E, 0x93, 0x82}, // ID + /*ATA6286*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0140, 4, 0x0100, 0x0200, // Mem + /*ATA6286*/ 2, 1, 27, vtab_ata6285, 17, cfgtab_ata6285, // ISRs, Config + /*ATA6286*/ 79, rgftab_ata6285, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA6286*/ 3, ports_ata5702m322, WDT_UNKNOWN}, // Ports, WDT + + //ATA6289 xml, avr-gcc 12.2.0, boot size (manual) // Sources + {"ATA6289", 215, F_AVR8, {0x1E, 0x93, 0x82}, // ID + /*ATA6289*/ 0, 0x02000, 0x040, 4, 0x0100, 0x00040, 0x0100, -1, 0x0100, 0x0200, // Mem + /*ATA6289*/ 2, 1, 27, vtab_ata6285, 17, cfgtab_ata6289, // ISRs, Config + /*ATA6289*/ 0, NULL, 0, UART_UNKNOWN, -1, NULL, // Register file, UART + /*ATA6289*/ 3, ports_ata6289, WDT_UNKNOWN}, // Ports, WDT + + //ATA6612C atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA6612C", 216, F_AVR8, {0x1E, 0x93, 0x0A}, // ID + /*ATA6612C*/ 0, 0x02000, 0x040, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATA6612C*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega88, // ISRs, Config + /*ATA6612C*/ 81, rgftab_ata6612c, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATA6612C*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATA6613C atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA6613C", 217, F_AVR8, {0x1E, 0x94, 0x06}, // ID + /*ATA6613C*/ 0, 0x04000, 0x080, 4, 0x0100, 0, 0x0200, 4, 0x0100, 0x0400, // Mem + /*ATA6613C*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega168, // ISRs, Config + /*ATA6613C*/ 81, rgftab_ata6612c, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATA6613C*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATA6614Q atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA6614Q", 218, F_AVR8, {0x1E, 0x95, 0x0F}, // ID + /*ATA6614Q*/ 0, 0x08000, 0x080, 4, 0x0200, 0, 0x0400, 4, 0x0100, 0x0800, // Mem + /*ATA6614Q*/ 3, 1, 26, vtab_atmega48, 14, cfgtab_atmega328, // ISRs, Config + /*ATA6614Q*/ 81, rgftab_ata6614q, 1, UART_CLASSIC_2x12, 1, uarts_atmega8, // Register file, UART + /*ATA6614Q*/ 3, ports_atmega48, WDT_CLASSIC4}, // Ports, WDT + + //ATA6616C atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA6616C", 219, F_AVR8, {0x1E, 0x93, 0x87}, // ID + /*ATA6616C*/ 0, 0x02000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATA6616C*/ 3, 1, 20, vtab_attiny87, 11, cfgtab_attiny87, // ISRs, Config + /*ATA6616C*/ 81, rgftab_ata6616c, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART + /*ATA6616C*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATA6617C atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA6617C", 220, F_AVR8, {0x1E, 0x94, 0x87}, // ID + /*ATA6617C*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATA6617C*/ 3, 1, 20, vtab_attiny87, 11, cfgtab_attiny87, // ISRs, Config + /*ATA6617C*/ 81, rgftab_ata6616c, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART + /*ATA6617C*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATA664251 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATA664251", 225, F_AVR8, {0x1E, 0x94, 0x87}, // ID + /*ATA664251*/ 0, 0x04000, 0x080, 0, 0, 0, 0x0200, 4, 0x0100, 0x0200, // Mem + /*ATA664251*/ 3, 1, 20, vtab_attiny87, 11, cfgtab_attiny87, // ISRs, Config + /*ATA664251*/ 81, rgftab_ata6616c, 1, UART_LIN, 1, uarts_attiny87, // Register file, UART + /*ATA664251*/ 2, ports_attiny87, WDT_CLASSIC4}, // Ports, WDT + + //ATA8210 atdf, avr-gcc 7.3.0 // Sources + {"ATA8210", 221, F_AVR8, {0x1E, 0x95, 0x65}, // ID + /*ATA8210*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA8210*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata8210, // ISRs, Config + /*ATA8210*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA8210*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT + + //ATA8215 atdf // Sources + {"ATA8215", 222, F_AVR8, {0x1E, 0x95, 0x64}, // ID + /*ATA8215*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA8215*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata8210, // ISRs, Config + /*ATA8215*/ 262, rgftab_ata5781, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA8215*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATA8510 atdf, avr-gcc 7.3.0 // Sources + {"ATA8510", 223, F_AVR8, {0x1E, 0x95, 0x61}, // ID + /*ATA8510*/ 0x08000, 0x05000, 0x040, 1, 0x5000, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA8510*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata8210, // ISRs, Config + /*ATA8510*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA8510*/ 2, ports_ata5782, WDT_UNKNOWN}, // Ports, WDT + + //ATA8515 atdf // Sources + {"ATA8515", 224, F_AVR8, {0x1E, 0x95, 0x63}, // ID + /*ATA8515*/ -1, -1, -1, 0, 0, 0, 0x0400, 16, 0x0200, 0x0400, // Mem + /*ATA8515*/ 1, 1, 42, vtab_ata5781, 11, cfgtab_ata8210, // ISRs, Config + /*ATA8515*/ 279, rgftab_ata5831, 0, UART_NONE, -1, NULL, // Register file, UART + /*ATA8515*/ 0, NULL, WDT_UNKNOWN}, // Ports, WDT + + + //ATxmega64A1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64A1", 243, F_XMEGA, {0x1E, 0x96, 0x4E}, // ID + /*ATxmega64A1*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64A1*/ 6, 1, 125, vtab_atxmega64a1, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega64A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART + /*ATxmega64A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128A1", 254, F_XMEGA, {0x1E, 0x97, 0x4C}, // ID + /*ATxmega128A1*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A1*/ 6, 1, 125, vtab_atxmega64a1, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega128A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART + /*ATxmega128A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A1revD avrdude, from ATxmega128A1 // Sources + {"ATxmega128A1revD", 255, F_XMEGA, {0x1E, 0x97, 0x41}, // ID + /*ATxmega128A1revD*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A1revD*/ 6, 1, 125, vtab_atxmega64a1, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega128A1revD*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART + /*ATxmega128A1revD*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega192A1 avrdude, from ATxmega128A1 // Sources + {"ATxmega192A1", 266, F_XMEGA, {0x1E, 0x97, 0x4E}, // ID + /*ATxmega192A1*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem + /*ATxmega192A1*/ 6, 1, 0, NULL, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega192A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART + /*ATxmega192A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega256A1 avrdude, from ATxmega128A1 // Sources + {"ATxmega256A1", 271, F_XMEGA, {0x1E, 0x98, 0x46}, // ID + /*ATxmega256A1*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256A1*/ 6, 1, 0, NULL, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega256A1*/ 814, rgftab_atxmega64a1, 8, UART_XMEGA, 8, uarts_atxmega64a1, // Register file, UART + /*ATxmega256A1*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega64A1U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64A1U", 244, F_XMEGA, {0x1E, 0x96, 0x4E}, // ID + /*ATxmega64A1U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64A1U*/ 6, 1, 127, vtab_atxmega64a1u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega64A1U*/ 943, rgftab_atxmega64a1u, 8, UART_XMEGA, 9, uarts_atxmega64a1u, // Register file, UART + /*ATxmega64A1U*/ 11, ports_atxmega64a1u, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A1U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128A1U", 256, F_XMEGA, {0x1E, 0x97, 0x4C}, // ID + /*ATxmega128A1U*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A1U*/ 6, 1, 127, vtab_atxmega64a1u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega128A1U*/ 943, rgftab_atxmega64a1u, 8, UART_XMEGA, 9, uarts_atxmega64a1u, // Register file, UART + /*ATxmega128A1U*/ 11, ports_atxmega64a1u, WDT_XMEGA}, // Ports, WDT + + //ATxmega64A3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64A3", 246, F_XMEGA, {0x1E, 0x96, 0x42}, // ID + /*ATxmega64A3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64A3*/ 6, 1, 122, vtab_atxmega64a3, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega64A3*/ 680, rgftab_atxmega64a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART + /*ATxmega64A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128A3", 258, F_XMEGA, {0x1E, 0x97, 0x42}, // ID + /*ATxmega128A3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A3*/ 6, 1, 122, vtab_atxmega64a3, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega128A3*/ 680, rgftab_atxmega64a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART + /*ATxmega128A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega192A3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega192A3", 267, F_XMEGA, {0x1E, 0x97, 0x44}, // ID + /*ATxmega192A3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem + /*ATxmega192A3*/ 6, 1, 122, vtab_atxmega64a3, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega192A3*/ 680, rgftab_atxmega64a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART + /*ATxmega192A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega256A3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega256A3", 272, F_XMEGA, {0x1E, 0x98, 0x42}, // ID + /*ATxmega256A3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256A3*/ 6, 1, 122, vtab_atxmega64a3, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega256A3*/ 680, rgftab_atxmega64a3, 7, UART_XMEGA, 7, uarts_atxmega64a3, // Register file, UART + /*ATxmega256A3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega256A3B atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega256A3B", 273, F_XMEGA, {0x1E, 0x98, 0x43}, // ID + /*ATxmega256A3B*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256A3B*/ 6, 1, 122, vtab_atxmega256a3b, 16, cfgtab_atxmega64a1, // ISRs, Config + /*ATxmega256A3B*/ 665, rgftab_atxmega256a3b, 6, UART_XMEGA, 6, uarts_atxmega256a3b, // Register file, UART + /*ATxmega256A3B*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega64A3U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64A3U", 247, F_XMEGA, {0x1E, 0x96, 0x42}, // ID + /*ATxmega64A3U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64A3U*/ 6, 1, 127, vtab_atxmega64a3u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega64A3U*/ 792, rgftab_atxmega64a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART + /*ATxmega64A3U*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A3U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128A3U", 259, F_XMEGA, {0x1E, 0x97, 0x42}, // ID + /*ATxmega128A3U*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A3U*/ 6, 1, 127, vtab_atxmega64a3u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega128A3U*/ 792, rgftab_atxmega64a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART + /*ATxmega128A3U*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega192A3U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega192A3U", 268, F_XMEGA, {0x1E, 0x97, 0x44}, // ID + /*ATxmega192A3U*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem + /*ATxmega192A3U*/ 6, 1, 127, vtab_atxmega64a3u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega192A3U*/ 792, rgftab_atxmega64a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART + /*ATxmega192A3U*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega256A3BU atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega256A3BU", 274, F_XMEGA, {0x1E, 0x98, 0x43}, // ID + /*ATxmega256A3BU*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256A3BU*/ 6, 1, 127, vtab_atxmega256a3bu, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega256A3BU*/ 780, rgftab_atxmega256a3bu, 6, UART_XMEGA, 8, uarts_atxmega256a3bu, // Register file, UART + /*ATxmega256A3BU*/ 7, ports_atxmega256a3bu, WDT_XMEGA}, // Ports, WDT + + //ATxmega256A3U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega256A3U", 275, F_XMEGA, {0x1E, 0x98, 0x42}, // ID + /*ATxmega256A3U*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256A3U*/ 6, 1, 127, vtab_atxmega64a3u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega256A3U*/ 792, rgftab_atxmega64a3u, 7, UART_XMEGA, 11, uarts_atxmega64a3u, // Register file, UART + /*ATxmega256A3U*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega16A4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega16A4", 231, F_XMEGA, {0x1E, 0x94, 0x41}, // ID + /*ATxmega16A4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem + /*ATxmega16A4*/ 6, 1, 94, vtab_atxmega16a4, 16, cfgtab_atxmega16a4, // ISRs, Config + /*ATxmega16A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega16A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega32A4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32A4", 238, F_XMEGA, {0x1E, 0x95, 0x41}, // ID + /*ATxmega32A4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32A4*/ 6, 1, 94, vtab_atxmega16a4, 16, cfgtab_atxmega16a4, // ISRs, Config + /*ATxmega32A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega32A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega64A4 avrdude, from ATxmega32A4 // Sources + {"ATxmega64A4", 251, F_XMEGA, {0x1E, 0x96, 0x46}, // ID + /*ATxmega64A4*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64A4*/ 6, 1, 0, NULL, 16, cfgtab_atxmega16a4, // ISRs, Config + /*ATxmega64A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega64A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A4 avrdude, from ATxmega32A4 // Sources + {"ATxmega128A4", 263, F_XMEGA, {0x1E, 0x97, 0x46}, // ID + /*ATxmega128A4*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A4*/ 6, 1, 0, NULL, 16, cfgtab_atxmega16a4, // ISRs, Config + /*ATxmega128A4*/ 553, rgftab_atxmega16a4, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega128A4*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega16A4U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega16A4U", 232, F_XMEGA, {0x1E, 0x94, 0x41}, // ID + /*ATxmega16A4U*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem + /*ATxmega16A4U*/ 6, 1, 127, vtab_atxmega16a4u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega16A4U*/ 630, rgftab_atxmega16a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega16A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega32A4U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32A4U", 239, F_XMEGA, {0x1E, 0x95, 0x41}, // ID + /*ATxmega32A4U*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32A4U*/ 6, 1, 127, vtab_atxmega16a4u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega32A4U*/ 630, rgftab_atxmega16a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega32A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega64A4U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64A4U", 252, F_XMEGA, {0x1E, 0x96, 0x46}, // ID + /*ATxmega64A4U*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64A4U*/ 6, 1, 127, vtab_atxmega16a4u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega64A4U*/ 632, rgftab_atxmega64a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega64A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega128A4U atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128A4U", 264, F_XMEGA, {0x1E, 0x97, 0x46}, // ID + /*ATxmega128A4U*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128A4U*/ 6, 1, 127, vtab_atxmega16a4u, 17, cfgtab_atxmega64a1u, // ISRs, Config + /*ATxmega128A4U*/ 632, rgftab_atxmega64a4u, 5, UART_XMEGA, 7, uarts_atxmega16a4, // Register file, UART + /*ATxmega128A4U*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega64B1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64B1", 245, F_XMEGA, {0x1E, 0x96, 0x52}, // ID + /*ATxmega64B1*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64B1*/ 6, 1, 81, vtab_atxmega64b1, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega64B1*/ 574, rgftab_atxmega64b1, 2, UART_XMEGA, 4, uarts_atxmega64b1, // Register file, UART + /*ATxmega64B1*/ 8, ports_atxmega64b1, WDT_XMEGA}, // Ports, WDT + + //ATxmega128B1 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128B1", 257, F_XMEGA, {0x1E, 0x97, 0x4D}, // ID + /*ATxmega128B1*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128B1*/ 6, 1, 81, vtab_atxmega64b1, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega128B1*/ 574, rgftab_atxmega64b1, 2, UART_XMEGA, 4, uarts_atxmega64b1, // Register file, UART + /*ATxmega128B1*/ 8, ports_atxmega64b1, WDT_XMEGA}, // Ports, WDT + + //ATxmega64B3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64B3", 248, F_XMEGA, {0x1E, 0x96, 0x51}, // ID + /*ATxmega64B3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64B3*/ 6, 1, 54, vtab_atxmega64b3, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega64B3*/ 458, rgftab_atxmega64b3, 1, UART_XMEGA, 2, uarts_atxmega64b3, // Register file, UART + /*ATxmega64B3*/ 6, ports_atxmega64b3, WDT_XMEGA}, // Ports, WDT + + //ATxmega128B3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128B3", 260, F_XMEGA, {0x1E, 0x97, 0x4B}, // ID + /*ATxmega128B3*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128B3*/ 6, 1, 54, vtab_atxmega64b3, 17, cfgtab_atxmega64b1, // ISRs, Config + /*ATxmega128B3*/ 458, rgftab_atxmega64b3, 1, UART_XMEGA, 2, uarts_atxmega64b3, // Register file, UART + /*ATxmega128B3*/ 6, ports_atxmega64b3, WDT_XMEGA}, // Ports, WDT + + //ATxmega32C3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32C3", 236, F_XMEGA, {0x1E, 0x95, 0x49}, // ID + /*ATxmega32C3*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32C3*/ 6, 1, 127, vtab_atxmega32c3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega32C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega32C3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega64C3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64C3", 249, F_XMEGA, {0x1E, 0x96, 0x49}, // ID + /*ATxmega64C3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64C3*/ 6, 1, 127, vtab_atxmega32c3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega64C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega64C3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega128C3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128C3", 261, F_XMEGA, {0x1E, 0x97, 0x52}, // ID + /*ATxmega128C3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128C3*/ 6, 1, 127, vtab_atxmega32c3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega128C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega128C3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega192C3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega192C3", 269, F_XMEGA, {0x1E, 0x97, 0x51}, // ID + /*ATxmega192C3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem + /*ATxmega192C3*/ 6, 1, 127, vtab_atxmega32c3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega192C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega192C3*/ 0, NULL, WDT_XMEGA}, // Ports, WDT + + //ATxmega256C3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega256C3", 276, F_XMEGA, {0x1E, 0x98, 0x46}, // ID + /*ATxmega256C3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256C3*/ 6, 1, 127, vtab_atxmega32c3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega256C3*/ 569, rgftab_atxmega32c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega256C3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega384C3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega384C3", 278, F_XMEGA, {0x1E, 0x98, 0x45}, // ID + /*ATxmega384C3*/ 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, // Mem + /*ATxmega384C3*/ 6, 1, 127, vtab_atxmega384c3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega384C3*/ 603, rgftab_atxmega384c3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega384C3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega16C4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega16C4", 233, F_XMEGA, {0x1E, 0x94, 0x43}, // ID + /*ATxmega16C4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem + /*ATxmega16C4*/ 6, 1, 127, vtab_atxmega16c4, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega16C4*/ 482, rgftab_atxmega16c4, 3, UART_XMEGA, 4, uarts_atxmega16c4, // Register file, UART + /*ATxmega16C4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega32C4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32C4", 240, F_XMEGA, {0x1E, 0x95, 0x44}, // ID + /*ATxmega32C4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32C4*/ 6, 1, 127, vtab_atxmega16c4, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega32C4*/ 482, rgftab_atxmega16c4, 3, UART_XMEGA, 4, uarts_atxmega16c4, // Register file, UART + /*ATxmega32C4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega32D3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32D3", 237, F_XMEGA, {0x1E, 0x95, 0x4A}, // ID + /*ATxmega32D3*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32D3*/ 6, 1, 114, vtab_atxmega32d3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega32D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega32D3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega64D3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64D3", 250, F_XMEGA, {0x1E, 0x96, 0x4A}, // ID + /*ATxmega64D3*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64D3*/ 6, 1, 114, vtab_atxmega32d3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega64D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega64D3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega128D3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128D3", 262, F_XMEGA, {0x1E, 0x97, 0x48}, // ID + /*ATxmega128D3*/ 0, 0x22000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128D3*/ 6, 1, 114, vtab_atxmega32d3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega128D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega128D3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega192D3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega192D3", 270, F_XMEGA, {0x1E, 0x97, 0x49}, // ID + /*ATxmega192D3*/ 0, 0x32000, 0x200, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x4000, // Mem + /*ATxmega192D3*/ 6, 1, 114, vtab_atxmega32d3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega192D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega192D3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega256D3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega256D3", 277, F_XMEGA, {0x1E, 0x98, 0x44}, // ID + /*ATxmega256D3*/ 0, 0x42000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x4000, // Mem + /*ATxmega256D3*/ 6, 1, 114, vtab_atxmega32d3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega256D3*/ 567, rgftab_atxmega32d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega256D3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega384D3 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega384D3", 279, F_XMEGA, {0x1E, 0x98, 0x47}, // ID + /*ATxmega384D3*/ 0, 0x62000, 0x200, 1, 0x2000, 0, 0x1000, 32, 0x2000, 0x8000, // Mem + /*ATxmega384D3*/ 6, 1, 114, vtab_atxmega32d3, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega384D3*/ 560, rgftab_atxmega384d3, 3, UART_XMEGA, 4, uarts_atxmega32c3, // Register file, UART + /*ATxmega384D3*/ 7, ports_atxmega64a3u, WDT_XMEGA}, // Ports, WDT + + //ATxmega16D4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega16D4", 234, F_XMEGA, {0x1E, 0x94, 0x42}, // ID + /*ATxmega16D4*/ 0, 0x05000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x0800, // Mem + /*ATxmega16D4*/ 6, 1, 91, vtab_atxmega16d4, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega16D4*/ 460, rgftab_atxmega16d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART + /*ATxmega16D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega32D4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32D4", 241, F_XMEGA, {0x1E, 0x95, 0x42}, // ID + /*ATxmega32D4*/ 0, 0x09000, 0x100, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32D4*/ 6, 1, 91, vtab_atxmega16d4, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega32D4*/ 460, rgftab_atxmega16d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART + /*ATxmega32D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega64D4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega64D4", 253, F_XMEGA, {0x1E, 0x96, 0x47}, // ID + /*ATxmega64D4*/ 0, 0x11000, 0x100, 1, 0x1000, 0, 0x0800, 32, 0x2000, 0x1000, // Mem + /*ATxmega64D4*/ 6, 1, 91, vtab_atxmega64d4, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega64D4*/ 460, rgftab_atxmega64d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART + /*ATxmega64D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega128D4 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega128D4", 265, F_XMEGA, {0x1E, 0x97, 0x47}, // ID + /*ATxmega128D4*/ 0, 0x22000, 0x100, 1, 0x2000, 0, 0x0800, 32, 0x2000, 0x2000, // Mem + /*ATxmega128D4*/ 6, 1, 91, vtab_atxmega64d4, 15, cfgtab_atxmega32c3, // ISRs, Config + /*ATxmega128D4*/ 460, rgftab_atxmega64d4, 2, UART_XMEGA, 3, uarts_atxmega16d4, // Register file, UART + /*ATxmega128D4*/ 6, ports_atxmega16a4u, WDT_XMEGA}, // Ports, WDT + + //ATxmega8E5 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega8E5", 230, F_XMEGA, {0x1E, 0x93, 0x41}, // ID + /*ATxmega8E5*/ 0, 0x02800, 0x080, 1, 0x0800, 0, 0x0200, 32, 0x2000, 0x0400, // Mem + /*ATxmega8E5*/ 7, 1, 43, vtab_atxmega8e5, 17, cfgtab_atxmega8e5, // ISRs, Config + /*ATxmega8E5*/ 438, rgftab_atxmega8e5, 2, UART_XMEGA, 4, uarts_atxmega8e5, // Register file, UART + /*ATxmega8E5*/ 4, ports_atxmega8e5, WDT_XMEGA}, // Ports, WDT + + //ATxmega16E5 atdf, avr-gcc 7.3.0, avrdude // Sources + {"ATxmega16E5", 235, F_XMEGA, {0x1E, 0x94, 0x45}, // ID + /*ATxmega16E5*/ 0, 0x05000, 0x080, 1, 0x1000, 0, 0x0200, 32, 0x2000, 0x0800, // Mem + /*ATxmega16E5*/ 7, 1, 43, vtab_atxmega8e5, 17, cfgtab_atxmega8e5, // ISRs, Config + /*ATxmega16E5*/ 438, rgftab_atxmega8e5, 2, UART_XMEGA, 4, uarts_atxmega8e5, // Register file, UART + /*ATxmega16E5*/ 4, ports_atxmega8e5, WDT_XMEGA}, // Ports, WDT + + //ATxmega32E5 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATxmega32E5", 242, F_XMEGA, {0x1E, 0x95, 0x4C}, // ID + /*ATxmega32E5*/ 0, 0x09000, 0x080, 1, 0x1000, 0, 0x0400, 32, 0x2000, 0x1000, // Mem + /*ATxmega32E5*/ 7, 1, 43, vtab_atxmega8e5, 17, cfgtab_atxmega8e5, // ISRs, Config + /*ATxmega32E5*/ 438, rgftab_atxmega8e5, 2, UART_XMEGA, 4, uarts_atxmega8e5, // Register file, UART + /*ATxmega32E5*/ 4, ports_atxmega8e5, WDT_XMEGA}, // Ports, WDT + + + //ATtiny202 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny202", 280, F_AVR8X, {0x1E, 0x91, 0x23}, // ID + /*ATtiny202*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem + /*ATtiny202*/ 10, 1, 26, vtab_attiny202, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny202*/ 217, rgftab_attiny202, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART + /*ATtiny202*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT + + //ATtiny204 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny204", 281, F_AVR8X, {0x1E, 0x91, 0x22}, // ID + /*ATtiny204*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem + /*ATtiny204*/ 10, 1, 26, vtab_attiny204, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny204*/ 235, rgftab_attiny204, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny204*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny402 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny402", 284, F_AVR8X, {0x1E, 0x92, 0x27}, // ID + /*ATtiny402*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny402*/ 10, 1, 26, vtab_attiny202, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny402*/ 217, rgftab_attiny202, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART + /*ATtiny402*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT + + //ATtiny404 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny404", 285, F_AVR8X, {0x1E, 0x92, 0x26}, // ID + /*ATtiny404*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny404*/ 10, 1, 26, vtab_attiny204, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny404*/ 235, rgftab_attiny204, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny404*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny406 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny406", 286, F_AVR8X, {0x1E, 0x92, 0x25}, // ID + /*ATtiny406*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny406*/ 10, 1, 26, vtab_attiny406, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny406*/ 253, rgftab_attiny406, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny406*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny804 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny804", 295, F_AVR8X, {0x1E, 0x93, 0x25}, // ID + /*ATtiny804*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny804*/ 10, 1, 31, vtab_attiny804, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny804*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny804*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny806 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny806", 296, F_AVR8X, {0x1E, 0x93, 0x24}, // ID + /*ATtiny806*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny806*/ 10, 1, 31, vtab_attiny804, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny806*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny806*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny807 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny807", 297, F_AVR8X, {0x1E, 0x93, 0x23}, // ID + /*ATtiny807*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny807*/ 10, 1, 31, vtab_attiny804, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny807*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny807*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny1604 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1604", 304, F_AVR8X, {0x1E, 0x94, 0x25}, // ID + /*ATtiny1604*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem + /*ATtiny1604*/ 10, 1, 31, vtab_attiny804, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny1604*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny1604*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny1606 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1606", 305, F_AVR8X, {0x1E, 0x94, 0x24}, // ID + /*ATtiny1606*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem + /*ATtiny1606*/ 10, 1, 31, vtab_attiny804, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny1606*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny1606*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny1607 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1607", 306, F_AVR8X, {0x1E, 0x94, 0x23}, // ID + /*ATtiny1607*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem + /*ATtiny1607*/ 10, 1, 31, vtab_attiny804, 15, cfgtab_attiny804, // ISRs, Config + /*ATtiny1607*/ 255, rgftab_attiny804, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny1607*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny212 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny212", 282, F_AVR8X, {0x1E, 0x91, 0x21}, // ID + /*ATtiny212*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem + /*ATtiny212*/ 10, 1, 26, vtab_attiny212, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny212*/ 247, rgftab_attiny212, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART + /*ATtiny212*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT + + //ATtiny214 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny214", 283, F_AVR8X, {0x1E, 0x91, 0x20}, // ID + /*ATtiny214*/ 0, 0x00800, 0x040, 1, 0x0100, 0x01400, 0x0040, 32, 0x3f80, 0x0080, // Mem + /*ATtiny214*/ 10, 1, 26, vtab_attiny214, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny214*/ 265, rgftab_attiny214, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny214*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny412 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny412", 287, F_AVR8X, {0x1E, 0x92, 0x23}, // ID + /*ATtiny412*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny412*/ 10, 1, 26, vtab_attiny212, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny412*/ 247, rgftab_attiny212, 1, UART_AVR8X, 2, uarts_attiny202, // Register file, UART + /*ATtiny412*/ 1, ports_attiny202, WDT_AVR8X}, // Ports, WDT + + //ATtiny414 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny414", 288, F_AVR8X, {0x1E, 0x92, 0x22}, // ID + /*ATtiny414*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny414*/ 10, 1, 26, vtab_attiny214, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny414*/ 265, rgftab_attiny214, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny414*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny416 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny416", 289, F_AVR8X, {0x1E, 0x92, 0x21}, // ID + /*ATtiny416*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny416*/ 10, 1, 26, vtab_attiny416, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny416*/ 283, rgftab_attiny416, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny416*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny416auto atdf, avrdude // Sources + {"ATtiny416auto", 290, F_AVR8X, {0x1E, 0x92, 0x28}, // ID + /*ATtiny416auto*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny416auto*/ 10, 1, 26, vtab_attiny416, 23, cfgtab_attiny416auto, // ISRs, Config + /*ATtiny416auto*/ 283, rgftab_attiny416auto, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny416auto*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny417 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny417", 291, F_AVR8X, {0x1E, 0x92, 0x20}, // ID + /*ATtiny417*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3f00, 0x0100, // Mem + /*ATtiny417*/ 10, 1, 26, vtab_attiny416, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny417*/ 283, rgftab_attiny417, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny417*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny814 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny814", 298, F_AVR8X, {0x1E, 0x93, 0x22}, // ID + /*ATtiny814*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny814*/ 10, 1, 26, vtab_attiny214, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny814*/ 265, rgftab_attiny814, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny814*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny816 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny816", 299, F_AVR8X, {0x1E, 0x93, 0x21}, // ID + /*ATtiny816*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny816*/ 10, 1, 26, vtab_attiny416, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny816*/ 283, rgftab_attiny417, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny816*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny817 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny817", 300, F_AVR8X, {0x1E, 0x93, 0x20}, // ID + /*ATtiny817*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny817*/ 10, 1, 26, vtab_attiny416, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny817*/ 283, rgftab_attiny417, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny817*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny1614 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1614", 307, F_AVR8X, {0x1E, 0x94, 0x22}, // ID + /*ATtiny1614*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATtiny1614*/ 10, 1, 31, vtab_attiny1614, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny1614*/ 308, rgftab_attiny1614, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny1614*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny1616 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1616", 308, F_AVR8X, {0x1E, 0x94, 0x21}, // ID + /*ATtiny1616*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATtiny1616*/ 10, 1, 31, vtab_attiny1616, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny1616*/ 326, rgftab_attiny1616, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny1616*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny1617 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny1617", 309, F_AVR8X, {0x1E, 0x94, 0x20}, // ID + /*ATtiny1617*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATtiny1617*/ 10, 1, 31, vtab_attiny1616, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny1617*/ 326, rgftab_attiny1616, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny1617*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny3214 avr-gcc 12.2.0 // Sources + {"ATtiny3214", 313, F_AVR8X, {0x1E, 0x95, 0x20}, // ID + /*ATtiny3214*/ 0, 0x08000, 0x080, 1, 0, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem + /*ATtiny3214*/ 10, 1, 31, vtab_attiny3214, 0, NULL, // ISRs, Config + /*ATtiny3214*/ 0, NULL, 1, UART_AVR8X, -1, NULL, // Register file, UART + /*ATtiny3214*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT + + //ATtiny3216 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny3216", 314, F_AVR8X, {0x1E, 0x95, 0x21}, // ID + /*ATtiny3216*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem + /*ATtiny3216*/ 10, 1, 31, vtab_attiny1616, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny3216*/ 326, rgftab_attiny3216, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny3216*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny3217 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATtiny3217", 315, F_AVR8X, {0x1E, 0x95, 0x22}, // ID + /*ATtiny3217*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3800, 0x0800, // Mem + /*ATtiny3217*/ 10, 1, 31, vtab_attiny1616, 23, cfgtab_attiny202, // ISRs, Config + /*ATtiny3217*/ 326, rgftab_attiny3216, 1, UART_AVR8X, 2, uarts_attiny204, // Register file, UART + /*ATtiny3217*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny424 atdf, avrdude // Sources + {"ATtiny424", 292, F_AVR8X, {0x1E, 0x92, 0x2C}, // ID + /*ATtiny424*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny424*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny424*/ 307, rgftab_attiny424, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART + /*ATtiny424*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny426 atdf, avrdude // Sources + {"ATtiny426", 293, F_AVR8X, {0x1E, 0x92, 0x2B}, // ID + /*ATtiny426*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny426*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny426*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny426*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny427 atdf, avrdude // Sources + {"ATtiny427", 294, F_AVR8X, {0x1E, 0x92, 0x2A}, // ID + /*ATtiny427*/ 0, 0x01000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3e00, 0x0200, // Mem + /*ATtiny427*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny427*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny427*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny824 atdf, avrdude // Sources + {"ATtiny824", 301, F_AVR8X, {0x1E, 0x93, 0x29}, // ID + /*ATtiny824*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem + /*ATtiny824*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny824*/ 307, rgftab_attiny424, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART + /*ATtiny824*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny826 atdf, avrdude // Sources + {"ATtiny826", 302, F_AVR8X, {0x1E, 0x93, 0x28}, // ID + /*ATtiny826*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem + /*ATtiny826*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny826*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny826*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny827 atdf, avrdude // Sources + {"ATtiny827", 303, F_AVR8X, {0x1E, 0x93, 0x27}, // ID + /*ATtiny827*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0080, 32, 0x3c00, 0x0400, // Mem + /*ATtiny827*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny827*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny827*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny1624 atdf, avrdude // Sources + {"ATtiny1624", 310, F_AVR8X, {0x1E, 0x94, 0x2A}, // ID + /*ATtiny1624*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATtiny1624*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny1624*/ 307, rgftab_attiny424, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART + /*ATtiny1624*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny1626 atdf, avrdude // Sources + {"ATtiny1626", 311, F_AVR8X, {0x1E, 0x94, 0x29}, // ID + /*ATtiny1626*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATtiny1626*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny1626*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny1626*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny1627 atdf, avrdude // Sources + {"ATtiny1627", 312, F_AVR8X, {0x1E, 0x94, 0x28}, // ID + /*ATtiny1627*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATtiny1627*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny1627*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny1627*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATtiny3224 atdf, avrdude // Sources + {"ATtiny3224", 316, F_AVR8X, {0x1E, 0x95, 0x28}, // ID + /*ATtiny3224*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem + /*ATtiny3224*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny3224*/ 307, rgftab_attiny424, 2, UART_AVR8X, 3, uarts_attiny424, // Register file, UART + /*ATtiny3224*/ 2, ports_attiny204, WDT_AVR8X}, // Ports, WDT + + //ATtiny3226 atdf, avrdude // Sources + {"ATtiny3226", 317, F_AVR8X, {0x1E, 0x95, 0x27}, // ID + /*ATtiny3226*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem + /*ATtiny3226*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny3226*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny3226*/ 3, ports_attiny406, WDT_AVR8X}, // Ports, WDT + + //ATtiny3227 atdf, avrdude // Sources + {"ATtiny3227", 318, F_AVR8X, {0x1E, 0x95, 0x26}, // ID + /*ATtiny3227*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3400, 0x0c00, // Mem + /*ATtiny3227*/ 10, 1, 30, vtab_attiny424, 16, cfgtab_attiny424, // ISRs, Config + /*ATtiny3227*/ 308, rgftab_attiny426, 2, UART_AVR8X, 4, uarts_attiny426, // Register file, UART + /*ATtiny3227*/ 3, ports_attiny807, WDT_AVR8X}, // Ports, WDT + + //ATmega808 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega808", 319, F_AVR8X, {0x1E, 0x93, 0x26}, // ID + /*ATmega808*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem + /*ATmega808*/ 10, 1, 36, vtab_atmega808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega808*/ 406, rgftab_atmega808, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART + /*ATmega808*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //ATmega809 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega809", 320, F_AVR8X, {0x1E, 0x93, 0x2A}, // ID + /*ATmega809*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3c00, 0x0400, // Mem + /*ATmega809*/ 10, 1, 40, vtab_atmega809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega809*/ 432, rgftab_atmega809, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART + /*ATmega809*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //ATmega1608 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1608", 321, F_AVR8X, {0x1E, 0x94, 0x27}, // ID + /*ATmega1608*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATmega1608*/ 10, 1, 36, vtab_atmega808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega1608*/ 406, rgftab_atmega808, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART + /*ATmega1608*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //ATmega1609 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega1609", 322, F_AVR8X, {0x1E, 0x94, 0x26}, // ID + /*ATmega1609*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0100, 32, 0x3800, 0x0800, // Mem + /*ATmega1609*/ 10, 1, 40, vtab_atmega809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega1609*/ 432, rgftab_atmega809, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART + /*ATmega1609*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //ATmega3208 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3208", 323, F_AVR8X, {0x1E, 0x95, 0x30}, // ID + /*ATmega3208*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3000, 0x1000, // Mem + /*ATmega3208*/ 10, 1, 36, vtab_atmega808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega3208*/ 406, rgftab_atmega3208, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART + /*ATmega3208*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //ATmega3209 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega3209", 324, F_AVR8X, {0x1E, 0x95, 0x31}, // ID + /*ATmega3209*/ 0, 0x08000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x3000, 0x1000, // Mem + /*ATmega3209*/ 10, 1, 40, vtab_atmega809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega3209*/ 432, rgftab_atmega3209, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART + /*ATmega3209*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //ATmega4808 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega4808", 325, F_AVR8X, {0x1E, 0x96, 0x50}, // ID + /*ATmega4808*/ 0, 0x0c000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x2800, 0x1800, // Mem + /*ATmega4808*/ 10, 1, 36, vtab_atmega808, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega4808*/ 406, rgftab_atmega3208, 3, UART_AVR8X, 5, uarts_atmega808, // Register file, UART + /*ATmega4808*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //ATmega4809 atdf, avr-gcc 12.2.0, avrdude // Sources + {"ATmega4809", 326, F_AVR8X, {0x1E, 0x96, 0x51}, // ID + /*ATmega4809*/ 0, 0x0c000, 0x080, 1, 0x0100, 0x01400, 0x0100, 64, 0x2800, 0x1800, // Mem + /*ATmega4809*/ 10, 1, 40, vtab_atmega809, 15, cfgtab_atmega808, // ISRs, Config + /*ATmega4809*/ 432, rgftab_atmega3209, 4, UART_AVR8X, 8, uarts_atmega809, // Register file, UART + /*ATmega4809*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR32DA28 atdf, avrdude // Sources + {"AVR32DA28", 338, F_AVR8X, {0x1E, 0x95, 0x34}, // ID + /*AVR32DA28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DA28*/ 16, 4, 41, vtab_avr32da28, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR32DA28*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR32DA28*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT + + //AVR32DA28S atdf, avrdude // Sources + {"AVR32DA28S", 405, F_AVR8X, {0x1E, 0x95, 0x72}, // ID + /*AVR32DA28S*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DA28S*/ 16, 4, 41, vtab_avr32da28, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR32DA28S*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR32DA28S*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT + + //AVR32DA32 atdf, avrdude // Sources + {"AVR32DA32", 342, F_AVR8X, {0x1E, 0x95, 0x33}, // ID + /*AVR32DA32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DA32*/ 16, 4, 44, vtab_avr32da32, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR32DA32*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR32DA32*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //AVR32DA32S atdf, avrdude // Sources + {"AVR32DA32S", 406, F_AVR8X, {0x1E, 0x95, 0x71}, // ID + /*AVR32DA32S*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DA32S*/ 16, 4, 44, vtab_avr32da32, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR32DA32S*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR32DA32S*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //AVR32DA48 atdf, avrdude // Sources + {"AVR32DA48", 346, F_AVR8X, {0x1E, 0x95, 0x32}, // ID + /*AVR32DA48*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DA48*/ 16, 4, 61, vtab_avr32da48, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR32DA48*/ 610, rgftab_avr32da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR32DA48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR32DA48S atdf, avrdude // Sources + {"AVR32DA48S", 407, F_AVR8X, {0x1E, 0x95, 0x70}, // ID + /*AVR32DA48S*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DA48S*/ 16, 4, 61, vtab_avr32da48, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR32DA48S*/ 610, rgftab_avr32da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR32DA48S*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR64DA28 atdf, avrdude // Sources + {"AVR64DA28", 351, F_AVR8X, {0x1E, 0x96, 0x15}, // ID + /*AVR64DA28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA28*/ 16, 4, 41, vtab_avr32da28, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA28*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR64DA28*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT + + //AVR64DA28S atdf, avrdude // Sources + {"AVR64DA28S", 408, F_AVR8X, {0x1E, 0x96, 0x2E}, // ID + /*AVR64DA28S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA28S*/ 16, 4, 41, vtab_avr32da28, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR64DA28S*/ 432, rgftab_avr32da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR64DA28S*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT + + //AVR64DA32 atdf, avrdude // Sources + {"AVR64DA32", 355, F_AVR8X, {0x1E, 0x96, 0x14}, // ID + /*AVR64DA32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA32*/ 16, 4, 44, vtab_avr32da32, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA32*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR64DA32*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //AVR64DA32S atdf, avrdude // Sources + {"AVR64DA32S", 409, F_AVR8X, {0x1E, 0x96, 0x2D}, // ID + /*AVR64DA32S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA32S*/ 16, 4, 44, vtab_avr32da32, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR64DA32S*/ 447, rgftab_avr32da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR64DA32S*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //AVR64DA48 atdf, avrdude // Sources + {"AVR64DA48", 359, F_AVR8X, {0x1E, 0x96, 0x13}, // ID + /*AVR64DA48*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA48*/ 16, 4, 58, vtab_avr64da48, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA48*/ 600, rgftab_avr64da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR64DA48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR64DA48S atdf, avrdude // Sources + {"AVR64DA48S", 410, F_AVR8X, {0x1E, 0x96, 0x2C}, // ID + /*AVR64DA48S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA48S*/ 16, 4, 58, vtab_avr64da48, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR64DA48S*/ 600, rgftab_avr64da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR64DA48S*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR64DA64 atdf, avrdude // Sources + {"AVR64DA64", 362, F_AVR8X, {0x1E, 0x96, 0x12}, // ID + /*AVR64DA64*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA64*/ 16, 4, 64, vtab_avr64da64, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR64DA64*/ 658, rgftab_avr64da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART + /*AVR64DA64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + + //AVR64DA64S atdf, avrdude // Sources + {"AVR64DA64S", 411, F_AVR8X, {0x1E, 0x96, 0x2B}, // ID + /*AVR64DA64S*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DA64S*/ 16, 4, 64, vtab_avr64da64, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR64DA64S*/ 658, rgftab_avr64da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART + /*AVR64DA64S*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + + //AVR128DA28 atdf, avrdude // Sources + {"AVR128DA28", 364, F_AVR8X, {0x1E, 0x97, 0x0A}, // ID + /*AVR128DA28*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA28*/ 16, 4, 41, vtab_avr32da28, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA28*/ 433, rgftab_avr128da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR128DA28*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT + + //AVR128DA28S atdf, avrdude // Sources + {"AVR128DA28S", 394, F_AVR8X, {0x1E, 0x97, 0x12}, // ID + /*AVR128DA28S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA28S*/ 16, 4, 41, vtab_avr32da28, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR128DA28S*/ 433, rgftab_avr128da28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR128DA28S*/ 4, ports_avr32da28, WDT_AVR8X}, // Ports, WDT + + //AVR128DA32 atdf, avrdude // Sources + {"AVR128DA32", 366, F_AVR8X, {0x1E, 0x97, 0x09}, // ID + /*AVR128DA32*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA32*/ 16, 4, 44, vtab_avr32da32, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA32*/ 448, rgftab_avr128da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR128DA32*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //AVR128DA32S atdf, avrdude // Sources + {"AVR128DA32S", 395, F_AVR8X, {0x1E, 0x97, 0x11}, // ID + /*AVR128DA32S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA32S*/ 16, 4, 44, vtab_avr32da32, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR128DA32S*/ 448, rgftab_avr128da32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR128DA32S*/ 4, ports_atmega808, WDT_AVR8X}, // Ports, WDT + + //AVR128DA48 atdf, avrdude // Sources + {"AVR128DA48", 368, F_AVR8X, {0x1E, 0x97, 0x08}, // ID + /*AVR128DA48*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA48*/ 16, 4, 58, vtab_avr64da48, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA48*/ 601, rgftab_avr128da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR128DA48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR128DA48S atdf, avrdude // Sources + {"AVR128DA48S", 396, F_AVR8X, {0x1E, 0x97, 0x10}, // ID + /*AVR128DA48S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA48S*/ 16, 4, 58, vtab_avr64da48, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR128DA48S*/ 601, rgftab_avr128da48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR128DA48S*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR128DA64 atdf, avrdude // Sources + {"AVR128DA64", 370, F_AVR8X, {0x1E, 0x97, 0x07}, // ID + /*AVR128DA64*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA64*/ 16, 4, 64, vtab_avr64da64, 15, cfgtab_avr32da28, // ISRs, Config + /*AVR128DA64*/ 659, rgftab_avr128da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART + /*AVR128DA64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + + //AVR128DA64S atdf, avrdude // Sources + {"AVR128DA64S", 397, F_AVR8X, {0x1E, 0x97, 0x0F}, // ID + /*AVR128DA64S*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DA64S*/ 16, 4, 64, vtab_avr64da64, 17, cfgtab_avr32da28s, // ISRs, Config + /*AVR128DA64S*/ 659, rgftab_avr128da64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART + /*AVR128DA64S*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + + //AVR32DB28 atdf, avrdude // Sources + {"AVR32DB28", 339, F_AVR8X, {0x1E, 0x95, 0x37}, // ID + /*AVR32DB28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DB28*/ 16, 4, 42, vtab_avr32db28, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR32DB28*/ 461, rgftab_avr32db28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR32DB28*/ 4, ports_avr32db28, WDT_AVR8X}, // Ports, WDT + + //AVR32DB32 atdf, avrdude // Sources + {"AVR32DB32", 343, F_AVR8X, {0x1E, 0x95, 0x36}, // ID + /*AVR32DB32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DB32*/ 16, 4, 44, vtab_avr32db32, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR32DB32*/ 476, rgftab_avr32db32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR32DB32*/ 4, ports_avr32db32, WDT_AVR8X}, // Ports, WDT + + //AVR32DB48 atdf, avrdude // Sources + {"AVR32DB48", 347, F_AVR8X, {0x1E, 0x95, 0x35}, // ID + /*AVR32DB48*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x7000, 0x1000, // Mem + /*AVR32DB48*/ 16, 4, 61, vtab_avr32db48, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR32DB48*/ 642, rgftab_avr32db48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR32DB48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR64DB28 atdf, avrdude // Sources + {"AVR64DB28", 352, F_AVR8X, {0x1E, 0x96, 0x19}, // ID + /*AVR64DB28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DB28*/ 16, 4, 42, vtab_avr32db28, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB28*/ 461, rgftab_avr32db28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR64DB28*/ 4, ports_avr32db28, WDT_AVR8X}, // Ports, WDT + + //AVR64DB32 atdf, avrdude // Sources + {"AVR64DB32", 356, F_AVR8X, {0x1E, 0x96, 0x18}, // ID + /*AVR64DB32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DB32*/ 16, 4, 44, vtab_avr32db32, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB32*/ 476, rgftab_avr32db32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR64DB32*/ 4, ports_avr32db32, WDT_AVR8X}, // Ports, WDT + + //AVR64DB48 atdf, avrdude // Sources + {"AVR64DB48", 360, F_AVR8X, {0x1E, 0x96, 0x17}, // ID + /*AVR64DB48*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DB48*/ 16, 4, 61, vtab_avr32db48, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB48*/ 642, rgftab_avr32db48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR64DB48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR64DB64 atdf, avrdude // Sources + {"AVR64DB64", 363, F_AVR8X, {0x1E, 0x96, 0x16}, // ID + /*AVR64DB64*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x6000, 0x2000, // Mem + /*AVR64DB64*/ 16, 4, 65, vtab_avr64db64, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR64DB64*/ 697, rgftab_avr64db64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART + /*AVR64DB64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + + //AVR128DB28 atdf, avrdude // Sources + {"AVR128DB28", 365, F_AVR8X, {0x1E, 0x97, 0x0E}, // ID + /*AVR128DB28*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DB28*/ 16, 4, 42, vtab_avr32db28, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB28*/ 462, rgftab_avr128db28, 3, UART_AVR8X, 4, uarts_avr32da28, // Register file, UART + /*AVR128DB28*/ 4, ports_avr32db28, WDT_AVR8X}, // Ports, WDT + + //AVR128DB32 atdf, avrdude // Sources + {"AVR128DB32", 367, F_AVR8X, {0x1E, 0x97, 0x0D}, // ID + /*AVR128DB32*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DB32*/ 16, 4, 44, vtab_avr32db32, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB32*/ 477, rgftab_avr128db32, 3, UART_AVR8X, 5, uarts_avr32da32, // Register file, UART + /*AVR128DB32*/ 4, ports_avr32db32, WDT_AVR8X}, // Ports, WDT + + //AVR128DB48 atdf, avrdude // Sources + {"AVR128DB48", 369, F_AVR8X, {0x1E, 0x97, 0x0C}, // ID + /*AVR128DB48*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DB48*/ 16, 4, 61, vtab_avr32db48, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB48*/ 643, rgftab_avr128db48, 5, UART_AVR8X, 9, uarts_avr32da48, // Register file, UART + /*AVR128DB48*/ 6, ports_atmega809, WDT_AVR8X}, // Ports, WDT + + //AVR128DB64 atdf, avrdude // Sources + {"AVR128DB64", 371, F_AVR8X, {0x1E, 0x97, 0x0B}, // ID + /*AVR128DB64*/ 0, 0x20000, 0x200, 1, 0x0200, 0x01400, 0x0200, 1, 0x4000, 0x4000, // Mem + /*AVR128DB64*/ 16, 4, 65, vtab_avr64db64, 16, cfgtab_avr32db28, // ISRs, Config + /*AVR128DB64*/ 698, rgftab_avr128db64, 6, UART_AVR8X, 12, uarts_avr64da64, // Register file, UART + /*AVR128DB64*/ 7, ports_avr64da64, WDT_AVR8X}, // Ports, WDT + + //AVR16DD14 atdf, avrdude // Sources + {"AVR16DD14", 329, F_AVR8X, {0x1E, 0x94, 0x34}, // ID + /*AVR16DD14*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DD14*/ 16, 4, 36, vtab_avr16dd14, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR16DD14*/ 390, rgftab_avr16dd14, 2, UART_AVR8X, 5, uarts_avr16dd14, // Register file, UART + /*AVR16DD14*/ 4, ports_avr16dd14, WDT_AVR8X}, // Ports, WDT + + //AVR16DD20 atdf, avrdude // Sources + {"AVR16DD20", 330, F_AVR8X, {0x1E, 0x94, 0x33}, // ID + /*AVR16DD20*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DD20*/ 16, 4, 36, vtab_avr16dd14, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR16DD20*/ 391, rgftab_avr16dd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART + /*AVR16DD20*/ 4, ports_avr16dd20, WDT_AVR8X}, // Ports, WDT + + //AVR16DD28 atdf, avrdude // Sources + {"AVR16DD28", 331, F_AVR8X, {0x1E, 0x94, 0x32}, // ID + /*AVR16DD28*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DD28*/ 16, 4, 36, vtab_avr16dd28, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR16DD28*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART + /*AVR16DD28*/ 4, ports_avr16dd28, WDT_AVR8X}, // Ports, WDT + + //AVR16DD32 atdf, avrdude // Sources + {"AVR16DD32", 333, F_AVR8X, {0x1E, 0x94, 0x31}, // ID + /*AVR16DD32*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DD32*/ 16, 4, 36, vtab_avr16dd28, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR16DD32*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART + /*AVR16DD32*/ 4, ports_avr16dd32, WDT_AVR8X}, // Ports, WDT + + //AVR32DD14 atdf, avrdude // Sources + {"AVR32DD14", 336, F_AVR8X, {0x1E, 0x95, 0x3B}, // ID + /*AVR32DD14*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DD14*/ 16, 4, 36, vtab_avr16dd14, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR32DD14*/ 390, rgftab_avr16dd14, 2, UART_AVR8X, 5, uarts_avr16dd14, // Register file, UART + /*AVR32DD14*/ 4, ports_avr16dd14, WDT_AVR8X}, // Ports, WDT + + //AVR32DD20 atdf, avrdude // Sources + {"AVR32DD20", 337, F_AVR8X, {0x1E, 0x95, 0x3A}, // ID + /*AVR32DD20*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DD20*/ 16, 4, 36, vtab_avr16dd14, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR32DD20*/ 391, rgftab_avr16dd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART + /*AVR32DD20*/ 4, ports_avr16dd20, WDT_AVR8X}, // Ports, WDT + + //AVR32DD28 atdf, avrdude // Sources + {"AVR32DD28", 340, F_AVR8X, {0x1E, 0x95, 0x39}, // ID + /*AVR32DD28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DD28*/ 16, 4, 36, vtab_avr16dd28, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR32DD28*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART + /*AVR32DD28*/ 4, ports_avr16dd28, WDT_AVR8X}, // Ports, WDT + + //AVR32DD32 atdf, avrdude // Sources + {"AVR32DD32", 344, F_AVR8X, {0x1E, 0x95, 0x38}, // ID + /*AVR32DD32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DD32*/ 16, 4, 36, vtab_avr16dd28, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR32DD32*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART + /*AVR32DD32*/ 4, ports_avr16dd32, WDT_AVR8X}, // Ports, WDT + + //AVR64DD14 atdf, avrdude // Sources + {"AVR64DD14", 349, F_AVR8X, {0x1E, 0x96, 0x1D}, // ID + /*AVR64DD14*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem + /*AVR64DD14*/ 16, 4, 36, vtab_avr16dd14, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR64DD14*/ 390, rgftab_avr16dd14, 2, UART_AVR8X, 5, uarts_avr16dd14, // Register file, UART + /*AVR64DD14*/ 4, ports_avr16dd14, WDT_AVR8X}, // Ports, WDT + + //AVR64DD20 atdf, avrdude // Sources + {"AVR64DD20", 350, F_AVR8X, {0x1E, 0x96, 0x1C}, // ID + /*AVR64DD20*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem + /*AVR64DD20*/ 16, 4, 36, vtab_avr16dd14, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR64DD20*/ 391, rgftab_avr16dd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART + /*AVR64DD20*/ 4, ports_avr16dd20, WDT_AVR8X}, // Ports, WDT + + //AVR64DD28 atdf, avrdude // Sources + {"AVR64DD28", 353, F_AVR8X, {0x1E, 0x96, 0x1B}, // ID + /*AVR64DD28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem + /*AVR64DD28*/ 16, 4, 36, vtab_avr16dd28, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR64DD28*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART + /*AVR64DD28*/ 4, ports_avr16dd28, WDT_AVR8X}, // Ports, WDT + + //AVR64DD32 atdf, avrdude // Sources + {"AVR64DD32", 357, F_AVR8X, {0x1E, 0x96, 0x1A}, // ID + /*AVR64DD32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem + /*AVR64DD32*/ 16, 4, 36, vtab_avr16dd28, 17, cfgtab_avr16dd14, // ISRs, Config + /*AVR64DD32*/ 401, rgftab_avr16dd28, 2, UART_AVR8X, 7, uarts_avr16dd28, // Register file, UART + /*AVR64DD32*/ 4, ports_avr16dd32, WDT_AVR8X}, // Ports, WDT + + //AVR16DU14 atdf, avrdude // Sources + {"AVR16DU14", 386, F_AVR8X, {0x1E, 0x94, 0x3B}, // ID + /*AVR16DU14*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DU14*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR16DU14*/ 370, rgftab_avr16du14, 2, UART_AVR8X, 3, uarts_avr16du14, // Register file, UART + /*AVR16DU14*/ 4, ports_avr16du14, WDT_AVR8X}, // Ports, WDT + + //AVR16DU20 atdf, avrdude // Sources + {"AVR16DU20", 387, F_AVR8X, {0x1E, 0x94, 0x3A}, // ID + /*AVR16DU20*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DU20*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR16DU20*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR16DU20*/ 4, ports_avr16du20, WDT_AVR8X}, // Ports, WDT + + //AVR16DU28 atdf, avrdude // Sources + {"AVR16DU28", 388, F_AVR8X, {0x1E, 0x94, 0x39}, // ID + /*AVR16DU28*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DU28*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR16DU28*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR16DU28*/ 4, ports_avr16du28, WDT_AVR8X}, // Ports, WDT + + //AVR16DU32 atdf, avrdude // Sources + {"AVR16DU32", 389, F_AVR8X, {0x1E, 0x94, 0x38}, // ID + /*AVR16DU32*/ 0, 0x04000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7800, 0x0800, // Mem + /*AVR16DU32*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR16DU32*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR16DU32*/ 4, ports_avr16du32, WDT_AVR8X}, // Ports, WDT + + //AVR32DU14 atdf, avrdude // Sources + {"AVR32DU14", 390, F_AVR8X, {0x1E, 0x95, 0x4F}, // ID + /*AVR32DU14*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DU14*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR32DU14*/ 370, rgftab_avr16du14, 2, UART_AVR8X, 3, uarts_avr16du14, // Register file, UART + /*AVR32DU14*/ 4, ports_avr16du14, WDT_AVR8X}, // Ports, WDT + + //AVR32DU20 atdf, avrdude // Sources + {"AVR32DU20", 391, F_AVR8X, {0x1E, 0x95, 0x4E}, // ID + /*AVR32DU20*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DU20*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR32DU20*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR32DU20*/ 4, ports_avr16du20, WDT_AVR8X}, // Ports, WDT + + //AVR32DU28 atdf, avrdude // Sources + {"AVR32DU28", 392, F_AVR8X, {0x1E, 0x95, 0x40}, // ID + /*AVR32DU28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DU28*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR32DU28*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR32DU28*/ 4, ports_avr16du28, WDT_AVR8X}, // Ports, WDT + + //AVR32DU32 atdf, avrdude // Sources + {"AVR32DU32", 393, F_AVR8X, {0x1E, 0x95, 0x3F}, // ID + /*AVR32DU32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32DU32*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR32DU32*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR32DU32*/ 4, ports_avr16du32, WDT_AVR8X}, // Ports, WDT + + //AVR64DU28 atdf, avrdude // Sources + {"AVR64DU28", 384, F_AVR8X, {0x1E, 0x96, 0x22}, // ID + /*AVR64DU28*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem + /*AVR64DU28*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR64DU28*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR64DU28*/ 4, ports_avr16du28, WDT_AVR8X}, // Ports, WDT + + //AVR64DU32 atdf, avrdude // Sources + {"AVR64DU32", 385, F_AVR8X, {0x1E, 0x96, 0x21}, // ID + /*AVR64DU32*/ 0, 0x10000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x6000, 0x2000, // Mem + /*AVR64DU32*/ 16, 4, 34, vtab_avr16du14, 20, cfgtab_avr16du14, // ISRs, Config + /*AVR64DU32*/ 371, rgftab_avr16du20, 2, UART_AVR8X, 5, uarts_avr16du20, // Register file, UART + /*AVR64DU32*/ 4, ports_avr16du32, WDT_AVR8X}, // Ports, WDT + + //AVR8EA28 avrdude // Sources + {"AVR8EA28", 327, F_AVR8X, {0x1E, 0x93, 0x2C}, // ID + /*AVR8EA28*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, -1, -1, // Mem + /*AVR8EA28*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AVR8EA28*/ 0, NULL, 0, UART_AVR8X, -1, NULL, // Register file, UART + /*AVR8EA28*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT + + //AVR8EA32 avrdude // Sources + {"AVR8EA32", 328, F_AVR8X, {0x1E, 0x93, 0x2B}, // ID + /*AVR8EA32*/ 0, 0x02000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, -1, -1, // Mem + /*AVR8EA32*/ -1, -1, 0, NULL, 0, NULL, // ISRs, Config + /*AVR8EA32*/ 0, NULL, 0, UART_AVR8X, -1, NULL, // Register file, UART + /*AVR8EA32*/ -1, NULL, WDT_UNKNOWN}, // Ports, WDT + + //AVR16EA28 atdf, avrdude // Sources + {"AVR16EA28", 332, F_AVR8X, {0x1E, 0x94, 0x37}, // ID + /*AVR16EA28*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EA28*/ 16, 4, 43, vtab_avr16ea28, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR16EA28*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART + /*AVR16EA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR16EA32 atdf, avrdude // Sources + {"AVR16EA32", 334, F_AVR8X, {0x1E, 0x94, 0x36}, // ID + /*AVR16EA32*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EA32*/ 16, 4, 43, vtab_avr16ea28, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR16EA32*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART + /*AVR16EA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR16EA48 atdf, avrdude // Sources + {"AVR16EA48", 335, F_AVR8X, {0x1E, 0x94, 0x35}, // ID + /*AVR16EA48*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EA48*/ 16, 4, 45, vtab_avr16ea48, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR16EA48*/ 502, rgftab_avr16ea48, 3, UART_AVR8X, 10, uarts_avr16ea48, // Register file, UART + /*AVR16EA48*/ 6, ports_avr16ea48, WDT_AVR8X}, // Ports, WDT + + //AVR32EA28 atdf, avrdude // Sources + {"AVR32EA28", 341, F_AVR8X, {0x1E, 0x95, 0x3E}, // ID + /*AVR32EA28*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem + /*AVR32EA28*/ 16, 4, 43, vtab_avr16ea28, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR32EA28*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART + /*AVR32EA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR32EA32 atdf, avrdude // Sources + {"AVR32EA32", 345, F_AVR8X, {0x1E, 0x95, 0x3D}, // ID + /*AVR32EA32*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem + /*AVR32EA32*/ 16, 4, 43, vtab_avr16ea28, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR32EA32*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART + /*AVR32EA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR32EA48 atdf, avrdude // Sources + {"AVR32EA48", 348, F_AVR8X, {0x1E, 0x95, 0x3C}, // ID + /*AVR32EA48*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7000, 0x1000, // Mem + /*AVR32EA48*/ 16, 4, 45, vtab_avr16ea48, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR32EA48*/ 502, rgftab_avr16ea48, 3, UART_AVR8X, 10, uarts_avr16ea48, // Register file, UART + /*AVR32EA48*/ 6, ports_avr16ea48, WDT_AVR8X}, // Ports, WDT + + //AVR64EA28 atdf, avrdude // Sources + {"AVR64EA28", 354, F_AVR8X, {0x1E, 0x96, 0x20}, // ID + /*AVR64EA28*/ 0, 0x10000, 0x080, 1, 0x0100, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem + /*AVR64EA28*/ 16, 4, 43, vtab_avr16ea28, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR64EA28*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART + /*AVR64EA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR64EA32 atdf, avrdude // Sources + {"AVR64EA32", 358, F_AVR8X, {0x1E, 0x96, 0x1F}, // ID + /*AVR64EA32*/ 0, 0x10000, 0x080, 1, 0x0100, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem + /*AVR64EA32*/ 16, 4, 43, vtab_avr16ea28, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR64EA32*/ 444, rgftab_avr16ea28, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART + /*AVR64EA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR64EA48 atdf, avrdude // Sources + {"AVR64EA48", 361, F_AVR8X, {0x1E, 0x96, 0x1E}, // ID + /*AVR64EA48*/ 0, 0x10000, 0x080, 1, 0x0100, 0x01400, 0x0200, 8, 0x6800, 0x1800, // Mem + /*AVR64EA48*/ 16, 4, 45, vtab_avr16ea48, 16, cfgtab_avr16ea28, // ISRs, Config + /*AVR64EA48*/ 502, rgftab_avr16ea48, 3, UART_AVR8X, 10, uarts_avr16ea48, // Register file, UART + /*AVR64EA48*/ 6, ports_avr16ea48, WDT_AVR8X}, // Ports, WDT + + //AVR16EB14 atdf, avrdude // Sources + {"AVR16EB14", 380, F_AVR8X, {0x1E, 0x94, 0x49}, // ID + /*AVR16EB14*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EB14*/ 16, 4, 31, vtab_avr16eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB14*/ 390, rgftab_avr16eb14, 1, UART_AVR8X, 4, uarts_avr16eb14, // Register file, UART + /*AVR16EB14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT + + //AVR16EB20 atdf, avrdude // Sources + {"AVR16EB20", 381, F_AVR8X, {0x1E, 0x94, 0x40}, // ID + /*AVR16EB20*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EB20*/ 16, 4, 31, vtab_avr16eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB20*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART + /*AVR16EB20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT + + //AVR16EB28 atdf, avrdude // Sources + {"AVR16EB28", 382, F_AVR8X, {0x1E, 0x94, 0x3F}, // ID + /*AVR16EB28*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EB28*/ 16, 4, 31, vtab_avr16eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB28*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART + /*AVR16EB28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR16EB32 atdf, avrdude // Sources + {"AVR16EB32", 383, F_AVR8X, {0x1E, 0x94, 0x3E}, // ID + /*AVR16EB32*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16EB32*/ 16, 4, 31, vtab_avr16eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR16EB32*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART + /*AVR16EB32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR32EB14 atdf, avrdude // Sources + {"AVR32EB14", 398, F_AVR8X, {0x1E, 0x95, 0x2D}, // ID + /*AVR32EB14*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem + /*AVR32EB14*/ 16, 4, 31, vtab_avr32eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR32EB14*/ 390, rgftab_avr16eb14, 1, UART_AVR8X, 4, uarts_avr16eb14, // Register file, UART + /*AVR32EB14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT + + //AVR32EB20 atdf, avrdude // Sources + {"AVR32EB20", 399, F_AVR8X, {0x1E, 0x95, 0x2C}, // ID + /*AVR32EB20*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem + /*AVR32EB20*/ 16, 4, 31, vtab_avr32eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR32EB20*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART + /*AVR32EB20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT + + //AVR32EB28 atdf, avrdude // Sources + {"AVR32EB28", 400, F_AVR8X, {0x1E, 0x95, 0x2B}, // ID + /*AVR32EB28*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem + /*AVR32EB28*/ 16, 4, 31, vtab_avr32eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR32EB28*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART + /*AVR32EB28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR32EB32 atdf, avrdude // Sources + {"AVR32EB32", 401, F_AVR8X, {0x1E, 0x95, 0x2A}, // ID + /*AVR32EB32*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7400, 0x0c00, // Mem + /*AVR32EB32*/ 16, 4, 31, vtab_avr32eb14, 18, cfgtab_avr16eb14, // ISRs, Config + /*AVR32EB32*/ 391, rgftab_avr16eb20, 1, UART_AVR8X, 6, uarts_avr16eb20, // Register file, UART + /*AVR32EB32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR16LA14 atdf // Sources + {"AVR16LA14", 414, F_AVR8X, {0x1E, 0x94, 0x54}, // ID + /*AVR16LA14*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16LA14*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR16LA14*/ 339, rgftab_avr16la14, 1, UART_AVR8X, 3, uarts_avr16la14, // Register file, UART + /*AVR16LA14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT + + //AVR16LA20 atdf // Sources + {"AVR16LA20", 415, F_AVR8X, {0x1E, 0x94, 0x53}, // ID + /*AVR16LA20*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16LA20*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR16LA20*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART + /*AVR16LA20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT + + //AVR16LA28 atdf // Sources + {"AVR16LA28", 416, F_AVR8X, {0x1E, 0x94, 0x52}, // ID + /*AVR16LA28*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16LA28*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR16LA28*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART + /*AVR16LA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR16LA32 atdf // Sources + {"AVR16LA32", 417, F_AVR8X, {0x1E, 0x94, 0x51}, // ID + /*AVR16LA32*/ 0, 0x04000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR16LA32*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR16LA32*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART + /*AVR16LA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR32LA14 atdf // Sources + {"AVR32LA14", 418, F_AVR8X, {0x1E, 0x95, 0x29}, // ID + /*AVR32LA14*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR32LA14*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR32LA14*/ 339, rgftab_avr16la14, 1, UART_AVR8X, 3, uarts_avr16la14, // Register file, UART + /*AVR32LA14*/ 4, ports_avr16eb14, WDT_AVR8X}, // Ports, WDT + + //AVR32LA20 atdf // Sources + {"AVR32LA20", 419, F_AVR8X, {0x1E, 0x95, 0x60}, // ID + /*AVR32LA20*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR32LA20*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR32LA20*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART + /*AVR32LA20*/ 4, ports_avr16eb20, WDT_AVR8X}, // Ports, WDT + + //AVR32LA28 atdf // Sources + {"AVR32LA28", 420, F_AVR8X, {0x1E, 0x95, 0x59}, // ID + /*AVR32LA28*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR32LA28*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR32LA28*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART + /*AVR32LA28*/ 4, ports_avr16ea28, WDT_AVR8X}, // Ports, WDT + + //AVR32LA32 atdf // Sources + {"AVR32LA32", 421, F_AVR8X, {0x1E, 0x95, 0x58}, // ID + /*AVR32LA32*/ 0, 0x08000, 0x040, 1, 0x0100, 0x01400, 0x0200, 8, 0x7800, 0x0800, // Mem + /*AVR32LA32*/ 12, 4, 29, vtab_avr16la14, 20, cfgtab_avr16la14, // ISRs, Config + /*AVR32LA32*/ 341, rgftab_avr16la20, 1, UART_AVR8X, 5, uarts_avr16la20, // Register file, UART + /*AVR32LA32*/ 4, ports_avr16ea32, WDT_AVR8X}, // Ports, WDT + + //AVR32SD20 atdf, avrdude // Sources + {"AVR32SD20", 402, F_AVR8X, {0x1E, 0x95, 0x54}, // ID + /*AVR32SD20*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32SD20*/ 16, 4, 50, vtab_avr32sd20, 18, cfgtab_avr32sd20, // ISRs, Config + /*AVR32SD20*/ 540, rgftab_avr32sd20, 2, UART_AVR8X, 7, uarts_avr16dd20, // Register file, UART + /*AVR32SD20*/ 4, ports_avr16dd20, WDT_AVR8X_DUAL}, // Ports, WDT + + //AVR32SD28 atdf, avrdude // Sources + {"AVR32SD28", 403, F_AVR8X, {0x1E, 0x95, 0x53}, // ID + /*AVR32SD28*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32SD28*/ 16, 4, 54, vtab_avr32sd28, 18, cfgtab_avr32sd20, // ISRs, Config + /*AVR32SD28*/ 559, rgftab_avr32sd28, 3, UART_AVR8X, 8, uarts_avr16ea28, // Register file, UART + /*AVR32SD28*/ 4, ports_avr16dd28, WDT_AVR8X_DUAL}, // Ports, WDT + + //AVR32SD32 atdf, avrdude // Sources + {"AVR32SD32", 404, F_AVR8X, {0x1E, 0x95, 0x52}, // ID + /*AVR32SD32*/ 0, 0x08000, 0x200, 1, 0x0200, 0x01400, 0x0100, 1, 0x7000, 0x1000, // Mem + /*AVR32SD32*/ 16, 4, 56, vtab_avr32sd32, 18, cfgtab_avr32sd20, // ISRs, Config + /*AVR32SD32*/ 575, rgftab_avr32sd32, 3, UART_AVR8X, 9, uarts_avr16ea32, // Register file, UART + /*AVR32SD32*/ 4, ports_avr16dd32, WDT_AVR8X_DUAL}, // Ports, WDT }; // Interrupt vector table interrupt names -// ATtiny9 ATtiny4 -const char * const vtab_attiny9[vts_attiny9] = { +// ATtiny4 ATtiny9 +const char * const vtab_attiny4[vts_attiny4] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "PCINT0", // 2: Pin Change Interrupt 0 @@ -3116,8 +3117,8 @@ const char * const vtab_attiny9[vts_attiny9] = { "VLM", // 9: Vcc Voltage Level Monitor }; -// ATtiny10 ATtiny5 -const char * const vtab_attiny10[vts_attiny10] = { +// ATtiny5 ATtiny10 +const char * const vtab_attiny5[vts_attiny5] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "PCINT0", // 2: Pin Change Interrupt 0 @@ -3174,8 +3175,8 @@ const char * const vtab_attiny40[vts_attiny40] = { "QTRIP", // 17: Touch Sensing }; -// ATtiny104 ATtiny102 -const char * const vtab_attiny104[vts_attiny104] = { +// ATtiny102 ATtiny104 +const char * const vtab_attiny102[vts_attiny102] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "PCINT0", // 2: Pin Change Interrupt 0 @@ -3194,362 +3195,73 @@ const char * const vtab_attiny104[vts_attiny104] = { "USART_TXC", // 15: USART Transmit Complete }; -// ATtiny11 -const char * const vtab_attiny11[vts_attiny11] = { +// AT90S1200 +const char * const vtab_at90s1200[vts_at90s1200] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 - "IO_PINS", // 2: External Interrupt - "TIMER0_OVF", // 3: Timer 0 Overflow - "ANA_COMP", // 4: Analog Comparator + "TIMER0_OVF", // 2: Timer 0 Overflow + "ANA_COMP", // 3: Analog Comparator }; -// ATtiny12 -const char * const vtab_attiny12[vts_attiny12] = { +// AT90S2313 +const char * const vtab_at90s2313[vts_at90s2313] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 - "IO_PINS", // 2: External Interrupt - "TIMER0_OVF", // 3: Timer 0 Overflow - "EE_RDY", // 4: EEPROM Ready - "ANA_COMP", // 5: Analog Comparator + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT1", // 3: Timer 1 Capture Event + "TIMER1_COMP1", // 4: Timer 1 Compare + "TIMER1_OVF1", // 5: Timer 1 Overflow + "TIMER0_OVF0", // 6: Timer 0 Overflow + "UART_RX", // 7: UART Receive Complete + "UART_UDRE", // 8: UART Data Register Empty + "UART_TX", // 9: UART Transmit Complete + "ANA_COMP", // 10: Analog Comparator }; -// ATtiny13A ATtiny13 -const char * const vtab_attiny13a[vts_attiny13a] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "TIM0_OVF", // 3: Timer 0 Overflow - "EE_RDY", // 4: EEPROM Ready - "ANA_COMP", // 5: Analog Comparator - "TIM0_COMPA", // 6: Timer 0 Compare Match A - "TIM0_COMPB", // 7: Timer 0 Compare Match B - "WDT", // 8: Watchdog Time-out - "ADC", // 9: ADC Conversion Complete -}; - -// ATtiny15 -const char * const vtab_attiny15[vts_attiny15] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "IO_PINS", // 2: External Interrupt - "TIMER1_COMP", // 3: Timer 1 Compare - "TIMER1_OVF", // 4: Timer 1 Overflow - "TIMER0_OVF", // 5: Timer 0 Overflow - "EE_RDY", // 6: EEPROM Ready - "ANA_COMP", // 7: Analog Comparator - "ADC", // 8: ADC Conversion Complete -}; - -// ATtiny22 AT90S2343 AT90S2323 -const char * const vtab_attiny22[vts_attiny22] = { +// AT90S2323 AT90S2343 ATtiny22 +const char * const vtab_at90s2323[vts_at90s2323] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "TIMER0_OVF0", // 2: Timer 0 Overflow }; -// ATtiny26 -const char * const vtab_attiny26[vts_attiny26] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "IO_PINS", // 2: External Interrupt - "TIMER1_CMPA", // 3: Timer 1 Compare Match A - "TIMER1_CMPB", // 4: Timer 1 Compare Match B - "TIMER1_OVF1", // 5: Timer 1 Overflow - "TIMER0_OVF0", // 6: Timer 0 Overflow - "USI_STRT", // 7: USI Start Condition - "USI_OVF", // 8: USI Overflow - "EE_RDY", // 9: EEPROM Ready - "ANA_COMP", // 10: Analog Comparator - "ADC", // 11: ADC Conversion Complete -}; - -// ATtiny28 -const char * const vtab_attiny28[vts_attiny28] = { +// AT90S2333 AT90S4433 +const char * const vtab_at90s2333[vts_at90s2333] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 - "LOW_LEVEL_IO_PINS", // 3: Low-level Input - "TIMER0_OVF", // 4: Timer 0 Overflow - "ANA_COMP", // 5: Analog Comparator -}; - -// ATtiny43U -const char * const vtab_attiny43u[vts_attiny43u] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "WDT", // 4: Watchdog Time-out - "TIM1_COMPA", // 5: Timer 1 Compare Match A - "TIM1_COMPB", // 6: Timer 1 Compare Match B - "TIM1_OVF", // 7: Timer 1 Overflow - "TIM0_COMPA", // 8: Timer 0 Compare Match A - "TIM0_COMPB", // 9: Timer 0 Compare Match B - "TIM0_OVF", // 10: Timer 0 Overflow - "ANA_COMP", // 11: Analog Comparator - "ADC", // 12: ADC Conversion Complete - "EE_RDY", // 13: EEPROM Ready - "USI_START", // 14: USI Start Condition - "USI_OVF", // 15: USI Overflow -}; - -// ATtiny84A ATtiny84 ATtiny44A ATtiny44 ATtiny24A ATtiny24 -const char * const vtab_attiny84a[vts_attiny84a] = { - "RESET", // 0: Reset (various reasons) - "EXT_INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "WDT", // 4: Watchdog Time-out - "TIM1_CAPT", // 5: Timer 1 Capture Event - "TIM1_COMPA", // 6: Timer 1 Compare Match A - "TIM1_COMPB", // 7: Timer 1 Compare Match B - "TIM1_OVF", // 8: Timer 1 Overflow - "TIM0_COMPA", // 9: Timer 0 Compare Match A - "TIM0_COMPB", // 10: Timer 0 Compare Match B - "TIM0_OVF", // 11: Timer 0 Overflow - "ANA_COMP", // 12: Analog Comparator - "ADC", // 13: ADC Conversion Complete - "EE_RDY", // 14: EEPROM Ready - "USI_STR", // 15: USI Start Condition - "USI_OVF", // 16: USI Overflow -}; - -// ATtiny85 ATtiny45 ATtiny25 -const char * const vtab_attiny85[vts_attiny85] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "TIMER1_COMPA", // 3: Timer 1 Compare Match A - "TIMER1_OVF", // 4: Timer 1 Overflow - "TIMER0_OVF", // 5: Timer 0 Overflow - "EE_RDY", // 6: EEPROM Ready - "ANA_COMP", // 7: Analog Comparator - "ADC", // 8: ADC Conversion Complete - "TIMER1_COMPB", // 9: Timer 1 Compare Match B - "TIMER0_COMPA", // 10: Timer 0 Compare Match A - "TIMER0_COMPB", // 11: Timer 0 Compare Match B - "WDT", // 12: Watchdog Time-out - "USI_START", // 13: USI Start Condition - "USI_OVF", // 14: USI Overflow -}; - -// ATtiny88 ATtiny48 -const char * const vtab_attiny88[vts_attiny88] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "PCINT2", // 5: Pin Change Interrupt 2 - "PCINT3", // 6: Pin Change Interrupt 3 - "WDT", // 7: Watchdog Time-out - "TIMER1_CAPT", // 8: Timer 1 Capture Event - "TIMER1_COMPA", // 9: Timer 1 Compare Match A - "TIMER1_COMPB", // 10: Timer 1 Compare Match B - "TIMER1_OVF", // 11: Timer 1 Overflow - "TIMER0_COMPA", // 12: Timer 0 Compare Match A - "TIMER0_COMPB", // 13: Timer 0 Compare Match B - "TIMER0_OVF", // 14: Timer 0 Overflow - "SPI_STC", // 15: SPI Serial Transfer Complete - "ADC", // 16: ADC Conversion Complete - "EE_RDY", // 17: EEPROM Ready - "ANALOG_COMP", // 18: Analog Comparator - "TWI", // 19: 2-Wire Interface -}; - -// ATtiny167 ATtiny87 ATA664251 ATA6617C ATA6616C ATA5505 -const char * const vtab_attiny167[vts_attiny167] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "WDT", // 5: Watchdog Time-out - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMPA", // 10: Timer 0 Compare Match A - "TIMER0_OVF", // 11: Timer 0 Overflow - "LIN_TC", // 12: LIN Transfer Complete - "LIN_ERR", // 13: LIN Error - "SPI_STC", // 14: SPI Serial Transfer Complete - "ADC", // 15: ADC Conversion Complete - "EE_RDY", // 16: EEPROM Ready - "ANA_COMP", // 17: Analog Comparator - "USI_START", // 18: USI Start Condition - "USI_OVF", // 19: USI Overflow -}; - -// ATtiny828R ATtiny828 -const char * const vtab_attiny828r[vts_attiny828r] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "PCINT2", // 5: Pin Change Interrupt 2 - "PCINT3", // 6: Pin Change Interrupt 3 - "WDT", // 7: Watchdog Time-out - "TIMER1_CAPT", // 8: Timer 1 Capture Event - "TIMER1_COMPA", // 9: Timer 1 Compare Match A - "TIMER1_COMPB", // 10: Timer 1 Compare Match B - "TIMER1_OVF", // 11: Timer 1 Overflow - "TIMER0_COMPA", // 12: Timer 0 Compare Match A - "TIMER0_COMPB", // 13: Timer 0 Compare Match B - "TIMER0_OVF", // 14: Timer 0 Overflow - "SPI_STC", // 15: SPI Serial Transfer Complete - "USART_START", // 16: USART Start - "USART_RX", // 17: USART Receive Complete - "USART_UDRE", // 18: USART Data Register Empty - "USART_TX", // 19: USART Transmit Complete - "ADC", // 20: ADC Conversion Complete - "EE_READY", // 21: EEPROM Ready - "ANALOG_COMP", // 22: Analog Comparator - "TWI_PERIPHERAL", // 23: 2-Wire Interface Peripheral - "SPM_Ready", // 24: Store Program Memory Ready - "QTRIP", // 25: Touch Sensing -}; - -// ATtiny841 ATtiny441 -const char * const vtab_attiny841[vts_attiny841] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "WDT", // 4: Watchdog Time-out - "TIMER1_CAPT", // 5: Timer 1 Capture Event - "TIMER1_COMPA", // 6: Timer 1 Compare Match A - "TIMER1_COMPB", // 7: Timer 1 Compare Match B - "TIMER1_OVF", // 8: Timer 1 Overflow - "TIMER0_COMPA", // 9: Timer 0 Compare Match A - "TIMER0_COMPB", // 10: Timer 0 Compare Match B - "TIMER0_OVF", // 11: Timer 0 Overflow - "ANA_COMP0", // 12: Analog Comparator 0 - "ADC", // 13: ADC Conversion Complete - "EE_RDY", // 14: EEPROM Ready - "ANA_COMP1", // 15: Analog Comparator 1 - "TIMER2_CAPT", // 16: Timer 2 Capture Event - "TIMER2_COMPA", // 17: Timer 2 Compare Match A - "TIMER2_COMPB", // 18: Timer 2 Compare Match B - "TIMER2_OVF", // 19: Timer 2 Overflow - "SPI", // 20: SPI Serial Peripheral Interface - "USART0_START", // 21: USART 0 Receive Start - "USART0_RX", // 22: USART 0 Receive Complete - "USART0_UDRE", // 23: USART 0 Data Register Empty - "USART0_TX", // 24: USART 0 Transmit Complete - "USART1_START", // 25: USART 1 Receive Start - "USART1_RX", // 26: USART 1 Receive Complete - "USART1_UDRE", // 27: USART 1 Data Register Empty - "USART1_TX", // 28: USART 1 Transmit Complete - "TWI_PERIPHERAL", // 29: 2-Wire Interface Peripheral -}; - -// ATtiny861A ATtiny861 ATtiny461A ATtiny461 ATtiny261A ATtiny261 -const char * const vtab_attiny861a[vts_attiny861a] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT", // 2: Pin Change Interrupt - "TIMER1_COMPA", // 3: Timer 1 Compare Match A - "TIMER1_COMPB", // 4: Timer 1 Compare Match B + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMP", // 4: Timer 1 Compare "TIMER1_OVF", // 5: Timer 1 Overflow "TIMER0_OVF", // 6: Timer 0 Overflow - "USI_START", // 7: USI Start Condition - "USI_OVF", // 8: USI Overflow - "EE_RDY", // 9: EEPROM Ready - "ANA_COMP", // 10: Analog Comparator + "SPI_STC", // 7: SPI Serial Transfer Complete + "UART_RX", // 8: UART Receive Complete + "UART_UDRE", // 9: UART Data Register Empty + "UART_TX", // 10: UART Transmit Complete "ADC", // 11: ADC Conversion Complete - "WDT", // 12: Watchdog Time-out - "INT1", // 13: External Interrupt 1 - "TIMER0_COMPA", // 14: Timer 0 Compare Match A - "TIMER0_COMPB", // 15: Timer 0 Compare Match B - "TIMER0_CAPT", // 16: Timer 0 Capture Event - "TIMER1_COMPD", // 17: Timer 1 Compare Match D - "FAULT_PROTECTION", // 18: Timer 1 Fault Protection -}; - -// ATtiny1634R ATtiny1634 -const char * const vtab_attiny1634r[vts_attiny1634r] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "PCINT2", // 4: Pin Change Interrupt 2 - "WDT", // 5: Watchdog Time-out - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMPA", // 10: Timer 0 Compare Match A - "TIMER0_COMPB", // 11: Timer 0 Compare Match B - "TIMER0_OVF", // 12: Timer 0 Overflow + "EE_RDY", // 12: EEPROM Ready "ANA_COMP", // 13: Analog Comparator - "ADC_READY", // 14: ADC Conversion Complete - "USART0_START", // 15: USART 0 Receive Start - "USART0_RXC", // 16: USART 0 Receive Complete - "USART0_UDRE", // 17: USART 0 Data Register Empty - "USART0_TXC", // 18: USART 0 Transmit Complete - "USART1_START", // 19: USART 1 Receive Start - "USART1_RXC", // 20: USART 1 Receive Complete - "USART1_UDRE", // 21: USART 1 Data Register Empty - "USART1_TXC", // 22: USART 1 Transmit Complete - "USI_START", // 23: USI Start Condition - "USI_OVERFLOW", // 24: USI Overflow - "TWI/TWI_PERIPHERAL", // 25: 2-Wire Interface/2-Wire Interface Peripheral - "EE_RDY", // 26: EEPROM Ready - "QTRIP", // 27: Touch Sensing }; -// ATtiny2313 -const char * const vtab_attiny2313[vts_attiny2313] = { +// AT90S4414 AT90S8515 +const char * const vtab_at90s4414[vts_at90s4414] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 "TIMER1_CAPT", // 3: Timer 1 Capture Event "TIMER1_COMPA", // 4: Timer 1 Compare Match A - "TIMER1_OVF", // 5: Timer 1 Overflow - "TIMER0_OVF", // 6: Timer 0 Overflow - "USART_RX", // 7: USART Receive Complete - "USART_UDRE", // 8: USART Data Register Empty - "USART_TX", // 9: USART Transmit Complete - "ANA_COMP", // 10: Analog Comparator - "PCINT", // 11: Pin Change Interrupt - "TIMER1_COMPB", // 12: Timer 1 Compare Match B - "TIMER0_COMPA", // 13: Timer 0 Compare Match A - "TIMER0_COMPB", // 14: Timer 0 Compare Match B - "USI_START", // 15: USI Start Condition - "USI_OVERFLOW", // 16: USI Overflow - "EEPROM_Ready", // 17: EEPROM Ready - "WDT_OVERFLOW", // 18: Watchdog Timer Overflow + "TIMER1_COMPB", // 5: Timer 1 Compare Match B + "TIMER1_OVF", // 6: Timer 1 Overflow + "TIMER0_OVF", // 7: Timer 0 Overflow + "SPI_STC", // 8: SPI Serial Transfer Complete + "UART_RX", // 9: UART Receive Complete + "UART_UDRE", // 10: UART Data Register Empty + "UART_TX", // 11: UART Transmit Complete + "ANA_COMP", // 12: Analog Comparator }; -// ATtiny4313 ATtiny2313A -const char * const vtab_attiny4313[vts_attiny4313] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "TIMER1_CAPT", // 3: Timer 1 Capture Event - "TIMER1_COMPA", // 4: Timer 1 Compare Match A - "TIMER1_OVF", // 5: Timer 1 Overflow - "TIMER0_OVF", // 6: Timer 0 Overflow - "USART_RX", // 7: USART Receive Complete - "USART_UDRE", // 8: USART Data Register Empty - "USART_TX", // 9: USART Transmit Complete - "ANA_COMP", // 10: Analog Comparator - "PCINT_B", // 11: Pin Change Interrupt B - "TIMER1_COMPB", // 12: Timer 1 Compare Match B - "TIMER0_COMPA", // 13: Timer 0 Compare Match A - "TIMER0_COMPB", // 14: Timer 0 Compare Match B - "USI_START", // 15: USI Start Condition - "USI_OVERFLOW", // 16: USI Overflow - "EEPROM_Ready", // 17: EEPROM Ready - "WDT_OVERFLOW", // 18: Watchdog Timer Overflow - "PCINT_A", // 19: Pin Change Interrupt A - "PCINT_D", // 20: Pin Change Interrupt D -}; - -// ATmega8A ATmega8 -const char * const vtab_atmega8a[vts_atmega8a] = { +// AT90S4434 AT90S8535 +const char * const vtab_at90s4434[vts_at90s4434] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -3561,127 +3273,225 @@ const char * const vtab_atmega8a[vts_atmega8a] = { "TIMER1_OVF", // 8: Timer 1 Overflow "TIMER0_OVF", // 9: Timer 0 Overflow "SPI_STC", // 10: SPI Serial Transfer Complete - "USART_RXC", // 11: USART Receive Complete - "USART_UDRE", // 12: USART Data Register Empty - "USART_TXC", // 13: USART Transmit Complete + "UART_RX", // 11: UART Receive Complete + "UART_UDRE", // 12: UART Data Register Empty + "UART_TX", // 13: UART Transmit Complete "ADC", // 14: ADC Conversion Complete "EE_RDY", // 15: EEPROM Ready "ANA_COMP", // 16: Analog Comparator - "TWI", // 17: 2-Wire Interface - "SPM_RDY", // 18: Store Program Memory Ready }; -// ATmega16A ATmega16 -const char * const vtab_atmega16a[vts_atmega16a] = { +// AT90CAN32 AT90CAN64 AT90CAN128 +const char * const vtab_at90can32[vts_at90can32] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 - "TIMER2_COMP", // 3: Timer 2 Compare Match - "TIMER2_OVF", // 4: Timer 2 Overflow - "TIMER1_CAPT", // 5: Timer 1 Capture Event - "TIMER1_COMPA", // 6: Timer 1 Compare Match A - "TIMER1_COMPB", // 7: Timer 1 Compare Match B - "TIMER1_OVF", // 8: Timer 1 Overflow - "TIMER0_OVF", // 9: Timer 0 Overflow - "SPI_STC", // 10: SPI Serial Transfer Complete - "USART_RXC", // 11: USART Receive Complete - "USART_UDRE", // 12: USART Data Register Empty - "USART_TXC", // 13: USART Transmit Complete - "ADC", // 14: ADC Conversion Complete - "EE_RDY", // 15: EEPROM Ready - "ANA_COMP", // 16: Analog Comparator - "TWI", // 17: 2-Wire Interface - "INT2", // 18: External Interrupt 2 - "TIMER0_COMP", // 19: Timer 0 Compare Match - "SPM_RDY", // 20: Store Program Memory Ready -}; - -// ATmega16HVA ATmega8HVA -const char * const vtab_atmega16hva[vts_atmega16hva] = { - "RESET", // 0: Reset (various reasons) - "BPINT", // 1: Battery Protection Interrupt - "VREGMON", // 2: Voltage Regulator Monitor - "INT0", // 3: External Interrupt 0 - "INT1", // 4: External Interrupt 1 - "INT2", // 5: External Interrupt 2 - "WDT", // 6: Watchdog Time-out - "TIMER1_IC", // 7: Timer 1 Input Capture - "TIMER1_COMPA", // 8: Timer 1 Compare Match A - "TIMER1_COMPB", // 9: Timer 1 Compare Match B - "TIMER1_OVF", // 10: Timer 1 Overflow - "TIMER0_IC", // 11: Timer 0 Capture Event - "TIMER0_COMPA", // 12: Timer 0 Compare Match A - "TIMER0_COMPB", // 13: Timer 0 Compare Match B - "TIMER0_OVF", // 14: Timer 0 Overflow - "SPI_STC", // 15: SPI Serial Transfer Complete - "VADC", // 16: Voltage ADC Conversion Complete - "CCADC_CONV", // 17: Coulomb Counter ADC Conversion Complete - "CCADC_REG_CUR", // 18: Coloumb Counter ADC Regular Current - "CCADC_ACC", // 19: Coloumb Counter ADC Accumulator - "EE_READY", // 20: EEPROM Ready -}; - -// ATmega16HVA2 -const char * const vtab_atmega16hva2[vts_atmega16hva2] = { - "RESET", // 0: Reset (various reasons) - "BPINT", // 1: Battery Protection Interrupt - "VREGMON", // 2: Voltage Regulator Monitor - "INT0", // 3: External Interrupt 0 - "INT1", // 4: External Interrupt 1 - "INT2", // 5: External Interrupt 2 - "PCINT0", // 6: Pin Change Interrupt 0 - "WDT", // 7: Watchdog Time-out - "TIMER1_IC", // 8: Timer 1 Input Capture - "TIMER1_COMPA", // 9: Timer 1 Compare Match A - "TIMER1_COMPB", // 10: Timer 1 Compare Match B - "TIMER1_OVF", // 11: Timer 1 Overflow - "TIMER0_IC", // 12: Timer 0 Capture Event - "TIMER0_COMPA", // 13: Timer 0 Compare Match A - "TIMER0_COMPB", // 14: Timer 0 Compare Match B - "TIMER0_OVF", // 15: Timer 0 Overflow - "SPI_STC", // 16: SPI Serial Transfer Complete - "VADC", // 17: Voltage ADC Conversion Complete - "CCADC_CONV", // 18: Coulomb Counter ADC Conversion Complete - "CCADC_REG_CUR", // 19: Coloumb Counter ADC Regular Current - "CCADC_ACC", // 20: Coloumb Counter ADC Accumulator - "EE_READY", // 21: EEPROM Ready -}; - -// ATmega32HVBrevB ATmega32HVB ATmega16HVBrevB ATmega16HVB -const char * const vtab_atmega32hvbrevb[vts_atmega32hvbrevb] = { - "RESET", // 0: Reset (various reasons) - "BPINT", // 1: Battery Protection Interrupt - "VREGMON", // 2: Voltage Regulator Monitor - "INT0", // 3: External Interrupt 0 - "INT1", // 4: External Interrupt 1 - "INT2", // 5: External Interrupt 2 - "INT3", // 6: External Interrupt 3 - "PCINT0", // 7: Pin Change Interrupt 0 - "PCINT1", // 8: Pin Change Interrupt 1 - "WDT", // 9: Watchdog Time-out - "BGSCD", // 10: Bandgap Buffer Short Circuit Detected - "CHDET", // 11: Charger Detect - "TIMER1_IC", // 12: Timer 1 Input Capture - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "TIMER2_COMP", // 9: Timer 2 Compare Match + "TIMER2_OVF", // 10: Timer 2 Overflow + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "TIMER1_COMPC", // 14: Timer 1 Compare Match C "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_IC", // 16: Timer 0 Capture Event - "TIMER0_COMPA", // 17: Timer 0 Compare Match A - "TIMER0_COMPB", // 18: Timer 0 Compare Match B - "TIMER0_OVF", // 19: Timer 0 Overflow - "TWIBUSCD", // 20: 2-Wire Interface Bus Connect/Disconnect - "TWI", // 21: 2-Wire Interface - "SPI_STC", // 22: SPI Serial Transfer Complete - "VADC", // 23: Voltage ADC Conversion Complete - "CCADC_CONV", // 24: Coulomb Counter ADC Conversion Complete - "CCADC_REG_CUR", // 25: Coloumb Counter ADC Regular Current - "CCADC_ACC", // 26: Coloumb Counter ADC Accumulator - "EE_READY", // 27: EEPROM Ready - "SPM", // 28: SPM Ready + "TIMER0_COMP", // 16: Timer 0 Compare Match + "TIMER0_OVF", // 17: Timer 0 Overflow + "CANIT", // 18: CAN Transfer Complete or Error + "OVRIT", // 19: CAN Timer Overrun + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART0_RX", // 21: USART 0 Receive Complete + "USART0_UDRE", // 22: USART 0 Data Register Empty + "USART0_TX", // 23: USART 0 Transmit Complete + "ANALOG_COMP", // 24: Analog Comparator + "ADC", // 25: ADC Conversion Complete + "EE_READY", // 26: EEPROM Ready + "TIMER3_CAPT", // 27: Timer 3 Capture Event + "TIMER3_COMPA", // 28: Timer 3 Compare Match A + "TIMER3_COMPB", // 29: Timer 3 Compare Match B + "TIMER3_COMPC", // 30: Timer 3 Compare Match C + "TIMER3_OVF", // 31: Timer 3 Overflow + "USART1_RX", // 32: USART 1 Receive Complete + "USART1_UDRE", // 33: USART 1 Data Register Empty + "USART1_TX", // 34: USART 1 Transmit Complete + "TWI", // 35: 2-Wire Interface + "SPM_READY", // 36: Store Program Memory Ready }; -// ATmega32U2 ATmega16U2 ATmega8U2 AT90USB162 AT90USB82 -const char * const vtab_atmega32u2[vts_atmega32u2] = { +// AT90PWM1 +const char * const vtab_at90pwm1[vts_at90pwm1] = { + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "RESERVED15", // 14: Reserved 15 + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP_A", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "RESERVED21", // 21: Reserved 21 + "RESERVED22", // 22: Reserved 22 + "RESERVED23", // 23: Reserved 23 + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "RESERVED30", // 29: Reserved 30 + "RESERVED31", // 30: Reserved 31 + "SPM_READY", // 31: Store Program Memory Ready +}; + +// AT90PWM81 AT90PWM161 +const char * const vtab_at90pwm81[vts_at90pwm81] = { + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC2_EEC", // 3: PSC 2 End Of Enhanced Cycle + "PSC0_CAPT", // 4: PSC 0 Capture Event + "PSC0_EC", // 5: PSC 0 End Cycle + "PSC0_EEC", // 6: PSC 0 End Of Enhanced Cycle + "ANALOG_COMP_1", // 7: Analog Comparator 1 + "ANALOG_COMP_2", // 8: Analog Comparator 2 + "ANALOG_COMP_3", // 9: Analog Comparator 3 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_OVF", // 12: Timer 1 Overflow + "ADC", // 13: ADC Conversion Complete + "INT1", // 14: External Interrupt 1 + "SPI_STC", // 15: SPI Serial Transfer Complete + "INT2", // 16: External Interrupt 2 + "WDT", // 17: Watchdog Time-out + "EE_READY", // 18: EEPROM Ready + "SPM_READY", // 19: Store Program Memory Ready +}; + +// AT90PWM2 +const char * const vtab_at90pwm2[vts_at90pwm2] = { + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "UNUSED", // 14: not implemented on this device + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP_A", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART_RX", // 21: USART Receive Complete + "USART_UDRE", // 22: USART Data Register Empty + "USART_TX", // 23: USART Transmit Complete + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "SPM_READY", // 31: Store Program Memory Ready +}; + +// AT90PWM2B AT90PWM3 AT90PWM3B +const char * const vtab_at90pwm2b[vts_at90pwm2b] = { + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "RESERVED15", // 14: Reserved 15 + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART_RX", // 21: USART Receive Complete + "USART_UDRE", // 22: USART Data Register Empty + "USART_TX", // 23: USART Transmit Complete + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "RESERVED30", // 29: Reserved 30 + "RESERVED31", // 30: Reserved 31 + "SPM_READY", // 31: Store Program Memory Ready +}; + +// AT90PWM216 AT90PWM316 +const char * const vtab_at90pwm216[vts_at90pwm216] = { + "RESET", // 0: Reset (various reasons) + "PSC2_CAPT", // 1: PSC 2 Capture Event + "PSC2_EC", // 2: PSC 2 End Cycle + "PSC1_CAPT", // 3: PSC 1 Capture Event + "PSC1_EC", // 4: PSC 1 End Cycle + "PSC0_CAPT", // 5: PSC 0 Capture Event + "PSC0_EC", // 6: PSC 0 End Cycle + "ANALOG_COMP_0", // 7: Analog Comparator 0 + "ANALOG_COMP_1", // 8: Analog Comparator 1 + "ANALOG_COMP_2", // 9: Analog Comparator 2 + "INT0", // 10: External Interrupt 0 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "RESERVED15", // 14: Reserved 15 + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP_A", // 16: Timer 0 Compare Match A + "TIMER0_OVF", // 17: Timer 0 Overflow + "ADC", // 18: ADC Conversion Complete + "INT1", // 19: External Interrupt 1 + "SPI_STC", // 20: SPI Serial Transfer Complete + "USART_RX", // 21: USART Receive Complete + "USART_UDRE", // 22: USART Data Register Empty + "USART_TX", // 23: USART Transmit Complete + "INT2", // 24: External Interrupt 2 + "WDT", // 25: Watchdog Time-out + "EE_READY", // 26: EEPROM Ready + "TIMER0_COMPB", // 27: Timer 0 Compare Match B + "INT3", // 28: External Interrupt 3 + "RESERVED30", // 29: Reserved 30 + "RESERVED31", // 30: Reserved 31 + "SPM_READY", // 31: Store Program Memory Ready +}; + +// AT90USB82 AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 +const char * const vtab_at90usb82[vts_at90usb82] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -3713,55 +3523,8 @@ const char * const vtab_atmega32u2[vts_atmega32u2] = { "SPM_READY", // 28: Store Program Memory Ready }; -// ATmega32U4 ATmega16U4 -const char * const vtab_atmega32u4[vts_atmega32u4] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "INT3", // 4: External Interrupt 3 - "Reserved1", // 5: Reserved 1 - "Reserved2", // 6: Reserved 2 - "INT6", // 7: External Interrupt 6 - "Reserved3", // 8: Reserved 3 - "PCINT0", // 9: Pin Change Interrupt 0 - "USB_GEN", // 10: USB General - "USB_COM", // 11: USB Endpoint/Pipe Interrupt Communication Request - "WDT", // 12: Watchdog Time-out - "Reserved4", // 13: Reserved 4 - "Reserved5", // 14: Reserved 5 - "Reserved6", // 15: Reserved 6 - "TIMER1_CAPT", // 16: Timer 1 Capture Event - "TIMER1_COMPA", // 17: Timer 1 Compare Match A - "TIMER1_COMPB", // 18: Timer 1 Compare Match B - "TIMER1_COMPC", // 19: Timer 1 Compare Match C - "TIMER1_OVF", // 20: Timer 1 Overflow - "TIMER0_COMPA", // 21: Timer 0 Compare Match A - "TIMER0_COMPB", // 22: Timer 0 Compare Match B - "TIMER0_OVF", // 23: Timer 0 Overflow - "SPI_STC", // 24: SPI Serial Transfer Complete - "USART1_RX", // 25: USART 1 Receive Complete - "USART1_UDRE", // 26: USART 1 Data Register Empty - "USART1_TX", // 27: USART 1 Transmit Complete - "ANALOG_COMP", // 28: Analog Comparator - "ADC", // 29: ADC Conversion Complete - "EE_READY", // 30: EEPROM Ready - "TIMER3_CAPT", // 31: Timer 3 Capture Event - "TIMER3_COMPA", // 32: Timer 3 Compare Match A - "TIMER3_COMPB", // 33: Timer 3 Compare Match B - "TIMER3_COMPC", // 34: Timer 3 Compare Match C - "TIMER3_OVF", // 35: Timer 3 Overflow - "TWI", // 36: 2-Wire Interface - "SPM_READY", // 37: Store Program Memory Ready - "TIMER4_COMPA", // 38: Timer 4 Compare Match A - "TIMER4_COMPB", // 39: Timer 4 Compare Match B - "TIMER4_COMPD", // 40: Timer 4 Compare Match D - "TIMER4_OVF", // 41: Timer 4 Overflow - "TIMER4_FPF", // 42: Timer 4 Fault Protection -}; - -// ATmega32U6 AT90USB1287 AT90USB1286 AT90USB647 AT90USB646 -const char * const vtab_atmega32u6[vts_atmega32u6] = { +// AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 ATmega32U6 +const char * const vtab_at90usb646[vts_at90usb646] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -3802,100 +3565,477 @@ const char * const vtab_atmega32u6[vts_atmega32u6] = { "SPM_READY", // 37: Store Program Memory Ready }; -// ATmega64M1 ATmegaS64M1 ATmega64C1 ATmega32M1 ATmega32C1 ATmega16M1 -const char * const vtab_atmega64m1[vts_atmega64m1] = { - "RESET", // 0: Reset (various reasons) - "ANACOMP0", // 1: Analog Comparator 0 - "ANACOMP1", // 2: Analog Comparator 1 - "ANACOMP2", // 3: Analog Comparator 2 - "ANACOMP3", // 4: Analog Comparator 3 - "PSC_FAULT", // 5: PSC Fault - "PSC_EC", // 6: PSC End of Cycle - "INT0", // 7: External Interrupt 0 - "INT1", // 8: External Interrupt 1 - "INT2", // 9: External Interrupt 2 - "INT3", // 10: External Interrupt 3 - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_COMPA", // 12: Timer 1 Compare Match A - "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "TIMER1_OVF", // 14: Timer 1 Overflow - "TIMER0_COMPA", // 15: Timer 0 Compare Match A - "TIMER0_COMPB", // 16: Timer 0 Compare Match B - "TIMER0_OVF", // 17: Timer 0 Overflow - "CAN_INT", // 18: CAN MOB, Burst, General Errors - "CAN_TOVF", // 19: CAN Timer Overflow - "LIN_TC", // 20: LIN Transfer Complete - "LIN_ERR", // 21: LIN Error - "PCINT0", // 22: Pin Change Interrupt 0 - "PCINT1", // 23: Pin Change Interrupt 1 - "PCINT2", // 24: Pin Change Interrupt 2 - "PCINT3", // 25: Pin Change Interrupt 3 - "SPI_STC", // 26: SPI Serial Transfer Complete - "ADC", // 27: ADC Conversion Complete - "WDT", // 28: Watchdog Time-out - "EE_READY", // 29: EEPROM Ready - "SPM_READY", // 30: Store Program Memory Ready -}; - -// ATmega64HVE2 ATmega64HVE ATmega32HVE2 -const char * const vtab_atmega64hve2[vts_atmega64hve2] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "WDT", // 4: Watchdog Time-out - "WAKEUP", // 5: Wake Up - "TIMER1_IC", // 6: Timer 1 Input Capture - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_IC", // 10: Timer 0 Capture Event - "TIMER0_COMPA", // 11: Timer 0 Compare Match A - "TIMER0_COMPB", // 12: Timer 0 Compare Match B - "TIMER0_OVF", // 13: Timer 0 Overflow - "LIN_STATUS", // 14: LIN Status Change - "LIN_ERROR", // 15: LIN Error - "SPI_STC", // 16: SPI Serial Transfer Complete - "VADC_CONV", // 17: Versatile Analog to Digital Conversion - "VADC_ACC", // 18: Versatile Analog to Digital Compare or Capture - "CADC_CONV", // 19: C-ADC Instantaneous Conversion Complete - "CADC_REG_CUR", // 20: C-ADC Regular Current - "CADC_ACC", // 21: C-ADC Accumulated Conversion Complete - "EE_READY", // 22: EEPROM Ready - "SPM", // 23: SPM Ready - "PLL", // 24: PLL -}; - -// ATmega103 -const char * const vtab_atmega103[vts_atmega103] = { +// AT90SCR100 AT90SCR100H +const char * const vtab_at90scr100[vts_at90scr100] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 "INT2", // 3: External Interrupt 2 "INT3", // 4: External Interrupt 3 - "INT4", // 5: External Interrupt 4 - "INT5", // 6: External Interrupt 5 - "INT6", // 7: External Interrupt 6 - "INT7", // 8: External Interrupt 7 - "TIMER2_COMP", // 9: Timer 2 Compare Match - "TIMER2_OVF", // 10: Timer 2 Overflow - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_COMPA", // 12: Timer 1 Compare Match A - "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "TIMER1_OVF", // 14: Timer 1 Overflow - "TIMER0_COMP", // 15: Timer 0 Compare Match - "TIMER0_OVF", // 16: Timer 0 Overflow - "SPI_STC", // 17: SPI Serial Transfer Complete - "UART_RX", // 18: UART Receive Complete - "UART_UDRE", // 19: UART Data Register Empty - "UART_TX", // 20: UART Transmit Complete - "ADC", // 21: ADC Conversion Complete - "EE_READY", // 22: EEPROM Ready - "ANALOG_COMP", // 23: Analog Comparator + "PCINT0", // 5: Pin Change Interrupt 0 + "PCINT1", // 6: Pin Change Interrupt 1 + "PCINT2", // 7: Pin Change Interrupt 2 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "SUPPLY_MON", // 23: Supply Monitor + "RFU", // 24: Reserved for Future Use + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready + "KEYBOARD", // 28: Keyboard Input Change + "AES_Operation", // 29: AES Operation + "HSSPI", // 30: High-Speed SPI + "USB_Endpoint", // 31: USB Endpoint + "USB_Protocol", // 32: USB Protocol + "SCIB", // 33: Smart Card Reader Interface + "USBHost_Control", // 34: USB Host Controller + "USBHost_Pipe", // 35: USB Host Pipe + "CPRES", // 36: Card Presence Detection + "PCINT3", // 37: Pin Change Interrupt 3 }; -// ATmega128A ATmegaS128 ATmega128 ATmega64A ATmega64 -const char * const vtab_atmega128a[vts_atmega128a] = { +// AT86RF401 +const char * const vtab_at86rf401[vts_at86rf401] = { + "RESET", // 0: Reset (various reasons) + "TXDONE", // 1: Transmit Complete + "TXEMPTY", // 2: Transmit Register Empty +}; + +// ATtiny11 +const char * const vtab_attiny11[vts_attiny11] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER0_OVF", // 3: Timer 0 Overflow + "ANA_COMP", // 4: Analog Comparator +}; + +// ATtiny12 +const char * const vtab_attiny12[vts_attiny12] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER0_OVF", // 3: Timer 0 Overflow + "EE_RDY", // 4: EEPROM Ready + "ANA_COMP", // 5: Analog Comparator +}; + +// ATtiny13 ATtiny13A +const char * const vtab_attiny13[vts_attiny13] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "TIM0_OVF", // 3: Timer 0 Overflow + "EE_RDY", // 4: EEPROM Ready + "ANA_COMP", // 5: Analog Comparator + "TIM0_COMPA", // 6: Timer 0 Compare Match A + "TIM0_COMPB", // 7: Timer 0 Compare Match B + "WDT", // 8: Watchdog Time-out + "ADC", // 9: ADC Conversion Complete +}; + +// ATtiny43U +const char * const vtab_attiny43u[vts_attiny43u] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIM1_COMPA", // 5: Timer 1 Compare Match A + "TIM1_COMPB", // 6: Timer 1 Compare Match B + "TIM1_OVF", // 7: Timer 1 Overflow + "TIM0_COMPA", // 8: Timer 0 Compare Match A + "TIM0_COMPB", // 9: Timer 0 Compare Match B + "TIM0_OVF", // 10: Timer 0 Overflow + "ANA_COMP", // 11: Analog Comparator + "ADC", // 12: ADC Conversion Complete + "EE_RDY", // 13: EEPROM Ready + "USI_START", // 14: USI Start Condition + "USI_OVF", // 15: USI Overflow +}; + +// ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A +const char * const vtab_attiny24[vts_attiny24] = { + "RESET", // 0: Reset (various reasons) + "EXT_INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIM1_CAPT", // 5: Timer 1 Capture Event + "TIM1_COMPA", // 6: Timer 1 Compare Match A + "TIM1_COMPB", // 7: Timer 1 Compare Match B + "TIM1_OVF", // 8: Timer 1 Overflow + "TIM0_COMPA", // 9: Timer 0 Compare Match A + "TIM0_COMPB", // 10: Timer 0 Compare Match B + "TIM0_OVF", // 11: Timer 0 Overflow + "ANA_COMP", // 12: Analog Comparator + "ADC", // 13: ADC Conversion Complete + "EE_RDY", // 14: EEPROM Ready + "USI_STR", // 15: USI Start Condition + "USI_OVF", // 16: USI Overflow +}; + +// ATtiny15 +const char * const vtab_attiny15[vts_attiny15] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER1_COMP", // 3: Timer 1 Compare + "TIMER1_OVF", // 4: Timer 1 Overflow + "TIMER0_OVF", // 5: Timer 0 Overflow + "EE_RDY", // 6: EEPROM Ready + "ANA_COMP", // 7: Analog Comparator + "ADC", // 8: ADC Conversion Complete +}; + +// ATtiny25 ATtiny45 ATtiny85 +const char * const vtab_attiny25[vts_attiny25] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "TIMER1_COMPA", // 3: Timer 1 Compare Match A + "TIMER1_OVF", // 4: Timer 1 Overflow + "TIMER0_OVF", // 5: Timer 0 Overflow + "EE_RDY", // 6: EEPROM Ready + "ANA_COMP", // 7: Analog Comparator + "ADC", // 8: ADC Conversion Complete + "TIMER1_COMPB", // 9: Timer 1 Compare Match B + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_COMPB", // 11: Timer 0 Compare Match B + "WDT", // 12: Watchdog Time-out + "USI_START", // 13: USI Start Condition + "USI_OVF", // 14: USI Overflow +}; + +// ATtiny26 +const char * const vtab_attiny26[vts_attiny26] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "IO_PINS", // 2: External Interrupt + "TIMER1_CMPA", // 3: Timer 1 Compare Match A + "TIMER1_CMPB", // 4: Timer 1 Compare Match B + "TIMER1_OVF1", // 5: Timer 1 Overflow + "TIMER0_OVF0", // 6: Timer 0 Overflow + "USI_STRT", // 7: USI Start Condition + "USI_OVF", // 8: USI Overflow + "EE_RDY", // 9: EEPROM Ready + "ANA_COMP", // 10: Analog Comparator + "ADC", // 11: ADC Conversion Complete +}; + +// ATtiny87 ATtiny167 ATA5505 ATA6616C ATA6617C ATA664251 +const char * const vtab_attiny87[vts_attiny87] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "WDT", // 5: Watchdog Time-out + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_OVF", // 11: Timer 0 Overflow + "LIN_TC", // 12: LIN Transfer Complete + "LIN_ERR", // 13: LIN Error + "SPI_STC", // 14: SPI Serial Transfer Complete + "ADC", // 15: ADC Conversion Complete + "EE_RDY", // 16: EEPROM Ready + "ANA_COMP", // 17: Analog Comparator + "USI_START", // 18: USI Start Condition + "USI_OVF", // 19: USI Overflow +}; + +// ATtiny28 +const char * const vtab_attiny28[vts_attiny28] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "LOW_LEVEL_IO_PINS", // 3: Low-level Input + "TIMER0_OVF", // 4: Timer 0 Overflow + "ANA_COMP", // 5: Analog Comparator +}; + +// ATtiny48 ATtiny88 +const char * const vtab_attiny48[vts_attiny48] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "PCINT3", // 6: Pin Change Interrupt 3 + "WDT", // 7: Watchdog Time-out + "TIMER1_CAPT", // 8: Timer 1 Capture Event + "TIMER1_COMPA", // 9: Timer 1 Compare Match A + "TIMER1_COMPB", // 10: Timer 1 Compare Match B + "TIMER1_OVF", // 11: Timer 1 Overflow + "TIMER0_COMPA", // 12: Timer 0 Compare Match A + "TIMER0_COMPB", // 13: Timer 0 Compare Match B + "TIMER0_OVF", // 14: Timer 0 Overflow + "SPI_STC", // 15: SPI Serial Transfer Complete + "ADC", // 16: ADC Conversion Complete + "EE_RDY", // 17: EEPROM Ready + "ANALOG_COMP", // 18: Analog Comparator + "TWI", // 19: 2-Wire Interface +}; + +// ATtiny828 ATtiny828R +const char * const vtab_attiny828[vts_attiny828] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "PCINT3", // 6: Pin Change Interrupt 3 + "WDT", // 7: Watchdog Time-out + "TIMER1_CAPT", // 8: Timer 1 Capture Event + "TIMER1_COMPA", // 9: Timer 1 Compare Match A + "TIMER1_COMPB", // 10: Timer 1 Compare Match B + "TIMER1_OVF", // 11: Timer 1 Overflow + "TIMER0_COMPA", // 12: Timer 0 Compare Match A + "TIMER0_COMPB", // 13: Timer 0 Compare Match B + "TIMER0_OVF", // 14: Timer 0 Overflow + "SPI_STC", // 15: SPI Serial Transfer Complete + "USART_START", // 16: USART Start + "USART_RX", // 17: USART Receive Complete + "USART_UDRE", // 18: USART Data Register Empty + "USART_TX", // 19: USART Transmit Complete + "ADC", // 20: ADC Conversion Complete + "EE_READY", // 21: EEPROM Ready + "ANALOG_COMP", // 22: Analog Comparator + "TWI_PERIPHERAL", // 23: 2-Wire Interface Peripheral + "SPM_Ready", // 24: Store Program Memory Ready + "QTRIP", // 25: Touch Sensing +}; + +// ATtiny1634 ATtiny1634R +const char * const vtab_attiny1634[vts_attiny1634] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "PCINT2", // 4: Pin Change Interrupt 2 + "WDT", // 5: Watchdog Time-out + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMPA", // 10: Timer 0 Compare Match A + "TIMER0_COMPB", // 11: Timer 0 Compare Match B + "TIMER0_OVF", // 12: Timer 0 Overflow + "ANA_COMP", // 13: Analog Comparator + "ADC_READY", // 14: ADC Conversion Complete + "USART0_START", // 15: USART 0 Receive Start + "USART0_RXC", // 16: USART 0 Receive Complete + "USART0_UDRE", // 17: USART 0 Data Register Empty + "USART0_TXC", // 18: USART 0 Transmit Complete + "USART1_START", // 19: USART 1 Receive Start + "USART1_RXC", // 20: USART 1 Receive Complete + "USART1_UDRE", // 21: USART 1 Data Register Empty + "USART1_TXC", // 22: USART 1 Transmit Complete + "USI_START", // 23: USI Start Condition + "USI_OVERFLOW", // 24: USI Overflow + "TWI/TWI_PERIPHERAL", // 25: 2-Wire Interface/2-Wire Interface Peripheral + "EE_RDY", // 26: EEPROM Ready + "QTRIP", // 27: Touch Sensing +}; + +// ATtiny441 ATtiny841 +const char * const vtab_attiny441[vts_attiny441] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_COMPA", // 9: Timer 0 Compare Match A + "TIMER0_COMPB", // 10: Timer 0 Compare Match B + "TIMER0_OVF", // 11: Timer 0 Overflow + "ANA_COMP0", // 12: Analog Comparator 0 + "ADC", // 13: ADC Conversion Complete + "EE_RDY", // 14: EEPROM Ready + "ANA_COMP1", // 15: Analog Comparator 1 + "TIMER2_CAPT", // 16: Timer 2 Capture Event + "TIMER2_COMPA", // 17: Timer 2 Compare Match A + "TIMER2_COMPB", // 18: Timer 2 Compare Match B + "TIMER2_OVF", // 19: Timer 2 Overflow + "SPI", // 20: SPI Serial Peripheral Interface + "USART0_START", // 21: USART 0 Receive Start + "USART0_RX", // 22: USART 0 Receive Complete + "USART0_UDRE", // 23: USART 0 Data Register Empty + "USART0_TX", // 24: USART 0 Transmit Complete + "USART1_START", // 25: USART 1 Receive Start + "USART1_RX", // 26: USART 1 Receive Complete + "USART1_UDRE", // 27: USART 1 Data Register Empty + "USART1_TX", // 28: USART 1 Transmit Complete + "TWI_PERIPHERAL", // 29: 2-Wire Interface Peripheral +}; + +// ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A +const char * const vtab_attiny261[vts_attiny261] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT", // 2: Pin Change Interrupt + "TIMER1_COMPA", // 3: Timer 1 Compare Match A + "TIMER1_COMPB", // 4: Timer 1 Compare Match B + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "USI_START", // 7: USI Start Condition + "USI_OVF", // 8: USI Overflow + "EE_RDY", // 9: EEPROM Ready + "ANA_COMP", // 10: Analog Comparator + "ADC", // 11: ADC Conversion Complete + "WDT", // 12: Watchdog Time-out + "INT1", // 13: External Interrupt 1 + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_CAPT", // 16: Timer 0 Capture Event + "TIMER1_COMPD", // 17: Timer 1 Compare Match D + "FAULT_PROTECTION", // 18: Timer 1 Fault Protection +}; + +// ATtiny2313 +const char * const vtab_attiny2313[vts_attiny2313] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMPA", // 4: Timer 1 Compare Match A + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "USART_RX", // 7: USART Receive Complete + "USART_UDRE", // 8: USART Data Register Empty + "USART_TX", // 9: USART Transmit Complete + "ANA_COMP", // 10: Analog Comparator + "PCINT", // 11: Pin Change Interrupt + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER0_COMPA", // 13: Timer 0 Compare Match A + "TIMER0_COMPB", // 14: Timer 0 Compare Match B + "USI_START", // 15: USI Start Condition + "USI_OVERFLOW", // 16: USI Overflow + "EEPROM_Ready", // 17: EEPROM Ready + "WDT_OVERFLOW", // 18: Watchdog Timer Overflow +}; + +// ATtiny2313A ATtiny4313 +const char * const vtab_attiny2313a[vts_attiny2313a] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER1_CAPT", // 3: Timer 1 Capture Event + "TIMER1_COMPA", // 4: Timer 1 Compare Match A + "TIMER1_OVF", // 5: Timer 1 Overflow + "TIMER0_OVF", // 6: Timer 0 Overflow + "USART_RX", // 7: USART Receive Complete + "USART_UDRE", // 8: USART Data Register Empty + "USART_TX", // 9: USART Transmit Complete + "ANA_COMP", // 10: Analog Comparator + "PCINT_B", // 11: Pin Change Interrupt B + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER0_COMPA", // 13: Timer 0 Compare Match A + "TIMER0_COMPB", // 14: Timer 0 Compare Match B + "USI_START", // 15: USI Start Condition + "USI_OVERFLOW", // 16: USI Overflow + "EEPROM_Ready", // 17: EEPROM Ready + "WDT_OVERFLOW", // 18: Watchdog Timer Overflow + "PCINT_A", // 19: Pin Change Interrupt A + "PCINT_D", // 20: Pin Change Interrupt D +}; + +// ATmega8 ATmega8A +const char * const vtab_atmega8[vts_atmega8] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "USART_RXC", // 11: USART Receive Complete + "USART_UDRE", // 12: USART Data Register Empty + "USART_TXC", // 13: USART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface + "SPM_RDY", // 18: Store Program Memory Ready +}; + +// ATmega16 ATmega16A +const char * const vtab_atmega16[vts_atmega16] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "USART_RXC", // 11: USART Receive Complete + "USART_UDRE", // 12: USART Data Register Empty + "USART_TXC", // 13: USART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface + "INT2", // 18: External Interrupt 2 + "TIMER0_COMP", // 19: Timer 0 Compare Match + "SPM_RDY", // 20: Store Program Memory Ready +}; + +// ATmega32 ATmega32A ATmega323 +const char * const vtab_atmega32[vts_atmega32] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART_RXC", // 13: USART Receive Complete + "USART_UDRE", // 14: USART Data Register Empty + "USART_TXC", // 15: USART Transmit Complete + "ADC", // 16: ADC Conversion Complete + "EE_RDY", // 17: EEPROM Ready + "ANA_COMP", // 18: Analog Comparator + "TWI", // 19: 2-Wire Interface + "SPM_RDY", // 20: Store Program Memory Ready +}; + +// ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 +const char * const vtab_atmega64[vts_atmega64] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -3933,6 +4073,102 @@ const char * const vtab_atmega128a[vts_atmega128a] = { "SPM_READY", // 34: Store Program Memory Ready }; +// ATmega640 ATmega1280 ATmega2560 +const char * const vtab_atmega640[vts_atmega640] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "PCINT1", // 10: Pin Change Interrupt 1 + "PCINT2", // 11: Pin Change Interrupt 2 + "WDT", // 12: Watchdog Time-out + "TIMER2_COMPA", // 13: Timer 2 Compare Match A + "TIMER2_COMPB", // 14: Timer 2 Compare Match B + "TIMER2_OVF", // 15: Timer 2 Overflow + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART0_RX", // 25: USART 0 Receive Complete + "USART0_UDRE", // 26: USART 0 Data Register Empty + "USART0_TX", // 27: USART 0 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "USART1_RX", // 36: USART 1 Receive Complete + "USART1_UDRE", // 37: USART 1 Data Register Empty + "USART1_TX", // 38: USART 1 Transmit Complete + "TWI", // 39: 2-Wire Interface + "SPM_READY", // 40: Store Program Memory Ready + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_COMPC", // 44: Timer 4 Compare Match C + "TIMER4_OVF", // 45: Timer 4 Overflow + "TIMER5_CAPT", // 46: Timer 5 Capture Event + "TIMER5_COMPA", // 47: Timer 5 Compare Match A + "TIMER5_COMPB", // 48: Timer 5 Compare Match B + "TIMER5_COMPC", // 49: Timer 5 Compare Match C + "TIMER5_OVF", // 50: Timer 5 Overflow + "USART2_RX", // 51: USART 2 Receive Complete + "USART2_UDRE", // 52: USART 2 Data Register Empty + "USART2_TX", // 53: USART 2 Transmit Complete + "USART3_RX", // 54: USART 3 Receive Complete + "USART3_UDRE", // 55: USART 3 Data Register Empty + "USART3_TX", // 56: USART 3 Transmit Complete +}; + +// ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 +const char * const vtab_atmega32c1[vts_atmega32c1] = { + "RESET", // 0: Reset (various reasons) + "ANACOMP0", // 1: Analog Comparator 0 + "ANACOMP1", // 2: Analog Comparator 1 + "ANACOMP2", // 3: Analog Comparator 2 + "ANACOMP3", // 4: Analog Comparator 3 + "PSC_FAULT", // 5: PSC Fault + "PSC_EC", // 6: PSC End of Cycle + "INT0", // 7: External Interrupt 0 + "INT1", // 8: External Interrupt 1 + "INT2", // 9: External Interrupt 2 + "INT3", // 10: External Interrupt 3 + "TIMER1_CAPT", // 11: Timer 1 Capture Event + "TIMER1_COMPA", // 12: Timer 1 Compare Match A + "TIMER1_COMPB", // 13: Timer 1 Compare Match B + "TIMER1_OVF", // 14: Timer 1 Overflow + "TIMER0_COMPA", // 15: Timer 0 Compare Match A + "TIMER0_COMPB", // 16: Timer 0 Compare Match B + "TIMER0_OVF", // 17: Timer 0 Overflow + "CAN_INT", // 18: CAN MOB, Burst, General Errors + "CAN_TOVF", // 19: CAN Timer Overflow + "LIN_TC", // 20: LIN Transfer Complete + "LIN_ERR", // 21: LIN Error + "PCINT0", // 22: Pin Change Interrupt 0 + "PCINT1", // 23: Pin Change Interrupt 1 + "PCINT2", // 24: Pin Change Interrupt 2 + "PCINT3", // 25: Pin Change Interrupt 3 + "SPI_STC", // 26: SPI Serial Transfer Complete + "ADC", // 27: ADC Conversion Complete + "WDT", // 28: Watchdog Time-out + "EE_READY", // 29: EEPROM Ready + "SPM_READY", // 30: Store Program Memory Ready +}; + // ATmega128RFA1 const char * const vtab_atmega128rfa1[vts_atmega128rfa1] = { "RESET", // 0: Reset (various reasons) @@ -4009,627 +4245,8 @@ const char * const vtab_atmega128rfa1[vts_atmega128rfa1] = { "BAT_LOW", // 71: Battery Voltage Below Threshold }; -// ATmega161 -const char * const vtab_atmega161[vts_atmega161] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "TIMER2_COMP", // 4: Timer 2 Compare Match - "TIMER2_OVF", // 5: Timer 2 Overflow - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMP", // 10: Timer 0 Compare Match - "TIMER0_OVF", // 11: Timer 0 Overflow - "SPI_STC", // 12: SPI Serial Transfer Complete - "UART0_RX", // 13: UART 0 Receive Complete - "UART1_RX", // 14: UART 1 Receive Complete - "UART0_UDRE", // 15: UART 0 Data Register Empty - "UART1_UDRE", // 16: UART 1 Data Register Empty - "UART0_TX", // 17: UART 0 Transmit Complete - "UART1_TX", // 18: UART 1 Transmit Complete - "EE_RDY", // 19: EEPROM Ready - "ANA_COMP", // 20: Analog Comparator -}; - -// ATmega162 -const char * const vtab_atmega162[vts_atmega162] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "PCINT0", // 4: Pin Change Interrupt 0 - "PCINT1", // 5: Pin Change Interrupt 1 - "TIMER3_CAPT", // 6: Timer 3 Capture Event - "TIMER3_COMPA", // 7: Timer 3 Compare Match A - "TIMER3_COMPB", // 8: Timer 3 Compare Match B - "TIMER3_OVF", // 9: Timer 3 Overflow - "TIMER2_COMP", // 10: Timer 2 Compare Match - "TIMER2_OVF", // 11: Timer 2 Overflow - "TIMER1_CAPT", // 12: Timer 1 Capture Event - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMP", // 16: Timer 0 Compare Match - "TIMER0_OVF", // 17: Timer 0 Overflow - "SPI_STC", // 18: SPI Serial Transfer Complete - "USART0_RXC", // 19: USART 0 Receive Complete - "USART1_RXC", // 20: USART 1 Receive Complete - "USART0_UDRE", // 21: USART 0 Data Register Empty - "USART1_UDRE", // 22: USART 1 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "USART1_TXC", // 24: USART 1 Transmit Complete - "EE_RDY", // 25: EEPROM Ready - "ANA_COMP", // 26: Analog Comparator - "SPM_RDY", // 27: Store Program Memory Ready -}; - -// ATmega163 -const char * const vtab_atmega163[vts_atmega163] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "TIMER2_COMP", // 3: Timer 2 Compare Match - "TIMER2_OVF", // 4: Timer 2 Overflow - "TIMER1_CAPT", // 5: Timer 1 Capture Event - "TIMER1_COMPA", // 6: Timer 1 Compare Match A - "TIMER1_COMPB", // 7: Timer 1 Compare Match B - "TIMER1_OVF", // 8: Timer 1 Overflow - "TIMER0_OVF", // 9: Timer 0 Overflow - "SPI_STC", // 10: SPI Serial Transfer Complete - "UART_RX", // 11: UART Receive Complete - "UART_UDRE", // 12: UART Data Register Empty - "UART_TX", // 13: UART Transmit Complete - "ADC", // 14: ADC Conversion Complete - "EE_RDY", // 15: EEPROM Ready - "ANA_COMP", // 16: Analog Comparator - "TWI", // 17: 2-Wire Interface -}; - -// ATmega168PB ATmega88PB ATmega48PB -const char * const vtab_atmega168pb[vts_atmega168pb] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "PCINT2", // 5: Pin Change Interrupt 2 - "WDT", // 6: Watchdog Time-out - "TIMER2_COMPA", // 7: Timer 2 Compare Match A - "TIMER2_COMPB", // 8: Timer 2 Compare Match B - "TIMER2_OVF", // 9: Timer 2 Overflow - "TIMER1_CAPT", // 10: Timer 1 Capture Event - "TIMER1_COMPA", // 11: Timer 1 Compare Match A - "TIMER1_COMPB", // 12: Timer 1 Compare Match B - "TIMER1_OVF", // 13: Timer 1 Overflow - "TIMER0_COMPA", // 14: Timer 0 Compare Match A - "TIMER0_COMPB", // 15: Timer 0 Compare Match B - "TIMER0_OVF", // 16: Timer 0 Overflow - "SPI_STC", // 17: SPI Serial Transfer Complete - "USART_RX", // 18: USART Receive Complete - "USART_UDRE", // 19: USART Data Register Empty - "USART_TX", // 20: USART Transmit Complete - "ADC", // 21: ADC Conversion Complete - "EE_READY", // 22: EEPROM Ready - "ANALOG_COMP", // 23: Analog Comparator - "TWI", // 24: 2-Wire Interface - "SPM_Ready", // 25: Store Program Memory Ready - "USART_START", // 26: USART Start -}; - -// ATmega323 ATmega32A ATmega32 -const char * const vtab_atmega323[vts_atmega323] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "TIMER2_COMP", // 4: Timer 2 Compare Match - "TIMER2_OVF", // 5: Timer 2 Overflow - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMP", // 10: Timer 0 Compare Match - "TIMER0_OVF", // 11: Timer 0 Overflow - "SPI_STC", // 12: SPI Serial Transfer Complete - "USART_RXC", // 13: USART Receive Complete - "USART_UDRE", // 14: USART Data Register Empty - "USART_TXC", // 15: USART Transmit Complete - "ADC", // 16: ADC Conversion Complete - "EE_RDY", // 17: EEPROM Ready - "ANA_COMP", // 18: Analog Comparator - "TWI", // 19: 2-Wire Interface - "SPM_RDY", // 20: Store Program Memory Ready -}; - -// ATmega324PB -const char * const vtab_atmega324pb[vts_atmega324pb] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "PCINT0", // 4: Pin Change Interrupt 0 - "PCINT1", // 5: Pin Change Interrupt 1 - "PCINT2", // 6: Pin Change Interrupt 2 - "PCINT3", // 7: Pin Change Interrupt 3 - "WDT", // 8: Watchdog Time-out - "TIMER2_COMPA", // 9: Timer 2 Compare Match A - "TIMER2_COMPB", // 10: Timer 2 Compare Match B - "TIMER2_OVF", // 11: Timer 2 Overflow - "TIMER1_CAPT", // 12: Timer 1 Capture Event - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMPA", // 16: Timer 0 Compare Match A - "TIMER0_COMPB", // 17: Timer 0 Compare Match B - "TIMER0_OVF", // 18: Timer 0 Overflow - "SPI0_STC", // 19: SPI 0 Serial Transfer Complete - "USART0_RX", // 20: USART 0 Receive Complete - "USART0_UDRE", // 21: USART 0 Data Register Empty - "USART0_TX", // 22: USART 0 Transmit Complete - "ANALOG_COMP", // 23: Analog Comparator - "ADC", // 24: ADC Conversion Complete - "EE_READY", // 25: EEPROM Ready - "TWI0", // 26: 2-Wire Interface 0 - "SPM_READY", // 27: Store Program Memory Ready - "USART1_RX", // 28: USART 1 Receive Complete - "USART1_UDRE", // 29: USART 1 Data Register Empty - "USART1_TX", // 30: USART 1 Transmit Complete - "TIMER3_CAPT", // 31: Timer 3 Capture Event - "TIMER3_COMPA", // 32: Timer 3 Compare Match A - "TIMER3_COMPB", // 33: Timer 3 Compare Match B - "TIMER3_OVF", // 34: Timer 3 Overflow - "USART0_START", // 35: USART 0 Receive Start - "USART1_START", // 36: USART 1 Receive Start - "PCINT4", // 37: Pin Change Interrupt 4 - "XOSCFD", // 38: Crystal Failure Detect - "PTC_EOC", // 39: PTC End of Conversion - "PTC_WCOMP", // 40: PTC Window Comparator Mode - "SPI1_STC", // 41: SPI 1 Serial Transfer Complete - "TWI1", // 42: 2-Wire Interface 1 - "TIMER4_CAPT", // 43: Timer 4 Capture Event - "TIMER4_COMPA", // 44: Timer 4 Compare Match A - "TIMER4_COMPB", // 45: Timer 4 Compare Match B - "TIMER4_OVF", // 46: Timer 4 Overflow - "USART2_RX", // 47: USART 2 Receive Complete - "USART2_UDRE", // 48: USART 2 Data Register Empty - "USART2_TX", // 49: USART 2 Transmit Complete - "USART2_START", // 50: USART 2 Receive Start -}; - -// ATmega328 ATmega168 -const char * const vtab_atmega328[vts_atmega328] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "PCINT2", // 5: Pin Change Interrupt 2 - "WDT", // 6: Watchdog Time-out - "TIMER2_COMPA", // 7: Timer 2 Compare Match A - "TIMER2_COMPB", // 8: Timer 2 Compare Match B - "TIMER2_OVF", // 9: Timer 2 Overflow - "TIMER1_CAPT", // 10: Timer 1 Capture Event - "TIMER1_COMPA", // 11: Timer 1 Compare Match A - "TIMER1_COMPB", // 12: Timer 1 Compare Match B - "TIMER1_OVF", // 13: Timer 1 Overflow - "TIMER0_COMPA", // 14: Timer 0 Compare Match A - "TIMER0_COMPB", // 15: Timer 0 Compare Match B - "TIMER0_OVF", // 16: Timer 0 Overflow - "SPI_STC", // 17: SPI Serial Transfer Complete - "USART_RX", // 18: USART Receive Complete - "USART_UDRE", // 19: USART Data Register Empty - "USART_TX", // 20: USART Transmit Complete - "ADC", // 21: ADC Conversion Complete - "EE_READY", // 22: EEPROM Ready - "ANALOG_COMP", // 23: Analog Comparator - "TWI", // 24: 2-Wire Interface - "SPM_READY", // 25: Store Program Memory Ready -}; - -/* - * ATmega328P ATmega168PA ATmega168P ATmega168A ATmega88PA ATmega88P ATmega88A ATmega88 ATmega48PA - * ATmega48P ATmega48A ATmega48 ATA6614Q ATA6613C ATA6612C LGT8F328P LGT8F168P LGT8F88P - */ -const char * const vtab_atmega328p[vts_atmega328p] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "PCINT2", // 5: Pin Change Interrupt 2 - "WDT", // 6: Watchdog Time-out - "TIMER2_COMPA", // 7: Timer 2 Compare Match A - "TIMER2_COMPB", // 8: Timer 2 Compare Match B - "TIMER2_OVF", // 9: Timer 2 Overflow - "TIMER1_CAPT", // 10: Timer 1 Capture Event - "TIMER1_COMPA", // 11: Timer 1 Compare Match A - "TIMER1_COMPB", // 12: Timer 1 Compare Match B - "TIMER1_OVF", // 13: Timer 1 Overflow - "TIMER0_COMPA", // 14: Timer 0 Compare Match A - "TIMER0_COMPB", // 15: Timer 0 Compare Match B - "TIMER0_OVF", // 16: Timer 0 Overflow - "SPI_STC", // 17: SPI Serial Transfer Complete - "USART_RX", // 18: USART Receive Complete - "USART_UDRE", // 19: USART Data Register Empty - "USART_TX", // 20: USART Transmit Complete - "ADC", // 21: ADC Conversion Complete - "EE_READY", // 22: EEPROM Ready - "ANALOG_COMP", // 23: Analog Comparator - "TWI", // 24: 2-Wire Interface - "SPM_Ready", // 25: Store Program Memory Ready -}; - -// ATmega328PB -const char * const vtab_atmega328pb[vts_atmega328pb] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCINT0", // 3: Pin Change Interrupt 0 - "PCINT1", // 4: Pin Change Interrupt 1 - "PCINT2", // 5: Pin Change Interrupt 2 - "WDT", // 6: Watchdog Time-out - "TIMER2_COMPA", // 7: Timer 2 Compare Match A - "TIMER2_COMPB", // 8: Timer 2 Compare Match B - "TIMER2_OVF", // 9: Timer 2 Overflow - "TIMER1_CAPT", // 10: Timer 1 Capture Event - "TIMER1_COMPA", // 11: Timer 1 Compare Match A - "TIMER1_COMPB", // 12: Timer 1 Compare Match B - "TIMER1_OVF", // 13: Timer 1 Overflow - "TIMER0_COMPA", // 14: Timer 0 Compare Match A - "TIMER0_COMPB", // 15: Timer 0 Compare Match B - "TIMER0_OVF", // 16: Timer 0 Overflow - "SPI0_STC", // 17: SPI 0 Serial Transfer Complete - "USART0_RX", // 18: USART 0 Receive Complete - "USART0_UDRE", // 19: USART 0 Data Register Empty - "USART0_TX", // 20: USART 0 Transmit Complete - "ADC", // 21: ADC Conversion Complete - "EE_READY", // 22: EEPROM Ready - "ANALOG_COMP", // 23: Analog Comparator - "TWI0", // 24: 2-Wire Interface 0 - "SPM_Ready", // 25: Store Program Memory Ready - "USART0_START", // 26: USART 0 Receive Start - "PCINT3", // 27: Pin Change Interrupt 3 - "USART1_RX", // 28: USART 1 Receive Complete - "USART1_UDRE", // 29: USART 1 Data Register Empty - "USART1_TX", // 30: USART 1 Transmit Complete - "USART1_START", // 31: USART 1 Receive Start - "TIMER3_CAPT", // 32: Timer 3 Capture Event - "TIMER3_COMPA", // 33: Timer 3 Compare Match A - "TIMER3_COMPB", // 34: Timer 3 Compare Match B - "TIMER3_OVF", // 35: Timer 3 Overflow - "CFD", // 36: Clock Failure Detection - "PTC_EOC", // 37: PTC End of Conversion - "PTC_WCOMP", // 38: PTC Window Comparator Mode - "SPI1_STC", // 39: SPI 1 Serial Transfer Complete - "TWI1", // 40: 2-Wire Interface 1 - "TIMER4_CAPT", // 41: Timer 4 Capture Event - "TIMER4_COMPA", // 42: Timer 4 Compare Match A - "TIMER4_COMPB", // 43: Timer 4 Compare Match B - "TIMER4_OVF", // 44: Timer 4 Overflow -}; - -// ATmega406 -const char * const vtab_atmega406[vts_atmega406] = { - "RESET", // 0: Reset (various reasons) - "BPINT", // 1: Battery Protection Interrupt - "INT0", // 2: External Interrupt 0 - "INT1", // 3: External Interrupt 1 - "INT2", // 4: External Interrupt 2 - "INT3", // 5: External Interrupt 3 - "PCINT0", // 6: Pin Change Interrupt 0 - "PCINT1", // 7: Pin Change Interrupt 1 - "WDT", // 8: Watchdog Time-out - "WAKE_UP", // 9: Wake Up - "TIM1_COMP", // 10: Timer 1 Compare and Match - "TIM1_OVF", // 11: Timer 1 Overflow - "TIM0_COMPA", // 12: Timer 0 Compare Match A - "TIM0_COMPB", // 13: Timer 0 Compare Match B - "TIM0_OVF", // 14: Timer 0 Overflow - "TWI_BUS_CD", // 15: 2-Wire Interface Bus Connect/Disconnect - "TWI", // 16: 2-Wire Interface - "VADC", // 17: Voltage ADC Conversion Complete - "CCADC_CONV", // 18: Coulomb Counter ADC Conversion Complete - "CCADC_REG_CUR", // 19: Coloumb Counter ADC Regular Current - "CCADC_ACC", // 20: Coloumb Counter ADC Accumulator - "EE_READY", // 21: EEPROM Ready - "SPM_READY", // 22: Store Program Memory Ready -}; - -// ATmega644 -const char * const vtab_atmega644[vts_atmega644] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "PCINT0", // 4: Pin Change Interrupt 0 - "PCINT1", // 5: Pin Change Interrupt 1 - "PCINT2", // 6: Pin Change Interrupt 2 - "PCINT3", // 7: Pin Change Interrupt 3 - "WDT", // 8: Watchdog Time-out - "TIMER2_COMPA", // 9: Timer 2 Compare Match A - "TIMER2_COMPB", // 10: Timer 2 Compare Match B - "TIMER2_OVF", // 11: Timer 2 Overflow - "TIMER1_CAPT", // 12: Timer 1 Capture Event - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMPA", // 16: Timer 0 Compare Match A - "TIMER0_COMPB", // 17: Timer 0 Compare Match B - "TIMER0_OVF", // 18: Timer 0 Overflow - "SPI_STC", // 19: SPI Serial Transfer Complete - "USART0_RX", // 20: USART 0 Receive Complete - "USART0_UDRE", // 21: USART 0 Data Register Empty - "USART0_TX", // 22: USART 0 Transmit Complete - "ANALOG_COMP", // 23: Analog Comparator - "ADC", // 24: ADC Conversion Complete - "EE_READY", // 25: EEPROM Ready - "TWI", // 26: 2-Wire Interface - "SPM_READY", // 27: Store Program Memory Ready -}; - -/* - * ATmega644PA ATmega644P ATmega644A ATmega324PA ATmega324P ATmega324A ATmega164PA ATmega164P - * ATmega164A - */ -const char * const vtab_atmega644pa[vts_atmega644pa] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "PCINT0", // 4: Pin Change Interrupt 0 - "PCINT1", // 5: Pin Change Interrupt 1 - "PCINT2", // 6: Pin Change Interrupt 2 - "PCINT3", // 7: Pin Change Interrupt 3 - "WDT", // 8: Watchdog Time-out - "TIMER2_COMPA", // 9: Timer 2 Compare Match A - "TIMER2_COMPB", // 10: Timer 2 Compare Match B - "TIMER2_OVF", // 11: Timer 2 Overflow - "TIMER1_CAPT", // 12: Timer 1 Capture Event - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMPA", // 16: Timer 0 Compare Match A - "TIMER0_COMPB", // 17: Timer 0 Compare Match B - "TIMER0_OVF", // 18: Timer 0 Overflow - "SPI_STC", // 19: SPI Serial Transfer Complete - "USART0_RX", // 20: USART 0 Receive Complete - "USART0_UDRE", // 21: USART 0 Data Register Empty - "USART0_TX", // 22: USART 0 Transmit Complete - "ANALOG_COMP", // 23: Analog Comparator - "ADC", // 24: ADC Conversion Complete - "EE_READY", // 25: EEPROM Ready - "TWI", // 26: 2-Wire Interface - "SPM_READY", // 27: Store Program Memory Ready - "USART1_RX", // 28: USART 1 Receive Complete - "USART1_UDRE", // 29: USART 1 Data Register Empty - "USART1_TX", // 30: USART 1 Transmit Complete -}; - -/* - * ATmega645P ATmega645A ATmega645 ATmega325PA ATmega325P ATmega325A ATmega325 ATmega165PA - * ATmega165P ATmega165A ATmega165 - */ -const char * const vtab_atmega645p[vts_atmega645p] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "TIMER2_COMP", // 4: Timer 2 Compare Match - "TIMER2_OVF", // 5: Timer 2 Overflow - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMP", // 10: Timer 0 Compare Match - "TIMER0_OVF", // 11: Timer 0 Overflow - "SPI_STC", // 12: SPI Serial Transfer Complete - "USART0_RX", // 13: USART 0 Receive Complete - "USART0_UDRE", // 14: USART 0 Data Register Empty - "USART0_TX", // 15: USART 0 Transmit Complete - "USI_START", // 16: USI Start Condition - "USI_OVERFLOW", // 17: USI Overflow - "ANALOG_COMP", // 18: Analog Comparator - "ADC", // 19: ADC Conversion Complete - "EE_READY", // 20: EEPROM Ready - "SPM_READY", // 21: Store Program Memory Ready -}; - -/* - * ATmega649P ATmega649A ATmega649 ATmega329PA ATmega329P ATmega329A ATmega329 ATmega169PA - * ATmega169P ATmega169A ATmega169 - */ -const char * const vtab_atmega649p[vts_atmega649p] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "TIMER2_COMP", // 4: Timer 2 Compare Match - "TIMER2_OVF", // 5: Timer 2 Overflow - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMP", // 10: Timer 0 Compare Match - "TIMER0_OVF", // 11: Timer 0 Overflow - "SPI_STC", // 12: SPI Serial Transfer Complete - "USART0_RX", // 13: USART 0 Receive Complete - "USART0_UDRE", // 14: USART 0 Data Register Empty - "USART0_TX", // 15: USART 0 Transmit Complete - "USI_START", // 16: USI Start Condition - "USI_OVERFLOW", // 17: USI Overflow - "ANALOG_COMP", // 18: Analog Comparator - "ADC", // 19: ADC Conversion Complete - "EE_READY", // 20: EEPROM Ready - "SPM_READY", // 21: Store Program Memory Ready - "LCD", // 22: LCD Start of Frame -}; - -// ATmega1284P ATmega1284 -const char * const vtab_atmega1284p[vts_atmega1284p] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "PCINT0", // 4: Pin Change Interrupt 0 - "PCINT1", // 5: Pin Change Interrupt 1 - "PCINT2", // 6: Pin Change Interrupt 2 - "PCINT3", // 7: Pin Change Interrupt 3 - "WDT", // 8: Watchdog Time-out - "TIMER2_COMPA", // 9: Timer 2 Compare Match A - "TIMER2_COMPB", // 10: Timer 2 Compare Match B - "TIMER2_OVF", // 11: Timer 2 Overflow - "TIMER1_CAPT", // 12: Timer 1 Capture Event - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMPA", // 16: Timer 0 Compare Match A - "TIMER0_COMPB", // 17: Timer 0 Compare Match B - "TIMER0_OVF", // 18: Timer 0 Overflow - "SPI_STC", // 19: SPI Serial Transfer Complete - "USART0_RX", // 20: USART 0 Receive Complete - "USART0_UDRE", // 21: USART 0 Data Register Empty - "USART0_TX", // 22: USART 0 Transmit Complete - "ANALOG_COMP", // 23: Analog Comparator - "ADC", // 24: ADC Conversion Complete - "EE_READY", // 25: EEPROM Ready - "TWI", // 26: 2-Wire Interface - "SPM_READY", // 27: Store Program Memory Ready - "USART1_RX", // 28: USART 1 Receive Complete - "USART1_UDRE", // 29: USART 1 Data Register Empty - "USART1_TX", // 30: USART 1 Transmit Complete - "TIMER3_CAPT", // 31: Timer 3 Capture Event - "TIMER3_COMPA", // 32: Timer 3 Compare Match A - "TIMER3_COMPB", // 33: Timer 3 Compare Match B - "TIMER3_OVF", // 34: Timer 3 Overflow -}; - -// ATmega2560 ATmega1280 ATmega640 -const char * const vtab_atmega2560[vts_atmega2560] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "INT3", // 4: External Interrupt 3 - "INT4", // 5: External Interrupt 4 - "INT5", // 6: External Interrupt 5 - "INT6", // 7: External Interrupt 6 - "INT7", // 8: External Interrupt 7 - "PCINT0", // 9: Pin Change Interrupt 0 - "PCINT1", // 10: Pin Change Interrupt 1 - "PCINT2", // 11: Pin Change Interrupt 2 - "WDT", // 12: Watchdog Time-out - "TIMER2_COMPA", // 13: Timer 2 Compare Match A - "TIMER2_COMPB", // 14: Timer 2 Compare Match B - "TIMER2_OVF", // 15: Timer 2 Overflow - "TIMER1_CAPT", // 16: Timer 1 Capture Event - "TIMER1_COMPA", // 17: Timer 1 Compare Match A - "TIMER1_COMPB", // 18: Timer 1 Compare Match B - "TIMER1_COMPC", // 19: Timer 1 Compare Match C - "TIMER1_OVF", // 20: Timer 1 Overflow - "TIMER0_COMPA", // 21: Timer 0 Compare Match A - "TIMER0_COMPB", // 22: Timer 0 Compare Match B - "TIMER0_OVF", // 23: Timer 0 Overflow - "SPI_STC", // 24: SPI Serial Transfer Complete - "USART0_RX", // 25: USART 0 Receive Complete - "USART0_UDRE", // 26: USART 0 Data Register Empty - "USART0_TX", // 27: USART 0 Transmit Complete - "ANALOG_COMP", // 28: Analog Comparator - "ADC", // 29: ADC Conversion Complete - "EE_READY", // 30: EEPROM Ready - "TIMER3_CAPT", // 31: Timer 3 Capture Event - "TIMER3_COMPA", // 32: Timer 3 Compare Match A - "TIMER3_COMPB", // 33: Timer 3 Compare Match B - "TIMER3_COMPC", // 34: Timer 3 Compare Match C - "TIMER3_OVF", // 35: Timer 3 Overflow - "USART1_RX", // 36: USART 1 Receive Complete - "USART1_UDRE", // 37: USART 1 Data Register Empty - "USART1_TX", // 38: USART 1 Transmit Complete - "TWI", // 39: 2-Wire Interface - "SPM_READY", // 40: Store Program Memory Ready - "TIMER4_CAPT", // 41: Timer 4 Capture Event - "TIMER4_COMPA", // 42: Timer 4 Compare Match A - "TIMER4_COMPB", // 43: Timer 4 Compare Match B - "TIMER4_COMPC", // 44: Timer 4 Compare Match C - "TIMER4_OVF", // 45: Timer 4 Overflow - "TIMER5_CAPT", // 46: Timer 5 Capture Event - "TIMER5_COMPA", // 47: Timer 5 Compare Match A - "TIMER5_COMPB", // 48: Timer 5 Compare Match B - "TIMER5_COMPC", // 49: Timer 5 Compare Match C - "TIMER5_OVF", // 50: Timer 5 Overflow - "USART2_RX", // 51: USART 2 Receive Complete - "USART2_UDRE", // 52: USART 2 Data Register Empty - "USART2_TX", // 53: USART 2 Transmit Complete - "USART3_RX", // 54: USART 3 Receive Complete - "USART3_UDRE", // 55: USART 3 Data Register Empty - "USART3_TX", // 56: USART 3 Transmit Complete -}; - -// ATmega2561 ATmega1281 -const char * const vtab_atmega2561[vts_atmega2561] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "INT3", // 4: External Interrupt 3 - "INT4", // 5: External Interrupt 4 - "INT5", // 6: External Interrupt 5 - "INT6", // 7: External Interrupt 6 - "INT7", // 8: External Interrupt 7 - "PCINT0", // 9: Pin Change Interrupt 0 - "PCINT1", // 10: Pin Change Interrupt 1 - "PCINT2", // 11: Pin Change Interrupt 2 - "WDT", // 12: Watchdog Time-out - "TIMER2_COMPA", // 13: Timer 2 Compare Match A - "TIMER2_COMPB", // 14: Timer 2 Compare Match B - "TIMER2_OVF", // 15: Timer 2 Overflow - "TIMER1_CAPT", // 16: Timer 1 Capture Event - "TIMER1_COMPA", // 17: Timer 1 Compare Match A - "TIMER1_COMPB", // 18: Timer 1 Compare Match B - "TIMER1_COMPC", // 19: Timer 1 Compare Match C - "TIMER1_OVF", // 20: Timer 1 Overflow - "TIMER0_COMPA", // 21: Timer 0 Compare Match A - "TIMER0_COMPB", // 22: Timer 0 Compare Match B - "TIMER0_OVF", // 23: Timer 0 Overflow - "SPI_STC", // 24: SPI Serial Transfer Complete - "USART0_RX", // 25: USART 0 Receive Complete - "USART0_UDRE", // 26: USART 0 Data Register Empty - "USART0_TX", // 27: USART 0 Transmit Complete - "ANALOG_COMP", // 28: Analog Comparator - "ADC", // 29: ADC Conversion Complete - "EE_READY", // 30: EEPROM Ready - "TIMER3_CAPT", // 31: Timer 3 Capture Event - "TIMER3_COMPA", // 32: Timer 3 Compare Match A - "TIMER3_COMPB", // 33: Timer 3 Compare Match B - "TIMER3_COMPC", // 34: Timer 3 Compare Match C - "TIMER3_OVF", // 35: Timer 3 Overflow - "USART1_RX", // 36: USART 1 Receive Complete - "USART1_UDRE", // 37: USART 1 Data Register Empty - "USART1_TX", // 38: USART 1 Transmit Complete - "TWI", // 39: 2-Wire Interface - "SPM_READY", // 40: Store Program Memory Ready - "TIMER4_CAPT", // 41: Timer 4 Capture Event - "TIMER4_COMPA", // 42: Timer 4 Compare Match A - "TIMER4_COMPB", // 43: Timer 4 Compare Match B - "TIMER4_COMPC", // 44: Timer 4 Compare Match C - "TIMER4_OVF", // 45: Timer 4 Overflow - "TIMER5_CAPT", // 46: Timer 5 Capture Event - "TIMER5_COMPA", // 47: Timer 5 Compare Match A - "TIMER5_COMPB", // 48: Timer 5 Compare Match B - "TIMER5_COMPC", // 49: Timer 5 Compare Match C - "TIMER5_OVF", // 50: Timer 5 Overflow - "UNUSED", // 51: not useful owing to limited pin count - "UNUSED", // 52: not useful owing to limited pin count - "UNUSED", // 53: not useful owing to limited pin count - "UNUSED", // 54: not useful owing to limited pin count - "UNUSED", // 55: not useful owing to limited pin count - "UNUSED", // 56: not useful owing to limited pin count -}; - -// ATmega2564RFR2 ATmega1284RFR2 ATmega644RFR2 ATmega256RFR2 ATmega128RFR2 ATmega64RFR2 -const char * const vtab_atmega2564rfr2[vts_atmega2564rfr2] = { +// ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 +const char * const vtab_atmega64rfr2[vts_atmega64rfr2] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -4709,8 +4326,388 @@ const char * const vtab_atmega2564rfr2[vts_atmega2564rfr2] = { "TRX24_AMI3", // 76: TRX24 Address Match 3 }; -// ATmega6450P ATmega6450A ATmega6450 ATmega3250PA ATmega3250P ATmega3250A ATmega3250 -const char * const vtab_atmega6450p[vts_atmega6450p] = { +// ATmega16U4 ATmega32U4 +const char * const vtab_atmega16u4[vts_atmega16u4] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "Reserved1", // 5: Reserved 1 + "Reserved2", // 6: Reserved 2 + "INT6", // 7: External Interrupt 6 + "Reserved3", // 8: Reserved 3 + "PCINT0", // 9: Pin Change Interrupt 0 + "USB_GEN", // 10: USB General + "USB_COM", // 11: USB Endpoint/Pipe Interrupt Communication Request + "WDT", // 12: Watchdog Time-out + "Reserved4", // 13: Reserved 4 + "Reserved5", // 14: Reserved 5 + "Reserved6", // 15: Reserved 6 + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART1_RX", // 25: USART 1 Receive Complete + "USART1_UDRE", // 26: USART 1 Data Register Empty + "USART1_TX", // 27: USART 1 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "TWI", // 36: 2-Wire Interface + "SPM_READY", // 37: Store Program Memory Ready + "TIMER4_COMPA", // 38: Timer 4 Compare Match A + "TIMER4_COMPB", // 39: Timer 4 Compare Match B + "TIMER4_COMPD", // 40: Timer 4 Compare Match D + "TIMER4_OVF", // 41: Timer 4 Overflow + "TIMER4_FPF", // 42: Timer 4 Fault Protection +}; + +// ATmega161 +const char * const vtab_atmega161[vts_atmega161] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "UART0_RX", // 13: UART 0 Receive Complete + "UART1_RX", // 14: UART 1 Receive Complete + "UART0_UDRE", // 15: UART 0 Data Register Empty + "UART1_UDRE", // 16: UART 1 Data Register Empty + "UART0_TX", // 17: UART 0 Transmit Complete + "UART1_TX", // 18: UART 1 Transmit Complete + "EE_RDY", // 19: EEPROM Ready + "ANA_COMP", // 20: Analog Comparator +}; + +// ATmega1281 ATmega2561 +const char * const vtab_atmega1281[vts_atmega1281] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "INT3", // 4: External Interrupt 3 + "INT4", // 5: External Interrupt 4 + "INT5", // 6: External Interrupt 5 + "INT6", // 7: External Interrupt 6 + "INT7", // 8: External Interrupt 7 + "PCINT0", // 9: Pin Change Interrupt 0 + "PCINT1", // 10: Pin Change Interrupt 1 + "PCINT2", // 11: Pin Change Interrupt 2 + "WDT", // 12: Watchdog Time-out + "TIMER2_COMPA", // 13: Timer 2 Compare Match A + "TIMER2_COMPB", // 14: Timer 2 Compare Match B + "TIMER2_OVF", // 15: Timer 2 Overflow + "TIMER1_CAPT", // 16: Timer 1 Capture Event + "TIMER1_COMPA", // 17: Timer 1 Compare Match A + "TIMER1_COMPB", // 18: Timer 1 Compare Match B + "TIMER1_COMPC", // 19: Timer 1 Compare Match C + "TIMER1_OVF", // 20: Timer 1 Overflow + "TIMER0_COMPA", // 21: Timer 0 Compare Match A + "TIMER0_COMPB", // 22: Timer 0 Compare Match B + "TIMER0_OVF", // 23: Timer 0 Overflow + "SPI_STC", // 24: SPI Serial Transfer Complete + "USART0_RX", // 25: USART 0 Receive Complete + "USART0_UDRE", // 26: USART 0 Data Register Empty + "USART0_TX", // 27: USART 0 Transmit Complete + "ANALOG_COMP", // 28: Analog Comparator + "ADC", // 29: ADC Conversion Complete + "EE_READY", // 30: EEPROM Ready + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_COMPC", // 34: Timer 3 Compare Match C + "TIMER3_OVF", // 35: Timer 3 Overflow + "USART1_RX", // 36: USART 1 Receive Complete + "USART1_UDRE", // 37: USART 1 Data Register Empty + "USART1_TX", // 38: USART 1 Transmit Complete + "TWI", // 39: 2-Wire Interface + "SPM_READY", // 40: Store Program Memory Ready + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_COMPC", // 44: Timer 4 Compare Match C + "TIMER4_OVF", // 45: Timer 4 Overflow + "TIMER5_CAPT", // 46: Timer 5 Capture Event + "TIMER5_COMPA", // 47: Timer 5 Compare Match A + "TIMER5_COMPB", // 48: Timer 5 Compare Match B + "TIMER5_COMPC", // 49: Timer 5 Compare Match C + "TIMER5_OVF", // 50: Timer 5 Overflow + "UNUSED", // 51: not useful owing to limited pin count + "UNUSED", // 52: not useful owing to limited pin count + "UNUSED", // 53: not useful owing to limited pin count + "UNUSED", // 54: not useful owing to limited pin count + "UNUSED", // 55: not useful owing to limited pin count + "UNUSED", // 56: not useful owing to limited pin count +}; + +// ATmega162 +const char * const vtab_atmega162[vts_atmega162] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "TIMER3_CAPT", // 6: Timer 3 Capture Event + "TIMER3_COMPA", // 7: Timer 3 Compare Match A + "TIMER3_COMPB", // 8: Timer 3 Compare Match B + "TIMER3_OVF", // 9: Timer 3 Overflow + "TIMER2_COMP", // 10: Timer 2 Compare Match + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMP", // 16: Timer 0 Compare Match + "TIMER0_OVF", // 17: Timer 0 Overflow + "SPI_STC", // 18: SPI Serial Transfer Complete + "USART0_RXC", // 19: USART 0 Receive Complete + "USART1_RXC", // 20: USART 1 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART1_UDRE", // 22: USART 1 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "USART1_TXC", // 24: USART 1 Transmit Complete + "EE_RDY", // 25: EEPROM Ready + "ANA_COMP", // 26: Analog Comparator + "SPM_RDY", // 27: Store Program Memory Ready +}; + +// ATmega163 +const char * const vtab_atmega163[vts_atmega163] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "TIMER2_COMP", // 3: Timer 2 Compare Match + "TIMER2_OVF", // 4: Timer 2 Overflow + "TIMER1_CAPT", // 5: Timer 1 Capture Event + "TIMER1_COMPA", // 6: Timer 1 Compare Match A + "TIMER1_COMPB", // 7: Timer 1 Compare Match B + "TIMER1_OVF", // 8: Timer 1 Overflow + "TIMER0_OVF", // 9: Timer 0 Overflow + "SPI_STC", // 10: SPI Serial Transfer Complete + "UART_RX", // 11: UART Receive Complete + "UART_UDRE", // 12: UART Data Register Empty + "UART_TX", // 13: UART Transmit Complete + "ADC", // 14: ADC Conversion Complete + "EE_RDY", // 15: EEPROM Ready + "ANA_COMP", // 16: Analog Comparator + "TWI", // 17: 2-Wire Interface +}; + +/* + * ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644A ATmega644P + * ATmega644PA + */ +const char * const vtab_atmega164a[vts_atmega164a] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete +}; + +// ATmega644 +const char * const vtab_atmega644[vts_atmega644] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready +}; + +// ATmega1284 ATmega1284P +const char * const vtab_atmega1284[vts_atmega1284] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI_STC", // 19: SPI Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI", // 26: 2-Wire Interface + "SPM_READY", // 27: Store Program Memory Ready + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_OVF", // 34: Timer 3 Overflow +}; + +// ATmega324PB +const char * const vtab_atmega324pb[vts_atmega324pb] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "INT2", // 3: External Interrupt 2 + "PCINT0", // 4: Pin Change Interrupt 0 + "PCINT1", // 5: Pin Change Interrupt 1 + "PCINT2", // 6: Pin Change Interrupt 2 + "PCINT3", // 7: Pin Change Interrupt 3 + "WDT", // 8: Watchdog Time-out + "TIMER2_COMPA", // 9: Timer 2 Compare Match A + "TIMER2_COMPB", // 10: Timer 2 Compare Match B + "TIMER2_OVF", // 11: Timer 2 Overflow + "TIMER1_CAPT", // 12: Timer 1 Capture Event + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B + "TIMER1_OVF", // 15: Timer 1 Overflow + "TIMER0_COMPA", // 16: Timer 0 Compare Match A + "TIMER0_COMPB", // 17: Timer 0 Compare Match B + "TIMER0_OVF", // 18: Timer 0 Overflow + "SPI0_STC", // 19: SPI 0 Serial Transfer Complete + "USART0_RX", // 20: USART 0 Receive Complete + "USART0_UDRE", // 21: USART 0 Data Register Empty + "USART0_TX", // 22: USART 0 Transmit Complete + "ANALOG_COMP", // 23: Analog Comparator + "ADC", // 24: ADC Conversion Complete + "EE_READY", // 25: EEPROM Ready + "TWI0", // 26: 2-Wire Interface 0 + "SPM_READY", // 27: Store Program Memory Ready + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete + "TIMER3_CAPT", // 31: Timer 3 Capture Event + "TIMER3_COMPA", // 32: Timer 3 Compare Match A + "TIMER3_COMPB", // 33: Timer 3 Compare Match B + "TIMER3_OVF", // 34: Timer 3 Overflow + "USART0_START", // 35: USART 0 Receive Start + "USART1_START", // 36: USART 1 Receive Start + "PCINT4", // 37: Pin Change Interrupt 4 + "XOSCFD", // 38: Crystal Failure Detect + "PTC_EOC", // 39: PTC End of Conversion + "PTC_WCOMP", // 40: PTC Window Comparator Mode + "SPI1_STC", // 41: SPI 1 Serial Transfer Complete + "TWI1", // 42: 2-Wire Interface 1 + "TIMER4_CAPT", // 43: Timer 4 Capture Event + "TIMER4_COMPA", // 44: Timer 4 Compare Match A + "TIMER4_COMPB", // 45: Timer 4 Compare Match B + "TIMER4_OVF", // 46: Timer 4 Overflow + "USART2_RX", // 47: USART 2 Receive Complete + "USART2_UDRE", // 48: USART 2 Data Register Empty + "USART2_TX", // 49: USART 2 Transmit Complete + "USART2_START", // 50: USART 2 Receive Start +}; + +/* + * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA + * ATmega645 ATmega645A ATmega645P + */ +const char * const vtab_atmega165[vts_atmega165] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART0_RX", // 13: USART 0 Receive Complete + "USART0_UDRE", // 14: USART 0 Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready +}; + +// ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P +const char * const vtab_atmega3250[vts_atmega3250] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "PCINT0", // 2: Pin Change Interrupt 0 @@ -4738,35 +4735,6 @@ const char * const vtab_atmega6450p[vts_atmega6450p] = { "PCINT3", // 24: Pin Change Interrupt 3 }; -// ATmega6490P ATmega6490A ATmega6490 ATmega3290PA ATmega3290P ATmega3290A ATmega3290 -const char * const vtab_atmega6490p[vts_atmega6490p] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "PCINT0", // 2: Pin Change Interrupt 0 - "PCINT1", // 3: Pin Change Interrupt 1 - "TIMER2_COMP", // 4: Timer 2 Compare Match - "TIMER2_OVF", // 5: Timer 2 Overflow - "TIMER1_CAPT", // 6: Timer 1 Capture Event - "TIMER1_COMPA", // 7: Timer 1 Compare Match A - "TIMER1_COMPB", // 8: Timer 1 Compare Match B - "TIMER1_OVF", // 9: Timer 1 Overflow - "TIMER0_COMP", // 10: Timer 0 Compare Match - "TIMER0_OVF", // 11: Timer 0 Overflow - "SPI_STC", // 12: SPI Serial Transfer Complete - "USART_RX", // 13: USART Receive Complete - "USART_UDRE", // 14: USART Data Register Empty - "USART0_TX", // 15: USART 0 Transmit Complete - "USI_START", // 16: USI Start Condition - "USI_OVERFLOW", // 17: USI Overflow - "ANALOG_COMP", // 18: Analog Comparator - "ADC", // 19: ADC Conversion Complete - "EE_READY", // 20: EEPROM Ready - "SPM_READY", // 21: Store Program Memory Ready - "LCD", // 22: LCD Start of Frame - "PCINT2", // 23: Pin Change Interrupt 2 - "PCINT3", // 24: Pin Change Interrupt 3 -}; - // ATmega8515 const char * const vtab_atmega8515[vts_atmega8515] = { "RESET", // 0: Reset (various reasons) @@ -4813,165 +4781,210 @@ const char * const vtab_atmega8535[vts_atmega8535] = { "SPM_RDY", // 20: Store Program Memory Ready }; -// AT86RF401 -const char * const vtab_at86rf401[vts_at86rf401] = { - "RESET", // 0: Reset (various reasons) - "TXDONE", // 1: Transmit Complete - "TXEMPTY", // 2: Transmit Register Empty -}; - -// AT90PWM1 -const char * const vtab_at90pwm1[vts_at90pwm1] = { - "RESET", // 0: Reset (various reasons) - "PSC2_CAPT", // 1: PSC 2 Capture Event - "PSC2_EC", // 2: PSC 2 End Cycle - "PSC1_CAPT", // 3: PSC 1 Capture Event - "PSC1_EC", // 4: PSC 1 End Cycle - "PSC0_CAPT", // 5: PSC 0 Capture Event - "PSC0_EC", // 6: PSC 0 End Cycle - "ANALOG_COMP_0", // 7: Analog Comparator 0 - "ANALOG_COMP_1", // 8: Analog Comparator 1 - "ANALOG_COMP_2", // 9: Analog Comparator 2 - "INT0", // 10: External Interrupt 0 - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_COMPA", // 12: Timer 1 Compare Match A - "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "RESERVED15", // 14: Reserved 15 - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMP_A", // 16: Timer 0 Compare Match A - "TIMER0_OVF", // 17: Timer 0 Overflow - "ADC", // 18: ADC Conversion Complete - "INT1", // 19: External Interrupt 1 - "SPI_STC", // 20: SPI Serial Transfer Complete - "RESERVED21", // 21: Reserved 21 - "RESERVED22", // 22: Reserved 22 - "RESERVED23", // 23: Reserved 23 - "INT2", // 24: External Interrupt 2 - "WDT", // 25: Watchdog Time-out - "EE_READY", // 26: EEPROM Ready - "TIMER0_COMPB", // 27: Timer 0 Compare Match B - "INT3", // 28: External Interrupt 3 - "RESERVED30", // 29: Reserved 30 - "RESERVED31", // 30: Reserved 31 - "SPM_READY", // 31: Store Program Memory Ready -}; - -// AT90PWM2 -const char * const vtab_at90pwm2[vts_at90pwm2] = { - "RESET", // 0: Reset (various reasons) - "PSC2_CAPT", // 1: PSC 2 Capture Event - "PSC2_EC", // 2: PSC 2 End Cycle - "PSC1_CAPT", // 3: PSC 1 Capture Event - "PSC1_EC", // 4: PSC 1 End Cycle - "PSC0_CAPT", // 5: PSC 0 Capture Event - "PSC0_EC", // 6: PSC 0 End Cycle - "ANALOG_COMP_0", // 7: Analog Comparator 0 - "ANALOG_COMP_1", // 8: Analog Comparator 1 - "ANALOG_COMP_2", // 9: Analog Comparator 2 - "INT0", // 10: External Interrupt 0 - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_COMPA", // 12: Timer 1 Compare Match A - "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "UNUSED", // 14: not implemented on this device - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMP_A", // 16: Timer 0 Compare Match A - "TIMER0_OVF", // 17: Timer 0 Overflow - "ADC", // 18: ADC Conversion Complete - "INT1", // 19: External Interrupt 1 - "SPI_STC", // 20: SPI Serial Transfer Complete - "USART_RX", // 21: USART Receive Complete - "USART_UDRE", // 22: USART Data Register Empty - "USART_TX", // 23: USART Transmit Complete - "INT2", // 24: External Interrupt 2 - "WDT", // 25: Watchdog Time-out - "EE_READY", // 26: EEPROM Ready - "TIMER0_COMPB", // 27: Timer 0 Compare Match B - "INT3", // 28: External Interrupt 3 - "UNUSED", // 29: not implemented on this device - "UNUSED", // 30: not implemented on this device - "SPM_READY", // 31: Store Program Memory Ready -}; - -// AT90PWM3B AT90PWM3 AT90PWM2B -const char * const vtab_at90pwm3b[vts_at90pwm3b] = { - "RESET", // 0: Reset (various reasons) - "PSC2_CAPT", // 1: PSC 2 Capture Event - "PSC2_EC", // 2: PSC 2 End Cycle - "PSC1_CAPT", // 3: PSC 1 Capture Event - "PSC1_EC", // 4: PSC 1 End Cycle - "PSC0_CAPT", // 5: PSC 0 Capture Event - "PSC0_EC", // 6: PSC 0 End Cycle - "ANALOG_COMP_0", // 7: Analog Comparator 0 - "ANALOG_COMP_1", // 8: Analog Comparator 1 - "ANALOG_COMP_2", // 9: Analog Comparator 2 - "INT0", // 10: External Interrupt 0 - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_COMPA", // 12: Timer 1 Compare Match A - "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "RESERVED15", // 14: Reserved 15 - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMPA", // 16: Timer 0 Compare Match A - "TIMER0_OVF", // 17: Timer 0 Overflow - "ADC", // 18: ADC Conversion Complete - "INT1", // 19: External Interrupt 1 - "SPI_STC", // 20: SPI Serial Transfer Complete - "USART_RX", // 21: USART Receive Complete - "USART_UDRE", // 22: USART Data Register Empty - "USART_TX", // 23: USART Transmit Complete - "INT2", // 24: External Interrupt 2 - "WDT", // 25: Watchdog Time-out - "EE_READY", // 26: EEPROM Ready - "TIMER0_COMPB", // 27: Timer 0 Compare Match B - "INT3", // 28: External Interrupt 3 - "RESERVED30", // 29: Reserved 30 - "RESERVED31", // 30: Reserved 31 - "SPM_READY", // 31: Store Program Memory Ready -}; - -// AT90SCR100H AT90SCR100 -const char * const vtab_at90scr100h[vts_at90scr100h] = { +/* + * ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168A + * ATmega168P ATmega168PA ATmega328P LGT8F88P LGT8F168P LGT8F328P ATA6612C ATA6613C ATA6614Q + */ +const char * const vtab_atmega48[vts_atmega48] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 - "INT2", // 3: External Interrupt 2 - "INT3", // 4: External Interrupt 3 - "PCINT0", // 5: Pin Change Interrupt 0 - "PCINT1", // 6: Pin Change Interrupt 1 - "PCINT2", // 7: Pin Change Interrupt 2 - "WDT", // 8: Watchdog Time-out - "TIMER2_COMPA", // 9: Timer 2 Compare Match A - "TIMER2_COMPB", // 10: Timer 2 Compare Match B - "TIMER2_OVF", // 11: Timer 2 Overflow - "TIMER1_CAPT", // 12: Timer 1 Capture Event - "TIMER1_COMPA", // 13: Timer 1 Compare Match A - "TIMER1_COMPB", // 14: Timer 1 Compare Match B - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMPA", // 16: Timer 0 Compare Match A - "TIMER0_COMPB", // 17: Timer 0 Compare Match B - "TIMER0_OVF", // 18: Timer 0 Overflow - "SPI_STC", // 19: SPI Serial Transfer Complete - "USART0_RX", // 20: USART 0 Receive Complete - "USART0_UDRE", // 21: USART 0 Data Register Empty - "USART0_TX", // 22: USART 0 Transmit Complete - "SUPPLY_MON", // 23: Supply Monitor - "RFU", // 24: Reserved for Future Use - "EE_READY", // 25: EEPROM Ready - "TWI", // 26: 2-Wire Interface - "SPM_READY", // 27: Store Program Memory Ready - "KEYBOARD", // 28: Keyboard Input Change - "AES_Operation", // 29: AES Operation - "HSSPI", // 30: High-Speed SPI - "USB_Endpoint", // 31: USB Endpoint - "USB_Protocol", // 32: USB Protocol - "SCIB", // 33: Smart Card Reader Interface - "USBHost_Control", // 34: USB Host Controller - "USBHost_Pipe", // 35: USB Host Pipe - "CPRES", // 36: Card Presence Detection - "PCINT3", // 37: Pin Change Interrupt 3 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART_RX", // 18: USART Receive Complete + "USART_UDRE", // 19: USART Data Register Empty + "USART_TX", // 20: USART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI", // 24: 2-Wire Interface + "SPM_Ready", // 25: Store Program Memory Ready }; -// AT90CAN128 AT90CAN64 AT90CAN32 -const char * const vtab_at90can128[vts_at90can128] = { +// ATmega168 ATmega328 +const char * const vtab_atmega168[vts_atmega168] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART_RX", // 18: USART Receive Complete + "USART_UDRE", // 19: USART Data Register Empty + "USART_TX", // 20: USART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI", // 24: 2-Wire Interface + "SPM_READY", // 25: Store Program Memory Ready +}; + +// ATmega48PB ATmega88PB ATmega168PB +const char * const vtab_atmega48pb[vts_atmega48pb] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "USART_RX", // 18: USART Receive Complete + "USART_UDRE", // 19: USART Data Register Empty + "USART_TX", // 20: USART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI", // 24: 2-Wire Interface + "SPM_Ready", // 25: Store Program Memory Ready + "USART_START", // 26: USART Start +}; + +// ATmega328PB +const char * const vtab_atmega328pb[vts_atmega328pb] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCINT0", // 3: Pin Change Interrupt 0 + "PCINT1", // 4: Pin Change Interrupt 1 + "PCINT2", // 5: Pin Change Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER2_COMPA", // 7: Timer 2 Compare Match A + "TIMER2_COMPB", // 8: Timer 2 Compare Match B + "TIMER2_OVF", // 9: Timer 2 Overflow + "TIMER1_CAPT", // 10: Timer 1 Capture Event + "TIMER1_COMPA", // 11: Timer 1 Compare Match A + "TIMER1_COMPB", // 12: Timer 1 Compare Match B + "TIMER1_OVF", // 13: Timer 1 Overflow + "TIMER0_COMPA", // 14: Timer 0 Compare Match A + "TIMER0_COMPB", // 15: Timer 0 Compare Match B + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI0_STC", // 17: SPI 0 Serial Transfer Complete + "USART0_RX", // 18: USART 0 Receive Complete + "USART0_UDRE", // 19: USART 0 Data Register Empty + "USART0_TX", // 20: USART 0 Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator + "TWI0", // 24: 2-Wire Interface 0 + "SPM_Ready", // 25: Store Program Memory Ready + "USART0_START", // 26: USART 0 Receive Start + "PCINT3", // 27: Pin Change Interrupt 3 + "USART1_RX", // 28: USART 1 Receive Complete + "USART1_UDRE", // 29: USART 1 Data Register Empty + "USART1_TX", // 30: USART 1 Transmit Complete + "USART1_START", // 31: USART 1 Receive Start + "TIMER3_CAPT", // 32: Timer 3 Capture Event + "TIMER3_COMPA", // 33: Timer 3 Compare Match A + "TIMER3_COMPB", // 34: Timer 3 Compare Match B + "TIMER3_OVF", // 35: Timer 3 Overflow + "CFD", // 36: Clock Failure Detection + "PTC_EOC", // 37: PTC End of Conversion + "PTC_WCOMP", // 38: PTC Window Comparator Mode + "SPI1_STC", // 39: SPI 1 Serial Transfer Complete + "TWI1", // 40: 2-Wire Interface 1 + "TIMER4_CAPT", // 41: Timer 4 Capture Event + "TIMER4_COMPA", // 42: Timer 4 Compare Match A + "TIMER4_COMPB", // 43: Timer 4 Compare Match B + "TIMER4_OVF", // 44: Timer 4 Overflow +}; + +/* + * ATmega169 ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P ATmega329PA + * ATmega649 ATmega649A ATmega649P + */ +const char * const vtab_atmega169[vts_atmega169] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART0_RX", // 13: USART 0 Receive Complete + "USART0_UDRE", // 14: USART 0 Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready + "LCD", // 22: LCD Start of Frame +}; + +// ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P +const char * const vtab_atmega3290[vts_atmega3290] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "TIMER2_COMP", // 4: Timer 2 Compare Match + "TIMER2_OVF", // 5: Timer 2 Overflow + "TIMER1_CAPT", // 6: Timer 1 Capture Event + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_COMP", // 10: Timer 0 Compare Match + "TIMER0_OVF", // 11: Timer 0 Overflow + "SPI_STC", // 12: SPI Serial Transfer Complete + "USART_RX", // 13: USART Receive Complete + "USART_UDRE", // 14: USART Data Register Empty + "USART0_TX", // 15: USART 0 Transmit Complete + "USI_START", // 16: USI Start Condition + "USI_OVERFLOW", // 17: USI Overflow + "ANALOG_COMP", // 18: Analog Comparator + "ADC", // 19: ADC Conversion Complete + "EE_READY", // 20: EEPROM Ready + "SPM_READY", // 21: Store Program Memory Ready + "LCD", // 22: LCD Start of Frame + "PCINT2", // 23: Pin Change Interrupt 2 + "PCINT3", // 24: Pin Change Interrupt 3 +}; + +// ATmega103 +const char * const vtab_atmega103[vts_atmega103] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -4986,168 +4999,156 @@ const char * const vtab_at90can128[vts_at90can128] = { "TIMER1_CAPT", // 11: Timer 1 Capture Event "TIMER1_COMPA", // 12: Timer 1 Compare Match A "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "TIMER1_COMPC", // 14: Timer 1 Compare Match C - "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMP", // 16: Timer 0 Compare Match - "TIMER0_OVF", // 17: Timer 0 Overflow - "CANIT", // 18: CAN Transfer Complete or Error - "OVRIT", // 19: CAN Timer Overrun - "SPI_STC", // 20: SPI Serial Transfer Complete - "USART0_RX", // 21: USART 0 Receive Complete - "USART0_UDRE", // 22: USART 0 Data Register Empty - "USART0_TX", // 23: USART 0 Transmit Complete - "ANALOG_COMP", // 24: Analog Comparator - "ADC", // 25: ADC Conversion Complete - "EE_READY", // 26: EEPROM Ready - "TIMER3_CAPT", // 27: Timer 3 Capture Event - "TIMER3_COMPA", // 28: Timer 3 Compare Match A - "TIMER3_COMPB", // 29: Timer 3 Compare Match B - "TIMER3_COMPC", // 30: Timer 3 Compare Match C - "TIMER3_OVF", // 31: Timer 3 Overflow - "USART1_RX", // 32: USART 1 Receive Complete - "USART1_UDRE", // 33: USART 1 Data Register Empty - "USART1_TX", // 34: USART 1 Transmit Complete - "TWI", // 35: 2-Wire Interface - "SPM_READY", // 36: Store Program Memory Ready + "TIMER1_OVF", // 14: Timer 1 Overflow + "TIMER0_COMP", // 15: Timer 0 Compare Match + "TIMER0_OVF", // 16: Timer 0 Overflow + "SPI_STC", // 17: SPI Serial Transfer Complete + "UART_RX", // 18: UART Receive Complete + "UART_UDRE", // 19: UART Data Register Empty + "UART_TX", // 20: UART Transmit Complete + "ADC", // 21: ADC Conversion Complete + "EE_READY", // 22: EEPROM Ready + "ANALOG_COMP", // 23: Analog Comparator }; -// AT90PWM161 AT90PWM81 -const char * const vtab_at90pwm161[vts_at90pwm161] = { +// ATmega8HVA ATmega16HVA +const char * const vtab_atmega8hva[vts_atmega8hva] = { "RESET", // 0: Reset (various reasons) - "PSC2_CAPT", // 1: PSC 2 Capture Event - "PSC2_EC", // 2: PSC 2 End Cycle - "PSC2_EEC", // 3: PSC 2 End Of Enhanced Cycle - "PSC0_CAPT", // 4: PSC 0 Capture Event - "PSC0_EC", // 5: PSC 0 End Cycle - "PSC0_EEC", // 6: PSC 0 End Of Enhanced Cycle - "ANALOG_COMP_1", // 7: Analog Comparator 1 - "ANALOG_COMP_2", // 8: Analog Comparator 2 - "ANALOG_COMP_3", // 9: Analog Comparator 3 - "INT0", // 10: External Interrupt 0 - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_OVF", // 12: Timer 1 Overflow - "ADC", // 13: ADC Conversion Complete - "INT1", // 14: External Interrupt 1 + "BPINT", // 1: Battery Protection Interrupt + "VREGMON", // 2: Voltage Regulator Monitor + "INT0", // 3: External Interrupt 0 + "INT1", // 4: External Interrupt 1 + "INT2", // 5: External Interrupt 2 + "WDT", // 6: Watchdog Time-out + "TIMER1_IC", // 7: Timer 1 Input Capture + "TIMER1_COMPA", // 8: Timer 1 Compare Match A + "TIMER1_COMPB", // 9: Timer 1 Compare Match B + "TIMER1_OVF", // 10: Timer 1 Overflow + "TIMER0_IC", // 11: Timer 0 Capture Event + "TIMER0_COMPA", // 12: Timer 0 Compare Match A + "TIMER0_COMPB", // 13: Timer 0 Compare Match B + "TIMER0_OVF", // 14: Timer 0 Overflow "SPI_STC", // 15: SPI Serial Transfer Complete - "INT2", // 16: External Interrupt 2 - "WDT", // 17: Watchdog Time-out - "EE_READY", // 18: EEPROM Ready - "SPM_READY", // 19: Store Program Memory Ready + "VADC", // 16: Voltage ADC Conversion Complete + "CCADC_CONV", // 17: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 18: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 19: Coloumb Counter ADC Accumulator + "EE_READY", // 20: EEPROM Ready }; -// AT90PWM316 AT90PWM216 -const char * const vtab_at90pwm316[vts_at90pwm316] = { +// ATmega16HVA2 +const char * const vtab_atmega16hva2[vts_atmega16hva2] = { "RESET", // 0: Reset (various reasons) - "PSC2_CAPT", // 1: PSC 2 Capture Event - "PSC2_EC", // 2: PSC 2 End Cycle - "PSC1_CAPT", // 3: PSC 1 Capture Event - "PSC1_EC", // 4: PSC 1 End Cycle - "PSC0_CAPT", // 5: PSC 0 Capture Event - "PSC0_EC", // 6: PSC 0 End Cycle - "ANALOG_COMP_0", // 7: Analog Comparator 0 - "ANALOG_COMP_1", // 8: Analog Comparator 1 - "ANALOG_COMP_2", // 9: Analog Comparator 2 - "INT0", // 10: External Interrupt 0 - "TIMER1_CAPT", // 11: Timer 1 Capture Event - "TIMER1_COMPA", // 12: Timer 1 Compare Match A - "TIMER1_COMPB", // 13: Timer 1 Compare Match B - "RESERVED15", // 14: Reserved 15 + "BPINT", // 1: Battery Protection Interrupt + "VREGMON", // 2: Voltage Regulator Monitor + "INT0", // 3: External Interrupt 0 + "INT1", // 4: External Interrupt 1 + "INT2", // 5: External Interrupt 2 + "PCINT0", // 6: Pin Change Interrupt 0 + "WDT", // 7: Watchdog Time-out + "TIMER1_IC", // 8: Timer 1 Input Capture + "TIMER1_COMPA", // 9: Timer 1 Compare Match A + "TIMER1_COMPB", // 10: Timer 1 Compare Match B + "TIMER1_OVF", // 11: Timer 1 Overflow + "TIMER0_IC", // 12: Timer 0 Capture Event + "TIMER0_COMPA", // 13: Timer 0 Compare Match A + "TIMER0_COMPB", // 14: Timer 0 Compare Match B + "TIMER0_OVF", // 15: Timer 0 Overflow + "SPI_STC", // 16: SPI Serial Transfer Complete + "VADC", // 17: Voltage ADC Conversion Complete + "CCADC_CONV", // 18: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 19: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 20: Coloumb Counter ADC Accumulator + "EE_READY", // 21: EEPROM Ready +}; + +// ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB +const char * const vtab_atmega16hvb[vts_atmega16hvb] = { + "RESET", // 0: Reset (various reasons) + "BPINT", // 1: Battery Protection Interrupt + "VREGMON", // 2: Voltage Regulator Monitor + "INT0", // 3: External Interrupt 0 + "INT1", // 4: External Interrupt 1 + "INT2", // 5: External Interrupt 2 + "INT3", // 6: External Interrupt 3 + "PCINT0", // 7: Pin Change Interrupt 0 + "PCINT1", // 8: Pin Change Interrupt 1 + "WDT", // 9: Watchdog Time-out + "BGSCD", // 10: Bandgap Buffer Short Circuit Detected + "CHDET", // 11: Charger Detect + "TIMER1_IC", // 12: Timer 1 Input Capture + "TIMER1_COMPA", // 13: Timer 1 Compare Match A + "TIMER1_COMPB", // 14: Timer 1 Compare Match B "TIMER1_OVF", // 15: Timer 1 Overflow - "TIMER0_COMP_A", // 16: Timer 0 Compare Match A - "TIMER0_OVF", // 17: Timer 0 Overflow - "ADC", // 18: ADC Conversion Complete - "INT1", // 19: External Interrupt 1 - "SPI_STC", // 20: SPI Serial Transfer Complete - "USART_RX", // 21: USART Receive Complete - "USART_UDRE", // 22: USART Data Register Empty - "USART_TX", // 23: USART Transmit Complete - "INT2", // 24: External Interrupt 2 - "WDT", // 25: Watchdog Time-out - "EE_READY", // 26: EEPROM Ready - "TIMER0_COMPB", // 27: Timer 0 Compare Match B - "INT3", // 28: External Interrupt 3 - "RESERVED30", // 29: Reserved 30 - "RESERVED31", // 30: Reserved 31 - "SPM_READY", // 31: Store Program Memory Ready + "TIMER0_IC", // 16: Timer 0 Capture Event + "TIMER0_COMPA", // 17: Timer 0 Compare Match A + "TIMER0_COMPB", // 18: Timer 0 Compare Match B + "TIMER0_OVF", // 19: Timer 0 Overflow + "TWIBUSCD", // 20: 2-Wire Interface Bus Connect/Disconnect + "TWI", // 21: 2-Wire Interface + "SPI_STC", // 22: SPI Serial Transfer Complete + "VADC", // 23: Voltage ADC Conversion Complete + "CCADC_CONV", // 24: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 25: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 26: Coloumb Counter ADC Accumulator + "EE_READY", // 27: EEPROM Ready + "SPM", // 28: SPM Ready }; -// AT90S1200 -const char * const vtab_at90s1200[vts_at90s1200] = { +// ATmega64HVE ATmega32HVE2 ATmega64HVE2 +const char * const vtab_atmega64hve[vts_atmega64hve] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 - "TIMER0_OVF", // 2: Timer 0 Overflow - "ANA_COMP", // 3: Analog Comparator + "PCINT0", // 2: Pin Change Interrupt 0 + "PCINT1", // 3: Pin Change Interrupt 1 + "WDT", // 4: Watchdog Time-out + "WAKEUP", // 5: Wake Up + "TIMER1_IC", // 6: Timer 1 Input Capture + "TIMER1_COMPA", // 7: Timer 1 Compare Match A + "TIMER1_COMPB", // 8: Timer 1 Compare Match B + "TIMER1_OVF", // 9: Timer 1 Overflow + "TIMER0_IC", // 10: Timer 0 Capture Event + "TIMER0_COMPA", // 11: Timer 0 Compare Match A + "TIMER0_COMPB", // 12: Timer 0 Compare Match B + "TIMER0_OVF", // 13: Timer 0 Overflow + "LIN_STATUS", // 14: LIN Status Change + "LIN_ERROR", // 15: LIN Error + "SPI_STC", // 16: SPI Serial Transfer Complete + "VADC_CONV", // 17: Versatile Analog to Digital Conversion + "VADC_ACC", // 18: Versatile Analog to Digital Compare or Capture + "CADC_CONV", // 19: C-ADC Instantaneous Conversion Complete + "CADC_REG_CUR", // 20: C-ADC Regular Current + "CADC_ACC", // 21: C-ADC Accumulated Conversion Complete + "EE_READY", // 22: EEPROM Ready + "SPM", // 23: SPM Ready + "PLL", // 24: PLL }; -// AT90S2313 -const char * const vtab_at90s2313[vts_at90s2313] = { +// ATmega406 +const char * const vtab_atmega406[vts_atmega406] = { "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "TIMER1_CAPT1", // 3: Timer 1 Capture Event - "TIMER1_COMP1", // 4: Timer 1 Compare - "TIMER1_OVF1", // 5: Timer 1 Overflow - "TIMER0_OVF0", // 6: Timer 0 Overflow - "UART_RX", // 7: UART Receive Complete - "UART_UDRE", // 8: UART Data Register Empty - "UART_TX", // 9: UART Transmit Complete - "ANA_COMP", // 10: Analog Comparator -}; - -// AT90S4433 AT90S2333 -const char * const vtab_at90s4433[vts_at90s4433] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "TIMER1_CAPT", // 3: Timer 1 Capture Event - "TIMER1_COMP", // 4: Timer 1 Compare - "TIMER1_OVF", // 5: Timer 1 Overflow - "TIMER0_OVF", // 6: Timer 0 Overflow - "SPI_STC", // 7: SPI Serial Transfer Complete - "UART_RX", // 8: UART Receive Complete - "UART_UDRE", // 9: UART Data Register Empty - "UART_TX", // 10: UART Transmit Complete - "ADC", // 11: ADC Conversion Complete - "EE_RDY", // 12: EEPROM Ready - "ANA_COMP", // 13: Analog Comparator -}; - -// AT90S8515 AT90S4414 -const char * const vtab_at90s8515[vts_at90s8515] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "TIMER1_CAPT", // 3: Timer 1 Capture Event - "TIMER1_COMPA", // 4: Timer 1 Compare Match A - "TIMER1_COMPB", // 5: Timer 1 Compare Match B - "TIMER1_OVF", // 6: Timer 1 Overflow - "TIMER0_OVF", // 7: Timer 0 Overflow - "SPI_STC", // 8: SPI Serial Transfer Complete - "UART_RX", // 9: UART Receive Complete - "UART_UDRE", // 10: UART Data Register Empty - "UART_TX", // 11: UART Transmit Complete - "ANA_COMP", // 12: Analog Comparator -}; - -// AT90S8535 AT90S4434 -const char * const vtab_at90s8535[vts_at90s8535] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "TIMER2_COMP", // 3: Timer 2 Compare Match - "TIMER2_OVF", // 4: Timer 2 Overflow - "TIMER1_CAPT", // 5: Timer 1 Capture Event - "TIMER1_COMPA", // 6: Timer 1 Compare Match A - "TIMER1_COMPB", // 7: Timer 1 Compare Match B - "TIMER1_OVF", // 8: Timer 1 Overflow - "TIMER0_OVF", // 9: Timer 0 Overflow - "SPI_STC", // 10: SPI Serial Transfer Complete - "UART_RX", // 11: UART Receive Complete - "UART_UDRE", // 12: UART Data Register Empty - "UART_TX", // 13: UART Transmit Complete - "ADC", // 14: ADC Conversion Complete - "EE_RDY", // 15: EEPROM Ready - "ANA_COMP", // 16: Analog Comparator + "BPINT", // 1: Battery Protection Interrupt + "INT0", // 2: External Interrupt 0 + "INT1", // 3: External Interrupt 1 + "INT2", // 4: External Interrupt 2 + "INT3", // 5: External Interrupt 3 + "PCINT0", // 6: Pin Change Interrupt 0 + "PCINT1", // 7: Pin Change Interrupt 1 + "WDT", // 8: Watchdog Time-out + "WAKE_UP", // 9: Wake Up + "TIM1_COMP", // 10: Timer 1 Compare and Match + "TIM1_OVF", // 11: Timer 1 Overflow + "TIM0_COMPA", // 12: Timer 0 Compare Match A + "TIM0_COMPB", // 13: Timer 0 Compare Match B + "TIM0_OVF", // 14: Timer 0 Overflow + "TWI_BUS_CD", // 15: 2-Wire Interface Bus Connect/Disconnect + "TWI", // 16: 2-Wire Interface + "VADC", // 17: Voltage ADC Conversion Complete + "CCADC_CONV", // 18: Coulomb Counter ADC Conversion Complete + "CCADC_REG_CUR", // 19: Coloumb Counter ADC Regular Current + "CCADC_ACC", // 20: Coloumb Counter ADC Accumulator + "EE_READY", // 21: EEPROM Ready + "SPM_READY", // 22: Store Program Memory Ready }; // ATA5272 @@ -5191,8 +5192,8 @@ const char * const vtab_ata5272[vts_ata5272] = { "USI_START", // 36: USI Start Condition }; -// ATA5702M322 ATA5700M322 -const char * const vtab_ata5702m322[vts_ata5702m322] = { +// ATA5700M322 ATA5702M322 +const char * const vtab_ata5700m322[vts_ata5700m322] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -5246,6 +5247,100 @@ const char * const vtab_ata5702m322[vts_ata5702m322] = { "TWI2", // 50: 2-Wire Interface 2 }; +// ATA5781 ATA5782 ATA5783 ATA5831 ATA5832 ATA5833 ATA8210 ATA8215 ATA8510 ATA8515 +const char * const vtab_ata5781[vts_ata5781] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCI0", // 3: Pin Change Interrupt Request 0 + "PCI1", // 4: Pin Change Interrupt Request 1 + "VMON", // 5: Voltage Monitoring + "AVCCR", // 6: AVCC Reset + "AVCCL", // 7: AVCC Low + "T0INT", // 8: Timer 0 Interrupt + "T1COMP", // 9: Timer 1 Compare and Match + "T1OVF", // 10: Timer 1 Overflow + "T2COMP", // 11: Timer 2 Compare and Match + "T2OVF", // 12: Timer 2 Overflow + "T3CAP", // 13: Timer 3 Capture Event + "T3COMP", // 14: Timer 3 Compare and Match + "T3OVF", // 15: Timer 3 Overflow + "T4CAP", // 16: Timer 4 Capture Event + "T4COMP", // 17: Timer 4 Compare and Match + "T4OVF", // 18: Timer 4 Overflow + "T5COMP", // 19: Timer 5 Compare and Match + "T5OVF", // 20: Timer 5 Overflow + "SPI", // 21: SPI Serial Peripheral Interface + "SRX_FIFO", // 22: SPI Receive Buffer + "STX_FIFO", // 23: SPI Transmit Buffer + "SSM", // 24: Sequencer State Machine + "DFFLR", // 25: Data FIFO Fill Level Reached + "DFOUE", // 26: Data FIFO Overflow or Underflow Error + "SFFLR", // 27: RSSI/Preamble FIFO Fill Level Reached + "SFOUE", // 28: RSSI/Preamble FIFO Overflow or Underflow Error + "TMTCF", // 29: Transmit Modulator Telegram Finished + "UHF_WCOB", // 30: UHF Receiver Wake Up OK on Receive Path B + "UHF_WCOA", // 31: UHF Receiver Wake Up OK on Receive Path A + "UHF_SOTB", // 32: UHF Receiver Start of Telegram OK on Receive Path B + "UHF_SOTA", // 33: UHF Receiver Start of Telegram OK on Receive Path A + "UHF_EOTB", // 34: UHF Receiver End of Telegram on Receive Path B + "UHF_EOTA", // 35: UHF Receiver End of Telegram on Receive Path A + "UHF_NBITB", // 36: UHF Receiver New Bit on Receive Path B + "UHF_NBITA", // 37: UHF Receiver New Bit on Receive Path A + "EXCM", // 38: External Input Clock Break Down + "ERDY", // 39: EEPROM Ready + "SPMR", // 40: Store Program Memory Ready + "IDFULL", // 41: IDSCAN Full +}; + +// ATA5787 ATA5835 +const char * const vtab_ata5787[vts_ata5787] = { + "RESET", // 0: Reset (various reasons) + "INT0", // 1: External Interrupt 0 + "INT1", // 2: External Interrupt 1 + "PCI0", // 3: Pin Change Interrupt Request 0 + "PCI1", // 4: Pin Change Interrupt Request 1 + "VMON", // 5: Voltage Monitoring + "AVCCR", // 6: AVCC Reset + "AVCCL", // 7: AVCC Low + "T0INT", // 8: Timer 0 Interrupt + "T1COMP", // 9: Timer 1 Compare and Match + "T1OVF", // 10: Timer 1 Overflow + "T2COMP", // 11: Timer 2 Compare and Match + "T2OVF", // 12: Timer 2 Overflow + "T3CAP", // 13: Timer 3 Capture Event + "T3COMP", // 14: Timer 3 Compare and Match + "T3OVF", // 15: Timer 3 Overflow + "T4CAP", // 16: Timer 4 Capture Event + "T4COMP", // 17: Timer 4 Compare and Match + "T4OVF", // 18: Timer 4 Overflow + "T5COMP", // 19: Timer 5 Compare and Match + "T5OVF", // 20: Timer 5 Overflow + "SPI", // 21: SPI Serial Peripheral Interface + "SRX_FIFO", // 22: SPI Receive Buffer + "STX_FIFO", // 23: SPI Transmit Buffer + "LINTC", // 24: LIN Transfer Complete + "LINERR", // 25: LIN Error + "SSM", // 26: Sequencer State Machine + "DFFLR", // 27: Data FIFO Fill Level Reached + "DFOUE", // 28: Data FIFO Overflow or Underflow Error + "SFFLR", // 29: RSSI/Preamble FIFO Fill Level Reached + "SFOUE", // 30: RSSI/Preamble FIFO Overflow or Underflow Error + "TMTCF", // 31: Transmit Modulator Telegram Finished + "UHF_WCOA", // 32: UHF Receiver Wake Up OK on Receive Path A + "UHF_WCOB", // 33: UHF Receiver Wake Up OK on Receive Path B + "UHF_SOTA", // 34: UHF Receiver Start of Telegram OK on Receive Path A + "UHF_SOTB", // 35: UHF Receiver Start of Telegram OK on Receive Path B + "UHF_EOTA", // 36: UHF Receiver End of Telegram on Receive Path A + "UHF_EOTB", // 37: UHF Receiver End of Telegram on Receive Path B + "UHF_NBITA", // 38: UHF Receiver New Bit on Receive Path A + "UHF_NBITB", // 39: UHF Receiver New Bit on Receive Path B + "EXCM", // 40: External Input Clock Break Down + "ERDY", // 41: EEPROM Ready + "SPMR", // 42: Store Program Memory Ready + "IDFULL", // 43: IDSCAN Full +}; + // ATA5790 const char * const vtab_ata5790[vts_ata5790] = { "RESET", // 0: Reset (various reasons) @@ -5280,8 +5375,8 @@ const char * const vtab_ata5790[vts_ata5790] = { "SPMREADY", // 29: Store Program Memory Ready }; -// ATA5791 ATA5790N -const char * const vtab_ata5791[vts_ata5791] = { +// ATA5790N ATA5791 +const char * const vtab_ata5790n[vts_ata5790n] = { "RESET", // 0: Reset (various reasons) "TPINT", // 1: Transponder Mode Interrupt "INT0", // 2: External Interrupt 0 @@ -5342,56 +5437,8 @@ const char * const vtab_ata5795[vts_ata5795] = { "SPMREADY", // 22: Store Program Memory Ready }; -// ATA5835 ATA5787 -const char * const vtab_ata5835[vts_ata5835] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCI0", // 3: Pin Change Interrupt Request 0 - "PCI1", // 4: Pin Change Interrupt Request 1 - "VMON", // 5: Voltage Monitoring - "AVCCR", // 6: AVCC Reset - "AVCCL", // 7: AVCC Low - "T0INT", // 8: Timer 0 Interrupt - "T1COMP", // 9: Timer 1 Compare and Match - "T1OVF", // 10: Timer 1 Overflow - "T2COMP", // 11: Timer 2 Compare and Match - "T2OVF", // 12: Timer 2 Overflow - "T3CAP", // 13: Timer 3 Capture Event - "T3COMP", // 14: Timer 3 Compare and Match - "T3OVF", // 15: Timer 3 Overflow - "T4CAP", // 16: Timer 4 Capture Event - "T4COMP", // 17: Timer 4 Compare and Match - "T4OVF", // 18: Timer 4 Overflow - "T5COMP", // 19: Timer 5 Compare and Match - "T5OVF", // 20: Timer 5 Overflow - "SPI", // 21: SPI Serial Peripheral Interface - "SRX_FIFO", // 22: SPI Receive Buffer - "STX_FIFO", // 23: SPI Transmit Buffer - "LINTC", // 24: LIN Transfer Complete - "LINERR", // 25: LIN Error - "SSM", // 26: Sequencer State Machine - "DFFLR", // 27: Data FIFO Fill Level Reached - "DFOUE", // 28: Data FIFO Overflow or Underflow Error - "SFFLR", // 29: RSSI/Preamble FIFO Fill Level Reached - "SFOUE", // 30: RSSI/Preamble FIFO Overflow or Underflow Error - "TMTCF", // 31: Transmit Modulator Telegram Finished - "UHF_WCOA", // 32: UHF Receiver Wake Up OK on Receive Path A - "UHF_WCOB", // 33: UHF Receiver Wake Up OK on Receive Path B - "UHF_SOTA", // 34: UHF Receiver Start of Telegram OK on Receive Path A - "UHF_SOTB", // 35: UHF Receiver Start of Telegram OK on Receive Path B - "UHF_EOTA", // 36: UHF Receiver End of Telegram on Receive Path A - "UHF_EOTB", // 37: UHF Receiver End of Telegram on Receive Path B - "UHF_NBITA", // 38: UHF Receiver New Bit on Receive Path A - "UHF_NBITB", // 39: UHF Receiver New Bit on Receive Path B - "EXCM", // 40: External Input Clock Break Down - "ERDY", // 41: EEPROM Ready - "SPMR", // 42: Store Program Memory Ready - "IDFULL", // 43: IDSCAN Full -}; - -// ATA6289 ATA6286 ATA6285 -const char * const vtab_ata6289[vts_ata6289] = { +// ATA6285 ATA6286 ATA6289 +const char * const vtab_ata6285[vts_ata6285] = { "RESET", // 0: Reset (various reasons) "INT0", // 1: External Interrupt 0 "INT1", // 2: External Interrupt 1 @@ -5421,425 +5468,8 @@ const char * const vtab_ata6289[vts_ata6289] = { "SPM_RDY", // 26: Store Program Memory Ready }; -// ATA8515 ATA8510 ATA8215 ATA8210 ATA5833 ATA5832 ATA5831 ATA5783 ATA5782 ATA5781 -const char * const vtab_ata8515[vts_ata8515] = { - "RESET", // 0: Reset (various reasons) - "INT0", // 1: External Interrupt 0 - "INT1", // 2: External Interrupt 1 - "PCI0", // 3: Pin Change Interrupt Request 0 - "PCI1", // 4: Pin Change Interrupt Request 1 - "VMON", // 5: Voltage Monitoring - "AVCCR", // 6: AVCC Reset - "AVCCL", // 7: AVCC Low - "T0INT", // 8: Timer 0 Interrupt - "T1COMP", // 9: Timer 1 Compare and Match - "T1OVF", // 10: Timer 1 Overflow - "T2COMP", // 11: Timer 2 Compare and Match - "T2OVF", // 12: Timer 2 Overflow - "T3CAP", // 13: Timer 3 Capture Event - "T3COMP", // 14: Timer 3 Compare and Match - "T3OVF", // 15: Timer 3 Overflow - "T4CAP", // 16: Timer 4 Capture Event - "T4COMP", // 17: Timer 4 Compare and Match - "T4OVF", // 18: Timer 4 Overflow - "T5COMP", // 19: Timer 5 Compare and Match - "T5OVF", // 20: Timer 5 Overflow - "SPI", // 21: SPI Serial Peripheral Interface - "SRX_FIFO", // 22: SPI Receive Buffer - "STX_FIFO", // 23: SPI Transmit Buffer - "SSM", // 24: Sequencer State Machine - "DFFLR", // 25: Data FIFO Fill Level Reached - "DFOUE", // 26: Data FIFO Overflow or Underflow Error - "SFFLR", // 27: RSSI/Preamble FIFO Fill Level Reached - "SFOUE", // 28: RSSI/Preamble FIFO Overflow or Underflow Error - "TMTCF", // 29: Transmit Modulator Telegram Finished - "UHF_WCOB", // 30: UHF Receiver Wake Up OK on Receive Path B - "UHF_WCOA", // 31: UHF Receiver Wake Up OK on Receive Path A - "UHF_SOTB", // 32: UHF Receiver Start of Telegram OK on Receive Path B - "UHF_SOTA", // 33: UHF Receiver Start of Telegram OK on Receive Path A - "UHF_EOTB", // 34: UHF Receiver End of Telegram on Receive Path B - "UHF_EOTA", // 35: UHF Receiver End of Telegram on Receive Path A - "UHF_NBITB", // 36: UHF Receiver New Bit on Receive Path B - "UHF_NBITA", // 37: UHF Receiver New Bit on Receive Path A - "EXCM", // 38: External Input Clock Break Down - "ERDY", // 39: EEPROM Ready - "SPMR", // 40: Store Program Memory Ready - "IDFULL", // 41: IDSCAN Full -}; - -// ATxmega32A4 ATxmega16A4 -const char * const vtab_atxmega32a4[vts_atxmega32a4] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "DMA_CH0", // 6: DMA Channel 0 - "DMA_CH1", // 7: DMA Channel 1 - "DMA_CH2", // 8: DMA Channel 2 - "DMA_CH3", // 9: DMA Channel 3 - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF", // 14: TC C0 Overflow - "TCC0_ERR", // 15: TC C0 Error - "TCC0_CCA", // 16: TC C0 Compare or Capture A - "TCC0_CCB", // 17: TC C0 Compare or Capture B - "TCC0_CCC", // 18: TC C0 Compare or Capture C - "TCC0_CCD", // 19: TC C0 Compare or Capture D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "USARTC1_RXC", // 28: USARTC 1 Reception Complete - "USARTC1_DRE", // 29: USARTC 1 Data Register Empty - "USARTC1_TXC", // 30: USARTC 1 Transmission Complete - "AES_INT", // 31: AES Interrupt - "NVM_EE", // 32: NVM EEPROM - "NVM_SPM", // 33: NVM SPM - "PORTB_INT0", // 34: External Interrupt 0 PORT B - "PORTB_INT1", // 35: External Interrupt 1 PORT B - "UNUSED", // 36: not implemented on this device - "UNUSED", // 37: not implemented on this device - "UNUSED", // 38: not implemented on this device - "UNUSED", // 39: not implemented on this device - "UNUSED", // 40: not implemented on this device - "UNUSED", // 41: not implemented on this device - "UNUSED", // 42: not implemented on this device - "PORTE_INT0", // 43: External Interrupt 0 PORT E - "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral - "TWIE_TWIM", // 46: 2-Wire Interface E Controller - "TCE0_OVF", // 47: TC E0 Overflow - "TCE0_ERR", // 48: TC E0 Error - "TCE0_CCA", // 49: TC E0 Compare or Capture A - "TCE0_CCB", // 50: TC E0 Compare or Capture B - "TCE0_CCC", // 51: TC E0 Compare or Capture C - "TCE0_CCD", // 52: TC E0 Compare or Capture D - "HIRESE_OVF", // 53: High-resolution Extension Overflow - "HIRESE_ERR", // 54: High-resolution Extension Error - "HIRESE_CCA", // 55: High-resolution Extension Compare and Capture A - "HIRESE_CCB", // 56: High-resolution Extension Compare and Capture B - "UNUSED", // 57: not implemented on this device - "USARTE0_RXC", // 58: USARTE 0 Reception Complete - "USARTE0_DRE", // 59: USARTE 0 Data Register Empty - "USARTE0_TXC", // 60: USARTE 0 Transmission Complete - "UNUSED", // 61: not implemented on this device - "UNUSED", // 62: not implemented on this device - "UNUSED", // 63: not implemented on this device - "PORTD_INT0", // 64: External Interrupt 0 PORT D - "PORTD_INT1", // 65: External Interrupt 1 PORT D - "PORTA_INT0", // 66: External Interrupt 0 PORT A - "PORTA_INT1", // 67: External Interrupt 1 PORT A - "ACA_AC0", // 68: ACA AC 0 Interrupt - "ACA_AC1", // 69: ACA AC 1 Interrupt - "ACA_ACW", // 70: ACA AC Window Mode - "ADCA_CH0", // 71: ADCA Interrupt 0 - "ADCA_CH1", // 72: ADCA Interrupt 1 - "ADCA_CH2", // 73: ADCA Interrupt 2 - "ADCA_CH3", // 74: ADCA Interrupt 3 - "UNUSED", // 75: not implemented on this device - "UNUSED", // 76: not implemented on this device - "TCD0_OVF", // 77: TC D0 Overflow - "TCD0_ERR", // 78: TC D0 Error - "TCD0_CCA", // 79: TC D0 Compare or Capture A - "TCD0_CCB", // 80: TC D0 Compare or Capture B - "TCD0_CCC", // 81: TC D0 Compare or Capture C - "TCD0_CCD", // 82: TC D0 Compare or Capture D - "TCD1_OVF", // 83: TC D1 Overflow - "TCD1_ERR", // 84: TC D1 Error - "TCD1_CCA", // 85: TC D1 Compare or Capture A - "TCD1_CCB", // 86: TC D1 Compare or Capture B - "SPID_INT", // 87: SPI D Interrupt - "USARTD0_RXC", // 88: USARTD 0 Reception Complete - "USARTD0_DRE", // 89: USARTD 0 Data Register Empty - "USARTD0_TXC", // 90: USARTD 0 Transmission Complete - "USARTD1_RXC", // 91: USARTD 1 Reception Complete - "USARTD1_DRE", // 92: USARTD 1 Data Register Empty - "USARTD1_TXC", // 93: USARTD 1 Transmission Complete -}; - -// ATxmega32C4 ATxmega16C4 -const char * const vtab_atxmega32c4[vts_atxmega32c4] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "UNUSED", // 6: not implemented on this device - "UNUSED", // 7: not implemented on this device - "UNUSED", // 8: not implemented on this device - "UNUSED", // 9: not implemented on this device - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow - "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow - "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A - "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B - "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C - "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "USARTC1_RXC", // 28: USARTC 1 Reception Complete - "USARTC1_DRE", // 29: USARTC 1 Data Register Empty - "USARTC1_TXC", // 30: USARTC 1 Transmission Complete - "UNUSED", // 31: not implemented on this device - "NVM_EE", // 32: NVM EEPROM - "NVM_SPM", // 33: NVM SPM - "PORTB_INT0", // 34: External Interrupt 0 PORT B - "PORTB_INT1", // 35: External Interrupt 1 PORT B - "UNUSED", // 36: not implemented on this device - "UNUSED", // 37: not implemented on this device - "UNUSED", // 38: not implemented on this device - "UNUSED", // 39: not implemented on this device - "UNUSED", // 40: not implemented on this device - "UNUSED", // 41: not implemented on this device - "UNUSED", // 42: not implemented on this device - "PORTE_INT0", // 43: External Interrupt 0 PORT E - "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral - "TWIE_TWIM", // 46: 2-Wire Interface E Controller - "TCE0_OVF", // 47: TC E0 Overflow - "TCE0_ERR", // 48: TC E0 Error - "TCE0_CCA", // 49: TC E0 Compare or Capture A - "TCE0_CCB", // 50: TC E0 Compare or Capture B - "TCE0_CCC", // 51: TC E0 Compare or Capture C - "TCE0_CCD", // 52: TC E0 Compare or Capture D - "UNUSED", // 53: not implemented on this device - "UNUSED", // 54: not implemented on this device - "UNUSED", // 55: not implemented on this device - "UNUSED", // 56: not implemented on this device - "UNUSED", // 57: not implemented on this device - "UNUSED", // 58: not implemented on this device - "UNUSED", // 59: not implemented on this device - "UNUSED", // 60: not implemented on this device - "UNUSED", // 61: not implemented on this device - "UNUSED", // 62: not implemented on this device - "UNUSED", // 63: not implemented on this device - "PORTD_INT0", // 64: External Interrupt 0 PORT D - "PORTD_INT1", // 65: External Interrupt 1 PORT D - "PORTA_INT0", // 66: External Interrupt 0 PORT A - "PORTA_INT1", // 67: External Interrupt 1 PORT A - "ACA_AC0", // 68: ACA AC 0 Interrupt - "ACA_AC1", // 69: ACA AC 1 Interrupt - "ACA_ACW", // 70: ACA AC Window Mode - "ADCA_CH0", // 71: ADCA Interrupt 0 - "UNUSED", // 72: not implemented on this device - "UNUSED", // 73: not implemented on this device - "UNUSED", // 74: not implemented on this device - "UNUSED", // 75: not implemented on this device - "UNUSED", // 76: not implemented on this device - "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow - "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow - "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A - "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B - "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C - "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D - "UNUSED", // 83: not implemented on this device - "UNUSED", // 84: not implemented on this device - "UNUSED", // 85: not implemented on this device - "UNUSED", // 86: not implemented on this device - "SPID_INT", // 87: SPI D Interrupt - "USARTD0_RXC", // 88: USARTD 0 Reception Complete - "USARTD0_DRE", // 89: USARTD 0 Data Register Empty - "USARTD0_TXC", // 90: USARTD 0 Transmission Complete - "UNUSED", // 91: not implemented on this device - "UNUSED", // 92: not implemented on this device - "UNUSED", // 93: not implemented on this device - "UNUSED", // 94: not implemented on this device - "UNUSED", // 95: not implemented on this device - "UNUSED", // 96: not implemented on this device - "UNUSED", // 97: not implemented on this device - "UNUSED", // 98: not implemented on this device - "UNUSED", // 99: not implemented on this device - "UNUSED", // 100: not implemented on this device - "UNUSED", // 101: not implemented on this device - "UNUSED", // 102: not implemented on this device - "UNUSED", // 103: not implemented on this device - "UNUSED", // 104: not implemented on this device - "UNUSED", // 105: not implemented on this device - "UNUSED", // 106: not implemented on this device - "UNUSED", // 107: not implemented on this device - "UNUSED", // 108: not implemented on this device - "UNUSED", // 109: not implemented on this device - "UNUSED", // 110: not implemented on this device - "UNUSED", // 111: not implemented on this device - "UNUSED", // 112: not implemented on this device - "UNUSED", // 113: not implemented on this device - "UNUSED", // 114: not implemented on this device - "UNUSED", // 115: not implemented on this device - "UNUSED", // 116: not implemented on this device - "UNUSED", // 117: not implemented on this device - "UNUSED", // 118: not implemented on this device - "UNUSED", // 119: not implemented on this device - "UNUSED", // 120: not implemented on this device - "UNUSED", // 121: not implemented on this device - "UNUSED", // 122: not implemented on this device - "UNUSED", // 123: not implemented on this device - "UNUSED", // 124: not implemented on this device - "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error - "USB_TRNCOMPL", // 126: USB Transaction Complete -}; - -// ATxmega32D4 ATxmega16D4 -const char * const vtab_atxmega32d4[vts_atxmega32d4] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "UNUSED", // 6: not implemented on this device - "UNUSED", // 7: not implemented on this device - "UNUSED", // 8: not implemented on this device - "UNUSED", // 9: not implemented on this device - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow - "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow - "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A - "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B - "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C - "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "UNUSED", // 28: not implemented on this device - "UNUSED", // 29: not implemented on this device - "UNUSED", // 30: not implemented on this device - "UNUSED", // 31: not implemented on this device - "NVM_EE", // 32: NVM EEPROM - "NVM_SPM", // 33: NVM SPM - "PORTB_INT0", // 34: External Interrupt 0 PORT B - "PORTB_INT1", // 35: External Interrupt 1 PORT B - "UNUSED", // 36: not implemented on this device - "UNUSED", // 37: not implemented on this device - "UNUSED", // 38: not implemented on this device - "UNUSED", // 39: not implemented on this device - "UNUSED", // 40: not implemented on this device - "UNUSED", // 41: not implemented on this device - "UNUSED", // 42: not implemented on this device - "PORTE_INT0", // 43: External Interrupt 0 PORT E - "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral - "TWIE_TWIM", // 46: 2-Wire Interface E Controller - "TCE0_OVF", // 47: TC E0 Overflow - "TCE0_ERR", // 48: TC E0 Error - "TCE0_CCA", // 49: TC E0 Compare or Capture A - "TCE0_CCB", // 50: TC E0 Compare or Capture B - "TCE0_CCC", // 51: TC E0 Compare or Capture C - "TCE0_CCD", // 52: TC E0 Compare or Capture D - "UNUSED", // 53: not implemented on this device - "UNUSED", // 54: not implemented on this device - "UNUSED", // 55: not implemented on this device - "UNUSED", // 56: not implemented on this device - "UNUSED", // 57: not implemented on this device - "UNUSED", // 58: not implemented on this device - "UNUSED", // 59: not implemented on this device - "UNUSED", // 60: not implemented on this device - "UNUSED", // 61: not implemented on this device - "UNUSED", // 62: not implemented on this device - "UNUSED", // 63: not implemented on this device - "PORTD_INT0", // 64: External Interrupt 0 PORT D - "PORTD_INT1", // 65: External Interrupt 1 PORT D - "PORTA_INT0", // 66: External Interrupt 0 PORT A - "PORTA_INT1", // 67: External Interrupt 1 PORT A - "ACA_AC0", // 68: ACA AC 0 Interrupt - "ACA_AC1", // 69: ACA AC 1 Interrupt - "ACA_ACW", // 70: ACA AC Window Mode - "ADCA_CH0", // 71: ADCA Interrupt 0 - "ADCA_CH1", // 72: ADCA Interrupt 1 - "ADCA_CH2", // 73: ADCA Interrupt 2 - "ADCA_CH3", // 74: ADCA Interrupt 3 - "UNUSED", // 75: not implemented on this device - "UNUSED", // 76: not implemented on this device - "TCD0_OVF", // 77: TC D0 Overflow - "TCD0_ERR", // 78: TC D0 Error - "TCD0_CCA", // 79: TC D0 Compare or Capture A - "TCD0_CCB", // 80: TC D0 Compare or Capture B - "TCD0_CCC", // 81: TC D0 Compare or Capture C - "TCD0_CCD", // 82: TC D0 Compare or Capture D - "UNUSED", // 83: not implemented on this device - "UNUSED", // 84: not implemented on this device - "UNUSED", // 85: not implemented on this device - "UNUSED", // 86: not implemented on this device - "SPID_INT", // 87: SPI D Interrupt - "USARTD0_RXC", // 88: USARTD 0 Reception Complete - "USARTD0_DRE", // 89: USARTD 0 Data Register Empty - "USARTD0_TXC", // 90: USARTD 0 Transmission Complete -}; - -// ATxmega32E5 ATxmega16E5 ATxmega8E5 -const char * const vtab_atxmega32e5[vts_atxmega32e5] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTR_INT", // 2: External Interrupt PORT R - "EDMA_CH0", // 3: External DMA Channel 0 - "EDMA_CH1", // 4: External DMA Channel 1 - "EDMA_CH2", // 5: External DMA Channel 2 - "EDMA_CH3", // 6: External DMA Channel 3 - "RTC_OVF", // 7: RTC Overflow - "RTC_COMP", // 8: RTC Compare - "PORTC_INT", // 9: External Interrupt PORT C - "TWIC_TWIP", // 10: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 11: 2-Wire Interface C Controller - "TCC4_OVF", // 12: TC C4 Overflow - "TCC4_ERR", // 13: TC C4 Error - "TCC4_CCA", // 14: TC C4 Compare or Capture A - "TCC4_CCB", // 15: TC C4 Compare or Capture B - "TCC4_CCC", // 16: TC C4 Compare or Capture C - "TCC4_CCD", // 17: TC C4 Compare or Capture D - "TCC5_OVF", // 18: TC C5 Overflow - "TCC5_ERR", // 19: TC C5 Error - "TCC5_CCA", // 20: TC C5 Compare or Capture A - "TCC5_CCB", // 21: TC C5 Compare or Capture B - "SPIC_INT", // 22: SPI C Interrupt - "USARTC0_RXC", // 23: USARTC 0 Reception Complete - "USARTC0_DRE", // 24: USARTC 0 Data Register Empty - "USARTC0_TXC", // 25: USARTC 0 Transmission Complete - "NVM_EE", // 26: NVM EEPROM - "NVM_SPM", // 27: NVM SPM - "XCL_UNF", // 28: XMEGA Custom Logic Underflow - "XCL_CC", // 29: XMEGA Custom Logic Compare or Capture - "PORTA_INT", // 30: External Interrupt PORT A - "ACA_AC0", // 31: ACA AC 0 Interrupt - "ACA_AC1", // 32: ACA AC 1 Interrupt - "ACA_ACW", // 33: ACA AC Window Mode - "ADCA_CH0", // 34: ADCA Interrupt 0 - "PORTD_INT", // 35: External Interrupt PORT D - "TCD5_OVF", // 36: TC D5 Overflow - "TCD5_ERR", // 37: TC D5 Error - "TCD5_CCA", // 38: TC D5 Compare or Capture A - "TCD5_CCB", // 39: TC D5 Compare or Capture B - "USARTD0_RXC", // 40: USARTD 0 Reception Complete - "USARTD0_DRE", // 41: USARTD 0 Data Register Empty - "USARTD0_TXC", // 42: USARTD 0 Transmission Complete -}; - -// ATxmega128A1revD ATxmega128A1 ATxmega64A1 -const char * const vtab_atxmega128a1revd[vts_atxmega128a1revd] = { +// ATxmega64A1 ATxmega128A1 ATxmega128A1revD +const char * const vtab_atxmega64a1[vts_atxmega64a1] = { "RESET", // 0: Reset (various reasons) "OSC_OSCF", // 1: Oscillator Failure NMI "PORTC_INT0", // 2: External Interrupt 0 PORT C @@ -5967,8 +5597,8 @@ const char * const vtab_atxmega128a1revd[vts_atxmega128a1revd] = { "USARTF1_TXC", // 124: USARTF 1 Transmission Complete }; -// ATxmega128A1U ATxmega64A1U -const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { +// ATxmega64A1U ATxmega128A1U +const char * const vtab_atxmega64a1u[vts_atxmega64a1u] = { "RESET", // 0: Reset (various reasons) "OSC_OSCF", // 1: Oscillator Failure NMI "PORTC_INT0", // 2: External Interrupt 0 PORT C @@ -6098,377 +5728,8 @@ const char * const vtab_atxmega128a1u[vts_atxmega128a1u] = { "USB_TRNCOMPL", // 126: USB Transaction Complete }; -// ATxmega128B1 ATxmega64B1 -const char * const vtab_atxmega128b1[vts_atxmega128b1] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "DMA_CH0", // 6: DMA Channel 0 - "DMA_CH1", // 7: DMA Channel 1 - "UNUSED", // 8: not implemented on this device - "UNUSED", // 9: not implemented on this device - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow - "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow - "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A - "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B - "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C - "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "UNUSED", // 28: not implemented on this device - "UNUSED", // 29: not implemented on this device - "UNUSED", // 30: not implemented on this device - "USB_BUSEVENT", // 31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error - "USB_TRNCOMPL", // 32: USB Transaction Complete - "UNUSED", // 33: not implemented on this device - "UNUSED", // 34: not implemented on this device - "LCD_INT", // 35: LCD Interrupt - "AES_INT", // 36: AES Interrupt - "NVM_EE", // 37: NVM EEPROM - "NVM_SPM", // 38: NVM SPM - "PORTB_INT0", // 39: External Interrupt 0 PORT B - "PORTB_INT1", // 40: External Interrupt 1 PORT B - "ACB_AC0", // 41: ACB AC 0 Interrupt - "ACB_AC1", // 42: ACB AC 1 Interrupt - "ACB_ACW", // 43: ACB AC Window Mode - "ADCB_CH0", // 44: ADCB Interrupt 0 - "UNUSED", // 45: not implemented on this device - "UNUSED", // 46: not implemented on this device - "UNUSED", // 47: not implemented on this device - "PORTD_INT0", // 48: External Interrupt 0 PORT D - "PORTD_INT1", // 49: External Interrupt 1 PORT D - "PORTG_INT0", // 50: External Interrupt 0 PORT G - "PORTG_INT1", // 51: External Interrupt 1 PORT G - "PORTM_INT0", // 52: External Interrupt 0 PORT M - "PORTM_INT1", // 53: External Interrupt 1 PORT M - "PORTE_INT0", // 54: External Interrupt 0 PORT E - "PORTE_INT1", // 55: External Interrupt 1 PORT E - "UNUSED", // 56: not implemented on this device - "UNUSED", // 57: not implemented on this device - "TCE0_OVF/TCE2_LUNF", // 58: TC E0 Overflow/TC E2 Low Byte Underflow - "TCE0_ERR/TCE2_HUNF", // 59: TC E0 Error/TC E2 High Byte Underflow - "TCE0_CCA/TCE2_LCMPA", // 60: TC E0 Compare or Capture A/TC E2 Low Byte Compare A - "TCE0_CCB/TCE2_LCMPB", // 61: TC E0 Compare or Capture B/TC E2 Low Byte Compare B - "TCE0_CCC/TCE2_LCMPC", // 62: TC E0 Compare or Capture C/TC E2 Low Byte Compare C - "TCE0_CCD/TCE2_LCMPD", // 63: TC E0 Compare or Capture D/TC E2 Low Byte Compare D - "UNUSED", // 64: not implemented on this device - "UNUSED", // 65: not implemented on this device - "UNUSED", // 66: not implemented on this device - "UNUSED", // 67: not implemented on this device - "UNUSED", // 68: not implemented on this device - "USARTE0_RXC", // 69: USARTE 0 Reception Complete - "USARTE0_DRE", // 70: USARTE 0 Data Register Empty - "USARTE0_TXC", // 71: USARTE 0 Transmission Complete - "UNUSED", // 72: not implemented on this device - "UNUSED", // 73: not implemented on this device - "UNUSED", // 74: not implemented on this device - "PORTA_INT0", // 75: External Interrupt 0 PORT A - "PORTA_INT1", // 76: External Interrupt 1 PORT A - "ACA_AC0", // 77: ACA AC 0 Interrupt - "ACA_AC1", // 78: ACA AC 1 Interrupt - "ACA_ACW", // 79: ACA AC Window Mode - "ADCA_CH0", // 80: ADCA Interrupt 0 -}; - -// ATxmega128B3 ATxmega64B3 -const char * const vtab_atxmega128b3[vts_atxmega128b3] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "DMA_CH0", // 6: DMA Channel 0 - "DMA_CH1", // 7: DMA Channel 1 - "UNUSED", // 8: not implemented on this device - "UNUSED", // 9: not implemented on this device - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow - "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow - "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A - "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B - "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C - "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "UNUSED", // 28: not implemented on this device - "UNUSED", // 29: not implemented on this device - "UNUSED", // 30: not implemented on this device - "USB_BUSEVENT", // 31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error - "USB_TRNCOMPL", // 32: USB Transaction Complete - "UNUSED", // 33: not implemented on this device - "UNUSED", // 34: not implemented on this device - "LCD_INT", // 35: LCD Interrupt - "AES_INT", // 36: AES Interrupt - "NVM_EE", // 37: NVM EEPROM - "NVM_SPM", // 38: NVM SPM - "PORTB_INT0", // 39: External Interrupt 0 PORT B - "PORTB_INT1", // 40: External Interrupt 1 PORT B - "ACB_AC0", // 41: ACB AC 0 Interrupt - "ACB_AC1", // 42: ACB AC 1 Interrupt - "ACB_ACW", // 43: ACB AC Window Mode - "ADCB_CH0", // 44: ADCB Interrupt 0 - "UNUSED", // 45: not implemented on this device - "UNUSED", // 46: not implemented on this device - "UNUSED", // 47: not implemented on this device - "PORTD_INT0", // 48: External Interrupt 0 PORT D - "PORTD_INT1", // 49: External Interrupt 1 PORT D - "PORTG_INT0", // 50: External Interrupt 0 PORT G - "PORTG_INT1", // 51: External Interrupt 1 PORT G - "PORTM_INT0", // 52: External Interrupt 0 PORT M - "PORTM_INT1", // 53: External Interrupt 1 PORT M -}; - -// ATxmega128A4U ATxmega64A4U ATxmega32A4U ATxmega16A4U -const char * const vtab_atxmega128a4u[vts_atxmega128a4u] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "DMA_CH0", // 6: DMA Channel 0 - "DMA_CH1", // 7: DMA Channel 1 - "DMA_CH2", // 8: DMA Channel 2 - "DMA_CH3", // 9: DMA Channel 3 - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow - "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow - "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A - "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B - "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C - "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "USARTC1_RXC", // 28: USARTC 1 Reception Complete - "USARTC1_DRE", // 29: USARTC 1 Data Register Empty - "USARTC1_TXC", // 30: USARTC 1 Transmission Complete - "AES_INT", // 31: AES Interrupt - "NVM_EE", // 32: NVM EEPROM - "NVM_SPM", // 33: NVM SPM - "PORTB_INT0", // 34: External Interrupt 0 PORT B - "PORTB_INT1", // 35: External Interrupt 1 PORT B - "UNUSED", // 36: not implemented on this device - "UNUSED", // 37: not implemented on this device - "UNUSED", // 38: not implemented on this device - "UNUSED", // 39: not implemented on this device - "UNUSED", // 40: not implemented on this device - "UNUSED", // 41: not implemented on this device - "UNUSED", // 42: not implemented on this device - "PORTE_INT0", // 43: External Interrupt 0 PORT E - "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral - "TWIE_TWIM", // 46: 2-Wire Interface E Controller - "TCE0_OVF", // 47: TC E0 Overflow - "TCE0_ERR", // 48: TC E0 Error - "TCE0_CCA", // 49: TC E0 Compare or Capture A - "TCE0_CCB", // 50: TC E0 Compare or Capture B - "TCE0_CCC", // 51: TC E0 Compare or Capture C - "TCE0_CCD", // 52: TC E0 Compare or Capture D - "UNUSED", // 53: not implemented on this device - "UNUSED", // 54: not implemented on this device - "UNUSED", // 55: not implemented on this device - "UNUSED", // 56: not implemented on this device - "UNUSED", // 57: not implemented on this device - "USARTE0_RXC", // 58: USARTE 0 Reception Complete - "USARTE0_DRE", // 59: USARTE 0 Data Register Empty - "USARTE0_TXC", // 60: USARTE 0 Transmission Complete - "UNUSED", // 61: not implemented on this device - "UNUSED", // 62: not implemented on this device - "UNUSED", // 63: not implemented on this device - "PORTD_INT0", // 64: External Interrupt 0 PORT D - "PORTD_INT1", // 65: External Interrupt 1 PORT D - "PORTA_INT0", // 66: External Interrupt 0 PORT A - "PORTA_INT1", // 67: External Interrupt 1 PORT A - "ACA_AC0", // 68: ACA AC 0 Interrupt - "ACA_AC1", // 69: ACA AC 1 Interrupt - "ACA_ACW", // 70: ACA AC Window Mode - "ADCA_CH0", // 71: ADCA Interrupt 0 - "ADCA_CH1", // 72: ADCA Interrupt 1 - "ADCA_CH2", // 73: ADCA Interrupt 2 - "ADCA_CH3", // 74: ADCA Interrupt 3 - "UNUSED", // 75: not implemented on this device - "UNUSED", // 76: not implemented on this device - "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow - "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow - "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A - "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B - "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C - "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D - "TCD1_OVF", // 83: TC D1 Overflow - "TCD1_ERR", // 84: TC D1 Error - "TCD1_CCA", // 85: TC D1 Compare or Capture A - "TCD1_CCB", // 86: TC D1 Compare or Capture B - "SPID_INT", // 87: SPI D Interrupt - "USARTD0_RXC", // 88: USARTD 0 Reception Complete - "USARTD0_DRE", // 89: USARTD 0 Data Register Empty - "USARTD0_TXC", // 90: USARTD 0 Transmission Complete - "USARTD1_RXC", // 91: USARTD 1 Reception Complete - "USARTD1_DRE", // 92: USARTD 1 Data Register Empty - "USARTD1_TXC", // 93: USARTD 1 Transmission Complete - "UNUSED", // 94: not implemented on this device - "UNUSED", // 95: not implemented on this device - "UNUSED", // 96: not implemented on this device - "UNUSED", // 97: not implemented on this device - "UNUSED", // 98: not implemented on this device - "UNUSED", // 99: not implemented on this device - "UNUSED", // 100: not implemented on this device - "UNUSED", // 101: not implemented on this device - "UNUSED", // 102: not implemented on this device - "UNUSED", // 103: not implemented on this device - "UNUSED", // 104: not implemented on this device - "UNUSED", // 105: not implemented on this device - "UNUSED", // 106: not implemented on this device - "UNUSED", // 107: not implemented on this device - "UNUSED", // 108: not implemented on this device - "UNUSED", // 109: not implemented on this device - "UNUSED", // 110: not implemented on this device - "UNUSED", // 111: not implemented on this device - "UNUSED", // 112: not implemented on this device - "UNUSED", // 113: not implemented on this device - "UNUSED", // 114: not implemented on this device - "UNUSED", // 115: not implemented on this device - "UNUSED", // 116: not implemented on this device - "UNUSED", // 117: not implemented on this device - "UNUSED", // 118: not implemented on this device - "UNUSED", // 119: not implemented on this device - "UNUSED", // 120: not implemented on this device - "UNUSED", // 121: not implemented on this device - "UNUSED", // 122: not implemented on this device - "UNUSED", // 123: not implemented on this device - "UNUSED", // 124: not implemented on this device - "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error - "USB_TRNCOMPL", // 126: USB Transaction Complete -}; - -// ATxmega128D4 ATxmega64D4 -const char * const vtab_atxmega128d4[vts_atxmega128d4] = { - "RESET", // 0: Reset (various reasons) - "OSC_OSCF", // 1: Oscillator Failure NMI - "PORTC_INT0", // 2: External Interrupt 0 PORT C - "PORTC_INT1", // 3: External Interrupt 1 PORT C - "PORTR_INT0", // 4: External Interrupt 0 PORT R - "PORTR_INT1", // 5: External Interrupt 1 PORT R - "UNUSED", // 6: not implemented on this device - "UNUSED", // 7: not implemented on this device - "UNUSED", // 8: not implemented on this device - "UNUSED", // 9: not implemented on this device - "RTC_OVF", // 10: RTC Overflow - "RTC_COMP", // 11: RTC Compare - "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral - "TWIC_TWIM", // 13: 2-Wire Interface C Controller - "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow - "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow - "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A - "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B - "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C - "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D - "TCC1_OVF", // 20: TC C1 Overflow - "TCC1_ERR", // 21: TC C1 Error - "TCC1_CCA", // 22: TC C1 Compare or Capture A - "TCC1_CCB", // 23: TC C1 Compare or Capture B - "SPIC_INT", // 24: SPI C Interrupt - "USARTC0_RXC", // 25: USARTC 0 Reception Complete - "USARTC0_DRE", // 26: USARTC 0 Data Register Empty - "USARTC0_TXC", // 27: USARTC 0 Transmission Complete - "UNUSED", // 28: not implemented on this device - "UNUSED", // 29: not implemented on this device - "UNUSED", // 30: not implemented on this device - "UNUSED", // 31: not implemented on this device - "NVM_EE", // 32: NVM EEPROM - "NVM_SPM", // 33: NVM SPM - "PORTB_INT0", // 34: External Interrupt 0 PORT B - "PORTB_INT1", // 35: External Interrupt 1 PORT B - "UNUSED", // 36: not implemented on this device - "UNUSED", // 37: not implemented on this device - "UNUSED", // 38: not implemented on this device - "UNUSED", // 39: not implemented on this device - "UNUSED", // 40: not implemented on this device - "UNUSED", // 41: not implemented on this device - "UNUSED", // 42: not implemented on this device - "PORTE_INT0", // 43: External Interrupt 0 PORT E - "PORTE_INT1", // 44: External Interrupt 1 PORT E - "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral - "TWIE_TWIM", // 46: 2-Wire Interface E Controller - "TCE0_OVF", // 47: TC E0 Overflow - "TCE0_ERR", // 48: TC E0 Error - "TCE0_CCA", // 49: TC E0 Compare or Capture A - "TCE0_CCB", // 50: TC E0 Compare or Capture B - "TCE0_CCC", // 51: TC E0 Compare or Capture C - "TCE0_CCD", // 52: TC E0 Compare or Capture D - "UNUSED", // 53: not implemented on this device - "UNUSED", // 54: not implemented on this device - "UNUSED", // 55: not implemented on this device - "UNUSED", // 56: not implemented on this device - "UNUSED", // 57: not implemented on this device - "UNUSED", // 58: not implemented on this device - "UNUSED", // 59: not implemented on this device - "UNUSED", // 60: not implemented on this device - "UNUSED", // 61: not implemented on this device - "UNUSED", // 62: not implemented on this device - "UNUSED", // 63: not implemented on this device - "PORTD_INT0", // 64: External Interrupt 0 PORT D - "PORTD_INT1", // 65: External Interrupt 1 PORT D - "PORTA_INT0", // 66: External Interrupt 0 PORT A - "PORTA_INT1", // 67: External Interrupt 1 PORT A - "ACA_AC0", // 68: ACA AC 0 Interrupt - "ACA_AC1", // 69: ACA AC 1 Interrupt - "ACA_ACW", // 70: ACA AC Window Mode - "ADCA_CH0", // 71: ADCA Interrupt 0 - "UNUSED", // 72: not implemented on this device - "UNUSED", // 73: not implemented on this device - "UNUSED", // 74: not implemented on this device - "UNUSED", // 75: not implemented on this device - "UNUSED", // 76: not implemented on this device - "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow - "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow - "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A - "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B - "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C - "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D - "UNUSED", // 83: not implemented on this device - "UNUSED", // 84: not implemented on this device - "UNUSED", // 85: not implemented on this device - "UNUSED", // 86: not implemented on this device - "SPID_INT", // 87: SPI D Interrupt - "USARTD0_RXC", // 88: USARTD 0 Reception Complete - "USARTD0_DRE", // 89: USARTD 0 Data Register Empty - "USARTD0_TXC", // 90: USARTD 0 Transmission Complete -}; - -// ATxmega256A3 ATxmega192A3 ATxmega128A3 ATxmega64A3 -const char * const vtab_atxmega256a3[vts_atxmega256a3] = { +// ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 +const char * const vtab_atxmega64a3[vts_atxmega64a3] = { "RESET", // 0: Reset (various reasons) "OSC_OSCF", // 1: Oscillator Failure NMI "PORTC_INT0", // 2: External Interrupt 0 PORT C @@ -6719,6 +5980,137 @@ const char * const vtab_atxmega256a3b[vts_atxmega256a3b] = { "USARTF0_TXC", // 121: USARTF 0 Transmission Complete }; +// ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3U +const char * const vtab_atxmega64a3u[vts_atxmega64a3u] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "ACB_AC0", // 36: ACB AC 0 Interrupt + "ACB_AC1", // 37: ACB AC 1 Interrupt + "ACB_ACW", // 38: ACB AC Window Mode + "ADCB_CH0", // 39: ADCB Interrupt 0 + "ADCB_CH1", // 40: ADCB Interrupt 1 + "ADCB_CH2", // 41: ADCB Interrupt 2 + "ADCB_CH3", // 42: ADCB Interrupt 3 + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "TCE1_OVF", // 53: TC E1 Overflow + "TCE1_ERR", // 54: TC E1 Error + "TCE1_CCA", // 55: TC E1 Compare or Capture A + "TCE1_CCB", // 56: TC E1 Compare or Capture B + "SPIE_INT", // 57: SPI E Interrupt + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "USARTE1_RXC", // 61: USARTE 1 Reception Complete + "USARTE1_DRE", // 62: USARTE 1 Data Register Empty + "USARTE1_TXC", // 63: USARTE 1 Transmission Complete + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "PORTF_INT0", // 104: External Interrupt 0 PORT F + "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow + "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow + "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A + "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B + "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C + "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "USARTF0_RXC", // 119: USARTF 0 Reception Complete + "USARTF0_DRE", // 120: USARTF 0 Data Register Empty + "USARTF0_TXC", // 121: USARTF 0 Transmission Complete + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + // ATxmega256A3BU const char * const vtab_atxmega256a3bu[vts_atxmega256a3bu] = { "RESET", // 0: Reset (various reasons) @@ -6850,8 +6242,106 @@ const char * const vtab_atxmega256a3bu[vts_atxmega256a3bu] = { "USB_TRNCOMPL", // 126: USB Transaction Complete }; -// ATxmega256A3U ATxmega192A3U ATxmega128A3U ATxmega64A3U -const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { +// ATxmega16A4 ATxmega32A4 +const char * const vtab_atxmega16a4[vts_atxmega16a4] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "DMA_CH2", // 8: DMA Channel 2 + "DMA_CH3", // 9: DMA Channel 3 + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF", // 14: TC C0 Overflow + "TCC0_ERR", // 15: TC C0 Error + "TCC0_CCA", // 16: TC C0 Compare or Capture A + "TCC0_CCB", // 17: TC C0 Compare or Capture B + "TCC0_CCC", // 18: TC C0 Compare or Capture C + "TCC0_CCD", // 19: TC C0 Compare or Capture D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "AES_INT", // 31: AES Interrupt + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "HIRESE_OVF", // 53: High-resolution Extension Overflow + "HIRESE_ERR", // 54: High-resolution Extension Error + "HIRESE_CCA", // 55: High-resolution Extension Compare and Capture A + "HIRESE_CCB", // 56: High-resolution Extension Compare and Capture B + "UNUSED", // 57: not implemented on this device + "USARTE0_RXC", // 58: USARTE 0 Reception Complete + "USARTE0_DRE", // 59: USARTE 0 Data Register Empty + "USARTE0_TXC", // 60: USARTE 0 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "TCD1_OVF", // 83: TC D1 Overflow + "TCD1_ERR", // 84: TC D1 Error + "TCD1_CCA", // 85: TC D1 Compare or Capture A + "TCD1_CCB", // 86: TC D1 Compare or Capture B + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "USARTD1_RXC", // 91: USARTD 1 Reception Complete + "USARTD1_DRE", // 92: USARTD 1 Data Register Empty + "USARTD1_TXC", // 93: USARTD 1 Transmission Complete +}; + +// ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U +const char * const vtab_atxmega16a4u[vts_atxmega16a4u] = { "RESET", // 0: Reset (various reasons) "OSC_OSCF", // 1: Oscillator Failure NMI "PORTC_INT0", // 2: External Interrupt 0 PORT C @@ -6888,34 +6378,34 @@ const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { "NVM_SPM", // 33: NVM SPM "PORTB_INT0", // 34: External Interrupt 0 PORT B "PORTB_INT1", // 35: External Interrupt 1 PORT B - "ACB_AC0", // 36: ACB AC 0 Interrupt - "ACB_AC1", // 37: ACB AC 1 Interrupt - "ACB_ACW", // 38: ACB AC Window Mode - "ADCB_CH0", // 39: ADCB Interrupt 0 - "ADCB_CH1", // 40: ADCB Interrupt 1 - "ADCB_CH2", // 41: ADCB Interrupt 2 - "ADCB_CH3", // 42: ADCB Interrupt 3 + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device "PORTE_INT0", // 43: External Interrupt 0 PORT E "PORTE_INT1", // 44: External Interrupt 1 PORT E "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral "TWIE_TWIM", // 46: 2-Wire Interface E Controller - "TCE0_OVF/TCE2_LUNF", // 47: TC E0 Overflow/TC E2 Low Byte Underflow - "TCE0_ERR/TCE2_HUNF", // 48: TC E0 Error/TC E2 High Byte Underflow - "TCE0_CCA/TCE2_LCMPA", // 49: TC E0 Compare or Capture A/TC E2 Low Byte Compare A - "TCE0_CCB/TCE2_LCMPB", // 50: TC E0 Compare or Capture B/TC E2 Low Byte Compare B - "TCE0_CCC/TCE2_LCMPC", // 51: TC E0 Compare or Capture C/TC E2 Low Byte Compare C - "TCE0_CCD/TCE2_LCMPD", // 52: TC E0 Compare or Capture D/TC E2 Low Byte Compare D - "TCE1_OVF", // 53: TC E1 Overflow - "TCE1_ERR", // 54: TC E1 Error - "TCE1_CCA", // 55: TC E1 Compare or Capture A - "TCE1_CCB", // 56: TC E1 Compare or Capture B - "SPIE_INT", // 57: SPI E Interrupt + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device "USARTE0_RXC", // 58: USARTE 0 Reception Complete "USARTE0_DRE", // 59: USARTE 0 Data Register Empty "USARTE0_TXC", // 60: USARTE 0 Transmission Complete - "USARTE1_RXC", // 61: USARTE 1 Reception Complete - "USARTE1_DRE", // 62: USARTE 1 Data Register Empty - "USARTE1_TXC", // 63: USARTE 1 Transmission Complete + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device "PORTD_INT0", // 64: External Interrupt 0 PORT D "PORTD_INT1", // 65: External Interrupt 1 PORT D "PORTA_INT0", // 66: External Interrupt 0 PORT A @@ -6956,24 +6446,24 @@ const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { "UNUSED", // 101: not implemented on this device "UNUSED", // 102: not implemented on this device "UNUSED", // 103: not implemented on this device - "PORTF_INT0", // 104: External Interrupt 0 PORT F - "PORTF_INT1", // 105: External Interrupt 1 PORT F + "UNUSED", // 104: not implemented on this device + "UNUSED", // 105: not implemented on this device "UNUSED", // 106: not implemented on this device "UNUSED", // 107: not implemented on this device - "TCF0_OVF/TCF2_LUNF", // 108: TC F0 Overflow/TC F2 Low Byte Underflow - "TCF0_ERR/TCF2_HUNF", // 109: TC F0 Error/TC F2 High Byte Underflow - "TCF0_CCA/TCF2_LCMPA", // 110: TC F0 Compare or Capture A/TC F2 Low Byte Compare A - "TCF0_CCB/TCF2_LCMPB", // 111: TC F0 Compare or Capture B/TC F2 Low Byte Compare B - "TCF0_CCC/TCF2_LCMPC", // 112: TC F0 Compare or Capture C/TC F2 Low Byte Compare C - "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D + "UNUSED", // 108: not implemented on this device + "UNUSED", // 109: not implemented on this device + "UNUSED", // 110: not implemented on this device + "UNUSED", // 111: not implemented on this device + "UNUSED", // 112: not implemented on this device + "UNUSED", // 113: not implemented on this device "UNUSED", // 114: not implemented on this device "UNUSED", // 115: not implemented on this device "UNUSED", // 116: not implemented on this device "UNUSED", // 117: not implemented on this device "UNUSED", // 118: not implemented on this device - "USARTF0_RXC", // 119: USARTF 0 Reception Complete - "USARTF0_DRE", // 120: USARTF 0 Data Register Empty - "USARTF0_TXC", // 121: USARTF 0 Transmission Complete + "UNUSED", // 119: not implemented on this device + "UNUSED", // 120: not implemented on this device + "UNUSED", // 121: not implemented on this device "UNUSED", // 122: not implemented on this device "UNUSED", // 123: not implemented on this device "UNUSED", // 124: not implemented on this device @@ -6981,8 +6471,151 @@ const char * const vtab_atxmega256a3u[vts_atxmega256a3u] = { "USB_TRNCOMPL", // 126: USB Transaction Complete }; -// ATxmega256C3 ATxmega192C3 ATxmega128C3 ATxmega64C3 ATxmega32C3 -const char * const vtab_atxmega256c3[vts_atxmega256c3] = { +// ATxmega64B1 ATxmega128B1 +const char * const vtab_atxmega64b1[vts_atxmega64b1] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "USB_BUSEVENT", // 31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 32: USB Transaction Complete + "UNUSED", // 33: not implemented on this device + "UNUSED", // 34: not implemented on this device + "LCD_INT", // 35: LCD Interrupt + "AES_INT", // 36: AES Interrupt + "NVM_EE", // 37: NVM EEPROM + "NVM_SPM", // 38: NVM SPM + "PORTB_INT0", // 39: External Interrupt 0 PORT B + "PORTB_INT1", // 40: External Interrupt 1 PORT B + "ACB_AC0", // 41: ACB AC 0 Interrupt + "ACB_AC1", // 42: ACB AC 1 Interrupt + "ACB_ACW", // 43: ACB AC Window Mode + "ADCB_CH0", // 44: ADCB Interrupt 0 + "UNUSED", // 45: not implemented on this device + "UNUSED", // 46: not implemented on this device + "UNUSED", // 47: not implemented on this device + "PORTD_INT0", // 48: External Interrupt 0 PORT D + "PORTD_INT1", // 49: External Interrupt 1 PORT D + "PORTG_INT0", // 50: External Interrupt 0 PORT G + "PORTG_INT1", // 51: External Interrupt 1 PORT G + "PORTM_INT0", // 52: External Interrupt 0 PORT M + "PORTM_INT1", // 53: External Interrupt 1 PORT M + "PORTE_INT0", // 54: External Interrupt 0 PORT E + "PORTE_INT1", // 55: External Interrupt 1 PORT E + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "TCE0_OVF/TCE2_LUNF", // 58: TC E0 Overflow/TC E2 Low Byte Underflow + "TCE0_ERR/TCE2_HUNF", // 59: TC E0 Error/TC E2 High Byte Underflow + "TCE0_CCA/TCE2_LCMPA", // 60: TC E0 Compare or Capture A/TC E2 Low Byte Compare A + "TCE0_CCB/TCE2_LCMPB", // 61: TC E0 Compare or Capture B/TC E2 Low Byte Compare B + "TCE0_CCC/TCE2_LCMPC", // 62: TC E0 Compare or Capture C/TC E2 Low Byte Compare C + "TCE0_CCD/TCE2_LCMPD", // 63: TC E0 Compare or Capture D/TC E2 Low Byte Compare D + "UNUSED", // 64: not implemented on this device + "UNUSED", // 65: not implemented on this device + "UNUSED", // 66: not implemented on this device + "UNUSED", // 67: not implemented on this device + "UNUSED", // 68: not implemented on this device + "USARTE0_RXC", // 69: USARTE 0 Reception Complete + "USARTE0_DRE", // 70: USARTE 0 Data Register Empty + "USARTE0_TXC", // 71: USARTE 0 Transmission Complete + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "PORTA_INT0", // 75: External Interrupt 0 PORT A + "PORTA_INT1", // 76: External Interrupt 1 PORT A + "ACA_AC0", // 77: ACA AC 0 Interrupt + "ACA_AC1", // 78: ACA AC 1 Interrupt + "ACA_ACW", // 79: ACA AC Window Mode + "ADCA_CH0", // 80: ADCA Interrupt 0 +}; + +// ATxmega64B3 ATxmega128B3 +const char * const vtab_atxmega64b3[vts_atxmega64b3] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "DMA_CH0", // 6: DMA Channel 0 + "DMA_CH1", // 7: DMA Channel 1 + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "USB_BUSEVENT", // 31: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 32: USB Transaction Complete + "UNUSED", // 33: not implemented on this device + "UNUSED", // 34: not implemented on this device + "LCD_INT", // 35: LCD Interrupt + "AES_INT", // 36: AES Interrupt + "NVM_EE", // 37: NVM EEPROM + "NVM_SPM", // 38: NVM SPM + "PORTB_INT0", // 39: External Interrupt 0 PORT B + "PORTB_INT1", // 40: External Interrupt 1 PORT B + "ACB_AC0", // 41: ACB AC 0 Interrupt + "ACB_AC1", // 42: ACB AC 1 Interrupt + "ACB_ACW", // 43: ACB AC Window Mode + "ADCB_CH0", // 44: ADCB Interrupt 0 + "UNUSED", // 45: not implemented on this device + "UNUSED", // 46: not implemented on this device + "UNUSED", // 47: not implemented on this device + "PORTD_INT0", // 48: External Interrupt 0 PORT D + "PORTD_INT1", // 49: External Interrupt 1 PORT D + "PORTG_INT0", // 50: External Interrupt 0 PORT G + "PORTG_INT1", // 51: External Interrupt 1 PORT G + "PORTM_INT0", // 52: External Interrupt 0 PORT M + "PORTM_INT1", // 53: External Interrupt 1 PORT M +}; + +// ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 +const char * const vtab_atxmega32c3[vts_atxmega32c3] = { "RESET", // 0: Reset (various reasons) "OSC_OSCF", // 1: Oscillator Failure NMI "PORTC_INT0", // 2: External Interrupt 0 PORT C @@ -7243,8 +6876,139 @@ const char * const vtab_atxmega384c3[vts_atxmega384c3] = { "USB_TRNCOMPL", // 126: USB Transaction Complete }; -// ATxmega384D3 ATxmega256D3 ATxmega192D3 ATxmega128D3 ATxmega64D3 ATxmega32D3 -const char * const vtab_atxmega384d3[vts_atxmega384d3] = { +// ATxmega16C4 ATxmega32C4 +const char * const vtab_atxmega16c4[vts_atxmega16c4] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "USARTC1_RXC", // 28: USARTC 1 Reception Complete + "USARTC1_DRE", // 29: USARTC 1 Data Register Empty + "USARTC1_TXC", // 30: USARTC 1 Transmission Complete + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "UNUSED", // 58: not implemented on this device + "UNUSED", // 59: not implemented on this device + "UNUSED", // 60: not implemented on this device + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete + "UNUSED", // 91: not implemented on this device + "UNUSED", // 92: not implemented on this device + "UNUSED", // 93: not implemented on this device + "UNUSED", // 94: not implemented on this device + "UNUSED", // 95: not implemented on this device + "UNUSED", // 96: not implemented on this device + "UNUSED", // 97: not implemented on this device + "UNUSED", // 98: not implemented on this device + "UNUSED", // 99: not implemented on this device + "UNUSED", // 100: not implemented on this device + "UNUSED", // 101: not implemented on this device + "UNUSED", // 102: not implemented on this device + "UNUSED", // 103: not implemented on this device + "UNUSED", // 104: not implemented on this device + "UNUSED", // 105: not implemented on this device + "UNUSED", // 106: not implemented on this device + "UNUSED", // 107: not implemented on this device + "UNUSED", // 108: not implemented on this device + "UNUSED", // 109: not implemented on this device + "UNUSED", // 110: not implemented on this device + "UNUSED", // 111: not implemented on this device + "UNUSED", // 112: not implemented on this device + "UNUSED", // 113: not implemented on this device + "UNUSED", // 114: not implemented on this device + "UNUSED", // 115: not implemented on this device + "UNUSED", // 116: not implemented on this device + "UNUSED", // 117: not implemented on this device + "UNUSED", // 118: not implemented on this device + "UNUSED", // 119: not implemented on this device + "UNUSED", // 120: not implemented on this device + "UNUSED", // 121: not implemented on this device + "UNUSED", // 122: not implemented on this device + "UNUSED", // 123: not implemented on this device + "UNUSED", // 124: not implemented on this device + "USB_BUSEVENT", // 125: SOF, Suspend, Resume, Reset Bus Event Interrupts, CRC, Underflow, Overflow or Stall Error + "USB_TRNCOMPL", // 126: USB Transaction Complete +}; + +// ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 ATxmega384D3 +const char * const vtab_atxmega32d3[vts_atxmega32d3] = { "RESET", // 0: Reset (various reasons) "OSC_OSCF", // 1: Oscillator Failure NMI "PORTC_INT0", // 2: External Interrupt 0 PORT C @@ -7361,8 +7125,245 @@ const char * const vtab_atxmega384d3[vts_atxmega384d3] = { "TCF0_CCD/TCF2_LCMPD", // 113: TC F0 Compare or Capture D/TC F2 Low Byte Compare D }; -// ATtiny402 ATtiny202 -const char * const vtab_attiny402[vts_attiny402] = { +// ATxmega16D4 ATxmega32D4 +const char * const vtab_atxmega16d4[vts_atxmega16d4] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "UNUSED", // 58: not implemented on this device + "UNUSED", // 59: not implemented on this device + "UNUSED", // 60: not implemented on this device + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "ADCA_CH1", // 72: ADCA Interrupt 1 + "ADCA_CH2", // 73: ADCA Interrupt 2 + "ADCA_CH3", // 74: ADCA Interrupt 3 + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF", // 77: TC D0 Overflow + "TCD0_ERR", // 78: TC D0 Error + "TCD0_CCA", // 79: TC D0 Compare or Capture A + "TCD0_CCB", // 80: TC D0 Compare or Capture B + "TCD0_CCC", // 81: TC D0 Compare or Capture C + "TCD0_CCD", // 82: TC D0 Compare or Capture D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete +}; + +// ATxmega64D4 ATxmega128D4 +const char * const vtab_atxmega64d4[vts_atxmega64d4] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTC_INT0", // 2: External Interrupt 0 PORT C + "PORTC_INT1", // 3: External Interrupt 1 PORT C + "PORTR_INT0", // 4: External Interrupt 0 PORT R + "PORTR_INT1", // 5: External Interrupt 1 PORT R + "UNUSED", // 6: not implemented on this device + "UNUSED", // 7: not implemented on this device + "UNUSED", // 8: not implemented on this device + "UNUSED", // 9: not implemented on this device + "RTC_OVF", // 10: RTC Overflow + "RTC_COMP", // 11: RTC Compare + "TWIC_TWIP", // 12: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 13: 2-Wire Interface C Controller + "TCC0_OVF/TCC2_LUNF", // 14: TC C0 Overflow/TC C2 Low Byte Underflow + "TCC0_ERR/TCC2_HUNF", // 15: TC C0 Error/TC C2 High Byte Underflow + "TCC0_CCA/TCC2_LCMPA", // 16: TC C0 Compare or Capture A/TC C2 Low Byte Compare A + "TCC0_CCB/TCC2_LCMPB", // 17: TC C0 Compare or Capture B/TC C2 Low Byte Compare B + "TCC0_CCC/TCC2_LCMPC", // 18: TC C0 Compare or Capture C/TC C2 Low Byte Compare C + "TCC0_CCD/TCC2_LCMPD", // 19: TC C0 Compare or Capture D/TC C2 Low Byte Compare D + "TCC1_OVF", // 20: TC C1 Overflow + "TCC1_ERR", // 21: TC C1 Error + "TCC1_CCA", // 22: TC C1 Compare or Capture A + "TCC1_CCB", // 23: TC C1 Compare or Capture B + "SPIC_INT", // 24: SPI C Interrupt + "USARTC0_RXC", // 25: USARTC 0 Reception Complete + "USARTC0_DRE", // 26: USARTC 0 Data Register Empty + "USARTC0_TXC", // 27: USARTC 0 Transmission Complete + "UNUSED", // 28: not implemented on this device + "UNUSED", // 29: not implemented on this device + "UNUSED", // 30: not implemented on this device + "UNUSED", // 31: not implemented on this device + "NVM_EE", // 32: NVM EEPROM + "NVM_SPM", // 33: NVM SPM + "PORTB_INT0", // 34: External Interrupt 0 PORT B + "PORTB_INT1", // 35: External Interrupt 1 PORT B + "UNUSED", // 36: not implemented on this device + "UNUSED", // 37: not implemented on this device + "UNUSED", // 38: not implemented on this device + "UNUSED", // 39: not implemented on this device + "UNUSED", // 40: not implemented on this device + "UNUSED", // 41: not implemented on this device + "UNUSED", // 42: not implemented on this device + "PORTE_INT0", // 43: External Interrupt 0 PORT E + "PORTE_INT1", // 44: External Interrupt 1 PORT E + "TWIE_TWIP", // 45: 2-Wire Interface E Peripheral + "TWIE_TWIM", // 46: 2-Wire Interface E Controller + "TCE0_OVF", // 47: TC E0 Overflow + "TCE0_ERR", // 48: TC E0 Error + "TCE0_CCA", // 49: TC E0 Compare or Capture A + "TCE0_CCB", // 50: TC E0 Compare or Capture B + "TCE0_CCC", // 51: TC E0 Compare or Capture C + "TCE0_CCD", // 52: TC E0 Compare or Capture D + "UNUSED", // 53: not implemented on this device + "UNUSED", // 54: not implemented on this device + "UNUSED", // 55: not implemented on this device + "UNUSED", // 56: not implemented on this device + "UNUSED", // 57: not implemented on this device + "UNUSED", // 58: not implemented on this device + "UNUSED", // 59: not implemented on this device + "UNUSED", // 60: not implemented on this device + "UNUSED", // 61: not implemented on this device + "UNUSED", // 62: not implemented on this device + "UNUSED", // 63: not implemented on this device + "PORTD_INT0", // 64: External Interrupt 0 PORT D + "PORTD_INT1", // 65: External Interrupt 1 PORT D + "PORTA_INT0", // 66: External Interrupt 0 PORT A + "PORTA_INT1", // 67: External Interrupt 1 PORT A + "ACA_AC0", // 68: ACA AC 0 Interrupt + "ACA_AC1", // 69: ACA AC 1 Interrupt + "ACA_ACW", // 70: ACA AC Window Mode + "ADCA_CH0", // 71: ADCA Interrupt 0 + "UNUSED", // 72: not implemented on this device + "UNUSED", // 73: not implemented on this device + "UNUSED", // 74: not implemented on this device + "UNUSED", // 75: not implemented on this device + "UNUSED", // 76: not implemented on this device + "TCD0_OVF/TCD2_LUNF", // 77: TC D0 Overflow/TC D2 Low Byte Underflow + "TCD0_ERR/TCD2_HUNF", // 78: TC D0 Error/TC D2 High Byte Underflow + "TCD0_CCA/TCD2_LCMPA", // 79: TC D0 Compare or Capture A/TC D2 Low Byte Compare A + "TCD0_CCB/TCD2_LCMPB", // 80: TC D0 Compare or Capture B/TC D2 Low Byte Compare B + "TCD0_CCC/TCD2_LCMPC", // 81: TC D0 Compare or Capture C/TC D2 Low Byte Compare C + "TCD0_CCD/TCD2_LCMPD", // 82: TC D0 Compare or Capture D/TC D2 Low Byte Compare D + "UNUSED", // 83: not implemented on this device + "UNUSED", // 84: not implemented on this device + "UNUSED", // 85: not implemented on this device + "UNUSED", // 86: not implemented on this device + "SPID_INT", // 87: SPI D Interrupt + "USARTD0_RXC", // 88: USARTD 0 Reception Complete + "USARTD0_DRE", // 89: USARTD 0 Data Register Empty + "USARTD0_TXC", // 90: USARTD 0 Transmission Complete +}; + +// ATxmega8E5 ATxmega16E5 ATxmega32E5 +const char * const vtab_atxmega8e5[vts_atxmega8e5] = { + "RESET", // 0: Reset (various reasons) + "OSC_OSCF", // 1: Oscillator Failure NMI + "PORTR_INT", // 2: External Interrupt PORT R + "EDMA_CH0", // 3: External DMA Channel 0 + "EDMA_CH1", // 4: External DMA Channel 1 + "EDMA_CH2", // 5: External DMA Channel 2 + "EDMA_CH3", // 6: External DMA Channel 3 + "RTC_OVF", // 7: RTC Overflow + "RTC_COMP", // 8: RTC Compare + "PORTC_INT", // 9: External Interrupt PORT C + "TWIC_TWIP", // 10: 2-Wire Interface C Peripheral + "TWIC_TWIM", // 11: 2-Wire Interface C Controller + "TCC4_OVF", // 12: TC C4 Overflow + "TCC4_ERR", // 13: TC C4 Error + "TCC4_CCA", // 14: TC C4 Compare or Capture A + "TCC4_CCB", // 15: TC C4 Compare or Capture B + "TCC4_CCC", // 16: TC C4 Compare or Capture C + "TCC4_CCD", // 17: TC C4 Compare or Capture D + "TCC5_OVF", // 18: TC C5 Overflow + "TCC5_ERR", // 19: TC C5 Error + "TCC5_CCA", // 20: TC C5 Compare or Capture A + "TCC5_CCB", // 21: TC C5 Compare or Capture B + "SPIC_INT", // 22: SPI C Interrupt + "USARTC0_RXC", // 23: USARTC 0 Reception Complete + "USARTC0_DRE", // 24: USARTC 0 Data Register Empty + "USARTC0_TXC", // 25: USARTC 0 Transmission Complete + "NVM_EE", // 26: NVM EEPROM + "NVM_SPM", // 27: NVM SPM + "XCL_UNF", // 28: XMEGA Custom Logic Underflow + "XCL_CC", // 29: XMEGA Custom Logic Compare or Capture + "PORTA_INT", // 30: External Interrupt PORT A + "ACA_AC0", // 31: ACA AC 0 Interrupt + "ACA_AC1", // 32: ACA AC 1 Interrupt + "ACA_ACW", // 33: ACA AC Window Mode + "ADCA_CH0", // 34: ADCA Interrupt 0 + "PORTD_INT", // 35: External Interrupt PORT D + "TCD5_OVF", // 36: TC D5 Overflow + "TCD5_ERR", // 37: TC D5 Error + "TCD5_CCA", // 38: TC D5 Compare or Capture A + "TCD5_CCB", // 39: TC D5 Compare or Capture B + "USARTD0_RXC", // 40: USARTD 0 Reception Complete + "USARTD0_DRE", // 41: USARTD 0 Data Register Empty + "USARTD0_TXC", // 42: USARTD 0 Transmission Complete +}; + +// ATtiny202 ATtiny402 +const char * const vtab_attiny202[vts_attiny202] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7391,8 +7392,8 @@ const char * const vtab_attiny402[vts_attiny402] = { "NVMCTRL_EE", // 25: NVM EEPROM }; -// ATtiny404 ATtiny204 -const char * const vtab_attiny404[vts_attiny404] = { +// ATtiny204 ATtiny404 +const char * const vtab_attiny204[vts_attiny204] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7451,98 +7452,8 @@ const char * const vtab_attiny406[vts_attiny406] = { "NVMCTRL_EE", // 25: NVM EEPROM }; -// ATtiny412 ATtiny212 -const char * const vtab_attiny412[vts_attiny412] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "PORTA_PORT", // 3: Interrupt PORT A - "UNUSED", // 4: not implemented on this device - "UNUSED", // 5: not implemented on this device - "RTC_CNT", // 6: RTC Counter Interrupt - "RTC_PIT", // 7: RTC Periodic Interrupt Timer - "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 9: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 13: TC B0 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "AC0_AC", // 16: AC0 AC Interrupt - "ADC0_RESRDY", // 17: ADC 0 Result Ready - "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller - "SPI0_INT", // 21: SPI 0 Interrupt - "USART0_RXC", // 22: USART 0 Receive Complete - "USART0_DRE", // 23: USART 0 Data Register Empty - "USART0_TXC", // 24: USART 0 Transmit Complete - "NVMCTRL_EE", // 25: NVM EEPROM -}; - -// ATtiny814 ATtiny414 ATtiny214 -const char * const vtab_attiny814[vts_attiny814] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "PORTA_PORT", // 3: Interrupt PORT A - "PORTB_PORT", // 4: Interrupt PORT B - "UNUSED", // 5: not implemented on this device - "RTC_CNT", // 6: RTC Counter Interrupt - "RTC_PIT", // 7: RTC Periodic Interrupt Timer - "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 9: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 13: TC B0 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "AC0_AC", // 16: AC0 AC Interrupt - "ADC0_RESRDY", // 17: ADC 0 Result Ready - "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller - "SPI0_INT", // 21: SPI 0 Interrupt - "USART0_RXC", // 22: USART 0 Receive Complete - "USART0_DRE", // 23: USART 0 Data Register Empty - "USART0_TXC", // 24: USART 0 Transmit Complete - "NVMCTRL_EE", // 25: NVM EEPROM -}; - -// ATtiny817 ATtiny816 ATtiny417 ATtiny416auto ATtiny416 -const char * const vtab_attiny817[vts_attiny817] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "PORTA_PORT", // 3: Interrupt PORT A - "PORTB_PORT", // 4: Interrupt PORT B - "PORTC_PORT", // 5: Interrupt PORT C - "RTC_CNT", // 6: RTC Counter Interrupt - "RTC_PIT", // 7: RTC Periodic Interrupt Timer - "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 9: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 13: TC B0 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "AC0_AC", // 16: AC0 AC Interrupt - "ADC0_RESRDY", // 17: ADC 0 Result Ready - "ADC0_WCOMP", // 18: ADC 0 Window Comparator - "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller - "SPI0_INT", // 21: SPI 0 Interrupt - "USART0_RXC", // 22: USART 0 Receive Complete - "USART0_DRE", // 23: USART 0 Data Register Empty - "USART0_TXC", // 24: USART 0 Transmit Complete - "NVMCTRL_EE", // 25: NVM EEPROM -}; - -// ATtiny1607 ATtiny1606 ATtiny1604 ATtiny807 ATtiny806 ATtiny804 -const char * const vtab_attiny1607[vts_attiny1607] = { +// ATtiny804 ATtiny806 ATtiny807 ATtiny1604 ATtiny1606 ATtiny1607 +const char * const vtab_attiny804[vts_attiny804] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7576,6 +7487,96 @@ const char * const vtab_attiny1607[vts_attiny1607] = { "NVMCTRL_EE", // 30: NVM EEPROM }; +// ATtiny212 ATtiny412 +const char * const vtab_attiny212[vts_attiny212] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "UNUSED", // 4: not implemented on this device + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +// ATtiny214 ATtiny414 ATtiny814 +const char * const vtab_attiny214[vts_attiny214] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "UNUSED", // 5: not implemented on this device + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + +// ATtiny416 ATtiny416auto ATtiny417 ATtiny816 ATtiny817 +const char * const vtab_attiny416[vts_attiny416] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "AC0_AC", // 16: AC0 AC Interrupt + "ADC0_RESRDY", // 17: ADC 0 Result Ready + "ADC0_WCOMP", // 18: ADC 0 Window Comparator + "TWI0_TWIP", // 19: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 20: 2-Wire Interface 0 Controller + "SPI0_INT", // 21: SPI 0 Interrupt + "USART0_RXC", // 22: USART 0 Receive Complete + "USART0_DRE", // 23: USART 0 Data Register Empty + "USART0_TXC", // 24: USART 0 Transmit Complete + "NVMCTRL_EE", // 25: NVM EEPROM +}; + // ATtiny1614 const char * const vtab_attiny1614[vts_attiny1614] = { "RESET", // 0: Reset (various reasons) @@ -7611,6 +7612,41 @@ const char * const vtab_attiny1614[vts_attiny1614] = { "NVMCTRL_EE", // 30: NVM EEPROM }; +// ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 +const char * const vtab_attiny1616[vts_attiny1616] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "PORTA_PORT", // 3: Interrupt PORT A + "PORTB_PORT", // 4: Interrupt PORT B + "PORTC_PORT", // 5: Interrupt PORT C + "RTC_CNT", // 6: RTC Counter Interrupt + "RTC_PIT", // 7: RTC Periodic Interrupt Timer + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TCD0_OVF", // 15: TC D0 Overflow + "TCD0_TRIG", // 16: TC D0 Trigger + "AC0_AC", // 17: AC0 AC Interrupt + "AC1_AC", // 18: AC1 AC Interrupt + "AC2_AC", // 19: AC2 AC Interrupt + "ADC0_RESRDY", // 20: ADC 0 Result Ready + "ADC0_WCOMP", // 21: ADC 0 Window Comparator + "ADC1_RESRDY", // 22: ADC 1 Result Ready + "ADC1_WCOMP", // 23: ADC 1 Window Comparator + "TWI0_TWIP", // 24: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller + "SPI0_INT", // 26: SPI 0 Interrupt + "USART0_RXC", // 27: USART 0 Receive Complete + "USART0_DRE", // 28: USART 0 Data Register Empty + "USART0_TXC", // 29: USART 0 Transmit Complete + "NVMCTRL_EE", // 30: NVM EEPROM +}; + // ATtiny3214 const char * const vtab_attiny3214[vts_attiny3214] = { "RESET", // 0: Reset (various reasons) @@ -7646,46 +7682,11 @@ const char * const vtab_attiny3214[vts_attiny3214] = { "NVMCTRL_EE", // 30: NVM EEPROM }; -// ATtiny3217 ATtiny3216 ATtiny1617 ATtiny1616 -const char * const vtab_attiny3217[vts_attiny3217] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "PORTA_PORT", // 3: Interrupt PORT A - "PORTB_PORT", // 4: Interrupt PORT B - "PORTC_PORT", // 5: Interrupt PORT C - "RTC_CNT", // 6: RTC Counter Interrupt - "RTC_PIT", // 7: RTC Periodic Interrupt Timer - "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 9: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 13: TC B0 Interrupt - "TCB1_INT", // 14: TC B1 Interrupt - "TCD0_OVF", // 15: TC D0 Overflow - "TCD0_TRIG", // 16: TC D0 Trigger - "AC0_AC", // 17: AC0 AC Interrupt - "AC1_AC", // 18: AC1 AC Interrupt - "AC2_AC", // 19: AC2 AC Interrupt - "ADC0_RESRDY", // 20: ADC 0 Result Ready - "ADC0_WCOMP", // 21: ADC 0 Window Comparator - "ADC1_RESRDY", // 22: ADC 1 Result Ready - "ADC1_WCOMP", // 23: ADC 1 Window Comparator - "TWI0_TWIP", // 24: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 25: 2-Wire Interface 0 Controller - "SPI0_INT", // 26: SPI 0 Interrupt - "USART0_RXC", // 27: USART 0 Receive Complete - "USART0_DRE", // 28: USART 0 Data Register Empty - "USART0_TXC", // 29: USART 0 Transmit Complete - "NVMCTRL_EE", // 30: NVM EEPROM -}; - /* - * ATtiny3227 ATtiny3226 ATtiny3224 ATtiny1627 ATtiny1626 ATtiny1624 ATtiny827 ATtiny826 ATtiny824 - * ATtiny427 ATtiny426 ATtiny424 + * ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 + * ATtiny3224 ATtiny3226 ATtiny3227 */ -const char * const vtab_attiny3227[vts_attiny3227] = { +const char * const vtab_attiny424[vts_attiny424] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7718,8 +7719,8 @@ const char * const vtab_attiny3227[vts_attiny3227] = { "NVMCTRL_EE", // 29: NVM EEPROM }; -// ATmega4808 ATmega3208 ATmega1608 ATmega808 -const char * const vtab_atmega4808[vts_atmega4808] = { +// ATmega808 ATmega1608 ATmega3208 ATmega4808 +const char * const vtab_atmega808[vts_atmega808] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7758,8 +7759,8 @@ const char * const vtab_atmega4808[vts_atmega4808] = { "PORTE_PORT", // 35: Interrupt PORT E }; -// ATmega4809 ATmega3209 ATmega1609 ATmega809 -const char * const vtab_atmega4809[vts_atmega4809] = { +// ATmega809 ATmega1609 ATmega3209 ATmega4809 +const char * const vtab_atmega809[vts_atmega809] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7802,8 +7803,741 @@ const char * const vtab_atmega4809[vts_atmega4809] = { "USART3_TXC", // 39: USART 3 Transmit Complete }; -// AVR16EB32 AVR16EB28 AVR16EB20 AVR16EB14 -const char * const vtab_avr16eb32[vts_avr16eb32] = { +// AVR32DA28 AVR32DA28S AVR64DA28 AVR64DA28S AVR128DA28 AVR128DA28S +const char * const vtab_avr32da28[vts_avr32da28] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt +}; + +// AVR32DA32 AVR32DA32S AVR64DA32 AVR64DA32S AVR128DA32 AVR128DA32S +const char * const vtab_avr32da32[vts_avr32da32] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "UNUSED", // 41: not implemented on this device + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller +}; + +// AVR32DA48 AVR32DA48S +const char * const vtab_avr32da48[vts_avr32da48] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "TCB3_INT", // 41: TC B3 Interrupt + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "PORTB_PORT", // 44: Interrupt PORT B + "PORTE_PORT", // 45: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 47: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 51: Zero Cross Detect 1 + "USART3_RXC", // 52: USART 3 Receive Complete + "USART3_DRE", // 53: USART 3 Data Register Empty + "USART3_TXC", // 54: USART 3 Transmit Complete + "USART4_RXC", // 55: USART 4 Receive Complete + "USART4_DRE", // 56: USART 4 Data Register Empty + "USART4_TXC", // 57: USART 4 Transmit Complete + "UNUSED", // 58: not implemented on this device + "UNUSED", // 59: not implemented on this device + "TCB4_INT", // 60: TC B4 Interrupt +}; + +// AVR64DA48 AVR64DA48S AVR128DA48 AVR128DA48S +const char * const vtab_avr64da48[vts_avr64da48] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "TCB3_INT", // 41: TC B3 Interrupt + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "PORTB_PORT", // 44: Interrupt PORT B + "PORTE_PORT", // 45: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 47: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 51: Zero Cross Detect 1 + "USART3_RXC", // 52: USART 3 Receive Complete + "USART3_DRE", // 53: USART 3 Data Register Empty + "USART3_TXC", // 54: USART 3 Transmit Complete + "USART4_RXC", // 55: USART 4 Receive Complete + "USART4_DRE", // 56: USART 4 Data Register Empty + "USART4_TXC", // 57: USART 4 Transmit Complete +}; + +// AVR64DA64 AVR64DA64S AVR128DA64 AVR128DA64S +const char * const vtab_avr64da64[vts_avr64da64] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 8: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TCD0_OVF", // 14: TC D0 Overflow + "TCD0_TRIG", // 15: TC D0 Trigger + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_WCMP", // 25: ADC 0 Window Comparator + "ZCD0_ZCD", // 26: Zero Cross Detect 0 + "PTC_PTC", // 27: PTC Interrupt + "AC1_AC", // 28: AC1 AC Interrupt + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM + "SPI1_INT", // 36: SPI 1 Interrupt + "USART2_RXC", // 37: USART 2 Receive Complete + "USART2_DRE", // 38: USART 2 Data Register Empty + "USART2_TXC", // 39: USART 2 Transmit Complete + "AC2_AC", // 40: AC2 AC Interrupt + "TCB3_INT", // 41: TC B3 Interrupt + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "PORTB_PORT", // 44: Interrupt PORT B + "PORTE_PORT", // 45: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 47: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 51: Zero Cross Detect 1 + "USART3_RXC", // 52: USART 3 Receive Complete + "USART3_DRE", // 53: USART 3 Data Register Empty + "USART3_TXC", // 54: USART 3 Transmit Complete + "USART4_RXC", // 55: USART 4 Receive Complete + "USART4_DRE", // 56: USART 4 Data Register Empty + "USART4_TXC", // 57: USART 4 Transmit Complete + "PORTG_PORT", // 58: Interrupt PORT G + "ZCD2_ZCD", // 59: Zero Cross Detect 2 + "TCB4_INT", // 60: TC B4 Interrupt + "USART5_RXC", // 61: USART 5 Receive Complete + "USART5_DRE", // 62: USART 5 Data Register Empty + "USART5_TXC", // 63: USART 5 Transmit Complete +}; + +// AVR32DB28 AVR64DB28 AVR128DB28 +const char * const vtab_avr32db28[vts_avr32db28] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt +}; + +// AVR32DB32 AVR64DB32 AVR128DB32 +const char * const vtab_avr32db32[vts_avr32db32] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller +}; + +// AVR32DB48 AVR64DB48 AVR128DB48 +const char * const vtab_avr32db48[vts_avr32db48] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "TCB3_INT", // 44: TC B3 Interrupt + "PORTB_PORT", // 45: Interrupt PORT B + "PORTE_PORT", // 46: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 47: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 48: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 49: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 50: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 51: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 52: Zero Cross Detect 1 + "USART3_RXC", // 53: USART 3 Receive Complete + "USART3_DRE", // 54: USART 3 Data Register Empty + "USART3_TXC", // 55: USART 3 Transmit Complete + "USART4_RXC", // 56: USART 4 Receive Complete + "USART4_DRE", // 57: USART 4 Data Register Empty + "USART4_TXC", // 58: USART 4 Transmit Complete + "UNUSED", // 59: not implemented on this device + "ZCD2_ZCD", // 60: Zero Cross Detect 2 +}; + +// AVR64DB64 AVR128DB64 +const char * const vtab_avr64db64[vts_avr64db64] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD0_ZCD", // 28: Zero Cross Detect 0 + "AC1_AC", // 29: AC1 AC Interrupt + "PORTC_PORT", // 30: Interrupt PORT C + "TCB2_INT", // 31: TC B2 Interrupt + "USART1_RXC", // 32: USART 1 Receive Complete + "USART1_DRE", // 33: USART 1 Data Register Empty + "USART1_TXC", // 34: USART 1 Transmit Complete + "PORTF_PORT", // 35: Interrupt PORT F + "NVMCTRL_EE", // 36: NVM EEPROM + "SPI1_INT", // 37: SPI 1 Interrupt + "USART2_RXC", // 38: USART 2 Receive Complete + "USART2_DRE", // 39: USART 2 Data Register Empty + "USART2_TXC", // 40: USART 2 Transmit Complete + "AC2_AC", // 41: AC2 AC Interrupt + "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral + "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller + "TCB3_INT", // 44: TC B3 Interrupt + "PORTB_PORT", // 45: Interrupt PORT B + "PORTE_PORT", // 46: Interrupt PORT E + "TCA1_LUNF/TCA1_OVF", // 47: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 48: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 49: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 50: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 51: TC A1 Compare 2/TC A1 Low Compare 2 + "ZCD1_ZCD", // 52: Zero Cross Detect 1 + "USART3_RXC", // 53: USART 3 Receive Complete + "USART3_DRE", // 54: USART 3 Data Register Empty + "USART3_TXC", // 55: USART 3 Transmit Complete + "USART4_RXC", // 56: USART 4 Receive Complete + "USART4_DRE", // 57: USART 4 Data Register Empty + "USART4_TXC", // 58: USART 4 Transmit Complete + "PORTG_PORT", // 59: Interrupt PORT G + "ZCD2_ZCD", // 60: Zero Cross Detect 2 + "TCB4_INT", // 61: TC B4 Interrupt + "USART5_RXC", // 62: USART 5 Receive Complete + "USART5_DRE", // 63: USART 5 Data Register Empty + "USART5_TXC", // 64: USART 5 Transmit Complete +}; + +// AVR16DD14 AVR16DD20 AVR32DD14 AVR32DD20 AVR64DD14 AVR64DD20 +const char * const vtab_avr16dd14[vts_avr16dd14] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD3_ZCD", // 28: Zero Cross Detect 3 + "PORTC_PORT", // 29: Interrupt PORT C + "UNUSED", // 30: not implemented on this device + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM +}; + +// AVR16DD28 AVR16DD32 AVR32DD28 AVR32DD32 AVR64DD28 AVR64DD32 +const char * const vtab_avr16dd28[vts_avr16dd28] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "MVIO_MVIO", // 4: Multi-Voltage I/O + "RTC_CNT", // 5: RTC Counter Interrupt + "RTC_PIT", // 6: RTC Periodic Interrupt Timer + "CCL_CCL", // 7: Configurable Custom Logic + "PORTA_PORT", // 8: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 10: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 14: TC B0 Interrupt + "TCB1_INT", // 15: TC B1 Interrupt + "TCD0_OVF", // 16: TC D0 Overflow + "TCD0_TRIG", // 17: TC D0 Trigger + "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller + "SPI0_INT", // 20: SPI 0 Interrupt + "USART0_RXC", // 21: USART 0 Receive Complete + "USART0_DRE", // 22: USART 0 Data Register Empty + "USART0_TXC", // 23: USART 0 Transmit Complete + "PORTD_PORT", // 24: Interrupt PORT D + "AC0_AC", // 25: AC0 AC Interrupt + "ADC0_RESRDY", // 26: ADC 0 Result Ready + "ADC0_WCMP", // 27: ADC 0 Window Comparator + "ZCD3_ZCD", // 28: Zero Cross Detect 3 + "PORTC_PORT", // 29: Interrupt PORT C + "TCB2_INT", // 30: TC B2 Interrupt + "USART1_RXC", // 31: USART 1 Receive Complete + "USART1_DRE", // 32: USART 1 Data Register Empty + "USART1_TXC", // 33: USART 1 Transmit Complete + "PORTF_PORT", // 34: Interrupt PORT F + "NVMCTRL_EE", // 35: NVM EEPROM +}; + +/* + * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 + * AVR64DU32 + */ +const char * const vtab_avr16du14[vts_avr16du14] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "RTC_CNT", // 4: RTC Counter Interrupt + "RTC_PIT", // 5: RTC Periodic Interrupt Timer + "CCL_CCL", // 6: Configurable Custom Logic + "USB0_BUSEVENT", // 7: USB 0 Bus Event + "USB0_TRNCOMPL", // 8: USB 0 Transaction Complete + "PORTA_PORT", // 9: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 10: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 11: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 12: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 13: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 14: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 15: TC B0 Interrupt + "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller + "SPI0_INT", // 18: SPI 0 Interrupt + "USART0_RXC", // 19: USART 0 Receive Complete + "USART0_DRE", // 20: USART 0 Data Register Empty + "USART0_TXC", // 21: USART 0 Transmit Complete + "PORTD_PORT", // 22: Interrupt PORT D + "PORTC_PORT", // 23: Interrupt PORT C + "PORTF_PORT", // 24: Interrupt PORT F + "NVMCTRL_NVMREADY", // 25: NVM Ready + "USART1_RXC", // 26: USART 1 Receive Complete + "USART1_DRE", // 27: USART 1 Data Register Empty + "USART1_TXC", // 28: USART 1 Transmit Complete + "TCB1_INT", // 29: TC B1 Interrupt + "AC0_AC", // 30: AC0 AC Interrupt + "ADC0_ERROR", // 31: ADC 0 Error + "ADC0_RESRDY", // 32: ADC 0 Result Ready + "ADC0_SAMPRDY", // 33: ADC 0 Sample Ready +}; + +// AVR16EA28 AVR16EA32 AVR32EA28 AVR32EA32 AVR64EA28 AVR64EA32 +const char * const vtab_avr16ea28[vts_avr16ea28] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "RTC_CNT", // 4: RTC Counter Interrupt + "RTC_PIT", // 5: RTC Periodic Interrupt Timer + "CCL_CCL", // 6: Configurable Custom Logic + "PORTA_PORT", // 7: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller + "SPI0_INT", // 17: SPI 0 Interrupt + "USART0_RXC", // 18: USART 0 Receive Complete + "USART0_DRE", // 19: USART 0 Data Register Empty + "USART0_TXC", // 20: USART 0 Transmit Complete + "PORTD_PORT", // 21: Interrupt PORT D + "AC0_AC", // 22: AC0 AC Interrupt + "ADC0_ERROR", // 23: ADC 0 Error + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready + "AC1_AC", // 26: AC1 AC Interrupt + "PORTC_PORT", // 27: Interrupt PORT C + "TCB2_INT", // 28: TC B2 Interrupt + "USART1_RXC", // 29: USART 1 Receive Complete + "USART1_DRE", // 30: USART 1 Data Register Empty + "USART1_TXC", // 31: USART 1 Transmit Complete + "PORTF_PORT", // 32: Interrupt PORT F + "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready + "USART2_RXC", // 34: USART 2 Receive Complete + "USART2_DRE", // 35: USART 2 Data Register Empty + "USART2_TXC", // 36: USART 2 Transmit Complete + "TCB3_INT", // 37: TC B3 Interrupt + "TCA1_LUNF/TCA1_OVF", // 38: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 39: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 40: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 41: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 42: TC A1 Compare 2/TC A1 Low Compare 2 +}; + +// AVR16EA48 AVR32EA48 AVR64EA48 +const char * const vtab_avr16ea48[vts_avr16ea48] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CLKCTRL_CFD", // 3: Clock Failure Detection + "RTC_CNT", // 4: RTC Counter Interrupt + "RTC_PIT", // 5: RTC Periodic Interrupt Timer + "CCL_CCL", // 6: Configurable Custom Logic + "PORTA_PORT", // 7: Interrupt PORT A + "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow + "TCA0_HUNF", // 9: TC A0 High Underflow + "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 + "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 + "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller + "SPI0_INT", // 17: SPI 0 Interrupt + "USART0_RXC", // 18: USART 0 Receive Complete + "USART0_DRE", // 19: USART 0 Data Register Empty + "USART0_TXC", // 20: USART 0 Transmit Complete + "PORTD_PORT", // 21: Interrupt PORT D + "AC0_AC", // 22: AC0 AC Interrupt + "ADC0_ERROR", // 23: ADC 0 Error + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready + "AC1_AC", // 26: AC1 AC Interrupt + "PORTC_PORT", // 27: Interrupt PORT C + "TCB2_INT", // 28: TC B2 Interrupt + "USART1_RXC", // 29: USART 1 Receive Complete + "USART1_DRE", // 30: USART 1 Data Register Empty + "USART1_TXC", // 31: USART 1 Transmit Complete + "PORTF_PORT", // 32: Interrupt PORT F + "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready + "USART2_RXC", // 34: USART 2 Receive Complete + "USART2_DRE", // 35: USART 2 Data Register Empty + "USART2_TXC", // 36: USART 2 Transmit Complete + "TCB3_INT", // 37: TC B3 Interrupt + "TCA1_LUNF/TCA1_OVF", // 38: TC A1 Low Underflow/TC A1 Overflow + "TCA1_HUNF", // 39: TC A1 High Underflow + "TCA1_CMP0/TCA1_LCMP0", // 40: TC A1 Compare 0/TC A1 Low Compare 0 + "TCA1_CMP1/TCA1_LCMP1", // 41: TC A1 Compare 1/TC A1 Low Compare 1 + "TCA1_CMP2/TCA1_LCMP2", // 42: TC A1 Compare 2/TC A1 Low Compare 2 + "PORTE_PORT", // 43: Interrupt PORT E + "PORTB_PORT", // 44: Interrupt PORT B +}; + +// AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 +const char * const vtab_avr16eb14[vts_avr16eb14] = { "RESET", // 0: Reset (various reasons) "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor @@ -7837,6 +8571,74 @@ const char * const vtab_avr16eb32[vts_avr16eb32] = { "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 30: NVM EEPROM Ready/NVM Flash Ready/NVM Ready }; +// AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 +const char * const vtab_avr32eb14[vts_avr32eb14] = { + "RESET", // 0: Reset (various reasons) + "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "RTC_CNT", // 3: RTC Counter Interrupt + "RTC_PIT", // 4: RTC Periodic Interrupt Timer + "CCL_CCL", // 5: Configurable Custom Logic + "PORTA_PORT", // 6: Interrupt PORT A + "WEX0_FAULTDET/WEX0_FDFEVA/WEX0_FDFEVB/WEX0_FDFEVC", // 7: Waveform Extention 0 Fault Detection/Waveform Extention 0 Fault Detection on Event Input A/Waveform Extention 0 Fault Detection on Event Input B/Waveform Extention 0 Fault Detection on Event Input C + "TCE0_OVF", // 8: TC E0 Overflow + "TCE0_CMP0", // 9: TC E0 Compare 0 + "TCE0_CMP1", // 10: TC E0 Compare 1 + "TCE0_CMP2", // 11: TC E0 Compare 2 + "TCE0_CMP3", // 12: TC E0 Compare 3 + "TCB0_INT", // 13: TC B0 Interrupt + "TCB1_INT", // 14: TC B1 Interrupt + "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller + "SPI0_INT", // 17: SPI 0 Interrupt + "USART0_RXC", // 18: USART 0 Receive Complete + "USART0_DRE", // 19: USART 0 Data Register Empty + "USART0_TXC", // 20: USART 0 Transmit Complete + "PORTD_PORT", // 21: Interrupt PORT D + "TCF0_INT", // 22: TC F0 Interrupt + "AC0_AC", // 23: AC0 AC Interrupt + "ADC0_ERROR", // 24: ADC 0 Error + "ADC0_RESRDY", // 25: ADC 0 Result Ready + "ADC0_SAMPRDY", // 26: ADC 0 Sample Ready + "AC1_AC", // 27: AC1 AC Interrupt + "PORTC_PORT", // 28: Interrupt PORT C + "PORTF_PORT", // 29: Interrupt PORT F + "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 30: NVM EEPROM Ready/NVM Flash Ready/NVM Ready +}; + +// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 +const char * const vtab_avr16la14[vts_avr16la14] = { + "RESET", // 0: Reset (various reasons) + "CPU_CRCSCAN_NMI", // 1: Non-Maskable Interrupt from CRCSCAN + "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor + "CRCSCAN_INT", // 3: Scan Period Done Interrupt from CRCSCAN + "RTC_CNT", // 4: RTC Counter Interrupt + "RTC_PIT", // 5: RTC Periodic Interrupt Timer + "CCL_CCL", // 6: Configurable Custom Logic + "PORTA_PORT", // 7: Interrupt PORT A + "TCE0_OVF", // 8: TC E0 Overflow + "TCE0_CMP0", // 9: TC E0 Compare 0 + "TCE0_CMP1", // 10: TC E0 Compare 1 + "TCE0_CMP2", // 11: TC E0 Compare 2 + "TCB0_INT", // 12: TC B0 Interrupt + "TCB1_INT", // 13: TC B1 Interrupt + "TWI0_TWIP", // 14: 2-Wire Interface 0 Peripheral + "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller + "SPI0_INT", // 16: SPI 0 Interrupt + "USART0_ERROR", // 17: USART 0 Error + "USART0_RXC", // 18: USART 0 Receive Complete + "USART0_DRE", // 19: USART 0 Data Register Empty + "USART0_TXC", // 20: USART 0 Transmit Complete + "PORTD_PORT", // 21: Interrupt PORT D + "AC0_INT", // 22: AC0 Interrupt + "ADC0_ERROR", // 23: ADC 0 Error + "ADC0_RESRDY", // 24: ADC 0 Result Ready + "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready + "PORTC_PORT", // 26: Interrupt PORT C + "PORTF_PORT", // 27: Interrupt PORT F + "NVMCTRL_NVMREADY", // 28: NVM Ready +}; + // AVR32SD20 const char * const vtab_avr32sd20[vts_avr32sd20] = { "RESET", // 0: Reset (various reasons) @@ -7949,74 +8751,6 @@ const char * const vtab_avr32sd28[vts_avr32sd28] = { "USART2_TXC", // 53: USART 2 Transmit Complete }; -// AVR32EB32 AVR32EB28 AVR32EB20 AVR32EB14 -const char * const vtab_avr32eb32[vts_avr32eb32] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "RTC_CNT", // 3: RTC Counter Interrupt - "RTC_PIT", // 4: RTC Periodic Interrupt Timer - "CCL_CCL", // 5: Configurable Custom Logic - "PORTA_PORT", // 6: Interrupt PORT A - "WEX0_FAULTDET/WEX0_FDFEVA/WEX0_FDFEVB/WEX0_FDFEVC", // 7: Waveform Extention 0 Fault Detection/Waveform Extention 0 Fault Detection on Event Input A/Waveform Extention 0 Fault Detection on Event Input B/Waveform Extention 0 Fault Detection on Event Input C - "TCE0_OVF", // 8: TC E0 Overflow - "TCE0_CMP0", // 9: TC E0 Compare 0 - "TCE0_CMP1", // 10: TC E0 Compare 1 - "TCE0_CMP2", // 11: TC E0 Compare 2 - "TCE0_CMP3", // 12: TC E0 Compare 3 - "TCB0_INT", // 13: TC B0 Interrupt - "TCB1_INT", // 14: TC B1 Interrupt - "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller - "SPI0_INT", // 17: SPI 0 Interrupt - "USART0_RXC", // 18: USART 0 Receive Complete - "USART0_DRE", // 19: USART 0 Data Register Empty - "USART0_TXC", // 20: USART 0 Transmit Complete - "PORTD_PORT", // 21: Interrupt PORT D - "TCF0_INT", // 22: TC F0 Interrupt - "AC0_AC", // 23: AC0 AC Interrupt - "ADC0_ERROR", // 24: ADC 0 Error - "ADC0_RESRDY", // 25: ADC 0 Result Ready - "ADC0_SAMPRDY", // 26: ADC 0 Sample Ready - "AC1_AC", // 27: AC1 AC Interrupt - "PORTC_PORT", // 28: Interrupt PORT C - "PORTF_PORT", // 29: Interrupt PORT F - "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 30: NVM EEPROM Ready/NVM Flash Ready/NVM Ready -}; - -// AVR32LA32 AVR32LA28 AVR32LA20 AVR32LA14 AVR16LA32 AVR16LA28 AVR16LA20 AVR16LA14 -const char * const vtab_avr32la32[vts_avr32la32] = { - "RESET", // 0: Reset (various reasons) - "CPU_CRCSCAN_NMI", // 1: Non-Maskable Interrupt from CRCSCAN - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CRCSCAN_INT", // 3: Scan Period Done Interrupt from CRCSCAN - "RTC_CNT", // 4: RTC Counter Interrupt - "RTC_PIT", // 5: RTC Periodic Interrupt Timer - "CCL_CCL", // 6: Configurable Custom Logic - "PORTA_PORT", // 7: Interrupt PORT A - "TCE0_OVF", // 8: TC E0 Overflow - "TCE0_CMP0", // 9: TC E0 Compare 0 - "TCE0_CMP1", // 10: TC E0 Compare 1 - "TCE0_CMP2", // 11: TC E0 Compare 2 - "TCB0_INT", // 12: TC B0 Interrupt - "TCB1_INT", // 13: TC B1 Interrupt - "TWI0_TWIP", // 14: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 15: 2-Wire Interface 0 Controller - "SPI0_INT", // 16: SPI 0 Interrupt - "USART0_ERROR", // 17: USART 0 Error - "USART0_RXC", // 18: USART 0 Receive Complete - "USART0_DRE", // 19: USART 0 Data Register Empty - "USART0_TXC", // 20: USART 0 Transmit Complete - "PORTD_PORT", // 21: Interrupt PORT D - "AC0_INT", // 22: AC0 Interrupt - "ADC0_ERROR", // 23: ADC 0 Error - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready - "PORTC_PORT", // 26: Interrupt PORT C - "PORTF_PORT", // 27: Interrupt PORT F - "NVMCTRL_NVMREADY", // 28: NVM Ready -}; - // AVR32SD32 const char * const vtab_avr32sd32[vts_avr32sd32] = { "RESET", // 0: Reset (various reasons) @@ -8077,921 +8811,649 @@ const char * const vtab_avr32sd32[vts_avr32sd32] = { "TWI1_TWIM", // 55: 2-Wire Interface 1 Controller }; -// AVR32DA48S AVR32DA48 -const char * const vtab_avr32da48s[vts_avr32da48s] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "RTC_CNT", // 3: RTC Counter Interrupt - "RTC_PIT", // 4: RTC Periodic Interrupt Timer - "CCL_CCL", // 5: Configurable Custom Logic - "PORTA_PORT", // 6: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 8: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 12: TC B0 Interrupt - "TCB1_INT", // 13: TC B1 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller - "SPI0_INT", // 18: SPI 0 Interrupt - "USART0_RXC", // 19: USART 0 Receive Complete - "USART0_DRE", // 20: USART 0 Data Register Empty - "USART0_TXC", // 21: USART 0 Transmit Complete - "PORTD_PORT", // 22: Interrupt PORT D - "AC0_AC", // 23: AC0 AC Interrupt - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_WCMP", // 25: ADC 0 Window Comparator - "ZCD0_ZCD", // 26: Zero Cross Detect 0 - "PTC_PTC", // 27: PTC Interrupt - "AC1_AC", // 28: AC1 AC Interrupt - "PORTC_PORT", // 29: Interrupt PORT C - "TCB2_INT", // 30: TC B2 Interrupt - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM - "SPI1_INT", // 36: SPI 1 Interrupt - "USART2_RXC", // 37: USART 2 Receive Complete - "USART2_DRE", // 38: USART 2 Data Register Empty - "USART2_TXC", // 39: USART 2 Transmit Complete - "AC2_AC", // 40: AC2 AC Interrupt - "TCB3_INT", // 41: TC B3 Interrupt - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller - "PORTB_PORT", // 44: Interrupt PORT B - "PORTE_PORT", // 45: Interrupt PORT E - "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 47: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 - "ZCD1_ZCD", // 51: Zero Cross Detect 1 - "USART3_RXC", // 52: USART 3 Receive Complete - "USART3_DRE", // 53: USART 3 Data Register Empty - "USART3_TXC", // 54: USART 3 Transmit Complete - "USART4_RXC", // 55: USART 4 Receive Complete - "USART4_DRE", // 56: USART 4 Data Register Empty - "USART4_TXC", // 57: USART 4 Transmit Complete - "UNUSED", // 58: not implemented on this device - "UNUSED", // 59: not implemented on this device - "TCB4_INT", // 60: TC B4 Interrupt -}; - -// AVR64DD20 AVR64DD14 AVR32DD20 AVR32DD14 AVR16DD20 AVR16DD14 -const char * const vtab_avr64dd20[vts_avr64dd20] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "MVIO_MVIO", // 4: Multi-Voltage I/O - "RTC_CNT", // 5: RTC Counter Interrupt - "RTC_PIT", // 6: RTC Periodic Interrupt Timer - "CCL_CCL", // 7: Configurable Custom Logic - "PORTA_PORT", // 8: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 10: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 14: TC B0 Interrupt - "TCB1_INT", // 15: TC B1 Interrupt - "TCD0_OVF", // 16: TC D0 Overflow - "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller - "SPI0_INT", // 20: SPI 0 Interrupt - "USART0_RXC", // 21: USART 0 Receive Complete - "USART0_DRE", // 22: USART 0 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "PORTD_PORT", // 24: Interrupt PORT D - "AC0_AC", // 25: AC0 AC Interrupt - "ADC0_RESRDY", // 26: ADC 0 Result Ready - "ADC0_WCMP", // 27: ADC 0 Window Comparator - "ZCD3_ZCD", // 28: Zero Cross Detect 3 - "PORTC_PORT", // 29: Interrupt PORT C - "UNUSED", // 30: not implemented on this device - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM -}; - -// AVR64DD32 AVR64DD28 AVR32DD32 AVR32DD28 AVR16DD32 AVR16DD28 -const char * const vtab_avr64dd32[vts_avr64dd32] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "MVIO_MVIO", // 4: Multi-Voltage I/O - "RTC_CNT", // 5: RTC Counter Interrupt - "RTC_PIT", // 6: RTC Periodic Interrupt Timer - "CCL_CCL", // 7: Configurable Custom Logic - "PORTA_PORT", // 8: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 10: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 14: TC B0 Interrupt - "TCB1_INT", // 15: TC B1 Interrupt - "TCD0_OVF", // 16: TC D0 Overflow - "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller - "SPI0_INT", // 20: SPI 0 Interrupt - "USART0_RXC", // 21: USART 0 Receive Complete - "USART0_DRE", // 22: USART 0 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "PORTD_PORT", // 24: Interrupt PORT D - "AC0_AC", // 25: AC0 AC Interrupt - "ADC0_RESRDY", // 26: ADC 0 Result Ready - "ADC0_WCMP", // 27: ADC 0 Window Comparator - "ZCD3_ZCD", // 28: Zero Cross Detect 3 - "PORTC_PORT", // 29: Interrupt PORT C - "TCB2_INT", // 30: TC B2 Interrupt - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM -}; - -/* - * AVR64DU32 AVR64DU28 AVR32DU32 AVR32DU28 AVR32DU20 AVR32DU14 AVR16DU32 AVR16DU28 AVR16DU20 - * AVR16DU14 - */ -const char * const vtab_avr64du32[vts_avr64du32] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "RTC_CNT", // 4: RTC Counter Interrupt - "RTC_PIT", // 5: RTC Periodic Interrupt Timer - "CCL_CCL", // 6: Configurable Custom Logic - "USB0_BUSEVENT", // 7: USB 0 Bus Event - "USB0_TRNCOMPL", // 8: USB 0 Transaction Complete - "PORTA_PORT", // 9: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 10: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 11: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 12: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 13: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 14: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 15: TC B0 Interrupt - "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller - "SPI0_INT", // 18: SPI 0 Interrupt - "USART0_RXC", // 19: USART 0 Receive Complete - "USART0_DRE", // 20: USART 0 Data Register Empty - "USART0_TXC", // 21: USART 0 Transmit Complete - "PORTD_PORT", // 22: Interrupt PORT D - "PORTC_PORT", // 23: Interrupt PORT C - "PORTF_PORT", // 24: Interrupt PORT F - "NVMCTRL_NVMREADY", // 25: NVM Ready - "USART1_RXC", // 26: USART 1 Receive Complete - "USART1_DRE", // 27: USART 1 Data Register Empty - "USART1_TXC", // 28: USART 1 Transmit Complete - "TCB1_INT", // 29: TC B1 Interrupt - "AC0_AC", // 30: AC0 AC Interrupt - "ADC0_ERROR", // 31: ADC 0 Error - "ADC0_RESRDY", // 32: ADC 0 Result Ready - "ADC0_SAMPRDY", // 33: ADC 0 Sample Ready -}; - -// AVR64EA32 AVR64EA28 AVR32EA32 AVR32EA28 AVR16EA32 AVR16EA28 -const char * const vtab_avr64ea32[vts_avr64ea32] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "RTC_CNT", // 4: RTC Counter Interrupt - "RTC_PIT", // 5: RTC Periodic Interrupt Timer - "CCL_CCL", // 6: Configurable Custom Logic - "PORTA_PORT", // 7: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 9: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 13: TC B0 Interrupt - "TCB1_INT", // 14: TC B1 Interrupt - "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller - "SPI0_INT", // 17: SPI 0 Interrupt - "USART0_RXC", // 18: USART 0 Receive Complete - "USART0_DRE", // 19: USART 0 Data Register Empty - "USART0_TXC", // 20: USART 0 Transmit Complete - "PORTD_PORT", // 21: Interrupt PORT D - "AC0_AC", // 22: AC0 AC Interrupt - "ADC0_ERROR", // 23: ADC 0 Error - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready - "AC1_AC", // 26: AC1 AC Interrupt - "PORTC_PORT", // 27: Interrupt PORT C - "TCB2_INT", // 28: TC B2 Interrupt - "USART1_RXC", // 29: USART 1 Receive Complete - "USART1_DRE", // 30: USART 1 Data Register Empty - "USART1_TXC", // 31: USART 1 Transmit Complete - "PORTF_PORT", // 32: Interrupt PORT F - "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready - "USART2_RXC", // 34: USART 2 Receive Complete - "USART2_DRE", // 35: USART 2 Data Register Empty - "USART2_TXC", // 36: USART 2 Transmit Complete - "TCB3_INT", // 37: TC B3 Interrupt - "TCA1_LUNF/TCA1_OVF", // 38: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 39: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 40: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 41: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 42: TC A1 Compare 2/TC A1 Low Compare 2 -}; - -// AVR64EA48 AVR32EA48 AVR16EA48 -const char * const vtab_avr64ea48[vts_avr64ea48] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "RTC_CNT", // 4: RTC Counter Interrupt - "RTC_PIT", // 5: RTC Periodic Interrupt Timer - "CCL_CCL", // 6: Configurable Custom Logic - "PORTA_PORT", // 7: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 8: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 9: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 10: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 11: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 12: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 13: TC B0 Interrupt - "TCB1_INT", // 14: TC B1 Interrupt - "TWI0_TWIP", // 15: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 16: 2-Wire Interface 0 Controller - "SPI0_INT", // 17: SPI 0 Interrupt - "USART0_RXC", // 18: USART 0 Receive Complete - "USART0_DRE", // 19: USART 0 Data Register Empty - "USART0_TXC", // 20: USART 0 Transmit Complete - "PORTD_PORT", // 21: Interrupt PORT D - "AC0_AC", // 22: AC0 AC Interrupt - "ADC0_ERROR", // 23: ADC 0 Error - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_SAMPRDY", // 25: ADC 0 Sample Ready - "AC1_AC", // 26: AC1 AC Interrupt - "PORTC_PORT", // 27: Interrupt PORT C - "TCB2_INT", // 28: TC B2 Interrupt - "USART1_RXC", // 29: USART 1 Receive Complete - "USART1_DRE", // 30: USART 1 Data Register Empty - "USART1_TXC", // 31: USART 1 Transmit Complete - "PORTF_PORT", // 32: Interrupt PORT F - "NVMCTRL_EEREADY/NVMCTRL_FLREADY/NVMCTRL_NVMREADY", // 33: NVM EEPROM Ready/NVM Flash Ready/NVM Ready - "USART2_RXC", // 34: USART 2 Receive Complete - "USART2_DRE", // 35: USART 2 Data Register Empty - "USART2_TXC", // 36: USART 2 Transmit Complete - "TCB3_INT", // 37: TC B3 Interrupt - "TCA1_LUNF/TCA1_OVF", // 38: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 39: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 40: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 41: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 42: TC A1 Compare 2/TC A1 Low Compare 2 - "PORTE_PORT", // 43: Interrupt PORT E - "PORTB_PORT", // 44: Interrupt PORT B -}; - -// AVR128DA28S AVR128DA28 AVR64DA28S AVR64DA28 AVR32DA28S AVR32DA28 -const char * const vtab_avr128da28s[vts_avr128da28s] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "RTC_CNT", // 3: RTC Counter Interrupt - "RTC_PIT", // 4: RTC Periodic Interrupt Timer - "CCL_CCL", // 5: Configurable Custom Logic - "PORTA_PORT", // 6: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 8: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 12: TC B0 Interrupt - "TCB1_INT", // 13: TC B1 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller - "SPI0_INT", // 18: SPI 0 Interrupt - "USART0_RXC", // 19: USART 0 Receive Complete - "USART0_DRE", // 20: USART 0 Data Register Empty - "USART0_TXC", // 21: USART 0 Transmit Complete - "PORTD_PORT", // 22: Interrupt PORT D - "AC0_AC", // 23: AC0 AC Interrupt - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_WCMP", // 25: ADC 0 Window Comparator - "ZCD0_ZCD", // 26: Zero Cross Detect 0 - "PTC_PTC", // 27: PTC Interrupt - "AC1_AC", // 28: AC1 AC Interrupt - "PORTC_PORT", // 29: Interrupt PORT C - "TCB2_INT", // 30: TC B2 Interrupt - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM - "SPI1_INT", // 36: SPI 1 Interrupt - "USART2_RXC", // 37: USART 2 Receive Complete - "USART2_DRE", // 38: USART 2 Data Register Empty - "USART2_TXC", // 39: USART 2 Transmit Complete - "AC2_AC", // 40: AC2 AC Interrupt -}; - -// AVR128DB28 AVR64DB28 AVR32DB28 -const char * const vtab_avr128db28[vts_avr128db28] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "MVIO_MVIO", // 4: Multi-Voltage I/O - "RTC_CNT", // 5: RTC Counter Interrupt - "RTC_PIT", // 6: RTC Periodic Interrupt Timer - "CCL_CCL", // 7: Configurable Custom Logic - "PORTA_PORT", // 8: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 10: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 14: TC B0 Interrupt - "TCB1_INT", // 15: TC B1 Interrupt - "TCD0_OVF", // 16: TC D0 Overflow - "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller - "SPI0_INT", // 20: SPI 0 Interrupt - "USART0_RXC", // 21: USART 0 Receive Complete - "USART0_DRE", // 22: USART 0 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "PORTD_PORT", // 24: Interrupt PORT D - "AC0_AC", // 25: AC0 AC Interrupt - "ADC0_RESRDY", // 26: ADC 0 Result Ready - "ADC0_WCMP", // 27: ADC 0 Window Comparator - "ZCD0_ZCD", // 28: Zero Cross Detect 0 - "AC1_AC", // 29: AC1 AC Interrupt - "PORTC_PORT", // 30: Interrupt PORT C - "TCB2_INT", // 31: TC B2 Interrupt - "USART1_RXC", // 32: USART 1 Receive Complete - "USART1_DRE", // 33: USART 1 Data Register Empty - "USART1_TXC", // 34: USART 1 Transmit Complete - "PORTF_PORT", // 35: Interrupt PORT F - "NVMCTRL_EE", // 36: NVM EEPROM - "SPI1_INT", // 37: SPI 1 Interrupt - "USART2_RXC", // 38: USART 2 Receive Complete - "USART2_DRE", // 39: USART 2 Data Register Empty - "USART2_TXC", // 40: USART 2 Transmit Complete - "AC2_AC", // 41: AC2 AC Interrupt -}; - -// AVR128DA32S AVR128DA32 AVR64DA32S AVR64DA32 AVR32DA32S AVR32DA32 -const char * const vtab_avr128da32s[vts_avr128da32s] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "RTC_CNT", // 3: RTC Counter Interrupt - "RTC_PIT", // 4: RTC Periodic Interrupt Timer - "CCL_CCL", // 5: Configurable Custom Logic - "PORTA_PORT", // 6: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 8: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 12: TC B0 Interrupt - "TCB1_INT", // 13: TC B1 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller - "SPI0_INT", // 18: SPI 0 Interrupt - "USART0_RXC", // 19: USART 0 Receive Complete - "USART0_DRE", // 20: USART 0 Data Register Empty - "USART0_TXC", // 21: USART 0 Transmit Complete - "PORTD_PORT", // 22: Interrupt PORT D - "AC0_AC", // 23: AC0 AC Interrupt - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_WCMP", // 25: ADC 0 Window Comparator - "ZCD0_ZCD", // 26: Zero Cross Detect 0 - "PTC_PTC", // 27: PTC Interrupt - "AC1_AC", // 28: AC1 AC Interrupt - "PORTC_PORT", // 29: Interrupt PORT C - "TCB2_INT", // 30: TC B2 Interrupt - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM - "SPI1_INT", // 36: SPI 1 Interrupt - "USART2_RXC", // 37: USART 2 Receive Complete - "USART2_DRE", // 38: USART 2 Data Register Empty - "USART2_TXC", // 39: USART 2 Transmit Complete - "AC2_AC", // 40: AC2 AC Interrupt - "UNUSED", // 41: not implemented on this device - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller -}; - -// AVR128DB32 AVR64DB32 AVR32DB32 -const char * const vtab_avr128db32[vts_avr128db32] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "MVIO_MVIO", // 4: Multi-Voltage I/O - "RTC_CNT", // 5: RTC Counter Interrupt - "RTC_PIT", // 6: RTC Periodic Interrupt Timer - "CCL_CCL", // 7: Configurable Custom Logic - "PORTA_PORT", // 8: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 10: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 14: TC B0 Interrupt - "TCB1_INT", // 15: TC B1 Interrupt - "TCD0_OVF", // 16: TC D0 Overflow - "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller - "SPI0_INT", // 20: SPI 0 Interrupt - "USART0_RXC", // 21: USART 0 Receive Complete - "USART0_DRE", // 22: USART 0 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "PORTD_PORT", // 24: Interrupt PORT D - "AC0_AC", // 25: AC0 AC Interrupt - "ADC0_RESRDY", // 26: ADC 0 Result Ready - "ADC0_WCMP", // 27: ADC 0 Window Comparator - "ZCD0_ZCD", // 28: Zero Cross Detect 0 - "AC1_AC", // 29: AC1 AC Interrupt - "PORTC_PORT", // 30: Interrupt PORT C - "TCB2_INT", // 31: TC B2 Interrupt - "USART1_RXC", // 32: USART 1 Receive Complete - "USART1_DRE", // 33: USART 1 Data Register Empty - "USART1_TXC", // 34: USART 1 Transmit Complete - "PORTF_PORT", // 35: Interrupt PORT F - "NVMCTRL_EE", // 36: NVM EEPROM - "SPI1_INT", // 37: SPI 1 Interrupt - "USART2_RXC", // 38: USART 2 Receive Complete - "USART2_DRE", // 39: USART 2 Data Register Empty - "USART2_TXC", // 40: USART 2 Transmit Complete - "AC2_AC", // 41: AC2 AC Interrupt - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller -}; - -// AVR128DA48S AVR128DA48 AVR64DA48S AVR64DA48 -const char * const vtab_avr128da48s[vts_avr128da48s] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "RTC_CNT", // 3: RTC Counter Interrupt - "RTC_PIT", // 4: RTC Periodic Interrupt Timer - "CCL_CCL", // 5: Configurable Custom Logic - "PORTA_PORT", // 6: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 8: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 12: TC B0 Interrupt - "TCB1_INT", // 13: TC B1 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller - "SPI0_INT", // 18: SPI 0 Interrupt - "USART0_RXC", // 19: USART 0 Receive Complete - "USART0_DRE", // 20: USART 0 Data Register Empty - "USART0_TXC", // 21: USART 0 Transmit Complete - "PORTD_PORT", // 22: Interrupt PORT D - "AC0_AC", // 23: AC0 AC Interrupt - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_WCMP", // 25: ADC 0 Window Comparator - "ZCD0_ZCD", // 26: Zero Cross Detect 0 - "PTC_PTC", // 27: PTC Interrupt - "AC1_AC", // 28: AC1 AC Interrupt - "PORTC_PORT", // 29: Interrupt PORT C - "TCB2_INT", // 30: TC B2 Interrupt - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM - "SPI1_INT", // 36: SPI 1 Interrupt - "USART2_RXC", // 37: USART 2 Receive Complete - "USART2_DRE", // 38: USART 2 Data Register Empty - "USART2_TXC", // 39: USART 2 Transmit Complete - "AC2_AC", // 40: AC2 AC Interrupt - "TCB3_INT", // 41: TC B3 Interrupt - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller - "PORTB_PORT", // 44: Interrupt PORT B - "PORTE_PORT", // 45: Interrupt PORT E - "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 47: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 - "ZCD1_ZCD", // 51: Zero Cross Detect 1 - "USART3_RXC", // 52: USART 3 Receive Complete - "USART3_DRE", // 53: USART 3 Data Register Empty - "USART3_TXC", // 54: USART 3 Transmit Complete - "USART4_RXC", // 55: USART 4 Receive Complete - "USART4_DRE", // 56: USART 4 Data Register Empty - "USART4_TXC", // 57: USART 4 Transmit Complete -}; - -// AVR128DB48 AVR64DB48 AVR32DB48 -const char * const vtab_avr128db48[vts_avr128db48] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "MVIO_MVIO", // 4: Multi-Voltage I/O - "RTC_CNT", // 5: RTC Counter Interrupt - "RTC_PIT", // 6: RTC Periodic Interrupt Timer - "CCL_CCL", // 7: Configurable Custom Logic - "PORTA_PORT", // 8: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 10: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 14: TC B0 Interrupt - "TCB1_INT", // 15: TC B1 Interrupt - "TCD0_OVF", // 16: TC D0 Overflow - "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller - "SPI0_INT", // 20: SPI 0 Interrupt - "USART0_RXC", // 21: USART 0 Receive Complete - "USART0_DRE", // 22: USART 0 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "PORTD_PORT", // 24: Interrupt PORT D - "AC0_AC", // 25: AC0 AC Interrupt - "ADC0_RESRDY", // 26: ADC 0 Result Ready - "ADC0_WCMP", // 27: ADC 0 Window Comparator - "ZCD0_ZCD", // 28: Zero Cross Detect 0 - "AC1_AC", // 29: AC1 AC Interrupt - "PORTC_PORT", // 30: Interrupt PORT C - "TCB2_INT", // 31: TC B2 Interrupt - "USART1_RXC", // 32: USART 1 Receive Complete - "USART1_DRE", // 33: USART 1 Data Register Empty - "USART1_TXC", // 34: USART 1 Transmit Complete - "PORTF_PORT", // 35: Interrupt PORT F - "NVMCTRL_EE", // 36: NVM EEPROM - "SPI1_INT", // 37: SPI 1 Interrupt - "USART2_RXC", // 38: USART 2 Receive Complete - "USART2_DRE", // 39: USART 2 Data Register Empty - "USART2_TXC", // 40: USART 2 Transmit Complete - "AC2_AC", // 41: AC2 AC Interrupt - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller - "TCB3_INT", // 44: TC B3 Interrupt - "PORTB_PORT", // 45: Interrupt PORT B - "PORTE_PORT", // 46: Interrupt PORT E - "TCA1_LUNF/TCA1_OVF", // 47: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 48: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 49: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 50: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 51: TC A1 Compare 2/TC A1 Low Compare 2 - "ZCD1_ZCD", // 52: Zero Cross Detect 1 - "USART3_RXC", // 53: USART 3 Receive Complete - "USART3_DRE", // 54: USART 3 Data Register Empty - "USART3_TXC", // 55: USART 3 Transmit Complete - "USART4_RXC", // 56: USART 4 Receive Complete - "USART4_DRE", // 57: USART 4 Data Register Empty - "USART4_TXC", // 58: USART 4 Transmit Complete - "UNUSED", // 59: not implemented on this device - "ZCD2_ZCD", // 60: Zero Cross Detect 2 -}; - -// AVR128DA64S AVR128DA64 AVR64DA64S AVR64DA64 -const char * const vtab_avr128da64s[vts_avr128da64s] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "RTC_CNT", // 3: RTC Counter Interrupt - "RTC_PIT", // 4: RTC Periodic Interrupt Timer - "CCL_CCL", // 5: Configurable Custom Logic - "PORTA_PORT", // 6: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 7: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 8: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 9: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 10: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 11: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 12: TC B0 Interrupt - "TCB1_INT", // 13: TC B1 Interrupt - "TCD0_OVF", // 14: TC D0 Overflow - "TCD0_TRIG", // 15: TC D0 Trigger - "TWI0_TWIP", // 16: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 17: 2-Wire Interface 0 Controller - "SPI0_INT", // 18: SPI 0 Interrupt - "USART0_RXC", // 19: USART 0 Receive Complete - "USART0_DRE", // 20: USART 0 Data Register Empty - "USART0_TXC", // 21: USART 0 Transmit Complete - "PORTD_PORT", // 22: Interrupt PORT D - "AC0_AC", // 23: AC0 AC Interrupt - "ADC0_RESRDY", // 24: ADC 0 Result Ready - "ADC0_WCMP", // 25: ADC 0 Window Comparator - "ZCD0_ZCD", // 26: Zero Cross Detect 0 - "PTC_PTC", // 27: PTC Interrupt - "AC1_AC", // 28: AC1 AC Interrupt - "PORTC_PORT", // 29: Interrupt PORT C - "TCB2_INT", // 30: TC B2 Interrupt - "USART1_RXC", // 31: USART 1 Receive Complete - "USART1_DRE", // 32: USART 1 Data Register Empty - "USART1_TXC", // 33: USART 1 Transmit Complete - "PORTF_PORT", // 34: Interrupt PORT F - "NVMCTRL_EE", // 35: NVM EEPROM - "SPI1_INT", // 36: SPI 1 Interrupt - "USART2_RXC", // 37: USART 2 Receive Complete - "USART2_DRE", // 38: USART 2 Data Register Empty - "USART2_TXC", // 39: USART 2 Transmit Complete - "AC2_AC", // 40: AC2 AC Interrupt - "TCB3_INT", // 41: TC B3 Interrupt - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller - "PORTB_PORT", // 44: Interrupt PORT B - "PORTE_PORT", // 45: Interrupt PORT E - "TCA1_LUNF/TCA1_OVF", // 46: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 47: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 48: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 49: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 50: TC A1 Compare 2/TC A1 Low Compare 2 - "ZCD1_ZCD", // 51: Zero Cross Detect 1 - "USART3_RXC", // 52: USART 3 Receive Complete - "USART3_DRE", // 53: USART 3 Data Register Empty - "USART3_TXC", // 54: USART 3 Transmit Complete - "USART4_RXC", // 55: USART 4 Receive Complete - "USART4_DRE", // 56: USART 4 Data Register Empty - "USART4_TXC", // 57: USART 4 Transmit Complete - "PORTG_PORT", // 58: Interrupt PORT G - "ZCD2_ZCD", // 59: Zero Cross Detect 2 - "TCB4_INT", // 60: TC B4 Interrupt - "USART5_RXC", // 61: USART 5 Receive Complete - "USART5_DRE", // 62: USART 5 Data Register Empty - "USART5_TXC", // 63: USART 5 Transmit Complete -}; - -// AVR128DB64 AVR64DB64 -const char * const vtab_avr128db64[vts_avr128db64] = { - "RESET", // 0: Reset (various reasons) - "CRCSCAN_NMI", // 1: CRCSCAN Non-maskable Interrupt - "BOD_VLM", // 2: Brown-out Detector Voltage Level Monitor - "CLKCTRL_CFD", // 3: Clock Failure Detection - "MVIO_MVIO", // 4: Multi-Voltage I/O - "RTC_CNT", // 5: RTC Counter Interrupt - "RTC_PIT", // 6: RTC Periodic Interrupt Timer - "CCL_CCL", // 7: Configurable Custom Logic - "PORTA_PORT", // 8: Interrupt PORT A - "TCA0_LUNF/TCA0_OVF", // 9: TC A0 Low Underflow/TC A0 Overflow - "TCA0_HUNF", // 10: TC A0 High Underflow - "TCA0_CMP0/TCA0_LCMP0", // 11: TC A0 Compare 0/TC A0 Low Compare 0 - "TCA0_CMP1/TCA0_LCMP1", // 12: TC A0 Compare 1/TC A0 Low Compare 1 - "TCA0_CMP2/TCA0_LCMP2", // 13: TC A0 Compare 2/TC A0 Low Compare 2 - "TCB0_INT", // 14: TC B0 Interrupt - "TCB1_INT", // 15: TC B1 Interrupt - "TCD0_OVF", // 16: TC D0 Overflow - "TCD0_TRIG", // 17: TC D0 Trigger - "TWI0_TWIP", // 18: 2-Wire Interface 0 Peripheral - "TWI0_TWIM", // 19: 2-Wire Interface 0 Controller - "SPI0_INT", // 20: SPI 0 Interrupt - "USART0_RXC", // 21: USART 0 Receive Complete - "USART0_DRE", // 22: USART 0 Data Register Empty - "USART0_TXC", // 23: USART 0 Transmit Complete - "PORTD_PORT", // 24: Interrupt PORT D - "AC0_AC", // 25: AC0 AC Interrupt - "ADC0_RESRDY", // 26: ADC 0 Result Ready - "ADC0_WCMP", // 27: ADC 0 Window Comparator - "ZCD0_ZCD", // 28: Zero Cross Detect 0 - "AC1_AC", // 29: AC1 AC Interrupt - "PORTC_PORT", // 30: Interrupt PORT C - "TCB2_INT", // 31: TC B2 Interrupt - "USART1_RXC", // 32: USART 1 Receive Complete - "USART1_DRE", // 33: USART 1 Data Register Empty - "USART1_TXC", // 34: USART 1 Transmit Complete - "PORTF_PORT", // 35: Interrupt PORT F - "NVMCTRL_EE", // 36: NVM EEPROM - "SPI1_INT", // 37: SPI 1 Interrupt - "USART2_RXC", // 38: USART 2 Receive Complete - "USART2_DRE", // 39: USART 2 Data Register Empty - "USART2_TXC", // 40: USART 2 Transmit Complete - "AC2_AC", // 41: AC2 AC Interrupt - "TWI1_TWIP", // 42: 2-Wire Interface 1 Peripheral - "TWI1_TWIM", // 43: 2-Wire Interface 1 Controller - "TCB3_INT", // 44: TC B3 Interrupt - "PORTB_PORT", // 45: Interrupt PORT B - "PORTE_PORT", // 46: Interrupt PORT E - "TCA1_LUNF/TCA1_OVF", // 47: TC A1 Low Underflow/TC A1 Overflow - "TCA1_HUNF", // 48: TC A1 High Underflow - "TCA1_CMP0/TCA1_LCMP0", // 49: TC A1 Compare 0/TC A1 Low Compare 0 - "TCA1_CMP1/TCA1_LCMP1", // 50: TC A1 Compare 1/TC A1 Low Compare 1 - "TCA1_CMP2/TCA1_LCMP2", // 51: TC A1 Compare 2/TC A1 Low Compare 2 - "ZCD1_ZCD", // 52: Zero Cross Detect 1 - "USART3_RXC", // 53: USART 3 Receive Complete - "USART3_DRE", // 54: USART 3 Data Register Empty - "USART3_TXC", // 55: USART 3 Transmit Complete - "USART4_RXC", // 56: USART 4 Receive Complete - "USART4_DRE", // 57: USART 4 Data Register Empty - "USART4_TXC", // 58: USART 4 Transmit Complete - "PORTG_PORT", // 59: Interrupt PORT G - "ZCD2_ZCD", // 60: Zero Cross Detect 2 - "TCB4_INT", // 61: TC B4 Interrupt - "USART5_RXC", // 62: USART 5 Receive Complete - "USART5_DRE", // 63: USART 5 Data Register Empty - "USART5_TXC", // 64: USART 5 Transmit Complete -}; - // Configuration value tables /* - * ATmega328 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA - * ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328P ATA6612C ATA6613C ATA6614Q + * ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 + * ATtiny84A ATtiny441 ATtiny841 */ -static const Configvalue _values_sut_cksel_atmega328[55] = { - {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x03, "intrcosc_128khz_6ck_14ck_0ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x04, "extlofxtal_1kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x05, "extlofxtal_32kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 0 ms"}, - {0x06, "extfsxtal_258ck_14ck_4ms1", "ext full-swing crystal; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x07, "extfsxtal_1kck_14ck_65ms", "ext full-swing crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x08, "extxosc_0mhz4_0mhz9_258ck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x09, "extxosc_0mhz4_0mhz9_1kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0a, "extxosc_0mhz9_3mhz_258ck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0b, "extxosc_0mhz9_3mhz_1kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0c, "extxosc_3mhz_8mhz_258ck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0d, "extxosc_3mhz_8mhz_1kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0e, "extxosc_8mhz_xx_258ck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0f, "extxosc_8mhz_xx_1kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x10, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x12, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x13, "intrcosc_128khz_6ck_14ck_4ms1", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x14, "extlofxtal_1kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x15, "extlofxtal_32kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 4.1 ms"}, - {0x16, "extfsxtal_258ck_14ck_65ms", "ext full-swing crystal; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x17, "extfsxtal_16kck_14ck_0ms", "ext full-swing crystal; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x18, "extxosc_0mhz4_0mhz9_258ck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1a, "extxosc_0mhz9_3mhz_258ck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1c, "extxosc_3mhz_8mhz_258ck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1e, "extxosc_8mhz_xx_258ck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x20, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x22, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x23, "intrcosc_128khz_6ck_14ck_65ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x24, "extlofxtal_1kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x25, "extlofxtal_32kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 65 ms"}, - {0x26, "extfsxtal_1kck_14ck_0ms", "ext full-swing crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x27, "extfsxtal_16kck_14ck_4ms1", "ext full-swing crystal; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x28, "extxosc_0mhz4_0mhz9_1kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2a, "extxosc_0mhz9_3mhz_1kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2c, "extxosc_3mhz_8mhz_1kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2e, "extxosc_8mhz_xx_1kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x36, "extfsxtal_1kck_14ck_4ms1", "ext full-swing crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x37, "extfsxtal_16kck_14ck_65ms", "ext full-swing crystal; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x38, "extxosc_0mhz4_0mhz9_1kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3a, "extxosc_0mhz9_3mhz_1kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3c, "extxosc_3mhz_8mhz_1kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3e, "extxosc_8mhz_xx_1kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, +static const Configvalue _values_rstdisbl_attiny4[2] = { + {0, "gpio_pb3_warning_external_reset_disabled", "reset pin configured as GPIO PB3 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATtiny40 ATtiny1634 ATtiny1634R +static const Configvalue _values_rstdisbl_attiny40[2] = { + {0, "gpio_pc3_warning_external_reset_disabled", "reset pin configured as GPIO PC3 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATtiny102 ATtiny104 ATtiny2313 ATtiny2313A ATtiny4313 +static const Configvalue _values_rstdisbl_attiny102[2] = { + {0, "gpio_pa2_warning_external_reset_disabled", "reset pin configured as GPIO PA2 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, }; /* - * ATmega16M1 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 AT90PWM2B AT90PWM3B - * AT90PWM316 + * AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 + * ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 */ -static const Configvalue _values_sut_cksel_atmega16m1[53] = { - {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x01, "pllclk_pllin_extclk_6kck_14ck_0ms", "PLL clock/4; PLL input: ext clock; startup time PWRDWN/RESET: 6K CK/14 CK + 0 ms"}, - {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x03, "pllclk_16mhz_1kck_14ck_0ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x04, "extxosc_pllin_extxosc_1kck_14ck_0ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x05, "pllclk_pllin_extxosc_1kck_14ck_0ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x08, "extxosc_0mhz4_0mhz9_258ck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x09, "extxosc_0mhz4_0mhz9_1kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0a, "extxosc_0mhz9_3mhz_258ck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0b, "extxosc_0mhz9_3mhz_1kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0c, "extxosc_3mhz_8mhz_258ck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0d, "extxosc_3mhz_8mhz_1kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0e, "extxosc_8mhz_xx_258ck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0f, "extxosc_8mhz_xx_1kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x10, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x11, "pllclk_pllin_extclk_6kck_14ck_4ms", "PLL clock/4; PLL input: ext clock; startup time PWRDWN/RESET: 6K CK/14 CK + 4 ms"}, - {0x12, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x13, "pllclk_16mhz_1kck_14ck_4ms1", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x14, "extxosc_pllin_extxosc_1kck_14ck_4ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 4 ms"}, - {0x15, "pllclk_pllin_extxosc_1kck_14ck_4ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 4 ms"}, - {0x18, "extxosc_0mhz4_0mhz9_258ck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1a, "extxosc_0mhz9_3mhz_258ck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1c, "extxosc_3mhz_8mhz_258ck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1e, "extxosc_8mhz_xx_258ck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x20, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x21, "pllclk_pllin_extclk_6kck_14ck_64ms", "PLL clock/4; PLL input: ext clock; startup time PWRDWN/RESET: 6K CK/14 CK + 64 ms"}, - {0x22, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x23, "pllclk_16mhz_1kck_14ck_65ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x24, "extxosc_pllin_extxosc_16kck_14ck_4ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 4 ms"}, - {0x25, "pllclk_pllin_extxosc_16kck_14ck_4ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 4 ms"}, - {0x28, "extxosc_0mhz4_0mhz9_1kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2a, "extxosc_0mhz9_3mhz_1kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2c, "extxosc_3mhz_8mhz_1kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2e, "extxosc_8mhz_xx_1kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x33, "pllclk_16mhz_16kck_14ck_0ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x34, "extxosc_pllin_extxosc_16kck_14ck_64ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 64 ms"}, - {0x35, "pllclk_pllin_extxosc_16kck_14ck_64ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 64 ms"}, - {0x38, "extxosc_0mhz4_0mhz9_1kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3a, "extxosc_0mhz9_3mhz_1kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3c, "extxosc_3mhz_8mhz_1kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3e, "extxosc_8mhz_xx_1kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, +static const Configvalue _values_rstdisbl_at90pwm1[2] = { + {0, "gpio_pe0_warning_external_reset_disabled", "reset pin configured as GPIO PE0 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, }; -// ATmega328PB ATmega48PB ATmega88PB ATmega168PB ATmega324PB -static const Configvalue _values_sut_cksel_atmega328pb[47] = { - {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x03, "intrcosc_128khz_6ck_14ck_0ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x04, "extlofxtal_1kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x05, "extlofxtal_32kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 0 ms"}, - {0x08, "extxosc_0mhz4_0mhz9_258ck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x09, "extxosc_0mhz4_0mhz9_1kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0a, "extxosc_0mhz9_3mhz_258ck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0b, "extxosc_0mhz9_3mhz_1kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0c, "extxosc_3mhz_8mhz_258ck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0d, "extxosc_3mhz_8mhz_1kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0e, "extxosc_8mhz_xx_258ck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0f, "extxosc_8mhz_xx_1kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x10, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x12, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x13, "intrcosc_128khz_6ck_14ck_4ms1", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x14, "extlofxtal_1kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x15, "extlofxtal_32kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 4.1 ms"}, - {0x18, "extxosc_0mhz4_0mhz9_258ck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1a, "extxosc_0mhz9_3mhz_258ck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1c, "extxosc_3mhz_8mhz_258ck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1e, "extxosc_8mhz_xx_258ck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x20, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x22, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x23, "intrcosc_128khz_6ck_14ck_65ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x24, "extlofxtal_1kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x25, "extlofxtal_32kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 65 ms"}, - {0x28, "extxosc_0mhz4_0mhz9_1kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2a, "extxosc_0mhz9_3mhz_1kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2c, "extxosc_3mhz_8mhz_1kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2e, "extxosc_8mhz_xx_1kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x38, "extxosc_0mhz4_0mhz9_1kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3a, "extxosc_0mhz9_3mhz_1kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3c, "extxosc_3mhz_8mhz_1kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3e, "extxosc_8mhz_xx_1kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, +// AT90USB82 AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 +static const Configvalue _values_rstdisbl_at90usb82[2] = { + {0, "gpio_pc1_warning_external_reset_disabled", "reset pin configured as GPIO PC1 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATtiny11 ATtiny12 ATtiny13 ATtiny13A ATtiny15 ATtiny25 ATtiny45 ATtiny85 +static const Configvalue _values_rstdisbl_attiny11[2] = { + {0, "gpio_pb5_warning_external_reset_disabled", "reset pin configured as GPIO PB5 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATtiny43U +static const Configvalue _values_rstdisbl_attiny43u[2] = { + {0, "gpio_pa7_warning_external_reset_disabled", "reset pin configured as GPIO PA7 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, }; /* - * ATmega8515 ATmega103comp AT90S8535comp ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A - * ATmega64 ATmega64A ATmega128 ATmegaS128 ATmega128A ATmega8535 AT90S8515comp + * ATtiny26 ATtiny87 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A + * ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 */ -static const Configvalue _values_sut_cksel_atmega8515[58] = { +static const Configvalue _values_rstdisbl_attiny26[2] = { + {0, "gpio_pb7_warning_external_reset_disabled", "reset pin configured as GPIO PB7 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +/* + * ATtiny48 ATtiny88 ATmega8 ATmega8A ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A + * ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P + * ATmega48PB ATmega88PB ATmega168PB ATmega328PB ATA6612C ATA6613C ATA6614Q + */ +static const Configvalue _values_rstdisbl_attiny48[2] = { + {0, "gpio_pc6_warning_external_reset_disabled", "reset pin configured as GPIO PC6 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATtiny828 ATtiny828R +static const Configvalue _values_rstdisbl_attiny828[2] = { + {0, "gpio_pd2_warning_external_reset_disabled", "reset pin configured as GPIO PD2 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +/* + * ATmega165 ATmega169 ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 + * ATxmega64A1U ATxmega128A1U ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B + * ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 + * ATxmega64A4 ATxmega128A4 ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 + * ATxmega128B1 ATxmega64B3 ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 + * ATxmega256C3 ATxmega384C3 ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 + * ATxmega192D3 ATxmega256D3 ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 + * ATxmega8E5 ATxmega16E5 ATxmega32E5 + */ +static const Configvalue _values_rstdisbl_atmega165[2] = { + {0, "rst_disabled", "external reset disabled"}, + {1, "rst_enabled", "external reset enabled"}, +}; + +/* + * ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 + * ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A + * ATmega6450P ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P ATmega329PA + * ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6490 + * ATmega6490A ATmega6490P + */ +static const Configvalue _values_rstdisbl_atmega165a[2] = { + {0, "gpio_pg5_warning_external_reset_disabled", "reset pin configured as GPIO PG5 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATA5781 ATA5782 ATA5783 ATA5831 ATA5832 ATA5833 ATA5835 +static const Configvalue _values_rstdisbl_ata5781[2] = { + {0, "gpio_pc0_warning_external_reset_disabled", "reset pin configured as GPIO PC0 (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +// ATA5787 ATA8210 ATA8215 ATA8510 ATA8515 +static const Configvalue _values_rstdisbl_ata5787[2] = { + {0, "gpio_warning_external_reset_disabled", "reset pin configured as GPIO (warning: external reset disabled)"}, + {1, "external_reset", "reset pin configured as external reset"}, +}; + +/* + * ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 ATtiny40 ATtiny102 ATtiny104 AT90S8515comp + * AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B + * AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 + * AT90USB1287 AT90SCR100 AT90SCR100H ATtiny13 ATtiny13A ATtiny43U ATtiny24 ATtiny24A ATtiny44 + * ATtiny44A ATtiny84 ATtiny84A ATtiny25 ATtiny45 ATtiny85 ATtiny87 ATtiny167 ATtiny48 ATtiny88 + * ATtiny828 ATtiny828R ATtiny1634 ATtiny1634R ATtiny441 ATtiny841 ATtiny261 ATtiny261A ATtiny461 + * ATtiny461A ATtiny861 ATtiny861A ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega64 + * ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 + * ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 + * ATmega256RFR2 ATmega8U2 ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161comp + * ATmega1281 ATmega2561 ATmega162 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 + * ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P ATmega48PB ATmega88PB ATmega168PB + * ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P + * ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A ATmega3290P ATmega3290PA + * ATmega6490 ATmega6490A ATmega6490P ATmega103comp ATmega8HVA ATmega16HVA ATmega16HVA2 + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5272 ATA5505 ATA5700M322 ATA5702M322 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 + * ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C + * ATA6613C ATA6614Q ATA6616C ATA6617C ATA664251 ATA8210 ATA8215 ATA8510 ATA8515 + */ +static const Configvalue _values_wdton_attiny4[2] = { + {0, "wdt_always_on", "watchdog timer always on"}, + {1, "wdt_programmable", "watchdog timer programmable"}, +}; + +/* + * ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 + * ATtiny84A ATtiny441 ATtiny841 + */ +static const Configvalue _values_ckout_attiny4[2] = { + {0, "gpio_pb2", "clock output on GPIO PB2"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +// ATtiny40 ATtiny1634 ATtiny1634R +static const Configvalue _values_ckout_attiny40[2] = { + {0, "gpio_pc2", "clock output on GPIO PC2"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * ATtiny102 ATtiny104 AT90SCR100 AT90SCR100H ATmega164A ATmega164P ATmega164PA ATmega324A + * ATmega324P ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P + * ATmega324PB + */ +static const Configvalue _values_ckout_attiny102[2] = { + {0, "gpio_pb1", "clock output on GPIO PB1"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * AT90CAN32 AT90CAN64 AT90CAN128 AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 + * AT90USB1287 ATmega8U2 ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 + */ +static const Configvalue _values_ckout_at90can32[2] = { + {0, "gpio_pc7", "clock output on GPIO PC7"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * AT90PWM1 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 ATmega32C1 ATmega64C1 + * ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 + */ +static const Configvalue _values_ckout_at90pwm1[2] = { + {0, "gpio_pd1", "clock output on GPIO PD1"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +// AT90PWM81 AT90PWM161 +static const Configvalue _values_ckout_at90pwm81[2] = { + {0, "gpio_pd0", "clock output on GPIO PD0"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +// ATtiny43U +static const Configvalue _values_ckout_attiny43u[2] = { + {0, "gpio_pb3", "clock output on GPIO PB3"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +// ATtiny25 ATtiny45 ATtiny85 +static const Configvalue _values_ckout_attiny25[2] = { + {0, "gpio_pb4", "clock output on GPIO PB4"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * ATtiny87 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A ATA5272 + * ATA5505 ATA6616C ATA6617C ATA664251 + */ +static const Configvalue _values_ckout_attiny87[2] = { + {0, "gpio_pb5", "clock output on GPIO PB5"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * ATtiny48 ATtiny88 ATmega161comp ATmega162 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 + * ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P + * ATmega48PB ATmega88PB ATmega168PB ATmega328PB ATA6612C ATA6613C ATA6614Q + */ +static const Configvalue _values_ckout_attiny48[2] = { + {0, "gpio_pb0", "clock output on GPIO PB0"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +// ATtiny828 ATtiny828R ATA6285 ATA6286 ATA6289 +static const Configvalue _values_ckout_attiny828[2] = { + {0, "gpio_pc1", "clock output on GPIO PC1"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +// ATtiny2313 ATtiny2313A ATtiny4313 +static const Configvalue _values_ckout_attiny2313[2] = { + {0, "gpio_pd2", "clock output on GPIO PD2"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * ATmega640 ATmega1280 ATmega2560 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 + * ATmega1281 ATmega2561 ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A + * ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A + * ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P + * ATmega169 ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P ATmega329PA + * ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6490 + * ATmega6490A ATmega6490P + */ +static const Configvalue _values_ckout_atmega640[2] = { + {0, "gpio_pe7", "clock output on GPIO PE7"}, + {1, "co_disabled", "clock signal is not output on a pin"}, +}; + +/* + * ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 ATtiny40 ATtiny102 ATtiny104 AT90S1200 AT90S2313 + * AT90S2323 AT90S2343 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90S8515comp AT90S8535 + * AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B + * AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 + * AT90USB1287 AT90SCR100 AT90SCR100H ATtiny11 ATtiny12 ATtiny22 ATtiny13 ATtiny13A ATtiny43U + * ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A ATtiny15 ATtiny25 ATtiny45 ATtiny85 + * ATtiny26 ATtiny87 ATtiny167 ATtiny28 ATtiny48 ATtiny88 ATtiny828 ATtiny828R ATtiny1634 + * ATtiny1634R ATtiny441 ATtiny841 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A + * ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A + * ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega640 ATmega1280 ATmega2560 ATmega32C1 + * ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 + * ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 + * ATmega161 ATmega161comp ATmega1281 ATmega2561 ATmega162 ATmega163 ATmega323 ATmega164A + * ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644 ATmega644A ATmega644P + * ATmega644PA ATmega1284 ATmega1284P ATmega324PB ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 + * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA + * ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 + * ATmega6450A ATmega6450P ATmega8515 ATmega8535 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 + * ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P + * ATmega48PB ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103 ATmega103comp + * ATmega8HVA ATmega16HVA ATmega16HVA2 ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB + * ATmega64HVE ATmega32HVE2 ATmega64HVE2 ATmega406 ATA5272 ATA5505 ATA5700M322 ATA5702M322 ATA5781 + * ATA5782 ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 + * ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA664251 ATA8210 ATA8215 + * ATA8510 ATA8515 + */ +static const Configvalue _values_lb_attiny4[3] = { + {0, "prog_ver_disabled", "further programming and verification disabled"}, + {2, "prog_disabled", "further programming disabled"}, + {3, "no_lock", "no memory lock features enabled"}, +}; + +// AT90S2333 +static const Configvalue _values_lb_at90s2333[3] = { + {0, "prog_ver_disabled", "further programming and verification disabled"}, + {1, "prog_disabled", "further programming disabled"}, + {3, "no_lock", "no memory lock features enabled"}, +}; + +/* + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A1U ATxmega128A1U + * ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B ATxmega64A3U ATxmega128A3U + * ATxmega192A3U ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 + * ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 ATxmega8E5 ATxmega16E5 + * ATxmega32E5 + */ +static const Configvalue _values_lb_atxmega64a1[3] = { + {0, "rwlock", "read and write not allowed"}, + {2, "wlock", "write not allowed"}, + {3, "nolock", "no locks"}, +}; + +/* + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 + */ +static const Configvalue _values_lb_attiny202[2] = { + {0x3a, "rwlock", "read and write not allowed"}, + {0xc5, "nolock", "no locks"}, +}; + +/* + * ATtiny20 ATtiny40 ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A ATtiny25 ATtiny45 + * ATtiny85 ATtiny48 ATtiny88 ATtiny828 ATtiny828R ATtiny2313 ATtiny2313A ATtiny4313 ATmega640 + * ATmega1280 ATmega2560 ATmega1281 ATmega2561 ATmega164A ATmega164P ATmega164PA ATmega324A + * ATmega324P ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P + * ATmega324PB ATmega165 ATmega165A ATmega165P ATmega165PA ATmega48 ATmega48A ATmega48P ATmega48PA + * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 + * ATmega328P ATmega48PB ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P + * ATmega169PA ATA6612C ATA6613C ATA6614Q + */ +static const Configvalue _values_bodlevel_attiny20[4] = { + {4, "bod_4v3", "brownout detection at 4.3 V"}, + {5, "bod_2v7", "brownout detection at 2.7 V"}, + {6, "bod_1v8", "brownout detection at 1.8 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +/* + * AT90S2333 AT90S4433 AT90S8515comp AT90S8535comp ATtiny15 ATtiny26 ATmega8 ATmega8A ATmega16 + * ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega163 + * ATmega323 ATmega8515 ATmega8535 ATmega103comp + */ +static const Configvalue _values_bodlevel_at90s2333[2] = { + {0, "bod_4v0", "brownout detection at 4.0 V"}, + {1, "bod_2v7", "brownout detection at 2.7 V"}, +}; + +// AT90CAN32 AT90CAN64 AT90CAN128 +static const Configvalue _values_bodlevel_at90can32[8] = { + {0, "bod_2v5", "brownout detection at 2.5 V"}, + {1, "bod_2v6", "brownout detection at 2.6 V"}, + {2, "bod_2v7", "brownout detection at 2.7 V"}, + {3, "bod_3v8", "brownout detection at 3.8 V"}, + {4, "bod_3v9", "brownout detection at 3.9 V"}, + {5, "bod_4v0", "brownout detection at 4.0 V"}, + {6, "bod_4v1", "brownout detection at 4.1 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +/* + * AT90PWM1 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 ATmega32C1 ATmega64C1 + * ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 + */ +static const Configvalue _values_bodlevel_at90pwm1[8] = { + {0, "bod_2v6", "brownout detection at 2.6 V"}, + {1, "bod_2v8", "brownout detection at 2.8 V"}, + {2, "bod_4v2", "brownout detection at 4.2 V"}, + {3, "bod_4v4", "brownout detection at 4.4 V"}, + {4, "bod_4v3", "brownout detection at 4.3 V"}, + {5, "bod_2v7", "brownout detection at 2.7 V"}, + {6, "bod_4v5", "brownout detection at 4.5 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +/* + * AT90PWM81 AT90PWM161 ATtiny43U ATtiny87 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A + * ATtiny861 ATtiny861A ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 + */ +static const Configvalue _values_bodlevel_at90pwm81[8] = { + {0, "bod_2v0", "brownout detection at 2.0 V"}, + {1, "bod_1v9", "brownout detection at 1.9 V"}, + {2, "bod_2v2", "brownout detection at 2.2 V"}, + {3, "bod_2v3", "brownout detection at 2.3 V"}, + {4, "bod_4v3", "brownout detection at 4.3 V"}, + {5, "bod_2v7", "brownout detection at 2.7 V"}, + {6, "bod_1v8", "brownout detection at 1.8 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +// AT90USB82 AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 +static const Configvalue _values_bodlevel_at90usb82[8] = { + {0, "bod_4v3", "brownout detection at 4.3 V"}, + {1, "bod_4v0", "brownout detection at 4.0 V"}, + {2, "bod_3v6", "brownout detection at 3.6 V"}, + {3, "bod_3v5", "brownout detection at 3.5 V"}, + {4, "bod_3v0", "brownout detection at 3.0 V"}, + {5, "bod_2v9", "brownout detection at 2.9 V"}, + {6, "bod_2v7", "brownout detection at 2.7 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +// AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 ATmega16U4 ATmega32U4 ATmega32U6 +static const Configvalue _values_bodlevel_at90usb646[8] = { + {0, "bod_4v3", "brownout detection at 4.3 V"}, + {1, "bod_3v5", "brownout detection at 3.5 V"}, + {2, "bod_3v4", "brownout detection at 3.4 V"}, + {3, "bod_2v6", "brownout detection at 2.6 V"}, + {4, "bod_2v4", "brownout detection at 2.4 V"}, + {5, "bod_2v2", "brownout detection at 2.2 V"}, + {6, "bod_2v0", "brownout detection at 2.0 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +// ATtiny12 +static const Configvalue _values_bodlevel_attiny12[2] = { + {0, "bod_2v7", "brownout detection at 2.7 V"}, + {1, "bod_1v8", "brownout detection at 1.8 V"}, +}; + +/* + * ATtiny13 ATtiny13A ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P + * ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega329 + * ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A + * ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P + */ +static const Configvalue _values_bodlevel_attiny13[4] = { + {0, "bod_4v3", "brownout detection at 4.3 V"}, + {1, "bod_2v7", "brownout detection at 2.7 V"}, + {2, "bod_1v8", "brownout detection at 1.8 V"}, + {3, "bod_disabled", "brownout detection disabled"}, +}; + +// ATtiny1634 ATtiny1634R ATtiny441 ATtiny841 +static const Configvalue _values_bodlevel_attiny1634[4] = { + {4, "bod_4v3", "brownout detection at 4.3 V"}, + {5, "bod_2v7", "brownout detection at 2.7 V"}, + {6, "bod_1v8", "brownout detection at 1.8 V"}, + {7, "bod_1v8_alt", "brownout detection at 1.8 V"}, +}; + +/* + * ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 + * ATmega2564RFR2 + */ +static const Configvalue _values_bodlevel_atmega128rfa1[8] = { + {0, "bod_2v4", "brownout detection at 2.4 V"}, + {1, "bod_2v3", "brownout detection at 2.3 V"}, + {2, "bod_2v2", "brownout detection at 2.2 V"}, + {3, "bod_2v1", "brownout detection at 2.1 V"}, + {4, "bod_2v0", "brownout detection at 2.0 V"}, + {5, "bod_1v9", "brownout detection at 1.9 V"}, + {6, "bod_1v8", "brownout detection at 1.8 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +// ATmega161comp ATmega162 +static const Configvalue _values_bodlevel_atmega161comp[5] = { + {3, "bod_2v3", "brownout detection at 2.3 V"}, + {4, "bod_4v3", "brownout detection at 4.3 V"}, + {5, "bod_2v7", "brownout detection at 2.7 V"}, + {6, "bod_1v8", "brownout detection at 1.8 V"}, + {7, "bod_disabled", "brownout detection disabled"}, +}; + +/* + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A3 ATxmega128A3 + * ATxmega192A3 ATxmega256A3 ATxmega256A3B + */ +static const Configvalue _values_bodlevel_atxmega64a1[8] = { + {0, "bod_3v4", "brownout detection at 3.4 V"}, + {1, "bod_3v2", "brownout detection at 3.2 V"}, + {2, "bod_2v9", "brownout detection at 2.9 V"}, + {3, "bod_2v6", "brownout detection at 2.6 V"}, + {4, "bod_2v4", "brownout detection at 2.4 V"}, + {5, "bod_2v1", "brownout detection at 2.1 V"}, + {6, "bod_1v9", "brownout detection at 1.9 V"}, + {7, "bod_1v6", "brownout detection at 1.6 V"}, +}; + +/* + * ATxmega64A1U ATxmega128A1U ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3U + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 + * ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 ATxmega8E5 ATxmega16E5 + * ATxmega32E5 + */ +static const Configvalue _values_bodlevel_atxmega64a1u[8] = { + {0, "bod_3v0", "brownout detection at 3.0 V"}, + {1, "bod_2v8", "brownout detection at 2.8 V"}, + {2, "bod_2v6", "brownout detection at 2.6 V"}, + {3, "bod_2v4", "brownout detection at 2.4 V"}, + {4, "bod_2v2", "brownout detection at 2.2 V"}, + {5, "bod_2v0", "brownout detection at 2.0 V"}, + {6, "bod_1v8", "brownout detection at 1.8 V"}, + {7, "bod_1v6", "brownout detection at 1.6 V"}, +}; + +// ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 +static const Configvalue _values_bodlevel_atxmega16a4[8] = { + {0, "bod_3v5", "brownout detection at 3.5 V"}, + {1, "bod_3v2", "brownout detection at 3.2 V"}, + {2, "bod_3v0", "brownout detection at 3.0 V"}, + {3, "bod_2v7", "brownout detection at 2.7 V"}, + {4, "bod_2v4", "brownout detection at 2.4 V"}, + {5, "bod_2v1", "brownout detection at 2.1 V"}, + {6, "bod_1v9", "brownout detection at 1.9 V"}, + {7, "bod_1v6", "brownout detection at 1.6 V"}, +}; + +/* + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny417 ATtiny814 + * ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 ATtiny426 + * ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 ATtiny3226 + * ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 ATmega4808 + * ATmega4809 + */ +static const Configvalue _values_bodlevel_attiny202[3] = { + {0, "bod_1v8", "brownout detection at 1.8 V"}, + {2, "bod_2v6", "brownout detection at 2.6 V"}, + {7, "bod_4v2", "brownout detection at 4.2 V"}, +}; + +// ATtiny416auto +static const Configvalue _values_bodlevel_attiny416auto[2] = { + {2, "bod_2v6", "brownout detection at 2.6 V"}, + {7, "bod_4v2", "brownout detection at 4.2 V"}, +}; + +/* + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR32SD20 AVR32SD28 AVR32SD32 + */ +static const Configvalue _values_bodlevel_avr32da28[4] = { + {0, "bod_1v9", "brownout detection at 1.9 V"}, + {1, "bod_2v45", "brownout detection at 2.45 V"}, + {2, "bod_2v7", "brownout detection at 2.7 V"}, + {3, "bod_2v85", "brownout detection at 2.85 V"}, +}; + +/* + * AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 + * AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 + */ +static const Configvalue _values_bodlevel_avr16ea28[4] = { + {0, "bod_disabled", "brownout detection disabled"}, + {1, "bod_1v9", "brownout detection at 1.9 V"}, + {2, "bod_2v7", "brownout detection at 2.7 V"}, + {3, "bod_4v5", "brownout detection at 4.5 V"}, +}; + +// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 +static const Configvalue _values_bodlevel_avr16la14[4] = { + {0, "bodlevel0", "1.65 V"}, + {1, "bodlevel1", "1.90 V"}, + {2, "bodlevel2", "2.60 V"}, + {3, "bodlevel3", "4.30 V"}, +}; + +/* + * ATtiny102 ATtiny104 ATtiny13 ATtiny13A ATtiny43U ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 + * ATtiny84A ATtiny25 ATtiny45 ATtiny85 ATtiny87 ATtiny167 ATtiny48 ATtiny88 ATtiny1634 + * ATtiny1634R ATtiny441 ATtiny841 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A + * ATtiny2313 ATtiny2313A ATtiny4313 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega8HVA + * ATmega16HVA ATmega16HVA2 ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 + */ +static const Configvalue _values_selfprgen_attiny102[2] = { + {0, "spm_enabled", "self programming enabled"}, + {1, "spm_disabled", "self programming disabled"}, +}; + +// AT90S1200 AT90S2343 ATtiny22 +static const Configvalue _values_rcen_at90s1200[2] = { + {0, "intrcosc", "internal RC oscillator"}, + {1, "extclk", "external clock"}, +}; + +/* + * AT90S1200 AT90S2313 AT90S2323 AT90S2333 AT90S2343 AT90S4414 AT90S4433 AT90S4434 AT90S8515 + * AT90S8515comp AT90S8535 AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 + * AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 + * AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny12 ATtiny22 ATtiny13 + * ATtiny13A ATtiny43U ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A ATtiny15 ATtiny25 + * ATtiny45 ATtiny85 ATtiny26 ATtiny87 ATtiny167 ATtiny48 ATtiny88 ATtiny828 ATtiny828R ATtiny1634 + * ATtiny1634R ATtiny441 ATtiny841 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A + * ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A + * ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega640 ATmega1280 ATmega2560 ATmega32C1 + * ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 + * ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 + * ATmega161 ATmega161comp ATmega1281 ATmega2561 ATmega162 ATmega163 ATmega323 ATmega164A + * ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644 ATmega644A ATmega644P + * ATmega644PA ATmega1284 ATmega1284P ATmega324PB ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 + * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA + * ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 + * ATmega6450A ATmega6450P ATmega8515 ATmega8535 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 + * ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P + * ATmega48PB ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103 ATmega103comp + * ATmega8HVA ATmega16HVA ATmega16HVA2 ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB + * ATmega64HVE ATmega32HVE2 ATmega64HVE2 ATA5272 ATA5505 ATA5700M322 ATA5702M322 ATA5781 ATA5782 + * ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 ATA6285 + * ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA664251 ATA8210 ATA8215 ATA8510 + * ATA8515 + */ +static const Configvalue _values_spien_at90s1200[2] = { + {0, "isp_enabled", "serial programming enabled"}, + {1, "isp_disabled", "serial programming disabled"}, +}; + +// AT90S2313 AT90S2323 AT90S4414 AT90S4434 AT90S8515 AT90S8535 ATtiny11 +static const Configvalue _values_fstrt_at90s2313[2] = { + {0, "sut_short", "startup time short"}, + {1, "sut_long", "startup time long"}, +}; + +// AT90S2333 AT90S4433 +static const Configvalue _values_sut_cksel_at90s2333[8] = { + {0, "extclk_slowpwr", "ext clock; slowly rising power"}, + {1, "extclk_boden_por", "ext clock; brownout detection or power-on reset"}, + {2, "xosc", "crystal osc"}, + {3, "xosc_fastpwr", "crystal osc; fast rising power"}, + {4, "xosc_boden_por", "crystal osc; brownout detection or power-on reset"}, + {5, "cres", "ceramic resonator"}, + {6, "cres_fastpwr", "ceramic res; fast rising power"}, + {7, "cres_boden_por", "ceramic res; brownout detection or power-on reset"}, +}; + +/* + * AT90S8515comp AT90S8535comp ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 + * ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega8515 ATmega8535 ATmega103comp + */ +static const Configvalue _values_sut_cksel_at90s8515comp[58] = { {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, {0x01, "intrcosc_1mhz_6ck_0ms", "int RC osc 1 MHz; startup time: 6 CK + 0 ms"}, {0x02, "intrcosc_2mhz_6ck_0ms", "int RC osc 2 MHz; startup time: 6 CK + 0 ms"}, @@ -9052,29 +9514,107 @@ static const Configvalue _values_sut_cksel_atmega8515[58] = { {0x3f, "exthifxtalres_16kck_64ms", "ext crystal/resonator high freq; startup time: 16384 CK + 64 ms"}, }; -// ATtiny441 ATtiny841 -static const Configvalue _values_sut_cksel_attiny441[17] = { - {0x00, "extclk_6ck_16ck_16ms", "ext clock; startup time PWRDWN/RESET: 6 CK/16 CK + 16 ms"}, - {0x02, "intrcosc_8mhz_6ck_16ck_16ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/16 CK + 16 ms"}, - {0x04, "intulposc_32khz_6ck_16ck_16ms", "int ultra-low-power osc 32 kHz; startup time PWRDWN/RESET: 6 CK/16 CK + 16 ms"}, - {0x06, "extlofxtal_1kck_16ck_16ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, - {0x08, "extcres_0mhz4_0mhz9_258ck_16ck_16ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, - {0x09, "extxosc_0mhz4_0mhz9_16kck_16ck_16ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/16 CK + 16 ms"}, - {0x0a, "extcres_0mhz9_3mhz_258ck_16ck_16ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, - {0x0b, "extxosc_0mhz9_3mhz_16kck_16ck_16ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/16 CK + 16 ms"}, - {0x0c, "extcres_3mhz_8mhz_258ck_16ck_16ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, - {0x0d, "extxosc_3mhz_8mhz_16kck_16ck_16ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16K CK/16 CK + 16 ms"}, - {0x0e, "extcres_8mhz_xx_258ck_16ck_16ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, - {0x0f, "extxosc_8mhz_xx_16kck_16ck_16ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/16 CK + 16 ms"}, - {0x16, "extlofxtal_32kck_14ck_16ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/16 CK + 16 ms"}, - {0x18, "extcres_0mhz4_0mhz9_1kck_16ck_16ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, - {0x1a, "extcres_0mhz9_3mhz_1kck_16ck_16ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, - {0x1c, "extcres_3mhz_8mhz_1kck_16ck_16ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, - {0x1e, "extcres_8mhz_xx_1kck_16ck_16ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, +// AT90CAN32 AT90CAN64 +static const Configvalue _values_sut_cksel_at90can32[38] = { + {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, + {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, + {0x04, "extlofxtal_1kck_0ms", "ext low-freq crystal; startup time: 1024 CK + 0 ms"}, + {0x05, "extlofxtal_32kck_0ms", "ext low-freq crystal; startup time: 32768 CK + 0 ms"}, + {0x06, "extlofxtal_1kck_0ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 0 ms; int cap"}, + {0x07, "extlofxtal_32kck_0ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 0 ms; int cap"}, + {0x08, "extxosc_0mhz4_0mhz9_258ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 4.1 ms"}, + {0x09, "extxosc_0mhz4_0mhz9_1kck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 65 ms"}, + {0x0a, "extxosc_0mhz9_3mhz_258ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 4.1 ms"}, + {0x0b, "extxosc_0mhz9_3mhz_1kck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 65 ms"}, + {0x0c, "extxosc_3mhz_8mhz_258ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 4.1 ms"}, + {0x0d, "extxosc_3mhz_8mhz_1kck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 65 ms"}, + {0x0e, "extxosc_8mhz_16mhz_258ck_4ms1", "ext crystal osc 8.0-16.0 MHz; startup time: 258 CK + 4.1 ms"}, + {0x0f, "extxosc_8mhz_16mhz_1kck_65ms", "ext crystal osc 8.0-16.0 MHz; startup time: 1024 CK + 65 ms"}, + {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, + {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, + {0x14, "extlofxtal_1kck_4ms1", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms"}, + {0x15, "extlofxtal_32kck_4ms1", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms"}, + {0x16, "extlofxtal_1kck_4ms1_intcap", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms; int cap"}, + {0x17, "extlofxtal_32kck_4ms1_intcap", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms; int cap"}, + {0x18, "extxosc_0mhz4_0mhz9_258ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 65 ms"}, + {0x1a, "extxosc_0mhz9_3mhz_258ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 65 ms"}, + {0x1c, "extxosc_3mhz_8mhz_258ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 65 ms"}, + {0x1e, "extxosc_8mhz_16mhz_258ck_65ms", "ext crystal osc 8.0-16.0 MHz; startup time: 258 CK + 65 ms"}, + {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, + {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, + {0x24, "extlofxtal_1kck_65ms", "ext low-freq crystal; startup time: 1024 CK + 65 ms"}, + {0x25, "extlofxtal_32kck_65ms", "ext low-freq crystal; startup time: 32768 CK + 65 ms"}, + {0x26, "extlofxtal_1kck_65ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 65 ms; int cap"}, + {0x27, "extlofxtal_32kck_65ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 65 ms; int cap"}, + {0x28, "extxosc_0mhz4_0mhz9_1kck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 0 ms"}, + {0x2a, "extxosc_0mhz9_3mhz_1kck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 0 ms"}, + {0x2c, "extxosc_3mhz_8mhz_1kck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 0 ms"}, + {0x2e, "extxosc_8mhz_16mhz_1kck_0ms", "ext crystal osc 8.0-16.0 MHz; startup time: 1024 CK + 0 ms"}, + {0x38, "extxosc_0mhz4_0mhz9_1kck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 4.1 ms"}, + {0x3a, "extxosc_0mhz9_3mhz_1kck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 4.1 ms"}, + {0x3c, "extxosc_3mhz_8mhz_1kck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 4.1 ms"}, + {0x3e, "extxosc_8mhz_16mhz_1kck_4ms1", "ext crystal osc 8.0-16.0 MHz; startup time: 1024 CK + 4.1 ms"}, }; -// AT90PWM2 AT90PWM1 AT90PWM3 AT90PWM216 -static const Configvalue _values_sut_cksel_at90pwm2[42] = { +/* + * AT90CAN128 AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 ATmega8U2 + * ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161comp ATmega162 + */ +static const Configvalue _values_sut_cksel_at90can128[50] = { + {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, + {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, + {0x04, "extlofxtal_1kck_0ms", "ext low-freq crystal; startup time: 1024 CK + 0 ms"}, + {0x05, "extlofxtal_32kck_0ms", "ext low-freq crystal; startup time: 32768 CK + 0 ms"}, + {0x06, "extlofxtal_1kck_0ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 0 ms; int cap"}, + {0x07, "extlofxtal_32kck_0ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 0 ms; int cap"}, + {0x08, "extxosc_0mhz4_0mhz9_258ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 4.1 ms"}, + {0x09, "extxosc_0mhz4_0mhz9_1kck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 65 ms"}, + {0x0a, "extxosc_0mhz9_3mhz_258ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 4.1 ms"}, + {0x0b, "extxosc_0mhz9_3mhz_1kck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 65 ms"}, + {0x0c, "extxosc_3mhz_8mhz_258ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 4.1 ms"}, + {0x0d, "extxosc_3mhz_8mhz_1kck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 65 ms"}, + {0x0e, "extxosc_8mhz_xx_258ck_4ms1", "ext crystal osc 8.0+ MHz; startup time: 258 CK + 4.1 ms"}, + {0x0f, "extxosc_8mhz_xx_1kck_65ms", "ext crystal osc 8.0+ MHz; startup time: 1024 CK + 65 ms"}, + {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, + {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, + {0x14, "extlofxtal_1kck_4ms1", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms"}, + {0x15, "extlofxtal_32kck_4ms1", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms"}, + {0x16, "extlofxtal_1kck_4ms1_intcap", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms; int cap"}, + {0x17, "extlofxtal_32kck_4ms1_intcap", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms; int cap"}, + {0x18, "extxosc_0mhz4_0mhz9_258ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 65 ms"}, + {0x19, "extxosc_0mhz4_0mhz9_16kck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time: 16384 CK + 0 ms"}, + {0x1a, "extxosc_0mhz9_3mhz_258ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 65 ms"}, + {0x1b, "extxosc_0mhz9_3mhz_16kck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time: 16384 CK + 0 ms"}, + {0x1c, "extxosc_3mhz_8mhz_258ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 65 ms"}, + {0x1d, "extxosc_3mhz_8mhz_16kck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time: 16384 CK + 0 ms"}, + {0x1e, "extxosc_8mhz_xx_258ck_65ms", "ext crystal osc 8.0+ MHz; startup time: 258 CK + 65 ms"}, + {0x1f, "extxosc_8mhz_xx_16kck_0ms", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 0 ms"}, + {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, + {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, + {0x24, "extlofxtal_1kck_65ms", "ext low-freq crystal; startup time: 1024 CK + 65 ms"}, + {0x25, "extlofxtal_32kck_65ms", "ext low-freq crystal; startup time: 32768 CK + 65 ms"}, + {0x26, "extlofxtal_1kck_65ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 65 ms; int cap"}, + {0x27, "extlofxtal_32kck_65ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 65 ms; int cap"}, + {0x28, "extxosc_0mhz4_0mhz9_1kck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 0 ms"}, + {0x29, "extxosc_0mhz4_0mhz9_16kck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 16384 CK + 4.1 ms"}, + {0x2a, "extxosc_0mhz9_3mhz_1kck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 0 ms"}, + {0x2b, "extxosc_0mhz9_3mhz_16kck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 16384 CK + 4.1 ms"}, + {0x2c, "extxosc_3mhz_8mhz_1kck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 0 ms"}, + {0x2d, "extxosc_3mhz_8mhz_16kck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 16384 CK + 4.1 ms"}, + {0x2e, "extxosc_8mhz_xx_1kck_0ms", "ext crystal osc 8.0+ MHz; startup time: 1024 CK + 0 ms"}, + {0x2f, "extxosc_8mhz_xx_16kck_4ms1", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 4.1 ms"}, + {0x38, "extxosc_0mhz4_0mhz9_1kck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 4.1 ms"}, + {0x39, "extxosc_0mhz4_0mhz9_16kck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 16384 CK + 65 ms"}, + {0x3a, "extxosc_0mhz9_3mhz_1kck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 4.1 ms"}, + {0x3b, "extxosc_0mhz9_3mhz_16kck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 16384 CK + 65 ms"}, + {0x3c, "extxosc_3mhz_8mhz_1kck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 4.1 ms"}, + {0x3d, "extxosc_3mhz_8mhz_16kck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 16384 CK + 65 ms"}, + {0x3e, "extxosc_8mhz_xx_1kck_4ms1", "ext crystal osc 8.0+ MHz; startup time: 1024 CK + 4.1 ms"}, + {0x3f, "extxosc_8mhz_xx_16kck_65ms", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 65 ms"}, +}; + +// AT90PWM1 AT90PWM2 AT90PWM216 AT90PWM3 +static const Configvalue _values_sut_cksel_at90pwm1[42] = { {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, {0x03, "pllclk_16mhz_1kck_14ck_0ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, @@ -9180,71 +9720,67 @@ static const Configvalue _values_sut_cksel_at90pwm81[56] = { }; /* - * AT90CAN128 AT90USB162 ATmega161comp ATmega8U2 ATmega16U2 ATmega16U4 ATmega32U2 ATmega32U4 - * ATmega32U6 ATmega162 AT90USB82 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 + * AT90PWM2B AT90PWM3B AT90PWM316 ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 + * ATmegaS64M1 */ -static const Configvalue _values_sut_cksel_at90can128[50] = { - {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, - {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, - {0x04, "extlofxtal_1kck_0ms", "ext low-freq crystal; startup time: 1024 CK + 0 ms"}, - {0x05, "extlofxtal_32kck_0ms", "ext low-freq crystal; startup time: 32768 CK + 0 ms"}, - {0x06, "extlofxtal_1kck_0ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 0 ms; int cap"}, - {0x07, "extlofxtal_32kck_0ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 0 ms; int cap"}, - {0x08, "extxosc_0mhz4_0mhz9_258ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 4.1 ms"}, - {0x09, "extxosc_0mhz4_0mhz9_1kck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 65 ms"}, - {0x0a, "extxosc_0mhz9_3mhz_258ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 4.1 ms"}, - {0x0b, "extxosc_0mhz9_3mhz_1kck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 65 ms"}, - {0x0c, "extxosc_3mhz_8mhz_258ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 4.1 ms"}, - {0x0d, "extxosc_3mhz_8mhz_1kck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 65 ms"}, - {0x0e, "extxosc_8mhz_xx_258ck_4ms1", "ext crystal osc 8.0+ MHz; startup time: 258 CK + 4.1 ms"}, - {0x0f, "extxosc_8mhz_xx_1kck_65ms", "ext crystal osc 8.0+ MHz; startup time: 1024 CK + 65 ms"}, - {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, - {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, - {0x14, "extlofxtal_1kck_4ms1", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms"}, - {0x15, "extlofxtal_32kck_4ms1", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms"}, - {0x16, "extlofxtal_1kck_4ms1_intcap", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms; int cap"}, - {0x17, "extlofxtal_32kck_4ms1_intcap", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms; int cap"}, - {0x18, "extxosc_0mhz4_0mhz9_258ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 65 ms"}, - {0x19, "extxosc_0mhz4_0mhz9_16kck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time: 16384 CK + 0 ms"}, - {0x1a, "extxosc_0mhz9_3mhz_258ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 65 ms"}, - {0x1b, "extxosc_0mhz9_3mhz_16kck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time: 16384 CK + 0 ms"}, - {0x1c, "extxosc_3mhz_8mhz_258ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 65 ms"}, - {0x1d, "extxosc_3mhz_8mhz_16kck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time: 16384 CK + 0 ms"}, - {0x1e, "extxosc_8mhz_xx_258ck_65ms", "ext crystal osc 8.0+ MHz; startup time: 258 CK + 65 ms"}, - {0x1f, "extxosc_8mhz_xx_16kck_0ms", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 0 ms"}, - {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, - {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, - {0x24, "extlofxtal_1kck_65ms", "ext low-freq crystal; startup time: 1024 CK + 65 ms"}, - {0x25, "extlofxtal_32kck_65ms", "ext low-freq crystal; startup time: 32768 CK + 65 ms"}, - {0x26, "extlofxtal_1kck_65ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 65 ms; int cap"}, - {0x27, "extlofxtal_32kck_65ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 65 ms; int cap"}, - {0x28, "extxosc_0mhz4_0mhz9_1kck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 0 ms"}, - {0x29, "extxosc_0mhz4_0mhz9_16kck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 16384 CK + 4.1 ms"}, - {0x2a, "extxosc_0mhz9_3mhz_1kck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 0 ms"}, - {0x2b, "extxosc_0mhz9_3mhz_16kck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 16384 CK + 4.1 ms"}, - {0x2c, "extxosc_3mhz_8mhz_1kck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 0 ms"}, - {0x2d, "extxosc_3mhz_8mhz_16kck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 16384 CK + 4.1 ms"}, - {0x2e, "extxosc_8mhz_xx_1kck_0ms", "ext crystal osc 8.0+ MHz; startup time: 1024 CK + 0 ms"}, - {0x2f, "extxosc_8mhz_xx_16kck_4ms1", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 4.1 ms"}, - {0x38, "extxosc_0mhz4_0mhz9_1kck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 4.1 ms"}, - {0x39, "extxosc_0mhz4_0mhz9_16kck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 16384 CK + 65 ms"}, - {0x3a, "extxosc_0mhz9_3mhz_1kck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 4.1 ms"}, - {0x3b, "extxosc_0mhz9_3mhz_16kck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 16384 CK + 65 ms"}, - {0x3c, "extxosc_3mhz_8mhz_1kck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 4.1 ms"}, - {0x3d, "extxosc_3mhz_8mhz_16kck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 16384 CK + 65 ms"}, - {0x3e, "extxosc_8mhz_xx_1kck_4ms1", "ext crystal osc 8.0+ MHz; startup time: 1024 CK + 4.1 ms"}, - {0x3f, "extxosc_8mhz_xx_16kck_65ms", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 65 ms"}, +static const Configvalue _values_sut_cksel_at90pwm2b[53] = { + {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x01, "pllclk_pllin_extclk_6kck_14ck_0ms", "PLL clock/4; PLL input: ext clock; startup time PWRDWN/RESET: 6K CK/14 CK + 0 ms"}, + {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x03, "pllclk_16mhz_1kck_14ck_0ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x04, "extxosc_pllin_extxosc_1kck_14ck_0ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x05, "pllclk_pllin_extxosc_1kck_14ck_0ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x08, "extxosc_0mhz4_0mhz9_258ck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x09, "extxosc_0mhz4_0mhz9_1kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0a, "extxosc_0mhz9_3mhz_258ck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0b, "extxosc_0mhz9_3mhz_1kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0c, "extxosc_3mhz_8mhz_258ck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0d, "extxosc_3mhz_8mhz_1kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0e, "extxosc_8mhz_xx_258ck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0f, "extxosc_8mhz_xx_1kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x10, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x11, "pllclk_pllin_extclk_6kck_14ck_4ms", "PLL clock/4; PLL input: ext clock; startup time PWRDWN/RESET: 6K CK/14 CK + 4 ms"}, + {0x12, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x13, "pllclk_16mhz_1kck_14ck_4ms1", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x14, "extxosc_pllin_extxosc_1kck_14ck_4ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 4 ms"}, + {0x15, "pllclk_pllin_extxosc_1kck_14ck_4ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 1024 CK/14 CK + 4 ms"}, + {0x18, "extxosc_0mhz4_0mhz9_258ck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1a, "extxosc_0mhz9_3mhz_258ck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1c, "extxosc_3mhz_8mhz_258ck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1e, "extxosc_8mhz_xx_258ck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x20, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x21, "pllclk_pllin_extclk_6kck_14ck_64ms", "PLL clock/4; PLL input: ext clock; startup time PWRDWN/RESET: 6K CK/14 CK + 64 ms"}, + {0x22, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x23, "pllclk_16mhz_1kck_14ck_65ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x24, "extxosc_pllin_extxosc_16kck_14ck_4ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 4 ms"}, + {0x25, "pllclk_pllin_extxosc_16kck_14ck_4ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 4 ms"}, + {0x28, "extxosc_0mhz4_0mhz9_1kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2a, "extxosc_0mhz9_3mhz_1kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2c, "extxosc_3mhz_8mhz_1kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2e, "extxosc_8mhz_xx_1kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x33, "pllclk_16mhz_16kck_14ck_0ms", "PLL clock 16 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x34, "extxosc_pllin_extxosc_16kck_14ck_64ms", "ext crystal osc; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 64 ms"}, + {0x35, "pllclk_pllin_extxosc_16kck_14ck_64ms", "PLL clock/4; PLL input: ext crystal osc; startup time PWRDWN/RESET: 16384 CK/14 CK + 64 ms"}, + {0x38, "extxosc_0mhz4_0mhz9_1kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3a, "extxosc_0mhz9_3mhz_1kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3c, "extxosc_3mhz_8mhz_1kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3e, "extxosc_8mhz_xx_1kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, }; -// ATA6285 ATA6286 ATA6289 -static const Configvalue _values_sut_cksel_ata6285[3] = { - {0, "sut_6ck_14ck_0ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {1, "sut_6ck_14ck_5ms7", "startup time PWRDWN/RESET: 6 CK/14 CK + 5.7 ms"}, - {2, "sut_6ck_14ck_90ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 90 ms"}, -}; - -// AT90SCR100H AT90SCR100 -static const Configvalue _values_sut_cksel_at90scr100h[14] = { +// AT90SCR100 AT90SCR100H +static const Configvalue _values_sut_cksel_at90scr100[14] = { {0x00, "extclk_bodenx00", "ext clock; brownout detection"}, {0x01, "extclk_bodenx01", "ext clock; brownout detection"}, {0x08, "cres_fastpwrx08", "ceramic res; fast rising power"}, @@ -9277,6 +9813,58 @@ static const Configvalue _values_sut_cksel_attiny13[12] = { {0x0b, "intrcosc_128khz_14ck_64ms", "int RC osc 128 kHz; startup time: 14 CK + 64 ms"}, }; +// ATtiny43U ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A +static const Configvalue _values_sut_cksel_attiny43u[48] = { + {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x01, "pllclk_1kck_14ck_8ms", "PLL clock; startup time PWRDWN/RESET: 1024 CK/14 CK + 8 ms"}, + {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x03, "wdosc_128khz_6ck_14ck_0ms", "WD osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x04, "extlofxtal_1kck_4ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/4 ms"}, + {0x08, "extcres_0mhz4_0mhz9_258ck_14ck_4ms1", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x09, "extcres_0mhz4_0mhz9_1kck_14ck_65ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0a, "extcres_0mhz9_3mhz_258ck_14ck_4ms1", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0b, "extcres_0mhz9_3mhz_1kck_14ck_65ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0c, "extcres_3mhz_8mhz_258ck_14ck_4ms1", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0d, "extcres_3mhz_8mhz_1kck_14ck_65ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0e, "extcres_8mhz_xx_258ck_14ck_4ms1", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0f, "extcres_8mhz_xx_1kck_14ck_65ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x10, "extclk_6ck_14ck_4ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, + {0x11, "pllclk_16kck_14ck_8ms", "PLL clock; startup time PWRDWN/RESET: 16384 CK/14 CK + 8 ms"}, + {0x12, "intrcosc_8mhz_6ck_14ck_4ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, + {0x13, "wdosc_128khz_6ck_14ck_4ms", "WD osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, + {0x14, "extlofxtal_1kck_64ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/64 ms"}, + {0x18, "extcres_0mhz4_0mhz9_258ck_14ck_65ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1a, "extcres_0mhz9_3mhz_258ck_14ck_65ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1c, "extcres_3mhz_8mhz_258ck_14ck_65ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1e, "extcres_8mhz_xx_258ck_14ck_65ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x20, "extclk_6ck_14ck_64ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, + {0x21, "pllclk_1kck_14ck_68ms", "PLL clock; startup time PWRDWN/RESET: 1024 CK/14 CK + 68 ms"}, + {0x22, "intrcosc_8mhz_6ck_14ck_64ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, + {0x23, "wdosc_128khz_6ck_14ck_64ms", "WD osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, + {0x24, "extlofxtal_32kck_64ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/64 ms"}, + {0x28, "extcres_0mhz4_0mhz9_1kck_14ck_0ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2a, "extcres_0mhz9_3mhz_1kck_14ck_0ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2c, "extcres_3mhz_8mhz_1kck_14ck_0ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2e, "extcres_8mhz_xx_1kck_14ck_0ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x31, "pllclk_16kck_14ck_68ms", "PLL clock; startup time PWRDWN/RESET: 16384 CK/14 CK + 68 ms"}, + {0x38, "extcres_0mhz4_0mhz9_1kck_14ck_4ms1", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3a, "extcres_0mhz9_3mhz_1kck_14ck_4ms1", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3c, "extcres_3mhz_8mhz_1kck_14ck_4ms1", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3e, "extcres_8mhz_xx_1kck_14ck_4ms1", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, +}; + // ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A static const Configvalue _values_sut_cksel_attiny24[44] = { {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, @@ -9446,71 +10034,6 @@ static const Configvalue _values_sut_cksel_attiny26[62] = { {0xbf, "exthifxtalres_16kck_64ms", "ext crystal/resonator high freq; startup time: 16384 CK + 64 ms"}, }; -// ATtiny43U ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A -static const Configvalue _values_sut_cksel_attiny43u[48] = { - {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x01, "pllclk_1kck_14ck_8ms", "PLL clock; startup time PWRDWN/RESET: 1024 CK/14 CK + 8 ms"}, - {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x03, "wdosc_128khz_6ck_14ck_0ms", "WD osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x04, "extlofxtal_1kck_4ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/4 ms"}, - {0x08, "extcres_0mhz4_0mhz9_258ck_14ck_4ms1", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x09, "extcres_0mhz4_0mhz9_1kck_14ck_65ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0a, "extcres_0mhz9_3mhz_258ck_14ck_4ms1", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0b, "extcres_0mhz9_3mhz_1kck_14ck_65ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0c, "extcres_3mhz_8mhz_258ck_14ck_4ms1", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0d, "extcres_3mhz_8mhz_1kck_14ck_65ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x0e, "extcres_8mhz_xx_258ck_14ck_4ms1", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, - {0x0f, "extcres_8mhz_xx_1kck_14ck_65ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, - {0x10, "extclk_6ck_14ck_4ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, - {0x11, "pllclk_16kck_14ck_8ms", "PLL clock; startup time PWRDWN/RESET: 16384 CK/14 CK + 8 ms"}, - {0x12, "intrcosc_8mhz_6ck_14ck_4ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, - {0x13, "wdosc_128khz_6ck_14ck_4ms", "WD osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, - {0x14, "extlofxtal_1kck_64ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/64 ms"}, - {0x18, "extcres_0mhz4_0mhz9_258ck_14ck_65ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1a, "extcres_0mhz9_3mhz_258ck_14ck_65ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1c, "extcres_3mhz_8mhz_258ck_14ck_65ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x1e, "extcres_8mhz_xx_258ck_14ck_65ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, - {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, - {0x20, "extclk_6ck_14ck_64ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, - {0x21, "pllclk_1kck_14ck_68ms", "PLL clock; startup time PWRDWN/RESET: 1024 CK/14 CK + 68 ms"}, - {0x22, "intrcosc_8mhz_6ck_14ck_64ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, - {0x23, "wdosc_128khz_6ck_14ck_64ms", "WD osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, - {0x24, "extlofxtal_32kck_64ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/64 ms"}, - {0x28, "extcres_0mhz4_0mhz9_1kck_14ck_0ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2a, "extcres_0mhz9_3mhz_1kck_14ck_0ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2c, "extcres_3mhz_8mhz_1kck_14ck_0ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x2e, "extcres_8mhz_xx_1kck_14ck_0ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, - {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, - {0x31, "pllclk_16kck_14ck_68ms", "PLL clock; startup time PWRDWN/RESET: 16384 CK/14 CK + 68 ms"}, - {0x38, "extcres_0mhz4_0mhz9_1kck_14ck_4ms1", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3a, "extcres_0mhz9_3mhz_1kck_14ck_4ms1", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3c, "extcres_3mhz_8mhz_1kck_14ck_4ms1", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, - {0x3e, "extcres_8mhz_xx_1kck_14ck_4ms1", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, - {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, -}; - -// ATtiny48 ATtiny88 -static const Configvalue _values_sut_cksel_attiny48[9] = { - {0x0c, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x0e, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x0f, "intrcosc_128khz_6ck_14ck_0ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, - {0x1c, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x1e, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x1f, "intrcosc_128khz_6ck_14ck_4ms1", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, - {0x2c, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x2e, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, - {0x2f, "intrcosc_128khz_6ck_14ck_65ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, -}; - // ATtiny87 ATtiny167 ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 static const Configvalue _values_sut_cksel_attiny87[44] = { {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, @@ -9559,6 +10082,19 @@ static const Configvalue _values_sut_cksel_attiny87[44] = { {0x3f, "extxosc_8mhz_16mhz_16kck_14ck_65ms", "ext crystal osc 8.0-16.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, }; +// ATtiny48 ATtiny88 +static const Configvalue _values_sut_cksel_attiny48[9] = { + {0x0c, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x0e, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x0f, "intrcosc_128khz_6ck_14ck_0ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x1c, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x1e, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x1f, "intrcosc_128khz_6ck_14ck_4ms1", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x2c, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x2e, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x2f, "intrcosc_128khz_6ck_14ck_65ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, +}; + // ATtiny828 ATtiny828R static const Configvalue _values_sut_cksel_attiny828[16] = { {0x00, "extclk_6ck_14ck_0msx00", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, @@ -9598,6 +10134,27 @@ static const Configvalue _values_sut_cksel_attiny1634[15] = { {0x1e, "extcres_8mhz_xx_1kck_16ck_16ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, }; +// ATtiny441 ATtiny841 +static const Configvalue _values_sut_cksel_attiny441[17] = { + {0x00, "extclk_6ck_16ck_16ms", "ext clock; startup time PWRDWN/RESET: 6 CK/16 CK + 16 ms"}, + {0x02, "intrcosc_8mhz_6ck_16ck_16ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/16 CK + 16 ms"}, + {0x04, "intulposc_32khz_6ck_16ck_16ms", "int ultra-low-power osc 32 kHz; startup time PWRDWN/RESET: 6 CK/16 CK + 16 ms"}, + {0x06, "extlofxtal_1kck_16ck_16ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, + {0x08, "extcres_0mhz4_0mhz9_258ck_16ck_16ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, + {0x09, "extxosc_0mhz4_0mhz9_16kck_16ck_16ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/16 CK + 16 ms"}, + {0x0a, "extcres_0mhz9_3mhz_258ck_16ck_16ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, + {0x0b, "extxosc_0mhz9_3mhz_16kck_16ck_16ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/16 CK + 16 ms"}, + {0x0c, "extcres_3mhz_8mhz_258ck_16ck_16ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, + {0x0d, "extxosc_3mhz_8mhz_16kck_16ck_16ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16K CK/16 CK + 16 ms"}, + {0x0e, "extcres_8mhz_xx_258ck_16ck_16ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/16 CK + 16 ms"}, + {0x0f, "extxosc_8mhz_xx_16kck_16ck_16ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/16 CK + 16 ms"}, + {0x16, "extlofxtal_32kck_14ck_16ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/16 CK + 16 ms"}, + {0x18, "extcres_0mhz4_0mhz9_1kck_16ck_16ms", "ext ceramic res 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, + {0x1a, "extcres_0mhz9_3mhz_1kck_16ck_16ms", "ext ceramic res 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, + {0x1c, "extcres_3mhz_8mhz_1kck_16ck_16ms", "ext ceramic res 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, + {0x1e, "extcres_8mhz_xx_1kck_16ck_16ms", "ext ceramic res 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/16 CK + 16 ms"}, +}; + // ATtiny2313 ATtiny2313A ATtiny4313 static const Configvalue _values_sut_cksel_attiny2313[44] = { {0x00, "extclk_14ck_0ms", "ext clock; startup time: 14 CK + 0 ms"}, @@ -9646,86 +10203,12 @@ static const Configvalue _values_sut_cksel_attiny2313[44] = { {0x3f, "extxosc_8mhz_xx_14ck_65msx3f", "ext crystal osc 8.0+ MHz; startup time: 14 CK + 65 ms"}, }; -// ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 -static const Configvalue _values_sut_cksel_atmega64rfr2[49] = { - {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, - {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, - {0x03, "intrcosc_128khz_6ck_0ms", "int 128 kHz RC osc; startup time: 6 CK + 0 ms"}, - {0x06, "tosc_258ck_4ms1x06", "transceiver osc; startup time: 258 CK + 4.1 ms"}, - {0x07, "tosc_1kck_65msx07", "transceiver osc; startup time: 1024 CK + 65 ms"}, - {0x08, "tosc_258ck_4ms1x08", "transceiver osc; startup time: 258 CK + 4.1 ms"}, - {0x09, "tosc_1kck_65msx09", "transceiver osc; startup time: 1024 CK + 65 ms"}, - {0x0a, "tosc_258ck_4ms1x0a", "transceiver osc; startup time: 258 CK + 4.1 ms"}, - {0x0b, "tosc_1kck_65msx0b", "transceiver osc; startup time: 1024 CK + 65 ms"}, - {0x0c, "tosc_258ck_4ms1x0c", "transceiver osc; startup time: 258 CK + 4.1 ms"}, - {0x0d, "tosc_1kck_65msx0d", "transceiver osc; startup time: 1024 CK + 65 ms"}, - {0x0e, "tosc_258ck_4ms1x0e", "transceiver osc; startup time: 258 CK + 4.1 ms"}, - {0x0f, "tosc_1kck_65msx0f", "transceiver osc; startup time: 1024 CK + 65 ms"}, - {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, - {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, - {0x13, "intrcosc_128khz_6ck_4ms1", "int 128 kHz RC osc; startup time: 6 CK + 4.1 ms"}, - {0x16, "tosc_258ck_65msx16", "transceiver osc; startup time: 258 CK + 65 ms"}, - {0x17, "tosc_16kck_0msx17", "transceiver osc; startup time: 16384 CK + 0 ms"}, - {0x18, "tosc_258ck_65msx18", "transceiver osc; startup time: 258 CK + 65 ms"}, - {0x19, "tosc_16kck_0msx19", "transceiver osc; startup time: 16384 CK + 0 ms"}, - {0x1a, "tosc_258ck_65msx1a", "transceiver osc; startup time: 258 CK + 65 ms"}, - {0x1b, "tosc_16kck_0msx1b", "transceiver osc; startup time: 16384 CK + 0 ms"}, - {0x1c, "tosc_258ck_65msx1c", "transceiver osc; startup time: 258 CK + 65 ms"}, - {0x1d, "tosc_16kck_0msx1d", "transceiver osc; startup time: 16384 CK + 0 ms"}, - {0x1e, "tosc_258ck_65msx1e", "transceiver osc; startup time: 258 CK + 65 ms"}, - {0x1f, "tosc_16kck_0msx1f", "transceiver osc; startup time: 16384 CK + 0 ms"}, - {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, - {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, - {0x23, "intrcosc_128khz_6ck_65ms", "int 128 kHz RC osc; startup time: 6 CK + 65 ms"}, - {0x26, "tosc_1kck_0msx26", "transceiver osc; startup time: 1024 CK + 0 ms"}, - {0x27, "tosc_16kck_4ms1x27", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, - {0x28, "tosc_1kck_0msx28", "transceiver osc; startup time: 1024 CK + 0 ms"}, - {0x29, "tosc_16kck_4ms1x29", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, - {0x2a, "tosc_1kck_0msx2a", "transceiver osc; startup time: 1024 CK + 0 ms"}, - {0x2b, "tosc_16kck_4ms1x2b", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, - {0x2c, "tosc_1kck_0msx2c", "transceiver osc; startup time: 1024 CK + 0 ms"}, - {0x2d, "tosc_16kck_4ms1x2d", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, - {0x2e, "tosc_1kck_0msx2e", "transceiver osc; startup time: 1024 CK + 0 ms"}, - {0x2f, "tosc_16kck_4ms1x2f", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, - {0x36, "tosc_1kck_4ms1x36", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, - {0x37, "tosc_16kck_65msx37", "transceiver osc; startup time: 16384 CK + 65 ms"}, - {0x38, "tosc_1kck_4ms1x38", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, - {0x39, "tosc_16kck_65msx39", "transceiver osc; startup time: 16384 CK + 65 ms"}, - {0x3a, "tosc_1kck_4ms1x3a", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, - {0x3b, "tosc_16kck_65msx3b", "transceiver osc; startup time: 16384 CK + 65 ms"}, - {0x3c, "tosc_1kck_4ms1x3c", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, - {0x3d, "tosc_16kck_65msx3d", "transceiver osc; startup time: 16384 CK + 65 ms"}, - {0x3e, "tosc_1kck_4ms1x3e", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, - {0x3f, "tosc_16kck_65msx3f", "transceiver osc; startup time: 16384 CK + 65 ms"}, -}; - -// ATmega128RFA1 -static const Configvalue _values_sut_cksel_atmega128rfa1[17] = { - {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, - {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, - {0x03, "intrcosc_128khz_6ck_0ms", "int 128 kHz RC osc; startup time: 6 CK + 0 ms"}, - {0x06, "tosc_258ck_4ms1", "transceiver osc; startup time: 258 CK + 4.1 ms"}, - {0x07, "tosc_1kck_65ms", "transceiver osc; startup time: 1024 CK + 65 ms"}, - {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, - {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, - {0x13, "intrcosc_128khz_6ck_4ms1", "int 128 kHz RC osc; startup time: 6 CK + 4.1 ms"}, - {0x16, "tosc_258ck_65ms", "transceiver osc; startup time: 258 CK + 65 ms"}, - {0x17, "tosc_16kck_0ms", "transceiver osc; startup time: 16384 CK + 0 ms"}, - {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, - {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, - {0x23, "intrcosc_128khz_6ck_65ms", "int 128 kHz RC osc; startup time: 6 CK + 65 ms"}, - {0x26, "tosc_1kck_0ms", "transceiver osc; startup time: 1024 CK + 0 ms"}, - {0x27, "tosc_16kck_4ms1", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, - {0x36, "tosc_1kck_4ms1", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, - {0x37, "tosc_16kck_65ms", "transceiver osc; startup time: 16384 CK + 65 ms"}, -}; - /* - * ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega640 ATmega644 - * ATmega644A ATmega644P ATmega644PA ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega2560 - * ATmega2561 + * ATmega640 ATmega1280 ATmega2560 ATmega1281 ATmega2561 ATmega164A ATmega164P ATmega164PA + * ATmega324A ATmega324P ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 + * ATmega1284P */ -static const Configvalue _values_sut_cksel_atmega164a[55] = { +static const Configvalue _values_sut_cksel_atmega640[55] = { {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, {0x03, "intrcosc_128khz_6ck_0ms", "int 128 kHz RC osc; startup time: 6 CK + 0 ms"}, @@ -9783,12 +10266,137 @@ static const Configvalue _values_sut_cksel_atmega164a[55] = { {0x3f, "extxosc_8mhz_xx_16kck_65ms", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 65 ms"}, }; +// ATmega128RFA1 +static const Configvalue _values_sut_cksel_atmega128rfa1[17] = { + {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, + {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, + {0x03, "intrcosc_128khz_6ck_0ms", "int 128 kHz RC osc; startup time: 6 CK + 0 ms"}, + {0x06, "tosc_258ck_4ms1", "transceiver osc; startup time: 258 CK + 4.1 ms"}, + {0x07, "tosc_1kck_65ms", "transceiver osc; startup time: 1024 CK + 65 ms"}, + {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, + {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, + {0x13, "intrcosc_128khz_6ck_4ms1", "int 128 kHz RC osc; startup time: 6 CK + 4.1 ms"}, + {0x16, "tosc_258ck_65ms", "transceiver osc; startup time: 258 CK + 65 ms"}, + {0x17, "tosc_16kck_0ms", "transceiver osc; startup time: 16384 CK + 0 ms"}, + {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, + {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, + {0x23, "intrcosc_128khz_6ck_65ms", "int 128 kHz RC osc; startup time: 6 CK + 65 ms"}, + {0x26, "tosc_1kck_0ms", "transceiver osc; startup time: 1024 CK + 0 ms"}, + {0x27, "tosc_16kck_4ms1", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, + {0x36, "tosc_1kck_4ms1", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, + {0x37, "tosc_16kck_65ms", "transceiver osc; startup time: 16384 CK + 65 ms"}, +}; + +// ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 +static const Configvalue _values_sut_cksel_atmega64rfr2[49] = { + {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, + {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, + {0x03, "intrcosc_128khz_6ck_0ms", "int 128 kHz RC osc; startup time: 6 CK + 0 ms"}, + {0x06, "tosc_258ck_4ms1x06", "transceiver osc; startup time: 258 CK + 4.1 ms"}, + {0x07, "tosc_1kck_65msx07", "transceiver osc; startup time: 1024 CK + 65 ms"}, + {0x08, "tosc_258ck_4ms1x08", "transceiver osc; startup time: 258 CK + 4.1 ms"}, + {0x09, "tosc_1kck_65msx09", "transceiver osc; startup time: 1024 CK + 65 ms"}, + {0x0a, "tosc_258ck_4ms1x0a", "transceiver osc; startup time: 258 CK + 4.1 ms"}, + {0x0b, "tosc_1kck_65msx0b", "transceiver osc; startup time: 1024 CK + 65 ms"}, + {0x0c, "tosc_258ck_4ms1x0c", "transceiver osc; startup time: 258 CK + 4.1 ms"}, + {0x0d, "tosc_1kck_65msx0d", "transceiver osc; startup time: 1024 CK + 65 ms"}, + {0x0e, "tosc_258ck_4ms1x0e", "transceiver osc; startup time: 258 CK + 4.1 ms"}, + {0x0f, "tosc_1kck_65msx0f", "transceiver osc; startup time: 1024 CK + 65 ms"}, + {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, + {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, + {0x13, "intrcosc_128khz_6ck_4ms1", "int 128 kHz RC osc; startup time: 6 CK + 4.1 ms"}, + {0x16, "tosc_258ck_65msx16", "transceiver osc; startup time: 258 CK + 65 ms"}, + {0x17, "tosc_16kck_0msx17", "transceiver osc; startup time: 16384 CK + 0 ms"}, + {0x18, "tosc_258ck_65msx18", "transceiver osc; startup time: 258 CK + 65 ms"}, + {0x19, "tosc_16kck_0msx19", "transceiver osc; startup time: 16384 CK + 0 ms"}, + {0x1a, "tosc_258ck_65msx1a", "transceiver osc; startup time: 258 CK + 65 ms"}, + {0x1b, "tosc_16kck_0msx1b", "transceiver osc; startup time: 16384 CK + 0 ms"}, + {0x1c, "tosc_258ck_65msx1c", "transceiver osc; startup time: 258 CK + 65 ms"}, + {0x1d, "tosc_16kck_0msx1d", "transceiver osc; startup time: 16384 CK + 0 ms"}, + {0x1e, "tosc_258ck_65msx1e", "transceiver osc; startup time: 258 CK + 65 ms"}, + {0x1f, "tosc_16kck_0msx1f", "transceiver osc; startup time: 16384 CK + 0 ms"}, + {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, + {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, + {0x23, "intrcosc_128khz_6ck_65ms", "int 128 kHz RC osc; startup time: 6 CK + 65 ms"}, + {0x26, "tosc_1kck_0msx26", "transceiver osc; startup time: 1024 CK + 0 ms"}, + {0x27, "tosc_16kck_4ms1x27", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, + {0x28, "tosc_1kck_0msx28", "transceiver osc; startup time: 1024 CK + 0 ms"}, + {0x29, "tosc_16kck_4ms1x29", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, + {0x2a, "tosc_1kck_0msx2a", "transceiver osc; startup time: 1024 CK + 0 ms"}, + {0x2b, "tosc_16kck_4ms1x2b", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, + {0x2c, "tosc_1kck_0msx2c", "transceiver osc; startup time: 1024 CK + 0 ms"}, + {0x2d, "tosc_16kck_4ms1x2d", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, + {0x2e, "tosc_1kck_0msx2e", "transceiver osc; startup time: 1024 CK + 0 ms"}, + {0x2f, "tosc_16kck_4ms1x2f", "transceiver osc; startup time: 16384 CK + 4.1 ms"}, + {0x36, "tosc_1kck_4ms1x36", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, + {0x37, "tosc_16kck_65msx37", "transceiver osc; startup time: 16384 CK + 65 ms"}, + {0x38, "tosc_1kck_4ms1x38", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, + {0x39, "tosc_16kck_65msx39", "transceiver osc; startup time: 16384 CK + 65 ms"}, + {0x3a, "tosc_1kck_4ms1x3a", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, + {0x3b, "tosc_16kck_65msx3b", "transceiver osc; startup time: 16384 CK + 65 ms"}, + {0x3c, "tosc_1kck_4ms1x3c", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, + {0x3d, "tosc_16kck_65msx3d", "transceiver osc; startup time: 16384 CK + 65 ms"}, + {0x3e, "tosc_1kck_4ms1x3e", "transceiver osc; startup time: 1024 CK + 4.1 ms"}, + {0x3f, "tosc_16kck_65msx3f", "transceiver osc; startup time: 16384 CK + 65 ms"}, +}; + +// ATmega324PB ATmega48PB ATmega88PB ATmega168PB ATmega328PB +static const Configvalue _values_sut_cksel_atmega324pb[47] = { + {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x03, "intrcosc_128khz_6ck_14ck_0ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x04, "extlofxtal_1kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x05, "extlofxtal_32kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 0 ms"}, + {0x08, "extxosc_0mhz4_0mhz9_258ck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x09, "extxosc_0mhz4_0mhz9_1kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0a, "extxosc_0mhz9_3mhz_258ck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0b, "extxosc_0mhz9_3mhz_1kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0c, "extxosc_3mhz_8mhz_258ck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0d, "extxosc_3mhz_8mhz_1kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0e, "extxosc_8mhz_xx_258ck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0f, "extxosc_8mhz_xx_1kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x10, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x12, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x13, "intrcosc_128khz_6ck_14ck_4ms1", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x14, "extlofxtal_1kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x15, "extlofxtal_32kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 4.1 ms"}, + {0x18, "extxosc_0mhz4_0mhz9_258ck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1a, "extxosc_0mhz9_3mhz_258ck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1c, "extxosc_3mhz_8mhz_258ck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1e, "extxosc_8mhz_xx_258ck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x20, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x22, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x23, "intrcosc_128khz_6ck_14ck_65ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x24, "extlofxtal_1kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x25, "extlofxtal_32kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 65 ms"}, + {0x28, "extxosc_0mhz4_0mhz9_1kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2a, "extxosc_0mhz9_3mhz_1kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2c, "extxosc_3mhz_8mhz_1kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2e, "extxosc_8mhz_xx_1kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x38, "extxosc_0mhz4_0mhz9_1kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3a, "extxosc_0mhz9_3mhz_1kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3c, "extxosc_3mhz_8mhz_1kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3e, "extxosc_8mhz_xx_1kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, +}; + /* - * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega169 ATmega169A ATmega169P ATmega169PA - * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega329 ATmega329A ATmega329P ATmega329PA - * ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P ATmega3250 ATmega3250A - * ATmega3250P ATmega3250PA ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A - * ATmega6450P ATmega6490 ATmega6490A ATmega6490P + * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA + * ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 + * ATmega6450A ATmega6450P ATmega169 ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A + * ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A ATmega3290P + * ATmega3290PA ATmega6490 ATmega6490A ATmega6490P */ static const Configvalue _values_sut_cksel_atmega165[44] = { {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, @@ -9837,6 +10445,68 @@ static const Configvalue _values_sut_cksel_atmega165[44] = { {0x3f, "extxosc_8mhz_xx_16kck_65ms", "ext crystal osc 8.0+ MHz; startup time: 16384 CK + 65 ms"}, }; +/* + * ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 + * ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P ATA6612C ATA6613C ATA6614Q + */ +static const Configvalue _values_sut_cksel_atmega48[55] = { + {0x00, "extclk_6ck_14ck_0ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x02, "intrcosc_8mhz_6ck_14ck_0ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x03, "intrcosc_128khz_6ck_14ck_0ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {0x04, "extlofxtal_1kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x05, "extlofxtal_32kck_14ck_0ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 0 ms"}, + {0x06, "extfsxtal_258ck_14ck_4ms1", "ext full-swing crystal; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x07, "extfsxtal_1kck_14ck_65ms", "ext full-swing crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x08, "extxosc_0mhz4_0mhz9_258ck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x09, "extxosc_0mhz4_0mhz9_1kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0a, "extxosc_0mhz9_3mhz_258ck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0b, "extxosc_0mhz9_3mhz_1kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0c, "extxosc_3mhz_8mhz_258ck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0d, "extxosc_3mhz_8mhz_1kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x0e, "extxosc_8mhz_xx_258ck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms"}, + {0x0f, "extxosc_8mhz_xx_1kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x10, "extclk_6ck_14ck_4ms1", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x12, "intrcosc_8mhz_6ck_14ck_4ms1", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x13, "intrcosc_128khz_6ck_14ck_4ms1", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms"}, + {0x14, "extlofxtal_1kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x15, "extlofxtal_32kck_14ck_4ms1", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 4.1 ms"}, + {0x16, "extfsxtal_258ck_14ck_65ms", "ext full-swing crystal; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x17, "extfsxtal_16kck_14ck_0ms", "ext full-swing crystal; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x18, "extxosc_0mhz4_0mhz9_258ck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x19, "extxosc_0mhz4_0mhz9_16kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1a, "extxosc_0mhz9_3mhz_258ck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1b, "extxosc_0mhz9_3mhz_16kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1c, "extxosc_3mhz_8mhz_258ck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1d, "extxosc_3mhz_8mhz_16kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x1e, "extxosc_8mhz_xx_258ck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 258 CK/14 CK + 65 ms"}, + {0x1f, "extxosc_8mhz_xx_16kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 0 ms"}, + {0x20, "extclk_6ck_14ck_65ms", "ext clock; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x22, "intrcosc_8mhz_6ck_14ck_65ms", "int RC osc 8 MHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x23, "intrcosc_128khz_6ck_14ck_65ms", "int RC osc 128 kHz; startup time PWRDWN/RESET: 6 CK/14 CK + 65 ms"}, + {0x24, "extlofxtal_1kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 65 ms"}, + {0x25, "extlofxtal_32kck_14ck_65ms", "ext low-freq crystal; startup time PWRDWN/RESET: 32768 CK/14 CK + 65 ms"}, + {0x26, "extfsxtal_1kck_14ck_0ms", "ext full-swing crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x27, "extfsxtal_16kck_14ck_4ms1", "ext full-swing crystal; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x28, "extxosc_0mhz4_0mhz9_1kck_14ck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x29, "extxosc_0mhz4_0mhz9_16kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2a, "extxosc_0mhz9_3mhz_1kck_14ck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2b, "extxosc_0mhz9_3mhz_16kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2c, "extxosc_3mhz_8mhz_1kck_14ck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2d, "extxosc_3mhz_8mhz_16kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x2e, "extxosc_8mhz_xx_1kck_14ck_0ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 0 ms"}, + {0x2f, "extxosc_8mhz_xx_16kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 4.1 ms"}, + {0x36, "extfsxtal_1kck_14ck_4ms1", "ext full-swing crystal; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x37, "extfsxtal_16kck_14ck_65ms", "ext full-swing crystal; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x38, "extxosc_0mhz4_0mhz9_1kck_14ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x39, "extxosc_0mhz4_0mhz9_16kck_14ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3a, "extxosc_0mhz9_3mhz_1kck_14ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3b, "extxosc_0mhz9_3mhz_16kck_14ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3c, "extxosc_3mhz_8mhz_1kck_14ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3d, "extxosc_3mhz_8mhz_16kck_14ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, + {0x3e, "extxosc_8mhz_xx_1kck_14ck_4ms1", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 1024 CK/14 CK + 4.1 ms"}, + {0x3f, "extxosc_8mhz_xx_16kck_14ck_65ms", "ext crystal osc 8.0+ MHz; startup time PWRDWN/RESET: 16384 CK/14 CK + 65 ms"}, +}; + // ATmega406 static const Configvalue _values_sut_cksel_atmega406[6] = { {0, "sut_14ck_0msx00", "startup time: 14 CK + 0 ms"}, @@ -9847,333 +10517,76 @@ static const Configvalue _values_sut_cksel_atmega406[6] = { {5, "sut_14ck_62ms5x05", "startup time: 14 CK + 62.5 ms"}, }; -// AT90CAN32 AT90CAN64 -static const Configvalue _values_sut_cksel_at90can32[38] = { - {0x00, "extclk_6ck_0ms", "ext clock; startup time: 6 CK + 0 ms"}, - {0x02, "intrcosc_6ck_0ms", "int RC osc; startup time: 6 CK + 0 ms"}, - {0x04, "extlofxtal_1kck_0ms", "ext low-freq crystal; startup time: 1024 CK + 0 ms"}, - {0x05, "extlofxtal_32kck_0ms", "ext low-freq crystal; startup time: 32768 CK + 0 ms"}, - {0x06, "extlofxtal_1kck_0ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 0 ms; int cap"}, - {0x07, "extlofxtal_32kck_0ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 0 ms; int cap"}, - {0x08, "extxosc_0mhz4_0mhz9_258ck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 4.1 ms"}, - {0x09, "extxosc_0mhz4_0mhz9_1kck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 65 ms"}, - {0x0a, "extxosc_0mhz9_3mhz_258ck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 4.1 ms"}, - {0x0b, "extxosc_0mhz9_3mhz_1kck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 65 ms"}, - {0x0c, "extxosc_3mhz_8mhz_258ck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 4.1 ms"}, - {0x0d, "extxosc_3mhz_8mhz_1kck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 65 ms"}, - {0x0e, "extxosc_8mhz_16mhz_258ck_4ms1", "ext crystal osc 8.0-16.0 MHz; startup time: 258 CK + 4.1 ms"}, - {0x0f, "extxosc_8mhz_16mhz_1kck_65ms", "ext crystal osc 8.0-16.0 MHz; startup time: 1024 CK + 65 ms"}, - {0x10, "extclk_6ck_4ms1", "ext clock; startup time: 6 CK + 4.1 ms"}, - {0x12, "intrcosc_6ck_4ms1", "int RC osc; startup time: 6 CK + 4.1 ms"}, - {0x14, "extlofxtal_1kck_4ms1", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms"}, - {0x15, "extlofxtal_32kck_4ms1", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms"}, - {0x16, "extlofxtal_1kck_4ms1_intcap", "ext low-freq crystal; startup time: 1024 CK + 4.1 ms; int cap"}, - {0x17, "extlofxtal_32kck_4ms1_intcap", "ext low-freq crystal; startup time: 32768 CK + 4.1 ms; int cap"}, - {0x18, "extxosc_0mhz4_0mhz9_258ck_65ms", "ext crystal osc 0.4-0.9 MHz; startup time: 258 CK + 65 ms"}, - {0x1a, "extxosc_0mhz9_3mhz_258ck_65ms", "ext crystal osc 0.9-3.0 MHz; startup time: 258 CK + 65 ms"}, - {0x1c, "extxosc_3mhz_8mhz_258ck_65ms", "ext crystal osc 3.0-8.0 MHz; startup time: 258 CK + 65 ms"}, - {0x1e, "extxosc_8mhz_16mhz_258ck_65ms", "ext crystal osc 8.0-16.0 MHz; startup time: 258 CK + 65 ms"}, - {0x20, "extclk_6ck_65ms", "ext clock; startup time: 6 CK + 65 ms"}, - {0x22, "intrcosc_6ck_65ms", "int RC osc; startup time: 6 CK + 65 ms"}, - {0x24, "extlofxtal_1kck_65ms", "ext low-freq crystal; startup time: 1024 CK + 65 ms"}, - {0x25, "extlofxtal_32kck_65ms", "ext low-freq crystal; startup time: 32768 CK + 65 ms"}, - {0x26, "extlofxtal_1kck_65ms_intcap", "ext low-freq crystal; startup time: 1024 CK + 65 ms; int cap"}, - {0x27, "extlofxtal_32kck_65ms_intcap", "ext low-freq crystal; startup time: 32768 CK + 65 ms; int cap"}, - {0x28, "extxosc_0mhz4_0mhz9_1kck_0ms", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 0 ms"}, - {0x2a, "extxosc_0mhz9_3mhz_1kck_0ms", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 0 ms"}, - {0x2c, "extxosc_3mhz_8mhz_1kck_0ms", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 0 ms"}, - {0x2e, "extxosc_8mhz_16mhz_1kck_0ms", "ext crystal osc 8.0-16.0 MHz; startup time: 1024 CK + 0 ms"}, - {0x38, "extxosc_0mhz4_0mhz9_1kck_4ms1", "ext crystal osc 0.4-0.9 MHz; startup time: 1024 CK + 4.1 ms"}, - {0x3a, "extxosc_0mhz9_3mhz_1kck_4ms1", "ext crystal osc 0.9-3.0 MHz; startup time: 1024 CK + 4.1 ms"}, - {0x3c, "extxosc_3mhz_8mhz_1kck_4ms1", "ext crystal osc 3.0-8.0 MHz; startup time: 1024 CK + 4.1 ms"}, - {0x3e, "extxosc_8mhz_16mhz_1kck_4ms1", "ext crystal osc 8.0-16.0 MHz; startup time: 1024 CK + 4.1 ms"}, -}; - -// AT90S2333 AT90S4433 -static const Configvalue _values_sut_cksel_at90s2333[8] = { - {0, "extclk_slowpwr", "ext clock; slowly rising power"}, - {1, "extclk_boden_por", "ext clock; brownout detection or power-on reset"}, - {2, "xosc", "crystal osc"}, - {3, "xosc_fastpwr", "crystal osc; fast rising power"}, - {4, "xosc_boden_por", "crystal osc; brownout detection or power-on reset"}, - {5, "cres", "ceramic resonator"}, - {6, "cres_fastpwr", "ceramic res; fast rising power"}, - {7, "cres_boden_por", "ceramic res; brownout detection or power-on reset"}, +// ATA6285 ATA6286 ATA6289 +static const Configvalue _values_sut_cksel_ata6285[3] = { + {0, "sut_6ck_14ck_0ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 0 ms"}, + {1, "sut_6ck_14ck_5ms7", "startup time PWRDWN/RESET: 6 CK/14 CK + 5.7 ms"}, + {2, "sut_6ck_14ck_90ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 90 ms"}, }; /* - * ATmega328 ATmega328PB ATmega161comp ATtiny48 ATtiny88 ATmega48 ATmega48A ATmega48P ATmega48PA - * ATmega48PB ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega162 ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega328P ATA6612C ATA6613C ATA6614Q + * AT90S2333 AT90S4433 AT90S8515comp AT90S8535comp ATtiny12 ATtiny15 ATtiny26 ATmega8 ATmega8A + * ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 + * ATmega163 ATmega323 ATmega8515 ATmega8535 ATmega103comp ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATA6285 ATA6286 ATA6289 */ -static const Configvalue _values_ckout_atmega328[2] = { - {0, "gpio_pb0", "clock output on GPIO PB0"}, - {1, "co_disabled", "clock signal is not output on a pin"}, +static const Configvalue _values_boden_at90s2333[2] = { + {0, "bod_enabled", "brownout detection enabled"}, + {1, "bod_disabled", "brownout detection disabled"}, +}; + +// AT90SCR100 AT90SCR100H +static const Configvalue _values_boden_at90scr100[2] = { + {0, "bod_disabled", "brownout detection disabled"}, + {1, "bod_enabled", "brownout detection enabled"}, }; /* - * ATmega16M1 AT90PWM2 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 AT90PWM1 AT90PWM2B - * AT90PWM3 AT90PWM3B AT90PWM216 AT90PWM316 + * AT90S8515comp AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 + * AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny828 ATtiny828R ATmega8 ATmega8A + * ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 + * ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 + * ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 + * ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161 ATmega161comp ATmega1281 ATmega2561 + * ATmega162 ATmega163 ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 + * ATmega328P ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5700M322 ATA5702M322 ATA5781 ATA5782 ATA5783 ATA5787 ATA5831 ATA5832 ATA5833 + * ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 ATA8515 + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A1U ATxmega128A1U + * ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B ATxmega64A3U ATxmega128A3U + * ATxmega192A3U ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 + * ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 ATxmega8E5 ATxmega16E5 + * ATxmega32E5 */ -static const Configvalue _values_ckout_atmega16m1[2] = { - {0, "gpio_pd1", "clock output on GPIO PD1"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -/* - * ATtiny102 AT90SCR100H ATtiny104 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P - * ATmega324PA ATmega324PB ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P - * AT90SCR100 - */ -static const Configvalue _values_ckout_attiny102[2] = { - {0, "gpio_pb1", "clock output on GPIO PB1"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -/* - * ATtiny441 ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 ATtiny24 ATtiny24A ATtiny44 ATtiny44A - * ATtiny84 ATtiny84A ATtiny841 - */ -static const Configvalue _values_ckout_attiny441[2] = { - {0, "gpio_pb2", "clock output on GPIO PB2"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -// AT90PWM81 AT90PWM161 -static const Configvalue _values_ckout_at90pwm81[2] = { - {0, "gpio_pd0", "clock output on GPIO PD0"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -/* - * AT90CAN128 AT90USB162 ATmega8U2 ATmega16U2 ATmega16U4 ATmega32U2 ATmega32U4 ATmega32U6 AT90CAN32 - * AT90CAN64 AT90USB82 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - */ -static const Configvalue _values_ckout_at90can128[2] = { - {0, "gpio_pc7", "clock output on GPIO PC7"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -// ATA6285 ATtiny828 ATtiny828R ATA6286 ATA6289 -static const Configvalue _values_ckout_ata6285[2] = { - {0, "gpio_pc1", "clock output on GPIO PC1"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -// ATtiny40 ATtiny1634 ATtiny1634R -static const Configvalue _values_ckout_attiny40[2] = { - {0, "gpio_pc2", "clock output on GPIO PC2"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -// ATtiny25 ATtiny45 ATtiny85 -static const Configvalue _values_ckout_attiny25[2] = { - {0, "gpio_pb4", "clock output on GPIO PB4"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -// ATtiny43U -static const Configvalue _values_ckout_attiny43u[2] = { - {0, "gpio_pb3", "clock output on GPIO PB3"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -/* - * ATtiny87 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A ATA5272 - * ATA5505 ATA6616C ATA6617C ATA664251 - */ -static const Configvalue _values_ckout_attiny87[2] = { - {0, "gpio_pb5", "clock output on GPIO PB5"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -// ATtiny2313 ATtiny2313A ATtiny4313 -static const Configvalue _values_ckout_attiny2313[2] = { - {0, "gpio_pd2", "clock output on GPIO PD2"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -/* - * ATmega64RFR2 ATmega128RFA1 ATmega128RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA ATmega169 - * ATmega169A ATmega169P ATmega169PA ATmega256RFR2 ATmega325 ATmega325A ATmega325P ATmega325PA - * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega640 ATmega644RFR2 ATmega645 ATmega645A - * ATmega645P ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284RFR2 ATmega2560 - * ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P - */ -static const Configvalue _values_ckout_atmega64rfr2[2] = { - {0, "gpio_pe7", "clock output on GPIO PE7"}, - {1, "co_disabled", "clock signal is not output on a pin"}, -}; - -/* - * ATmega328 ATmega16M1 ATmega64HVE ATmega328PB ATtiny441 AT90PWM2 AT90PWM81 AT90CAN128 AT90USB162 - * ATA5781 ATA5790 ATA6285 ATmega161comp ATtiny13 ATtiny13A ATtiny24 ATtiny24A ATtiny25 ATtiny43U - * ATtiny44 ATtiny44A ATtiny45 ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny87 ATtiny88 ATtiny167 - * ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny828 ATtiny828R ATtiny841 ATtiny861 ATtiny861A - * ATtiny1634 ATtiny1634R ATtiny2313 ATtiny2313A ATtiny4313 ATmega8U2 ATmega16HVB ATmega16U2 - * ATmega16U4 ATmega32HVB ATmega32C1 ATmega32M1 ATmega32U2 ATmega32U4 ATmega32U6 ATmega48 - * ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega64C1 ATmegaS64M1 ATmega64M1 ATmega64HVE2 - * ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega128RFA1 ATmega128RFR2 - * ATmega162 ATmega164A ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA - * ATmega168 ATmega168A ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P - * ATmega169PA ATmega256RFR2 ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A - * ATmega325P ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P - * ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 - * ATmega2560 ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 AT90PWM161 - * AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 ATA5272 ATA5505 ATA5782 - * ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 ATA6286 ATA6289 - * ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA8210 ATA8215 ATA8510 ATA8515 ATA664251 - * ATmega32HVE2 - */ -static const Configvalue _values_ckdiv8_atmega328[2] = { - {0, "by_8", "F_CPU prescaled by 8"}, - {1, "by_1", "F_CPU prescaled by 1"}, -}; - -/* - * ATmega328 ATmega16M1 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 AT90PWM2 AT90PWM81 - * AT90CAN128 AT90USB162 ATA5700M322 ATA5781 ATA6285 ATxmega16E5 ATxmega192A1 ATxmega256A1 - * ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 ATmega103comp AT90SCR100H ATmega161comp - * AT90S8535comp ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega8U2 ATmega16 ATmega16A ATmega16HVB - * ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega128 - * ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A - * ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 - * ATmega323 ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P - * ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P - * ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 - * ATmega2560 ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 - * AT90SCR100 AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - * AT90S8515comp ATA5702M322 ATA5782 ATA5783 ATA5787 ATA5831 ATA5832 ATA5833 ATA5835 ATA6286 - * ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 ATA8515 ATxmega8E5 ATxmega16A4 - * ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 ATxmega32D3 ATxmega32A4 ATxmega32A4U - * ATxmega32C4 ATxmega32D4 ATxmega32E5 ATxmega64A1 ATxmega64A1U ATxmega64B1 ATxmega64A3 - * ATxmega64A3U ATxmega64B3 ATxmega64C3 ATxmega64D3 ATxmega64A4U ATxmega64D4 ATxmega128A1 - * ATxmega128A1revD ATxmega128A1U ATxmega128B1 ATxmega128B3 ATxmega128C3 ATxmega128D3 - * ATxmega128A4U ATxmega128D4 ATxmega192A3 ATxmega192A3U ATxmega192C3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3BU ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 ATxmega384D3 - * ATmega32HVE2 - */ -static const Configvalue _values_bootrst_atmega328[2] = { +static const Configvalue _values_bootrst_at90s8515comp[2] = { {0, "boot_section", "reset jumps to start of boot section"}, {1, "application", "reset jumps to start of memory"}, }; /* - * ATmega328 ATmega32HVBrevB ATmega328PB ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega32U4 ATmega32U6 ATmega323 ATmega324A ATmega324P ATmega324PA ATmega324PB - * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P - * ATmega329PA ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A ATmega3290P - * ATmega3290PA ATA6614Q + * AT90S8515comp AT90S8535comp AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM3 AT90PWM3B + * ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega8515 ATmega8535 ATmega88 ATmega88A ATmega88P + * ATmega88PA ATmega88PB ATA6612C */ -static const Configvalue _values_bootsz_atmega328[4] = { - {0, "bs_2048w", "boot size 4096 bytes; boot address 0x7000"}, - {1, "bs_1024w", "boot size 2048 bytes; boot address 0x7800"}, - {2, "bs_512w", "boot size 1024 bytes; boot address 0x7c00"}, - {3, "bs_256w", "boot size 512 bytes; boot address 0x7e00"}, -}; - -/* - * ATmega16M1 AT90USB162 ATmega16HVB ATmega16HVBrevB ATmega16U2 ATmega16U4 AT90USB82 AT90PWM216 - * AT90PWM316 - */ -static const Configvalue _values_bootsz_atmega16m1[4] = { - {0, "bs_2048w", "boot size 4096 bytes; boot address 0x3000"}, - {1, "bs_1024w", "boot size 2048 bytes; boot address 0x3800"}, - {2, "bs_512w", "boot size 1024 bytes; boot address 0x3c00"}, - {3, "bs_256w", "boot size 512 bytes; boot address 0x3e00"}, -}; - -/* - * ATmega64HVE AT90SCR100H ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 ATmega64HVE2 - * ATmega64RFR2 ATmega640 ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 - * ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P ATmega6450 ATmega6450A ATmega6450P - * ATmega6490 ATmega6490A ATmega6490P AT90CAN64 AT90SCR100 ATmega32HVE2 - */ -static const Configvalue _values_bootsz_atmega64hve[4] = { - {0, "bs_4096w", "boot size 8192 bytes; boot address 0xe000"}, - {1, "bs_2048w", "boot size 4096 bytes; boot address 0xf000"}, - {2, "bs_1024w", "boot size 2048 bytes; boot address 0xf800"}, - {3, "bs_512w", "boot size 1024 bytes; boot address 0xfc00"}, -}; - -/* - * ATmega8515 AT90PWM2 AT90PWM81 AT90S8535comp ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega88 - * ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B - * AT90PWM161 AT90S8515comp ATA6612C - */ -static const Configvalue _values_bootsz_atmega8515[4] = { +static const Configvalue _values_bootsz_at90s8515comp[4] = { {0, "bs_1024w", "boot size 2048 bytes; boot address 0x1800"}, {1, "bs_512w", "boot size 1024 bytes; boot address 0x1c00"}, {2, "bs_256w", "boot size 512 bytes; boot address 0x1e00"}, {3, "bs_128w", "boot size 256 bytes; boot address 0x1f00"}, }; -/* - * AT90CAN128 ATmega103comp ATmega128 ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega1280 - * ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 AT90USB1286 AT90USB1287 - */ -static const Configvalue _values_bootsz_at90can128[4] = { - {0, "bs_4096w", "boot size 8192 bytes; boot address 0x1e000"}, - {1, "bs_2048w", "boot size 4096 bytes; boot address 0x1f000"}, - {2, "bs_1024w", "boot size 2048 bytes; boot address 0x1f800"}, - {3, "bs_512w", "boot size 1024 bytes; boot address 0x1fc00"}, -}; - -// ATA6285 ATA6286 ATA6289 -static const Configvalue _values_bootsz_ata6285[4] = { - {0, "bs_1024w", "boot size 2048 bytes"}, - {1, "bs_512w", "boot size 1024 bytes"}, - {2, "bs_256w", "boot size 512 bytes"}, - {3, "bs_128w", "boot size 256 bytes"}, -}; - -/* - * ATmega161comp ATmega16 ATmega16A ATmega162 ATmega163 ATmega164A ATmega164P ATmega164PA ATmega165 - * ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega168PB - * ATmega169 ATmega169A ATmega169P ATmega169PA ATA6613C - */ -static const Configvalue _values_bootsz_atmega161comp[4] = { - {0, "bs_1024w", "boot size 2048 bytes; boot address 0x3800"}, - {1, "bs_512w", "boot size 1024 bytes; boot address 0x3c00"}, - {2, "bs_256w", "boot size 512 bytes; boot address 0x3e00"}, - {3, "bs_128w", "boot size 256 bytes; boot address 0x3f00"}, -}; - -// ATmega8U2 -static const Configvalue _values_bootsz_atmega8u2[4] = { - {0, "bs_2048w", "boot size 4096 bytes; boot address 0x1000"}, - {1, "bs_1024w", "boot size 2048 bytes; boot address 0x1800"}, - {2, "bs_512w", "boot size 1024 bytes; boot address 0x1c00"}, - {3, "bs_256w", "boot size 512 bytes; boot address 0x1e00"}, -}; - -// ATmega256RFR2 ATmega2560 ATmega2561 ATmega2564RFR2 -static const Configvalue _values_bootsz_atmega256rfr2[4] = { - {0, "bs_4096w", "boot size 8192 bytes; boot address 0x3e000"}, - {1, "bs_2048w", "boot size 4096 bytes; boot address 0x3f000"}, - {2, "bs_1024w", "boot size 2048 bytes; boot address 0x3f800"}, - {3, "bs_512w", "boot size 1024 bytes; boot address 0x3fc00"}, -}; - -// ATmega406 -static const Configvalue _values_bootsz_atmega406[4] = { - {0, "bs_2048w", "boot size 4096 bytes; boot address 0x9000"}, - {1, "bs_1024w", "boot size 2048 bytes; boot address 0x9800"}, - {2, "bs_512w", "boot size 1024 bytes; boot address 0x9c00"}, - {3, "bs_256w", "boot size 512 bytes; boot address 0x9e00"}, -}; - // AT90CAN32 static const Configvalue _values_bootsz_at90can32[4] = { {0, "bs_4096w", "boot size 8192 bytes; boot address 0x6000"}, @@ -10182,6 +10595,41 @@ static const Configvalue _values_bootsz_at90can32[4] = { {3, "bs_512w", "boot size 1024 bytes; boot address 0x7c00"}, }; +/* + * AT90CAN64 AT90SCR100 AT90SCR100H ATmega64 ATmega64A ATmega640 ATmega64C1 ATmega64M1 ATmegaS64M1 + * ATmega64RFR2 ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A + * ATmega645P ATmega6450 ATmega6450A ATmega6450P ATmega649 ATmega649A ATmega649P ATmega6490 + * ATmega6490A ATmega6490P ATmega64HVE ATmega32HVE2 ATmega64HVE2 + */ +static const Configvalue _values_bootsz_at90can64[4] = { + {0, "bs_4096w", "boot size 8192 bytes; boot address 0xe000"}, + {1, "bs_2048w", "boot size 4096 bytes; boot address 0xf000"}, + {2, "bs_1024w", "boot size 2048 bytes; boot address 0xf800"}, + {3, "bs_512w", "boot size 1024 bytes; boot address 0xfc00"}, +}; + +/* + * AT90CAN128 AT90USB1286 AT90USB1287 ATmega128 ATmega128A ATmegaS128 ATmega1280 ATmega128RFA1 + * ATmega128RFR2 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega103comp + */ +static const Configvalue _values_bootsz_at90can128[4] = { + {0, "bs_4096w", "boot size 8192 bytes; boot address 0x1e000"}, + {1, "bs_2048w", "boot size 4096 bytes; boot address 0x1f000"}, + {2, "bs_1024w", "boot size 2048 bytes; boot address 0x1f800"}, + {3, "bs_512w", "boot size 1024 bytes; boot address 0x1fc00"}, +}; + +/* + * AT90PWM216 AT90PWM316 AT90USB82 AT90USB162 ATmega16M1 ATmega16U2 ATmega16U4 ATmega16HVB + * ATmega16HVBrevB + */ +static const Configvalue _values_bootsz_at90pwm216[4] = { + {0, "bs_2048w", "boot size 4096 bytes; boot address 0x3000"}, + {1, "bs_1024w", "boot size 2048 bytes; boot address 0x3800"}, + {2, "bs_512w", "boot size 1024 bytes; boot address 0x3c00"}, + {3, "bs_256w", "boot size 512 bytes; boot address 0x3e00"}, +}; + // AT90USB646 AT90USB647 static const Configvalue _values_bootsz_at90usb646[4] = { {0, "bs_4096w", "boot size 8192 bytes; boot address 0xf000"}, @@ -10191,597 +10639,167 @@ static const Configvalue _values_bootsz_at90usb646[4] = { }; /* - * ATmega328 ATmega16M1 ATmega16HVA2 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 ATtiny441 - * AT90PWM2 AT90PWM81 AT90CAN128 AT90USB162 ATA5700M322 ATA5781 ATA5790 ATA6285 ATxmega16E5 - * ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 ATmega103comp - * AT90SCR100H ATmega161comp AT90S8535comp ATtiny13 ATtiny13A ATtiny24 ATtiny24A ATtiny25 ATtiny26 - * ATtiny43U ATtiny44 ATtiny44A ATtiny45 ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny87 ATtiny88 - * ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny828 ATtiny828R ATtiny841 ATtiny861 - * ATtiny861A ATtiny1634 ATtiny1634R ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega8HVA - * ATmega8U2 ATmega16 ATmega16A ATmega16HVA ATmega16HVB ATmega16HVBrevB ATmega16U2 ATmega16U4 - * ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 ATmega32U2 ATmega32U4 ATmega32U6 ATmega48 - * ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega103 - * ATmega128 ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega162 ATmega164A ATmega164P - * ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A ATmega168P - * ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 ATmega323 - * ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA - * ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 ATmega644 ATmega644A - * ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A - * ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega2560 ATmega2561 - * ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A - * ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - * ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 AT90SCR100 - * AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 AT90S8515comp - * ATA5272 ATA5505 ATA5702M322 ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 - * ATA5833 ATA5835 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA8210 ATA8215 - * ATA8510 ATA8515 ATA664251 ATxmega8E5 ATxmega16A4 ATxmega16A4U ATxmega16C4 ATxmega16D4 - * ATxmega32C3 ATxmega32D3 ATxmega32A4 ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega32E5 - * ATxmega64A1 ATxmega64A1U ATxmega64B1 ATxmega64A3 ATxmega64A3U ATxmega64B3 ATxmega64C3 - * ATxmega64D3 ATxmega64A4U ATxmega64D4 ATxmega128A1 ATxmega128A1revD ATxmega128A1U ATxmega128B1 - * ATxmega128B3 ATxmega128C3 ATxmega128D3 ATxmega128A4U ATxmega128D4 ATxmega192A3 ATxmega192A3U - * ATxmega192C3 ATxmega192D3 ATxmega256A3 ATxmega256A3B ATxmega256A3BU ATxmega256A3U ATxmega256C3 - * ATxmega256D3 ATxmega384C3 ATxmega384D3 ATmega32HVE2 + * ATmega16 ATmega16A ATmega161comp ATmega162 ATmega163 ATmega164A ATmega164P ATmega164PA ATmega165 + * ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega168PB + * ATmega169 ATmega169A ATmega169P ATmega169PA ATA6613C */ -static const Configvalue _values_eesave_atmega328[2] = { +static const Configvalue _values_bootsz_atmega16[4] = { + {0, "bs_1024w", "boot size 2048 bytes; boot address 0x3800"}, + {1, "bs_512w", "boot size 1024 bytes; boot address 0x3c00"}, + {2, "bs_256w", "boot size 512 bytes; boot address 0x3e00"}, + {3, "bs_128w", "boot size 256 bytes; boot address 0x3f00"}, +}; + +/* + * ATmega32 ATmega32A ATmega32C1 ATmega32M1 ATmega32U2 ATmega32U4 ATmega32U6 ATmega323 ATmega324A + * ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega328 ATmega328P ATmega328PB ATmega329 ATmega329A + * ATmega329P ATmega329PA ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega32HVB + * ATmega32HVBrevB ATA6614Q + */ +static const Configvalue _values_bootsz_atmega32[4] = { + {0, "bs_2048w", "boot size 4096 bytes; boot address 0x7000"}, + {1, "bs_1024w", "boot size 2048 bytes; boot address 0x7800"}, + {2, "bs_512w", "boot size 1024 bytes; boot address 0x7c00"}, + {3, "bs_256w", "boot size 512 bytes; boot address 0x7e00"}, +}; + +// ATmega2560 ATmega256RFR2 ATmega2561 ATmega2564RFR2 +static const Configvalue _values_bootsz_atmega2560[4] = { + {0, "bs_4096w", "boot size 8192 bytes; boot address 0x3e000"}, + {1, "bs_2048w", "boot size 4096 bytes; boot address 0x3f000"}, + {2, "bs_1024w", "boot size 2048 bytes; boot address 0x3f800"}, + {3, "bs_512w", "boot size 1024 bytes; boot address 0x3fc00"}, +}; + +// ATmega8U2 +static const Configvalue _values_bootsz_atmega8u2[4] = { + {0, "bs_2048w", "boot size 4096 bytes; boot address 0x1000"}, + {1, "bs_1024w", "boot size 2048 bytes; boot address 0x1800"}, + {2, "bs_512w", "boot size 1024 bytes; boot address 0x1c00"}, + {3, "bs_256w", "boot size 512 bytes; boot address 0x1e00"}, +}; + +// ATmega406 +static const Configvalue _values_bootsz_atmega406[4] = { + {0, "bs_2048w", "boot size 4096 bytes; boot address 0x9000"}, + {1, "bs_1024w", "boot size 2048 bytes; boot address 0x9800"}, + {2, "bs_512w", "boot size 1024 bytes; boot address 0x9c00"}, + {3, "bs_256w", "boot size 512 bytes; boot address 0x9e00"}, +}; + +// ATA6285 ATA6286 ATA6289 +static const Configvalue _values_bootsz_ata6285[4] = { + {0, "bs_1024w", "boot size 2048 bytes"}, + {1, "bs_512w", "boot size 1024 bytes"}, + {2, "bs_256w", "boot size 512 bytes"}, + {3, "bs_128w", "boot size 256 bytes"}, +}; + +/* + * AT90S8515comp AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 + * AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny13 ATtiny13A ATtiny43U ATtiny24 + * ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A ATtiny25 ATtiny45 ATtiny85 ATtiny26 ATtiny87 + * ATtiny167 ATtiny48 ATtiny88 ATtiny828 ATtiny828R ATtiny1634 ATtiny1634R ATtiny441 ATtiny841 + * ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A ATtiny2313 ATtiny2313A + * ATtiny4313 ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 + * ATmega128A ATmegaS128 ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 ATmega16M1 + * ATmega32M1 ATmega64M1 ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 + * ATmega8U2 ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161comp ATmega1281 + * ATmega2561 ATmega162 ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 + * ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P ATmega48PB ATmega88PB ATmega168PB + * ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P + * ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A ATmega3290P ATmega3290PA + * ATmega6490 ATmega6490A ATmega6490P ATmega103 ATmega103comp ATmega8HVA ATmega16HVA ATmega16HVA2 + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5272 ATA5505 ATA5700M322 ATA5702M322 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 + * ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C + * ATA6613C ATA6614Q ATA6616C ATA6617C ATA664251 ATA8210 ATA8215 ATA8510 ATA8515 ATxmega64A1 + * ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A1U ATxmega128A1U ATxmega64A3 + * ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B ATxmega64A3U ATxmega128A3U ATxmega192A3U + * ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 ATxmega16A4U + * ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 ATxmega128B3 + * ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 ATxmega16C4 + * ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 ATxmega384D3 + * ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 ATxmega8E5 ATxmega16E5 ATxmega32E5 + */ +static const Configvalue _values_eesave_at90s8515comp[2] = { {0, "ee_preserved", "EEPROM content is preserved during chip erase"}, {1, "ee_erased", "EEPROM content is erased during chip erase"}, }; /* - * ATtiny204 ATtiny1624 AVR32DD14 AVR64EA48 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 - * ATtiny406 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 - * ATtiny804 ATtiny806 ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 - * ATtiny1604 ATtiny1606 ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 - * ATtiny3216 ATtiny3217 ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 - * ATmega1609 ATmega3208 ATmega3209 ATmega4808 ATmega4809 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 - * AVR16DD20 AVR16DU20 AVR16EB20 AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 - * AVR16DD32 AVR16DU32 AVR16EA32 AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 - * AVR32DD20 AVR32DU20 AVR32EB20 AVR32LA20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 - * AVR32DU28 AVR32EA28 AVR32EB28 AVR32LA28 AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 - * AVR32DU32 AVR32EA32 AVR32EB32 AVR32LA32 AVR32SD32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 - * AVR64DD14 AVR64DD20 AVR64DA28 AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 - * AVR64DA32S AVR64DB32 AVR64DD32 AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 - * AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 - * AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S AVR128DB64 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 + * AVR64DA28S AVR64DA32 AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 + * AVR128DA28S AVR128DA32 AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 + * AVR32DB32 AVR32DB48 AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 + * AVR128DB64 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 + * AVR64DD14 AVR64DD20 AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 + * AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 + * AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 + * AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 + * AVR32LA20 AVR32LA28 AVR32LA32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_eesave_attiny204[2] = { +static const Configvalue _values_eesave_attiny202[2] = { {0, "eex_erased", "EEPROM content is erased during chip erase"}, {1, "eex_preserved", "EEPROM content is preserved during chip erase"}, }; /* - * ATmega328 ATmega16M1 ATmega16HVA2 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 ATtiny102 - * ATtiny441 AT90PWM2 AT90PWM81 AT90CAN128 AT90USB162 ATA5700M322 ATA5781 ATA5790 ATA6285 - * ATmega103comp AT90SCR100H ATmega161comp AT90S8535comp ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 - * ATtiny40 ATtiny104 ATtiny13 ATtiny13A ATtiny24 ATtiny24A ATtiny25 ATtiny43U ATtiny44 ATtiny44A - * ATtiny45 ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny87 ATtiny88 ATtiny167 ATtiny261 ATtiny261A - * ATtiny461 ATtiny461A ATtiny828 ATtiny828R ATtiny841 ATtiny861 ATtiny861A ATtiny1634 ATtiny1634R - * ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega8HVA ATmega8U2 ATmega16HVA ATmega16HVB - * ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32HVB ATmega32C1 ATmega32M1 ATmega32U2 ATmega32U4 - * ATmega32U6 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega64 ATmega64A ATmega64C1 - * ATmegaS64M1 ATmega64M1 ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA - * ATmega88PB ATmega128 ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega162 ATmega164A - * ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 - * ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA - * ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 ATmega644 ATmega644A - * ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A - * ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega2560 ATmega2561 - * ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A - * ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - * ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 AT90SCR100 - * AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 AT90S8515comp - * ATA5272 ATA5505 ATA5702M322 ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 - * ATA5833 ATA5835 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA8210 ATA8215 - * ATA8510 ATA8515 ATA664251 ATmega32HVE2 + * AT90S8515comp AT90S8535comp ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 + * ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega8515 ATmega8535 ATmega103comp */ -static const Configvalue _values_wdton_atmega328[2] = { - {0, "wdt_always_on", "watchdog timer always on"}, - {1, "wdt_programmable", "watchdog timer programmable"}, +static const Configvalue _values_ckopt_at90s8515comp[2] = { + {0, "full_railtorail", "oscillator swings full rail-to-rail"}, + {1, "less_than_full_railtorail", "oscillator swings less than full rail-to-rail"}, +}; + +// ATtiny26 +static const Configvalue _values_ckopt_attiny26[2] = { + {0, "int_caps_enabled", "internal capacitors on XTAL1 and XTAL2 enabled"}, + {1, "no_int_caps", "no internal capacitors on XTAL1 and XTAL2"}, +}; + +// AT90S8515comp ATmega8515 +static const Configvalue _values_s8515c_at90s8515comp[2] = { + {0, "c8515_enabled", "AT90S4414/8515 compatibility mode enabled"}, + {1, "c8515_disabled", "AT90S4414/8515 compatibility mode disabled"}, }; /* - * ATmega328 ATmega16M1 ATmega16HVA2 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 ATtiny441 - * AT90PWM2 AT90PWM81 AT90CAN128 AT90USB162 AT90S1200 AT90S2313 ATA5700M322 ATA5781 ATA5790 - * ATA6285 ATmega103comp AT90SCR100H ATmega161comp AT90S8535comp ATtiny12 ATtiny13 ATtiny13A - * ATtiny15 ATtiny22 ATtiny24 ATtiny24A ATtiny25 ATtiny26 ATtiny43U ATtiny44 ATtiny44A ATtiny45 - * ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny87 ATtiny88 ATtiny167 ATtiny261 ATtiny261A ATtiny461 - * ATtiny461A ATtiny828 ATtiny828R ATtiny841 ATtiny861 ATtiny861A ATtiny1634 ATtiny1634R - * ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega8HVA ATmega8U2 ATmega16 ATmega16A - * ATmega16HVA ATmega16HVB ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB - * ATmega32C1 ATmega32M1 ATmega32U2 ATmega32U4 ATmega32U6 ATmega48 ATmega48A ATmega48P ATmega48PA - * ATmega48PB ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 ATmega64HVE2 ATmega64RFR2 - * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega103 ATmega128 ATmegaS128 ATmega128A - * ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A ATmega164P ATmega164PA - * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A ATmega168P ATmega168PA - * ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 ATmega323 ATmega324A - * ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA ATmega328P - * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega640 ATmega644 ATmega644A ATmega644P - * ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P - * ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega2560 ATmega2561 - * ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A - * ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - * ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 AT90SCR100 - * AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 AT90S2323 - * AT90S2333 AT90S2343 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90S8515comp AT90S8535 ATA5272 - * ATA5505 ATA5702M322 ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 - * ATA5835 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA8210 ATA8215 ATA8510 - * ATA8515 ATA664251 ATmega32HVE2 + * AT90S8515comp AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 + * AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny828 ATtiny828R ATmega8 ATmega8A + * ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 + * ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 + * ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 + * ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161 ATmega161comp ATmega1281 ATmega2561 + * ATmega162 ATmega163 ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 + * ATmega328P ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 + * ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 + * ATA8515 */ -static const Configvalue _values_spien_atmega328[2] = { - {0, "isp_enabled", "serial programming enabled"}, - {1, "isp_disabled", "serial programming disabled"}, -}; - -/* - * ATmega328 ATmega16M1 ATmega16HVA2 ATmega32HVBrevB ATmega64HVE ATmega328PB ATtiny441 AT90PWM2 - * AT90PWM81 AT90USB162 ATA5700M322 ATA5781 ATA5790 ATA6285 ATtiny13 ATtiny13A ATtiny24 ATtiny24A - * ATtiny25 ATtiny43U ATtiny44 ATtiny44A ATtiny45 ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny87 - * ATtiny88 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny828 ATtiny828R ATtiny841 - * ATtiny861 ATtiny861A ATtiny1634 ATtiny1634R ATtiny2313 ATtiny2313A ATtiny4313 ATmega8HVA - * ATmega8U2 ATmega16HVA ATmega16HVB ATmega16HVBrevB ATmega16U2 ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega168 ATmega168A ATmega168P - * ATmega168PA ATmega168PB ATmega328P AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90USB82 AT90PWM161 - * AT90PWM216 AT90PWM316 ATA5272 ATA5505 ATA5702M322 ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 - * ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C - * ATA6617C ATA8210 ATA8215 ATA8510 ATA8515 ATA664251 ATmega32HVE2 - */ -static const Configvalue _values_dwen_atmega328[2] = { - {0, "dw_enabled", "debugWIRE enabled"}, - {1, "dw_off", "debugWIRE off"}, -}; - -/* - * ATmega328 ATmega328PB ATtiny48 ATtiny88 ATmega8 ATmega8A ATmega48 ATmega48A ATmega48P ATmega48PA - * ATmega48PB ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega168 ATmega168A ATmega168P - * ATmega168PA ATmega168PB ATmega328P ATA6612C ATA6613C ATA6614Q - */ -static const Configvalue _values_rstdisbl_atmega328[2] = { - {0, "gpio_pc6_warning_external_reset_disabled", "reset pin configured as GPIO PC6 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -/* - * ATmega16M1 AT90PWM2 AT90PWM81 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 AT90PWM1 - * AT90PWM2B AT90PWM3 AT90PWM3B AT90PWM161 AT90PWM216 AT90PWM316 - */ -static const Configvalue _values_rstdisbl_atmega16m1[2] = { - {0, "gpio_pe0_warning_external_reset_disabled", "reset pin configured as GPIO PE0 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// ATtiny102 ATtiny104 ATtiny2313 ATtiny2313A ATtiny4313 -static const Configvalue _values_rstdisbl_attiny102[2] = { - {0, "gpio_pa2_warning_external_reset_disabled", "reset pin configured as GPIO PA2 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -/* - * ATtiny441 ATtiny4 ATtiny5 ATtiny9 ATtiny10 ATtiny20 ATtiny24 ATtiny24A ATtiny44 ATtiny44A - * ATtiny84 ATtiny84A ATtiny841 - */ -static const Configvalue _values_rstdisbl_attiny441[2] = { - {0, "gpio_pb3_warning_external_reset_disabled", "reset pin configured as GPIO PB3 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 AT90USB82 -static const Configvalue _values_rstdisbl_at90usb162[2] = { - {0, "gpio_pc1_warning_external_reset_disabled", "reset pin configured as GPIO PC1 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// ATA5781 ATA5782 ATA5783 ATA5831 ATA5832 ATA5833 ATA5835 -static const Configvalue _values_rstdisbl_ata5781[2] = { - {0, "gpio_pc0_warning_external_reset_disabled", "reset pin configured as GPIO PC0 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -/* - * ATxmega16E5 ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 - * ATmega165 ATmega169 ATxmega8E5 ATxmega16A4 ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 - * ATxmega32D3 ATxmega32A4 ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega32E5 ATxmega64A1 - * ATxmega64A1U ATxmega64B1 ATxmega64A3 ATxmega64A3U ATxmega64B3 ATxmega64C3 ATxmega64D3 - * ATxmega64A4U ATxmega64D4 ATxmega128A1 ATxmega128A1revD ATxmega128A1U ATxmega128B1 ATxmega128B3 - * ATxmega128C3 ATxmega128D3 ATxmega128A4U ATxmega128D4 ATxmega192A3 ATxmega192A3U ATxmega192C3 - * ATxmega192D3 ATxmega256A3 ATxmega256A3B ATxmega256A3BU ATxmega256A3U ATxmega256C3 ATxmega256D3 - * ATxmega384C3 ATxmega384D3 - */ -static const Configvalue _values_rstdisbl_atxmega16e5[2] = { - {0, "rst_disabled", "external reset disabled"}, - {1, "rst_enabled", "external reset enabled"}, -}; - -// ATtiny40 ATtiny1634 ATtiny1634R -static const Configvalue _values_rstdisbl_attiny40[2] = { - {0, "gpio_pc3_warning_external_reset_disabled", "reset pin configured as GPIO PC3 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// ATtiny11 ATtiny12 ATtiny13 ATtiny13A ATtiny15 ATtiny25 ATtiny45 ATtiny85 -static const Configvalue _values_rstdisbl_attiny11[2] = { - {0, "gpio_pb5_warning_external_reset_disabled", "reset pin configured as GPIO PB5 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -/* - * ATtiny26 ATtiny87 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A - * ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 - */ -static const Configvalue _values_rstdisbl_attiny26[2] = { - {0, "gpio_pb7_warning_external_reset_disabled", "reset pin configured as GPIO PB7 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// ATtiny43U -static const Configvalue _values_rstdisbl_attiny43u[2] = { - {0, "gpio_pa7_warning_external_reset_disabled", "reset pin configured as GPIO PA7 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// ATtiny828 ATtiny828R -static const Configvalue _values_rstdisbl_attiny828[2] = { - {0, "gpio_pd2_warning_external_reset_disabled", "reset pin configured as GPIO PD2 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -/* - * ATmega165A ATmega165P ATmega165PA ATmega169A ATmega169P ATmega169PA ATmega325 ATmega325A - * ATmega325P ATmega325PA ATmega329 ATmega329A ATmega329P ATmega329PA ATmega645 ATmega645A - * ATmega645P ATmega649 ATmega649A ATmega649P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA - * ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 - * ATmega6490A ATmega6490P - */ -static const Configvalue _values_rstdisbl_atmega165a[2] = { - {0, "gpio_pg5_warning_external_reset_disabled", "reset pin configured as GPIO PG5 (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -// ATA5787 ATA8210 ATA8215 ATA8510 ATA8515 -static const Configvalue _values_rstdisbl_ata5787[2] = { - {0, "gpio_warning_external_reset_disabled", "reset pin configured as GPIO (warning: external reset disabled)"}, - {1, "external_reset", "reset pin configured as external reset"}, -}; - -/* - * ATmega328 ATmega328PB ATtiny20 ATtiny40 ATtiny24 ATtiny24A ATtiny25 ATtiny44 ATtiny44A ATtiny45 - * ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny88 ATtiny828 ATtiny828R ATtiny2313 ATtiny2313A - * ATtiny4313 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega88 ATmega88A ATmega88P - * ATmega88PA ATmega88PB ATmega164A ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P - * ATmega165PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A - * ATmega169P ATmega169PA ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega328P ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1280 ATmega1281 ATmega1284 ATmega1284P - * ATmega2560 ATmega2561 ATA6612C ATA6613C ATA6614Q - */ -static const Configvalue _values_bodlevel_atmega328[4] = { - {4, "bod_4v3", "brownout detection at 4.3 V"}, - {5, "bod_2v7", "brownout detection at 2.7 V"}, - {6, "bod_1v8", "brownout detection at 1.8 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -/* - * ATmega16M1 AT90PWM2 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 AT90PWM1 AT90PWM2B - * AT90PWM3 AT90PWM3B AT90PWM216 AT90PWM316 - */ -static const Configvalue _values_bodlevel_atmega16m1[8] = { - {0, "bod_2v6", "brownout detection at 2.6 V"}, - {1, "bod_2v8", "brownout detection at 2.8 V"}, - {2, "bod_4v2", "brownout detection at 4.2 V"}, - {3, "bod_4v4", "brownout detection at 4.4 V"}, - {4, "bod_4v3", "brownout detection at 4.3 V"}, - {5, "bod_2v7", "brownout detection at 2.7 V"}, - {6, "bod_4v5", "brownout detection at 4.5 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -/* - * ATmega8515 ATmega103comp AT90S8535comp ATtiny15 ATtiny26 ATmega8 ATmega8A ATmega16 ATmega16A - * ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmegaS128 ATmega128A ATmega163 ATmega323 - * ATmega8535 AT90S2333 AT90S4433 AT90S8515comp - */ -static const Configvalue _values_bodlevel_atmega8515[2] = { - {0, "bod_4v0", "brownout detection at 4.0 V"}, - {1, "bod_2v7", "brownout detection at 2.7 V"}, -}; - -// ATtiny441 ATtiny841 ATtiny1634 ATtiny1634R -static const Configvalue _values_bodlevel_attiny441[4] = { - {4, "bod_4v3", "brownout detection at 4.3 V"}, - {5, "bod_2v7", "brownout detection at 2.7 V"}, - {6, "bod_1v8", "brownout detection at 1.8 V"}, - {7, "bod_1v8_alt", "brownout detection at 1.8 V"}, -}; - -/* - * AT90PWM81 ATtiny43U ATtiny87 ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 - * ATtiny861A AT90PWM161 ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 - */ -static const Configvalue _values_bodlevel_at90pwm81[8] = { - {0, "bod_2v0", "brownout detection at 2.0 V"}, - {1, "bod_1v9", "brownout detection at 1.9 V"}, - {2, "bod_2v2", "brownout detection at 2.2 V"}, - {3, "bod_2v3", "brownout detection at 2.3 V"}, - {4, "bod_4v3", "brownout detection at 4.3 V"}, - {5, "bod_2v7", "brownout detection at 2.7 V"}, - {6, "bod_1v8", "brownout detection at 1.8 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -// AT90CAN128 AT90CAN32 AT90CAN64 -static const Configvalue _values_bodlevel_at90can128[8] = { - {0, "bod_2v5", "brownout detection at 2.5 V"}, - {1, "bod_2v6", "brownout detection at 2.6 V"}, - {2, "bod_2v7", "brownout detection at 2.7 V"}, - {3, "bod_3v8", "brownout detection at 3.8 V"}, - {4, "bod_3v9", "brownout detection at 3.9 V"}, - {5, "bod_4v0", "brownout detection at 4.0 V"}, - {6, "bod_4v1", "brownout detection at 4.1 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -// AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 AT90USB82 -static const Configvalue _values_bodlevel_at90usb162[8] = { - {0, "bod_4v3", "brownout detection at 4.3 V"}, - {1, "bod_4v0", "brownout detection at 4.0 V"}, - {2, "bod_3v6", "brownout detection at 3.6 V"}, - {3, "bod_3v5", "brownout detection at 3.5 V"}, - {4, "bod_3v0", "brownout detection at 3.0 V"}, - {5, "bod_2v9", "brownout detection at 2.9 V"}, - {6, "bod_2v7", "brownout detection at 2.7 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -/* - * ATxmega16E5 ATxmega128A3U ATxmega8E5 ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 - * ATxmega32D3 ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega32E5 ATxmega64A1U ATxmega64B1 - * ATxmega64A3U ATxmega64B3 ATxmega64C3 ATxmega64D3 ATxmega64A4U ATxmega64D4 ATxmega128A1U - * ATxmega128B1 ATxmega128B3 ATxmega128C3 ATxmega128D3 ATxmega128A4U ATxmega128D4 ATxmega192A3U - * ATxmega192C3 ATxmega192D3 ATxmega256A3BU ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 - * ATxmega384D3 - */ -static const Configvalue _values_bodlevel_atxmega16e5[8] = { - {0, "bod_3v0", "brownout detection at 3.0 V"}, - {1, "bod_2v8", "brownout detection at 2.8 V"}, - {2, "bod_2v6", "brownout detection at 2.6 V"}, - {3, "bod_2v4", "brownout detection at 2.4 V"}, - {4, "bod_2v2", "brownout detection at 2.2 V"}, - {5, "bod_2v0", "brownout detection at 2.0 V"}, - {6, "bod_1v8", "brownout detection at 1.8 V"}, - {7, "bod_1v6", "brownout detection at 1.6 V"}, -}; - -/* - * ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega64A1 ATxmega64A3 ATxmega128A1 ATxmega128A1revD - * ATxmega192A3 ATxmega256A3 ATxmega256A3B - */ -static const Configvalue _values_bodlevel_atxmega192a1[8] = { - {0, "bod_3v4", "brownout detection at 3.4 V"}, - {1, "bod_3v2", "brownout detection at 3.2 V"}, - {2, "bod_2v9", "brownout detection at 2.9 V"}, - {3, "bod_2v6", "brownout detection at 2.6 V"}, - {4, "bod_2v4", "brownout detection at 2.4 V"}, - {5, "bod_2v1", "brownout detection at 2.1 V"}, - {6, "bod_1v9", "brownout detection at 1.9 V"}, - {7, "bod_1v6", "brownout detection at 1.6 V"}, -}; - -// ATxmega64A4 ATxmega128A4 ATxmega16A4 ATxmega32A4 -static const Configvalue _values_bodlevel_atxmega64a4[8] = { - {0, "bod_3v5", "brownout detection at 3.5 V"}, - {1, "bod_3v2", "brownout detection at 3.2 V"}, - {2, "bod_3v0", "brownout detection at 3.0 V"}, - {3, "bod_2v7", "brownout detection at 2.7 V"}, - {4, "bod_2v4", "brownout detection at 2.4 V"}, - {5, "bod_2v1", "brownout detection at 2.1 V"}, - {6, "bod_1v9", "brownout detection at 1.9 V"}, - {7, "bod_1v6", "brownout detection at 1.6 V"}, -}; - -/* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 ATtiny807 - * ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 ATtiny1607 - * ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 ATtiny3224 - * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 - * ATmega4808 ATmega4809 - */ -static const Configvalue _values_bodlevel_attiny204[3] = { - {0, "bod_1v8", "brownout detection at 1.8 V"}, - {2, "bod_2v6", "brownout detection at 2.6 V"}, - {7, "bod_4v2", "brownout detection at 4.2 V"}, -}; - -/* - * AVR32DD14 AVR16DD14 AVR16DU14 AVR16DD20 AVR16DU20 AVR16DD28 AVR16DU28 AVR16DD32 AVR16DU32 - * AVR32DU14 AVR32DD20 AVR32DU20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 - * AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32SD32 AVR32DA48 AVR32DA48S - * AVR32DB48 AVR64DD14 AVR64DD20 AVR64DA28 AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64DA32 - * AVR64DA32S AVR64DB32 AVR64DD32 AVR64DU32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S - * AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 - * AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S AVR128DB64 - */ -static const Configvalue _values_bodlevel_avr32dd14[4] = { - {0, "bod_1v9", "brownout detection at 1.9 V"}, - {1, "bod_2v45", "brownout detection at 2.45 V"}, - {2, "bod_2v7", "brownout detection at 2.7 V"}, - {3, "bod_2v85", "brownout detection at 2.85 V"}, -}; - -/* - * AVR64EA48 AVR16EB14 AVR16EB20 AVR16EA28 AVR16EB28 AVR16EA32 AVR16EB32 AVR16EA48 AVR32EB14 - * AVR32EB20 AVR32EA28 AVR32EB28 AVR32EA32 AVR32EB32 AVR32EA48 AVR64EA28 AVR64EA32 - */ -static const Configvalue _values_bodlevel_avr64ea48[4] = { - {0, "bod_disabled", "brownout detection disabled"}, - {1, "bod_1v9", "brownout detection at 1.9 V"}, - {2, "bod_2v7", "brownout detection at 2.7 V"}, - {3, "bod_4v5", "brownout detection at 4.5 V"}, -}; - -// ATmega161comp ATmega162 -static const Configvalue _values_bodlevel_atmega161comp[5] = { - {3, "bod_2v3", "brownout detection at 2.3 V"}, - {4, "bod_4v3", "brownout detection at 4.3 V"}, - {5, "bod_2v7", "brownout detection at 2.7 V"}, - {6, "bod_1v8", "brownout detection at 1.8 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -// ATtiny12 -static const Configvalue _values_bodlevel_attiny12[2] = { - {0, "bod_2v7", "brownout detection at 2.7 V"}, - {1, "bod_1v8", "brownout detection at 1.8 V"}, -}; - -/* - * ATtiny13 ATtiny13A ATmega325 ATmega325A ATmega325P ATmega325PA ATmega329 ATmega329A ATmega329P - * ATmega329PA ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P ATmega3250 - * ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6450 - * ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - */ -static const Configvalue _values_bodlevel_attiny13[4] = { - {0, "bod_4v3", "brownout detection at 4.3 V"}, - {1, "bod_2v7", "brownout detection at 2.7 V"}, - {2, "bod_1v8", "brownout detection at 1.8 V"}, - {3, "bod_disabled", "brownout detection disabled"}, -}; - -// ATmega16U4 ATmega32U4 ATmega32U6 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 -static const Configvalue _values_bodlevel_atmega16u4[8] = { - {0, "bod_4v3", "brownout detection at 4.3 V"}, - {1, "bod_3v5", "brownout detection at 3.5 V"}, - {2, "bod_3v4", "brownout detection at 3.4 V"}, - {3, "bod_2v6", "brownout detection at 2.6 V"}, - {4, "bod_2v4", "brownout detection at 2.4 V"}, - {5, "bod_2v2", "brownout detection at 2.2 V"}, - {6, "bod_2v0", "brownout detection at 2.0 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -/* - * ATmega64RFR2 ATmega128RFA1 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 - * ATmega2564RFR2 - */ -static const Configvalue _values_bodlevel_atmega64rfr2[8] = { - {0, "bod_2v4", "brownout detection at 2.4 V"}, - {1, "bod_2v3", "brownout detection at 2.3 V"}, - {2, "bod_2v2", "brownout detection at 2.2 V"}, - {3, "bod_2v1", "brownout detection at 2.1 V"}, - {4, "bod_2v0", "brownout detection at 2.0 V"}, - {5, "bod_1v9", "brownout detection at 1.9 V"}, - {6, "bod_1v8", "brownout detection at 1.8 V"}, - {7, "bod_disabled", "brownout detection disabled"}, -}; - -// ATtiny416auto -static const Configvalue _values_bodlevel_attiny416auto[2] = { - {2, "bod_2v6", "brownout detection at 2.6 V"}, - {7, "bod_4v2", "brownout detection at 4.2 V"}, -}; - -// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 -static const Configvalue _values_bodlevel_avr16la14[4] = { - {0, "bodlevel0", "1.65 V"}, - {1, "bodlevel1", "1.90 V"}, - {2, "bodlevel2", "2.60 V"}, - {3, "bodlevel3", "4.30 V"}, -}; - -/* - * ATmega328 ATmega16M1 ATmega16HVA2 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 ATtiny102 - * ATtiny28 ATtiny441 AT90PWM2 AT90PWM81 AT90CAN128 AT90USB162 AT90S1200 AT90S2313 ATA5700M322 - * ATA5781 ATA5790 ATA6285 ATmega103comp AT90SCR100H ATmega161comp AT90S8535comp ATtiny4 ATtiny5 - * ATtiny9 ATtiny10 ATtiny20 ATtiny40 ATtiny104 ATtiny11 ATtiny12 ATtiny13 ATtiny13A ATtiny15 - * ATtiny22 ATtiny24 ATtiny24A ATtiny25 ATtiny26 ATtiny43U ATtiny44 ATtiny44A ATtiny45 ATtiny48 - * ATtiny84 ATtiny84A ATtiny85 ATtiny87 ATtiny88 ATtiny167 ATtiny261 ATtiny261A ATtiny461 - * ATtiny461A ATtiny828 ATtiny828R ATtiny841 ATtiny861 ATtiny861A ATtiny1634 ATtiny1634R - * ATtiny2313 ATtiny2313A ATtiny4313 ATmega8 ATmega8A ATmega8HVA ATmega8U2 ATmega16 ATmega16A - * ATmega16HVA ATmega16HVB ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB - * ATmega32C1 ATmega32M1 ATmega32U2 ATmega32U4 ATmega32U6 ATmega48 ATmega48A ATmega48P ATmega48PA - * ATmega48PB ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 ATmega64HVE2 ATmega64RFR2 - * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega103 ATmega128 ATmegaS128 ATmega128A - * ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A ATmega164P ATmega164PA - * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A ATmega168P ATmega168PA - * ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 ATmega323 ATmega324A - * ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA ATmega328P - * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 ATmega644 ATmega644A ATmega644P - * ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P - * ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega2560 ATmega2561 - * ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A - * ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - * ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 AT90SCR100 - * AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 AT90S2323 - * AT90S2343 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90S8515comp AT90S8535 ATA5272 ATA5505 - * ATA5702M322 ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 - * ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA8210 ATA8215 ATA8510 ATA8515 - * ATA664251 ATmega32HVE2 - */ -static const Configvalue _values_lb_atmega328[3] = { - {0, "prog_ver_disabled", "further programming and verification disabled"}, - {2, "prog_disabled", "further programming disabled"}, - {3, "no_lock", "no memory lock features enabled"}, -}; - -/* - * ATxmega16E5 ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 - * ATxmega8E5 ATxmega16A4 ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 ATxmega32D3 ATxmega32A4 - * ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega32E5 ATxmega64A1 ATxmega64A1U ATxmega64B1 - * ATxmega64A3 ATxmega64A3U ATxmega64B3 ATxmega64C3 ATxmega64D3 ATxmega64A4U ATxmega64D4 - * ATxmega128A1 ATxmega128A1revD ATxmega128A1U ATxmega128B1 ATxmega128B3 ATxmega128C3 ATxmega128D3 - * ATxmega128A4U ATxmega128D4 ATxmega192A3 ATxmega192A3U ATxmega192C3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3BU ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 ATxmega384D3 - */ -static const Configvalue _values_lb_atxmega16e5[3] = { - {0, "rwlock", "read and write not allowed"}, - {2, "wlock", "write not allowed"}, - {3, "nolock", "no locks"}, -}; - -/* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 - */ -static const Configvalue _values_lb_attiny204[2] = { - {0x3a, "rwlock", "read and write not allowed"}, - {0xc5, "nolock", "no locks"}, -}; - -// AT90S2333 -static const Configvalue _values_lb_at90s2333[3] = { - {0, "prog_ver_disabled", "further programming and verification disabled"}, - {1, "prog_disabled", "further programming disabled"}, - {3, "no_lock", "no memory lock features enabled"}, -}; - -/* - * ATmega328 ATmega16M1 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 AT90PWM2 AT90PWM81 - * AT90CAN128 AT90USB162 ATA5781 ATA5790 ATA6285 ATmega103comp AT90SCR100H ATmega161comp - * AT90S8535comp ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega8U2 ATmega16 ATmega16A ATmega16HVB - * ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega128 - * ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A - * ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 - * ATmega323 ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P - * ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P - * ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 - * ATmega2560 ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 - * AT90SCR100 AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - * AT90S8515comp ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 - * ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 ATA8515 ATmega32HVE2 - */ -static const Configvalue _values_blb0_atmega328[4] = { +static const Configvalue _values_blb0_at90s8515comp[4] = { {0, "lpm_spm_disabled_in_app", "LPM and SPM prohibited in application section"}, {1, "lpm_disabled_in_app", "LPM prohibited in application section"}, {2, "spm_disabled_in_app", "SPM prohibited in application section"}, @@ -10789,147 +10807,190 @@ static const Configvalue _values_blb0_atmega328[4] = { }; /* - * ATmega328 ATmega16M1 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 AT90PWM2 AT90PWM81 - * AT90CAN128 AT90USB162 ATA5781 ATA5790 ATA6285 ATmega103comp AT90SCR100H ATmega161comp - * AT90S8535comp ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega8U2 ATmega16 ATmega16A ATmega16HVB - * ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega128 - * ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A - * ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 - * ATmega323 ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P - * ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P - * ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 - * ATmega2560 ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 - * AT90SCR100 AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - * AT90S8515comp ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 - * ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 ATA8515 ATmega32HVE2 + * AT90S8515comp AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 + * AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny828 ATtiny828R ATmega8 ATmega8A + * ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 + * ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 + * ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 + * ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161 ATmega161comp ATmega1281 ATmega2561 + * ATmega162 ATmega163 ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 + * ATmega328P ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 + * ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 + * ATA8515 */ -static const Configvalue _values_blb1_atmega328[4] = { +static const Configvalue _values_blb1_at90s8515comp[4] = { {0, "lpm_spm_disabled_in_boot", "LPM and SPM prohibited in boot section"}, {1, "lpm_disabled_in_boot", "LPM prohibited in boot section"}, {2, "spm_disabled_in_boot", "SPM prohibited in boot section"}, {3, "no_lock_in_boot", "no lock on SPM and LPM in boot section"}, }; -// ATmega16M1 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 -static const Configvalue _values_pscrvb_atmega16m1[2] = { - {0, "v_0", "PSC0UTnB reset value 0"}, - {1, "v_1", "PSC0UTnB reset value 1"}, -}; - -// ATmega16M1 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 -static const Configvalue _values_pscrva_atmega16m1[2] = { - {0, "v_0", "PSCOUTnA reset value 0"}, - {1, "v_1", "PSCOUTnA reset value 1"}, -}; - -// ATmega16M1 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 -static const Configvalue _values_pscrb_atmega16m1[2] = { - {0, "rb_enabled", "PSC reset behavior enabled"}, - {1, "rb_disabled", "PSC reset behavior disabled"}, -}; - -// ATmega16HVA2 ATmega8HVA ATmega16HVA -static const Configvalue _values_sut_atmega16hva2[8] = { - {0, "sut_6ck_14ck_4ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, - {1, "sut_6ck_14ck_8ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 8 ms"}, - {2, "sut_6ck_14ck_16ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 16 ms"}, - {3, "sut_6ck_14ck_32ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 32 ms"}, - {4, "sut_6ck_14ck_64ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, - {5, "sut_6ck_14ck_128ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 128 ms"}, - {6, "sut_6ck_14ck_256ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 256 ms"}, - {7, "sut_6ck_14ck_512ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 512 ms"}, -}; - -// ATmega32HVBrevB ATmega16HVB ATmega16HVBrevB ATmega32HVB -static const Configvalue _values_sut_atmega32hvbrevb[8] = { - {0, "sut_14ck_4ms", "startup time: 14 CK + 4 ms"}, - {1, "sut_14ck_8ms", "startup time: 14 CK + 8 ms"}, - {2, "sut_14ck_16ms", "startup time: 14 CK + 16 ms"}, - {3, "sut_14ck_32ms", "startup time: 14 CK + 32 ms"}, - {4, "sut_14ck_64ms", "startup time: 14 CK + 64 ms"}, - {5, "sut_14ck_128ms", "startup time: 14 CK + 128 ms"}, - {6, "sut_14ck_256ms", "startup time: 14 CK + 256 ms"}, - {7, "sut_14ck_512ms", "startup time: 14 CK + 512 ms"}, -}; - -// ATmega64HVE ATmega64HVE2 ATmega32HVE2 -static const Configvalue _values_sut_atmega64hve[4] = { - {0, "sut_14ck_0ms", "startup time: 14 CK + 0 ms"}, - {1, "sut_14ck_16ms", "startup time: 14 CK + 16 ms"}, - {2, "sut_14ck_32ms", "startup time: 14 CK + 32 ms"}, - {3, "sut_14ck_64ms", "startup time: 14 CK + 64 ms"}, +// AT90S8535comp ATmega8535 +static const Configvalue _values_s8535c_at90s8535comp[2] = { + {0, "c8535_enabled", "AT90S4434/8535 compatibility mode enabled"}, + {1, "c8535_disabled", "AT90S4434/8535 compatibility mode disabled"}, }; /* - * ATtiny204 ATtiny1624 AVR32DD14 AVR64EA48 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 - * ATtiny406 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 - * ATtiny804 ATtiny806 ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 - * ATtiny1604 ATtiny1606 ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 - * ATtiny3216 ATtiny3217 ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 - * ATmega1609 ATmega3208 ATmega3209 ATmega4808 ATmega4809 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 - * AVR16DD20 AVR16DU20 AVR16EB20 AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 - * AVR16DD32 AVR16DU32 AVR16EA32 AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 - * AVR32DD20 AVR32DU20 AVR32EB20 AVR32LA20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 - * AVR32DU28 AVR32EA28 AVR32EB28 AVR32LA28 AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 - * AVR32DU32 AVR32EA32 AVR32EB32 AVR32LA32 AVR32SD32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 - * AVR64DD14 AVR64DD20 AVR64DA28 AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 - * AVR64DA32S AVR64DB32 AVR64DD32 AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 - * AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 - * AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S AVR128DB64 + * AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 + * AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 + * AT90USB1287 ATtiny13 ATtiny13A ATtiny43U ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 + * ATtiny84A ATtiny25 ATtiny45 ATtiny85 ATtiny87 ATtiny167 ATtiny48 ATtiny88 ATtiny828 ATtiny828R + * ATtiny1634 ATtiny1634R ATtiny441 ATtiny841 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 + * ATtiny861A ATtiny2313 ATtiny2313A ATtiny4313 ATmega640 ATmega1280 ATmega2560 ATmega32C1 + * ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 + * ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 + * ATmega161comp ATmega1281 ATmega2561 ATmega162 ATmega164A ATmega164P ATmega164PA ATmega324A + * ATmega324P ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P + * ATmega324PB ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P + * ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P + * ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega48 + * ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A + * ATmega168P ATmega168PA ATmega328 ATmega328P ATmega48PB ATmega88PB ATmega168PB ATmega328PB + * ATmega169 ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P ATmega329PA + * ATmega649 ATmega649A ATmega649P ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6490 + * ATmega6490A ATmega6490P ATmega16HVB ATmega32HVB ATmega64HVE ATmega32HVE2 ATmega64HVE2 ATA5272 + * ATA5505 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 + * ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA6616C ATA6617C ATA664251 + * ATA8210 ATA8215 ATA8510 ATA8515 */ -static const Configvalue _values_sut_attiny204[8] = { - {0, "sut_0ms", "startup time 0 ms"}, - {1, "sut_1ms", "startup time 1 ms"}, - {2, "sut_2ms", "startup time 2 ms"}, - {3, "sut_4ms", "startup time 4 ms"}, - {4, "sut_8ms", "startup time 8 ms"}, - {5, "sut_16ms", "startup time 16 ms"}, - {6, "sut_32ms", "startup time 32 ms"}, - {7, "sut_64ms", "startup time 64 ms"}, -}; - -// ATmega161 -static const Configvalue _values_sut_atmega161[2] = { - {0, "sut_long", "start up time long"}, - {1, "sut_short", "start up time short"}, +static const Configvalue _values_ckdiv8_at90can32[2] = { + {0, "by_8", "F_CPU prescaled by 8"}, + {1, "by_1", "F_CPU prescaled by 1"}, }; /* - * ATmega16HVA2 ATtiny102 ATtiny441 ATtiny104 ATtiny13 ATtiny13A ATtiny24 ATtiny24A ATtiny25 - * ATtiny43U ATtiny44 ATtiny44A ATtiny45 ATtiny48 ATtiny84 ATtiny84A ATtiny85 ATtiny87 ATtiny88 - * ATtiny167 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny841 ATtiny861 ATtiny861A ATtiny1634 - * ATtiny1634R ATtiny2313 ATtiny2313A ATtiny4313 ATmega8HVA ATmega16HVA ATmega48 ATmega48A - * ATmega48P ATmega48PA ATmega48PB ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 + * AT90CAN32 AT90CAN64 AT90CAN128 AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 + * AT90SCR100H ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A + * ATmegaS128 ATmega640 ATmega1280 ATmega2560 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 + * ATmega256RFR2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161comp ATmega1281 ATmega2561 ATmega162 + * ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644 + * ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB ATmega644RFR2 + * ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A + * ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P + * ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp ATmega406 + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A1U ATxmega128A1U + * ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B ATxmega64A3U ATxmega128A3U + * ATxmega192A3U ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 */ -static const Configvalue _values_selfprgen_atmega16hva2[2] = { - {0, "spm_enabled", "self programming enabled"}, - {1, "spm_disabled", "self programming disabled"}, +static const Configvalue _values_jtagen_at90can32[2] = { + {0, "jtag_enabled", "JTAG interface enabled"}, + {1, "jtag_disabled", "JTAG interface disabled"}, }; -// ATmega16HVA2 -static const Configvalue _values_cksel_atmega16hva2[2] = { - {1, "slow_rcosc", "slow RC osc"}, - {2, "ulp_rcosc", "ultra-low-power RC osc"}, +/* + * AT90CAN32 AT90CAN64 AT90CAN128 AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 + * AT90SCR100H ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A + * ATmegaS128 ATmega640 ATmega1280 ATmega2560 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 + * ATmega256RFR2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161comp ATmega1281 ATmega2561 ATmega162 + * ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644 + * ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB ATmega644RFR2 + * ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A + * ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P + * ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp ATmega406 + */ +static const Configvalue _values_ocden_at90can32[2] = { + {0, "ocd_enabled", "on-chip debug enabled"}, + {1, "ocd_disabled", "on-chip debug disabled"}, }; -// ATmega32HVBrevB ATmega16HVB ATmega16HVBrevB ATmega32HVB -static const Configvalue _values_cksel_atmega32hvbrevb[1] = { - {1, "default", "default"}, +// AT90CAN32 AT90CAN64 AT90CAN128 +static const Configvalue _values_ta0sel_at90can32[2] = { + {0, "ft_enabled", "factory tests enabled"}, + {1, "ft_disabled", "factory tests disabled"}, }; -// ATmega64HVE ATmega64HVE2 ATmega32HVE2 -static const Configvalue _values_cksel_atmega64hve[1] = { - {1, "osel_default", "oscillator selection default"}, +/* + * AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 + * AT90USB82 AT90USB162 ATtiny13 ATtiny13A ATtiny43U ATtiny24 ATtiny24A ATtiny44 ATtiny44A + * ATtiny84 ATtiny84A ATtiny25 ATtiny45 ATtiny85 ATtiny87 ATtiny167 ATtiny48 ATtiny88 ATtiny828 + * ATtiny828R ATtiny1634 ATtiny1634R ATtiny441 ATtiny841 ATtiny261 ATtiny261A ATtiny461 ATtiny461A + * ATtiny861 ATtiny861A ATtiny2313 ATtiny2313A ATtiny4313 ATmega32C1 ATmega64C1 ATmega16M1 + * ATmega32M1 ATmega64M1 ATmegaS64M1 ATmega8U2 ATmega16U2 ATmega32U2 ATmega48 ATmega48A ATmega48P + * ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA + * ATmega328 ATmega328P ATmega48PB ATmega88PB ATmega168PB ATmega328PB ATmega8HVA ATmega16HVA + * ATmega16HVA2 ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 + * ATmega64HVE2 ATA5272 ATA5505 ATA5700M322 ATA5702M322 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 + * ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C + * ATA6613C ATA6614Q ATA6616C ATA6617C ATA664251 ATA8210 ATA8215 ATA8510 ATA8515 + */ +static const Configvalue _values_dwen_at90pwm1[2] = { + {0, "dw_enabled", "debugWIRE enabled"}, + {1, "dw_off", "debugWIRE off"}, }; -// ATtiny28 ATtiny12 -static const Configvalue _values_cksel_attiny28[16] = { +// AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 +static const Configvalue _values_pscrv_at90pwm1[2] = { + {0, "v_0", "PSCOUT reset value 0"}, + {1, "v_1", "PSCOUT reset value 1"}, +}; + +// AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 +static const Configvalue _values_psc0rb_at90pwm1[2] = { + {0, "rb_enabled", "PSC0 reset behavior enabled"}, + {1, "rb_disabled", "PSC0 reset behavior disabled"}, +}; + +// AT90PWM1 AT90PWM81 AT90PWM161 AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 +static const Configvalue _values_psc2rb_at90pwm1[2] = { + {0, "rb_enabled", "PSC2 reset behavior enabled"}, + {1, "rb_disabled", "PSC2 reset behavior disabled"}, +}; + +// AT90PWM81 AT90PWM161 +static const Configvalue _values_pscinrb_at90pwm81[2] = { + {0, "rb_enabled", "PSC2 and PSC0 input reset behavior enabled"}, + {1, "rb_disabled", "PSC2 and PSC0 input reset behavior disabled"}, +}; + +// AT90PWM81 AT90PWM161 +static const Configvalue _values_psc2rba_at90pwm81[2] = { + {0, "rb_enabled", "PSC2 reset behavior for 22 and 23 enabled"}, + {1, "rb_disabled", "PSC2 reset behavior for 22 and 23 disabled"}, +}; + +// AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 +static const Configvalue _values_psc1rb_at90pwm2[2] = { + {0, "rb_enabled", "PSC1 reset behavior enabled"}, + {1, "rb_disabled", "PSC1 reset behavior disabled"}, +}; + +/* + * AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 ATmega8U2 ATmega16U2 + * ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 + */ +static const Configvalue _values_hwbe_at90usb82[2] = { + {0, "gpio_pin_can_force_reset_to_boot_section", "GPIO pin can force reset to boot section"}, + {1, "gpio_pin_cannot_force_reset_to_boot_section", "GPIO pin cannot force reset to boot section"}, +}; + +// ATtiny11 +static const Configvalue _values_cksel_attiny11[5] = { + {0, "extclk", "external clock"}, + {4, "intrcosc", "internal RC oscillator"}, + {5, "extrcosc", "external RC oscillator"}, + {6, "extlofxtal", "external low-frequency crystal"}, + {7, "extxtalcres", "external crystal/ceramic resonator"}, +}; + +// ATtiny12 ATtiny28 +static const Configvalue _values_cksel_attiny12[16] = { {0x00, "extclkx00", "external clock"}, {0x01, "extclkx01", "external clock"}, {0x02, "intrcoscx02", "internal RC oscillator"}, @@ -10948,13 +11009,10 @@ static const Configvalue _values_cksel_attiny28[16] = { {0x0f, "extxtalcresx0f", "external crystal/ceramic resonator"}, }; -// ATtiny11 -static const Configvalue _values_cksel_attiny11[5] = { - {0, "extclk", "external clock"}, - {4, "intrcosc", "internal RC oscillator"}, - {5, "extrcosc", "external RC oscillator"}, - {6, "extlofxtal", "external low-frequency crystal"}, - {7, "extxtalcres", "external crystal/ceramic resonator"}, +// AT90S1200 AT90S2343 ATtiny22 +static const Configvalue _values_cksel_at90s1200[2] = { + {0, "intrcosc", "internal RC oscillator"}, + {1, "extclk", "external clock"}, }; // ATtiny15 @@ -10965,20 +11023,6 @@ static const Configvalue _values_cksel_attiny15[4] = { {3, "vquickpwr", "very quickly rising power"}, }; -// AT90S1200 ATtiny22 AT90S2343 -static const Configvalue _values_cksel_at90s1200[2] = { - {0, "intrcosc", "internal RC oscillator"}, - {1, "extclk", "external clock"}, -}; - -// ATmega103 -static const Configvalue _values_cksel_atmega103[4] = { - {0, "sut_5ck", "startup time 5 CPU cycles"}, - {1, "sut_0ms5", "startup time 0.5 ms"}, - {2, "sut_4ms", "startup time 4 ms"}, - {3, "sut_16ms", "startup time 16 ms"}, -}; - // ATmega161 static const Configvalue _values_cksel_atmega161[8] = { {0, "extclk_fastpwr", "ext clock; fast rising power"}, @@ -11011,60 +11055,28 @@ static const Configvalue _values_cksel_atmega163[16] = { {0x0f, "cres_boden", "ceramic res; brownout detection"}, }; +// ATmega103 +static const Configvalue _values_cksel_atmega103[4] = { + {0, "sut_5ck", "startup time 5 CPU cycles"}, + {1, "sut_0ms5", "startup time 0.5 ms"}, + {2, "sut_4ms", "startup time 4 ms"}, + {3, "sut_16ms", "startup time 16 ms"}, +}; + // ATmega16HVA2 -static const Configvalue _values_compmode_atmega16hva2[2] = { - {0, "cm_programmed", "compatibility mode programmed"}, - {1, "cm_unprogrammed", "compatibility mode unprogrammed"}, +static const Configvalue _values_cksel_atmega16hva2[2] = { + {1, "slow_rcosc", "slow RC osc"}, + {2, "ulp_rcosc", "ultra-low-power RC osc"}, }; -// ATmega32HVBrevB ATmega16HVBrevB -static const Configvalue _values_duvrdinit_atmega32hvbrevb[2] = { - {0, "duvr_on", "DUVR mode on"}, - {1, "duvr_off", "DUVR mode off"}, +// ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB +static const Configvalue _values_cksel_atmega16hvb[1] = { + {1, "default", "default"}, }; -/* - * ATmega64HVE ATmega8515 ATA6285 ATmega103comp AT90S8535comp ATtiny12 ATtiny15 ATtiny26 ATmega8 - * ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega64HVE2 ATmega128 - * ATmegaS128 ATmega128A ATmega163 ATmega323 ATmega8535 AT90S2333 AT90S4433 AT90S8515comp ATA6286 - * ATA6289 ATmega32HVE2 - */ -static const Configvalue _values_boden_atmega64hve[2] = { - {0, "bod_enabled", "brownout detection enabled"}, - {1, "bod_disabled", "brownout detection disabled"}, -}; - -// AT90SCR100H AT90SCR100 -static const Configvalue _values_boden_at90scr100h[2] = { - {0, "bod_disabled", "brownout detection disabled"}, - {1, "bod_enabled", "brownout detection enabled"}, -}; - -// ATmega328PB ATmega324PB -static const Configvalue _values_cfd_atmega328pb[2] = { - {0, "cfd_disabled", "clock failure detection disabled"}, - {1, "cfd_enabled", "clock failure detection enabled"}, -}; - -/* - * ATmega8515 ATmega103comp AT90S8535comp ATmega8 ATmega8A ATmega16 ATmega16A ATmega32 ATmega32A - * ATmega64 ATmega64A ATmega128 ATmegaS128 ATmega128A ATmega8535 AT90S8515comp - */ -static const Configvalue _values_ckopt_atmega8515[2] = { - {0, "full_railtorail", "oscillator swings full rail-to-rail"}, - {1, "less_than_full_railtorail", "oscillator swings less than full rail-to-rail"}, -}; - -// ATtiny26 -static const Configvalue _values_ckopt_attiny26[2] = { - {0, "int_caps_enabled", "internal capacitors on XTAL1 and XTAL2 enabled"}, - {1, "no_int_caps", "no internal capacitors on XTAL1 and XTAL2"}, -}; - -// ATmega8515 AT90S8515comp -static const Configvalue _values_s8515c_atmega8515[2] = { - {0, "c8515_enabled", "AT90S4414/8515 compatibility mode enabled"}, - {1, "c8515_disabled", "AT90S4414/8515 compatibility mode disabled"}, +// ATmega64HVE ATmega32HVE2 ATmega64HVE2 +static const Configvalue _values_cksel_atmega64hve[1] = { + {1, "osel_default", "oscillator selection default"}, }; // ATtiny28 @@ -11074,66 +11086,66 @@ static const Configvalue _values_intcap_attiny28[2] = { }; /* - * ATtiny441 ATtiny441 ATtiny828 ATtiny828 ATtiny828R ATtiny828R ATtiny841 ATtiny841 ATtiny1634 - * ATtiny1634 ATtiny1634R ATtiny1634R + * ATtiny828 ATtiny828 ATtiny828R ATtiny828R ATtiny1634 ATtiny1634 ATtiny1634R ATtiny1634R + * ATtiny441 ATtiny441 ATtiny841 ATtiny841 */ -static const Configvalue _values_bodact_attiny441[3] = { +static const Configvalue _values_bodact_attiny828[3] = { {1, "bod_sampled", "brownout detection in sampled mode"}, {2, "bod_enabled", "brownout detection enabled"}, {3, "bod_disabled", "brownout detection disabled"}, }; /* - * ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega128A3 - * ATxmega128A3 ATxmega128A3U ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U ATxmega16C4 ATxmega16C4 - * ATxmega16D4 ATxmega16D4 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32D4 ATxmega32D4 ATxmega32E5 - * ATxmega32E5 ATxmega64A1 ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64B3 ATxmega64B3 ATxmega64C3 - * ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1U ATxmega128A1U - * ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128D3 - * ATxmega128D3 ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega192A3 ATxmega192A3 - * ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3U - * ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 - * ATxmega384D3 ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega192A1 + * ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 + * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU ATxmega256A3U ATxmega256A3U + * ATxmega16A4 ATxmega16A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U ATxmega64A4U ATxmega64A4U + * ATxmega128A4U ATxmega128A4U ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 ATxmega64C3 ATxmega64C3 + * ATxmega128C3 ATxmega128C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 ATxmega32D3 ATxmega32D3 + * ATxmega64D3 ATxmega64D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 ATxmega32D4 ATxmega32D4 + * ATxmega64D4 ATxmega64D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_bodact_atxmega16e5[3] = { +static const Configvalue _values_bodact_atxmega64a1[3] = { {1, "bod_sampled", "brownout detection in sampled mode"}, {2, "bod_continuous", "brownout detection enabled in continuous mode"}, {3, "bod_disabled", "brownout detection disabled"}, }; /* - * ATtiny441 ATtiny441 ATtiny828 ATtiny828 ATtiny828R ATtiny828R ATtiny841 ATtiny841 ATtiny1634 - * ATtiny1634 ATtiny1634R ATtiny1634R + * ATtiny828 ATtiny828 ATtiny828R ATtiny828R ATtiny1634 ATtiny1634 ATtiny1634R ATtiny1634R + * ATtiny441 ATtiny441 ATtiny841 ATtiny841 */ -static const Configvalue _values_bodpd_attiny441[3] = { +static const Configvalue _values_bodpd_attiny828[3] = { {1, "bod_sampled", "brownout detection in sampled mode"}, {2, "bod_enabled", "brownout detection enabled"}, {3, "bod_disabled", "brownout detection disabled"}, }; /* - * ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega128A3 - * ATxmega128A3 ATxmega128A3U ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U ATxmega16C4 ATxmega16C4 - * ATxmega16D4 ATxmega16D4 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32D4 ATxmega32D4 ATxmega32E5 - * ATxmega32E5 ATxmega64A1 ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64B3 ATxmega64B3 ATxmega64C3 - * ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1U ATxmega128A1U - * ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128D3 - * ATxmega128D3 ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega192A3 ATxmega192A3 - * ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3U - * ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 - * ATxmega384D3 ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega192A1 + * ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 + * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU ATxmega256A3U ATxmega256A3U + * ATxmega16A4 ATxmega16A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U ATxmega64A4U ATxmega64A4U + * ATxmega128A4U ATxmega128A4U ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 ATxmega64C3 ATxmega64C3 + * ATxmega128C3 ATxmega128C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 ATxmega32D3 ATxmega32D3 + * ATxmega64D3 ATxmega64D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 ATxmega32D4 ATxmega32D4 + * ATxmega64D4 ATxmega64D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_bodpd_atxmega16e5[3] = { +static const Configvalue _values_bodpd_atxmega64a1[3] = { {1, "bod_sampled", "brownout detection in sampled mode"}, {2, "bod_continuous", "brownout detection enabled in continuous mode"}, {3, "bod_disabled", "brownout detection disabled"}, @@ -11148,108 +11160,118 @@ static const Configvalue _values_ulposcsel_attiny441[5] = { {7, "ulposc_32khz", "ultra-low-power clock running at 32 kHz"}, }; -// AT90PWM2 AT90PWM81 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90PWM161 AT90PWM216 AT90PWM316 -static const Configvalue _values_pscrv_at90pwm2[2] = { - {0, "v_0", "PSCOUT reset value 0"}, - {1, "v_1", "PSCOUT reset value 1"}, +// ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega103comp +static const Configvalue _values_m103c_atmega64[2] = { + {0, "c103_enabled", "ATmega103 compatibility mode enabled"}, + {1, "c103_disabled", "ATmega103 compatibility mode disabled"}, }; -// AT90PWM2 AT90PWM81 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90PWM161 AT90PWM216 AT90PWM316 -static const Configvalue _values_psc0rb_at90pwm2[2] = { - {0, "rb_enabled", "PSC0 reset behavior enabled"}, - {1, "rb_disabled", "PSC0 reset behavior disabled"}, +// ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 +static const Configvalue _values_pscrvb_atmega32c1[2] = { + {0, "v_0", "PSC0UTnB reset value 0"}, + {1, "v_1", "PSC0UTnB reset value 1"}, }; -// AT90PWM2 AT90PWM2B AT90PWM3 AT90PWM3B AT90PWM216 AT90PWM316 -static const Configvalue _values_psc1rb_at90pwm2[2] = { - {0, "rb_enabled", "PSC1 reset behavior enabled"}, - {1, "rb_disabled", "PSC1 reset behavior disabled"}, +// ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 +static const Configvalue _values_pscrva_atmega32c1[2] = { + {0, "v_0", "PSCOUTnA reset value 0"}, + {1, "v_1", "PSCOUTnA reset value 1"}, }; -// AT90PWM2 AT90PWM81 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90PWM161 AT90PWM216 AT90PWM316 -static const Configvalue _values_psc2rb_at90pwm2[2] = { - {0, "rb_enabled", "PSC2 reset behavior enabled"}, - {1, "rb_disabled", "PSC2 reset behavior disabled"}, +// ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 +static const Configvalue _values_pscrb_atmega32c1[2] = { + {0, "rb_enabled", "PSC reset behavior enabled"}, + {1, "rb_disabled", "PSC reset behavior disabled"}, }; -// AT90PWM81 AT90PWM161 -static const Configvalue _values_pscinrb_at90pwm81[2] = { - {0, "rb_enabled", "PSC2 and PSC0 input reset behavior enabled"}, - {1, "rb_disabled", "PSC2 and PSC0 input reset behavior disabled"}, +// ATmega161 +static const Configvalue _values_sut_atmega161[2] = { + {0, "sut_long", "start up time long"}, + {1, "sut_short", "start up time short"}, }; -// AT90PWM81 AT90PWM161 -static const Configvalue _values_psc2rba_at90pwm81[2] = { - {0, "rb_enabled", "PSC2 reset behavior for 22 and 23 enabled"}, - {1, "rb_disabled", "PSC2 reset behavior for 22 and 23 disabled"}, +// ATmega8HVA ATmega16HVA ATmega16HVA2 +static const Configvalue _values_sut_atmega8hva[8] = { + {0, "sut_6ck_14ck_4ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 4 ms"}, + {1, "sut_6ck_14ck_8ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 8 ms"}, + {2, "sut_6ck_14ck_16ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 16 ms"}, + {3, "sut_6ck_14ck_32ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 32 ms"}, + {4, "sut_6ck_14ck_64ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 64 ms"}, + {5, "sut_6ck_14ck_128ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 128 ms"}, + {6, "sut_6ck_14ck_256ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 256 ms"}, + {7, "sut_6ck_14ck_512ms", "startup time PWRDWN/RESET: 6 CK/14 CK + 512 ms"}, +}; + +// ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB +static const Configvalue _values_sut_atmega16hvb[8] = { + {0, "sut_14ck_4ms", "startup time: 14 CK + 4 ms"}, + {1, "sut_14ck_8ms", "startup time: 14 CK + 8 ms"}, + {2, "sut_14ck_16ms", "startup time: 14 CK + 16 ms"}, + {3, "sut_14ck_32ms", "startup time: 14 CK + 32 ms"}, + {4, "sut_14ck_64ms", "startup time: 14 CK + 64 ms"}, + {5, "sut_14ck_128ms", "startup time: 14 CK + 128 ms"}, + {6, "sut_14ck_256ms", "startup time: 14 CK + 256 ms"}, + {7, "sut_14ck_512ms", "startup time: 14 CK + 512 ms"}, +}; + +// ATmega64HVE ATmega32HVE2 ATmega64HVE2 +static const Configvalue _values_sut_atmega64hve[4] = { + {0, "sut_14ck_0ms", "startup time: 14 CK + 0 ms"}, + {1, "sut_14ck_16ms", "startup time: 14 CK + 16 ms"}, + {2, "sut_14ck_32ms", "startup time: 14 CK + 32 ms"}, + {3, "sut_14ck_64ms", "startup time: 14 CK + 64 ms"}, }; /* - * AT90CAN128 ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 - * ATmega103comp AT90SCR100H ATmega161comp ATmega16 ATmega16A ATmega16U4 ATmega32 ATmega32A - * ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64RFR2 ATmega128 ATmegaS128 ATmega128A - * ATmega128RFA1 ATmega128RFR2 ATmega162 ATmega164A ATmega164P ATmega164PA ATmega165 ATmega165A - * ATmega165P ATmega165PA ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 ATmega323 - * ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA - * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 ATmega644 ATmega644A ATmega644P - * ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P - * ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega2560 ATmega2561 - * ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A - * ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - * AT90CAN32 AT90CAN64 AT90SCR100 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 ATxmega16A4 - * ATxmega16A4U ATxmega32A4 ATxmega32A4U ATxmega64A1 ATxmega64A1U ATxmega64B1 ATxmega64A3 - * ATxmega64A3U ATxmega64B3 ATxmega64A4U ATxmega128A1 ATxmega128A1revD ATxmega128A1U ATxmega128B1 - * ATxmega128B3 ATxmega128A4U ATxmega192A3 ATxmega192A3U ATxmega256A3 ATxmega256A3B ATxmega256A3BU - * ATxmega256A3U + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 + * AVR64DA28S AVR64DA32 AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 + * AVR128DA28S AVR128DA32 AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 + * AVR32DB32 AVR32DB48 AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 + * AVR128DB64 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 + * AVR64DD14 AVR64DD20 AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 + * AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 + * AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 + * AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 + * AVR32LA20 AVR32LA28 AVR32LA32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_jtagen_at90can128[2] = { - {0, "jtag_enabled", "JTAG interface enabled"}, - {1, "jtag_disabled", "JTAG interface disabled"}, +static const Configvalue _values_sut_attiny202[8] = { + {0, "sut_0ms", "startup time 0 ms"}, + {1, "sut_1ms", "startup time 1 ms"}, + {2, "sut_2ms", "startup time 2 ms"}, + {3, "sut_4ms", "startup time 4 ms"}, + {4, "sut_8ms", "startup time 8 ms"}, + {5, "sut_16ms", "startup time 16 ms"}, + {6, "sut_32ms", "startup time 32 ms"}, + {7, "sut_64ms", "startup time 64 ms"}, }; -/* - * AT90CAN128 ATmega103comp AT90SCR100H ATmega161comp ATmega16 ATmega16A ATmega16U4 ATmega32 - * ATmega32A ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64RFR2 ATmega128 ATmegaS128 ATmega128A - * ATmega128RFA1 ATmega128RFR2 ATmega162 ATmega164A ATmega164P ATmega164PA ATmega165 ATmega165A - * ATmega165P ATmega165PA ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 ATmega323 - * ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P ATmega325PA - * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 ATmega644 ATmega644A ATmega644P - * ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P - * ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 ATmega2560 ATmega2561 - * ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A - * ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P - * AT90CAN32 AT90CAN64 AT90SCR100 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - */ -static const Configvalue _values_ocden_at90can128[2] = { - {0, "ocd_enabled", "on-chip debug enabled"}, - {1, "ocd_disabled", "on-chip debug disabled"}, +// ATmega161comp ATmega162 +static const Configvalue _values_m161c_atmega161comp[2] = { + {0, "c161_enabled", "ATmega161 compatibility mode enabled"}, + {1, "c161_disabled", "ATmega161 compatibility mode disabled"}, }; -// AT90CAN128 AT90CAN32 AT90CAN64 -static const Configvalue _values_ta0sel_at90can128[2] = { - {0, "ft_enabled", "factory tests enabled"}, - {1, "ft_disabled", "factory tests disabled"}, +// ATmega324PB ATmega328PB +static const Configvalue _values_cfd_atmega324pb[2] = { + {0, "cfd_disabled", "clock failure detection disabled"}, + {1, "cfd_enabled", "clock failure detection enabled"}, }; -/* - * AT90USB162 ATmega8U2 ATmega16U2 ATmega16U4 ATmega32U2 ATmega32U4 ATmega32U6 AT90USB82 AT90USB646 - * AT90USB647 AT90USB1286 AT90USB1287 - */ -static const Configvalue _values_hwbe_at90usb162[2] = { - {0, "gpio_pin_can_force_reset_to_boot_section", "GPIO pin can force reset to boot section"}, - {1, "gpio_pin_cannot_force_reset_to_boot_section", "GPIO pin cannot force reset to boot section"}, +// ATmega16HVA2 +static const Configvalue _values_compmode_atmega16hva2[2] = { + {0, "cm_programmed", "compatibility mode programmed"}, + {1, "cm_unprogrammed", "compatibility mode unprogrammed"}, }; -// AT90S1200 ATtiny22 AT90S2343 -static const Configvalue _values_rcen_at90s1200[2] = { - {0, "intrcosc", "internal RC oscillator"}, - {1, "extclk", "external clock"}, -}; - -// AT90S2313 ATtiny11 AT90S2323 AT90S4414 AT90S4434 AT90S8515 AT90S8535 -static const Configvalue _values_fstrt_at90s2313[2] = { - {0, "sut_short", "startup time short"}, - {1, "sut_long", "startup time long"}, +// ATmega16HVBrevB ATmega32HVBrevB +static const Configvalue _values_duvrdinit_atmega16hvbrevb[2] = { + {0, "duvr_on", "DUVR mode on"}, + {1, "duvr_off", "DUVR mode off"}, }; // ATA5700M322 ATA5702M322 @@ -11271,7 +11293,7 @@ static const Configvalue _values_ckstart_ata5700m322[2] = { }; /* - * ATA5781 ATA5790 ATA5782 ATA5783 ATA5787 ATA5791 ATA5831 ATA5832 ATA5833 ATA5835 ATA8210 ATA8215 + * ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 ATA5791 ATA5831 ATA5832 ATA5833 ATA5835 ATA8210 ATA8215 * ATA8510 ATA8515 */ static const Configvalue _values_extclken_ata5781[2] = { @@ -11280,27 +11302,28 @@ static const Configvalue _values_extclken_ata5781[2] = { }; /* - * ATmega328 ATmega16M1 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 AT90PWM2 AT90PWM81 - * AT90CAN128 AT90USB162 ATA5781 ATA5790 ATA6285 ATmega103comp AT90SCR100H ATmega161comp - * AT90S8535comp ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega8U2 ATmega16 ATmega16A ATmega16HVB - * ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega128 - * ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A - * ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 - * ATmega323 ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P - * ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P - * ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 - * ATmega2560 ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 - * AT90SCR100 AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - * AT90S8515comp ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 - * ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 ATA8515 ATmega32HVE2 + * AT90S8515comp AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 + * AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny828 ATtiny828R ATmega8 ATmega8A + * ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 + * ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 + * ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 + * ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161 ATmega161comp ATmega1281 ATmega2561 + * ATmega162 ATmega163 ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 + * ATmega328P ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 + * ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 + * ATA8515 */ -static const Configvalue _values_ap_atmega328[4] = { +static const Configvalue _values_ap_at90s8515comp[4] = { {0, "lpm_spm_disabled_in_app", "LPM and SPM prohibited in application section"}, {1, "lpm_disabled_in_app", "LPM prohibited in application section"}, {2, "spm_disabled_in_app", "SPM prohibited in application section"}, @@ -11308,27 +11331,28 @@ static const Configvalue _values_ap_atmega328[4] = { }; /* - * ATmega328 ATmega16M1 ATmega32HVBrevB ATmega64HVE ATmega328PB ATmega8515 AT90PWM2 AT90PWM81 - * AT90CAN128 AT90USB162 ATA5781 ATA5790 ATA6285 ATmega103comp AT90SCR100H ATmega161comp - * AT90S8535comp ATtiny828 ATtiny828R ATmega8 ATmega8A ATmega8U2 ATmega16 ATmega16A ATmega16HVB - * ATmega16HVBrevB ATmega16U2 ATmega16U4 ATmega32 ATmega32A ATmega32HVB ATmega32C1 ATmega32M1 - * ATmega32U2 ATmega32U4 ATmega32U6 ATmega64 ATmega64A ATmega64C1 ATmegaS64M1 ATmega64M1 - * ATmega64HVE2 ATmega64RFR2 ATmega88 ATmega88A ATmega88P ATmega88PA ATmega88PB ATmega128 - * ATmegaS128 ATmega128A ATmega128RFA1 ATmega128RFR2 ATmega161 ATmega162 ATmega163 ATmega164A - * ATmega164P ATmega164PA ATmega165 ATmega165A ATmega165P ATmega165PA ATmega168 ATmega168A - * ATmega168P ATmega168PA ATmega168PB ATmega169 ATmega169A ATmega169P ATmega169PA ATmega256RFR2 - * ATmega323 ATmega324A ATmega324P ATmega324PA ATmega324PB ATmega325 ATmega325A ATmega325P - * ATmega325PA ATmega328P ATmega329 ATmega329A ATmega329P ATmega329PA ATmega406 ATmega640 - * ATmega644 ATmega644A ATmega644P ATmega644PA ATmega644RFR2 ATmega645 ATmega645A ATmega645P - * ATmega649 ATmega649A ATmega649P ATmega1280 ATmega1281 ATmega1284 ATmega1284P ATmega1284RFR2 - * ATmega2560 ATmega2561 ATmega2564RFR2 ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 - * ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A - * ATmega6490P ATmega8535 AT90PWM1 AT90PWM2B AT90PWM3 AT90PWM3B AT90CAN32 AT90CAN64 AT90USB82 - * AT90SCR100 AT90PWM161 AT90PWM216 AT90PWM316 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 - * AT90S8515comp ATA5782 ATA5783 ATA5787 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 ATA5833 ATA5835 - * ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 ATA8515 ATmega32HVE2 + * AT90S8515comp AT90S8535comp AT90CAN32 AT90CAN64 AT90CAN128 AT90PWM1 AT90PWM81 AT90PWM161 + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 AT90USB82 AT90USB162 AT90USB646 + * AT90USB1286 AT90USB647 AT90USB1287 AT90SCR100 AT90SCR100H ATtiny828 ATtiny828R ATmega8 ATmega8A + * ATmega16 ATmega16A ATmega32 ATmega32A ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 + * ATmega640 ATmega1280 ATmega2560 ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 + * ATmegaS64M1 ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega8U2 ATmega16U2 + * ATmega32U2 ATmega16U4 ATmega32U4 ATmega32U6 ATmega161 ATmega161comp ATmega1281 ATmega2561 + * ATmega162 ATmega163 ATmega323 ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P + * ATmega324PA ATmega644 ATmega644A ATmega644P ATmega644PA ATmega1284 ATmega1284P ATmega324PB + * ATmega644RFR2 ATmega1284RFR2 ATmega2564RFR2 ATmega165 ATmega165A ATmega165P ATmega165PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 + * ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega8515 ATmega8535 + * ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 + * ATmega328P ATmega88PB ATmega168PB ATmega328PB ATmega169 ATmega169A ATmega169P ATmega169PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 ATmega649A ATmega649P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P ATmega103comp + * ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB ATmega64HVE ATmega32HVE2 ATmega64HVE2 + * ATmega406 ATA5781 ATA5782 ATA5783 ATA5787 ATA5790 ATA5790N ATA5791 ATA5795 ATA5831 ATA5832 + * ATA5833 ATA5835 ATA6285 ATA6286 ATA6289 ATA6612C ATA6613C ATA6614Q ATA8210 ATA8215 ATA8510 + * ATA8515 */ -static const Configvalue _values_blp_atmega328[4] = { +static const Configvalue _values_blp_at90s8515comp[4] = { {0, "lpm_spm_disabled_in_boot", "LPM and SPM prohibited in boot section"}, {1, "lpm_disabled_in_boot", "LPM prohibited in boot section"}, {2, "spm_disabled_in_boot", "SPM prohibited in boot section"}, @@ -11371,23 +11395,23 @@ static const Configvalue _values_eelock_ata6285[2] = { }; /* - * ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega128A3 - * ATxmega128A3 ATxmega128A3U ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U ATxmega16C4 ATxmega16C4 - * ATxmega16D4 ATxmega16D4 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32D4 ATxmega32D4 ATxmega32E5 - * ATxmega32E5 ATxmega64A1 ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64B3 ATxmega64B3 ATxmega64C3 - * ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1U ATxmega128A1U - * ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128D3 - * ATxmega128D3 ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega192A3 ATxmega192A3 - * ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3U - * ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 - * ATxmega384D3 ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega192A1 + * ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 + * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU ATxmega256A3U ATxmega256A3U + * ATxmega16A4 ATxmega16A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U ATxmega64A4U ATxmega64A4U + * ATxmega128A4U ATxmega128A4U ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 ATxmega64C3 ATxmega64C3 + * ATxmega128C3 ATxmega128C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 ATxmega32D3 ATxmega32D3 + * ATxmega64D3 ATxmega64D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 ATxmega32D4 ATxmega32D4 + * ATxmega64D4 ATxmega64D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_wdper_atxmega16e5[11] = { +static const Configvalue _values_wdper_atxmega64a1[11] = { {0x00, "t_0s008", "8 cycles (8 ms)"}, {0x01, "t_0s016", "16 cycles (16 ms)"}, {0x02, "t_0s032", "32 cycles (32 ms)"}, @@ -11402,23 +11426,23 @@ static const Configvalue _values_wdper_atxmega16e5[11] = { }; /* - * ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega128A3 - * ATxmega128A3 ATxmega128A3U ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U ATxmega16C4 ATxmega16C4 - * ATxmega16D4 ATxmega16D4 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32D4 ATxmega32D4 ATxmega32E5 - * ATxmega32E5 ATxmega64A1 ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64B3 ATxmega64B3 ATxmega64C3 - * ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1U ATxmega128A1U - * ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128D3 - * ATxmega128D3 ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega192A3 ATxmega192A3 - * ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3U - * ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 - * ATxmega384D3 ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega192A1 + * ATxmega192A1 ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 + * ATxmega256A3 ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU ATxmega256A3U ATxmega256A3U + * ATxmega16A4 ATxmega16A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U ATxmega64A4U ATxmega64A4U + * ATxmega128A4U ATxmega128A4U ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 ATxmega64C3 ATxmega64C3 + * ATxmega128C3 ATxmega128C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 ATxmega32D3 ATxmega32D3 + * ATxmega64D3 ATxmega64D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 ATxmega32D4 ATxmega32D4 + * ATxmega64D4 ATxmega64D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_wdwper_atxmega16e5[11] = { +static const Configvalue _values_wdwper_atxmega64a1[11] = { {0x00, "t_0s008", "8 cycles (8 ms)"}, {0x01, "t_0s016", "16 cycles (16 ms)"}, {0x02, "t_0s032", "32 cycles (32 ms)"}, @@ -11433,71 +11457,61 @@ static const Configvalue _values_wdwper_atxmega16e5[11] = { }; /* - * ATxmega16E5 ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 - * ATxmega8E5 ATxmega16A4 ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 ATxmega32D3 ATxmega32A4 - * ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega32E5 ATxmega64A1 ATxmega64A1U ATxmega64B1 - * ATxmega64A3 ATxmega64A3U ATxmega64B3 ATxmega64C3 ATxmega64D3 ATxmega64A4U ATxmega64D4 - * ATxmega128A1 ATxmega128A1revD ATxmega128A1U ATxmega128B1 ATxmega128B3 ATxmega128C3 ATxmega128D3 - * ATxmega128A4U ATxmega128D4 ATxmega192A3 ATxmega192A3U ATxmega192C3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3BU ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 ATxmega384D3 + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A1U ATxmega128A1U + * ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B ATxmega64A3U ATxmega128A3U + * ATxmega192A3U ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 + * ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 ATxmega8E5 ATxmega16E5 + * ATxmega32E5 */ -static const Configvalue _values_wdlock_atxmega16e5[2] = { +static const Configvalue _values_wdlock_atxmega64a1[2] = { {0, "wd_locked", "watchdog timer locked"}, {1, "wd_unlocked", "watchdog timer unlocked"}, }; /* - * ATxmega16E5 ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega128A3U ATxmega64A4 ATxmega128A4 - * ATxmega8E5 ATxmega16A4 ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 ATxmega32D3 ATxmega32A4 - * ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega32E5 ATxmega64A1 ATxmega64A1U ATxmega64B1 - * ATxmega64A3 ATxmega64A3U ATxmega64B3 ATxmega64C3 ATxmega64D3 ATxmega64A4U ATxmega64D4 - * ATxmega128A1 ATxmega128A1revD ATxmega128A1U ATxmega128B1 ATxmega128B3 ATxmega128C3 ATxmega128D3 - * ATxmega128A4U ATxmega128D4 ATxmega192A3 ATxmega192A3U ATxmega192C3 ATxmega192D3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3BU ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 ATxmega384D3 + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A1U ATxmega128A1U + * ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 ATxmega256A3B ATxmega64A3U ATxmega128A3U + * ATxmega192A3U ATxmega256A3BU ATxmega256A3U ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 + * ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 ATxmega8E5 ATxmega16E5 + * ATxmega32E5 */ -static const Configvalue _values_startuptime_atxmega16e5[3] = { +static const Configvalue _values_startuptime_atxmega64a1[3] = { {0, "sut_64ms", "startup time 64 ms"}, {1, "sut_4ms", "startup time 4 ms"}, {3, "sut_0ms", "startup time 0 ms"}, }; -// ATxmega16E5 ATxmega16E5 ATxmega8E5 ATxmega8E5 ATxmega32E5 ATxmega32E5 -static const Configvalue _values_fdact4_atxmega16e5[2] = { - {0, "gpio_from_value_fuse", "during reset and until a timer/counter compare channel is enabled the port pins are set to the VALUEn fuse bits"}, - {1, "default_io", "default I/O pin configuration"}, -}; - -// ATxmega16E5 ATxmega16E5 ATxmega8E5 ATxmega8E5 ATxmega32E5 ATxmega32E5 -static const Configvalue _values_fdact5_atxmega16e5[2] = { - {0, "gpio_from_value_fuse", "during reset and until a timer/counter compare channel is enabled the port pins are set to the VALUEn fuse bits"}, - {1, "default_io", "default I/O pin configuration"}, -}; - /* - * ATxmega16E5 ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega192A1 ATxmega256A1 - * ATxmega256A1 ATxmega256A1 ATxmega128A3 ATxmega128A3 ATxmega128A3 ATxmega128A3U ATxmega128A3U - * ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U - * ATxmega16A4U ATxmega16C4 ATxmega16C4 ATxmega16C4 ATxmega16D4 ATxmega16D4 ATxmega16D4 - * ATxmega32C3 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4 ATxmega32A4U ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32C4 - * ATxmega32D4 ATxmega32D4 ATxmega32D4 ATxmega32E5 ATxmega32E5 ATxmega32E5 ATxmega64A1 ATxmega64A1 - * ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64A3U ATxmega64B3 - * ATxmega64B3 ATxmega64B3 ATxmega64C3 ATxmega64C3 ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64D3 - * ATxmega64A4U ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 ATxmega64D4 ATxmega128A1 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1revD ATxmega128A1U - * ATxmega128A1U ATxmega128A1U ATxmega128B1 ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 - * ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128C3 ATxmega128D3 ATxmega128D3 ATxmega128D3 - * ATxmega128A4U ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega128D4 ATxmega192A3 - * ATxmega192A3 ATxmega192A3 ATxmega192A3U ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 - * ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega192D3 ATxmega256A3 ATxmega256A3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3BU - * ATxmega256A3U ATxmega256A3U ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256C3 ATxmega256D3 - * ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 ATxmega384C3 ATxmega384D3 ATxmega384D3 - * ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD + * ATxmega128A1revD ATxmega128A1revD ATxmega192A1 ATxmega192A1 ATxmega192A1 ATxmega256A1 + * ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega128A1U ATxmega64A3 ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega128A3 + * ATxmega192A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 ATxmega256A3 ATxmega256A3 ATxmega256A3B + * ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega128A3U ATxmega192A3U ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU + * ATxmega256A3BU ATxmega256A3U ATxmega256A3U ATxmega256A3U ATxmega16A4 ATxmega16A4 ATxmega16A4 + * ATxmega32A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U + * ATxmega32A4U ATxmega64A4U ATxmega64A4U ATxmega64A4U ATxmega128A4U ATxmega128A4U ATxmega128A4U + * ATxmega64B1 ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 + * ATxmega32C3 ATxmega64C3 ATxmega64C3 ATxmega64C3 ATxmega128C3 ATxmega128C3 ATxmega128C3 + * ATxmega192C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 + * ATxmega32C4 ATxmega32D3 ATxmega32D3 ATxmega32D3 ATxmega64D3 ATxmega64D3 ATxmega64D3 + * ATxmega128D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 + * ATxmega16D4 ATxmega32D4 ATxmega32D4 ATxmega32D4 ATxmega64D4 ATxmega64D4 ATxmega64D4 + * ATxmega128D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega16E5 ATxmega32E5 ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_blbat_atxmega16e5[4] = { +static const Configvalue _values_blbat_atxmega64a1[4] = { {0, "rwlock", "read and write not allowed"}, {1, "rlock", "read not allowed"}, {2, "wlock", "write not allowed"}, @@ -11505,30 +11519,30 @@ static const Configvalue _values_blbat_atxmega16e5[4] = { }; /* - * ATxmega16E5 ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega192A1 ATxmega256A1 - * ATxmega256A1 ATxmega256A1 ATxmega128A3 ATxmega128A3 ATxmega128A3 ATxmega128A3U ATxmega128A3U - * ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U - * ATxmega16A4U ATxmega16C4 ATxmega16C4 ATxmega16C4 ATxmega16D4 ATxmega16D4 ATxmega16D4 - * ATxmega32C3 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4 ATxmega32A4U ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32C4 - * ATxmega32D4 ATxmega32D4 ATxmega32D4 ATxmega32E5 ATxmega32E5 ATxmega32E5 ATxmega64A1 ATxmega64A1 - * ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64A3U ATxmega64B3 - * ATxmega64B3 ATxmega64B3 ATxmega64C3 ATxmega64C3 ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64D3 - * ATxmega64A4U ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 ATxmega64D4 ATxmega128A1 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1revD ATxmega128A1U - * ATxmega128A1U ATxmega128A1U ATxmega128B1 ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 - * ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128C3 ATxmega128D3 ATxmega128D3 ATxmega128D3 - * ATxmega128A4U ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega128D4 ATxmega192A3 - * ATxmega192A3 ATxmega192A3 ATxmega192A3U ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 - * ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega192D3 ATxmega256A3 ATxmega256A3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3BU - * ATxmega256A3U ATxmega256A3U ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256C3 ATxmega256D3 - * ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 ATxmega384C3 ATxmega384D3 ATxmega384D3 - * ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD + * ATxmega128A1revD ATxmega128A1revD ATxmega192A1 ATxmega192A1 ATxmega192A1 ATxmega256A1 + * ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega128A1U ATxmega64A3 ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega128A3 + * ATxmega192A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 ATxmega256A3 ATxmega256A3 ATxmega256A3B + * ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega128A3U ATxmega192A3U ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU + * ATxmega256A3BU ATxmega256A3U ATxmega256A3U ATxmega256A3U ATxmega16A4 ATxmega16A4 ATxmega16A4 + * ATxmega32A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U + * ATxmega32A4U ATxmega64A4U ATxmega64A4U ATxmega64A4U ATxmega128A4U ATxmega128A4U ATxmega128A4U + * ATxmega64B1 ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 + * ATxmega32C3 ATxmega64C3 ATxmega64C3 ATxmega64C3 ATxmega128C3 ATxmega128C3 ATxmega128C3 + * ATxmega192C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 + * ATxmega32C4 ATxmega32D3 ATxmega32D3 ATxmega32D3 ATxmega64D3 ATxmega64D3 ATxmega64D3 + * ATxmega128D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 + * ATxmega16D4 ATxmega32D4 ATxmega32D4 ATxmega32D4 ATxmega64D4 ATxmega64D4 ATxmega64D4 + * ATxmega128D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega16E5 ATxmega32E5 ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_blba_atxmega16e5[4] = { +static const Configvalue _values_blba_atxmega64a1[4] = { {0, "rwlock", "read and write not allowed"}, {1, "rlock", "read not allowed"}, {2, "wlock", "write not allowed"}, @@ -11536,30 +11550,30 @@ static const Configvalue _values_blba_atxmega16e5[4] = { }; /* - * ATxmega16E5 ATxmega16E5 ATxmega16E5 ATxmega192A1 ATxmega192A1 ATxmega192A1 ATxmega256A1 - * ATxmega256A1 ATxmega256A1 ATxmega128A3 ATxmega128A3 ATxmega128A3 ATxmega128A3U ATxmega128A3U - * ATxmega128A3U ATxmega64A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 ATxmega128A4 ATxmega128A4 - * ATxmega8E5 ATxmega8E5 ATxmega8E5 ATxmega16A4 ATxmega16A4 ATxmega16A4 ATxmega16A4U ATxmega16A4U - * ATxmega16A4U ATxmega16C4 ATxmega16C4 ATxmega16C4 ATxmega16D4 ATxmega16D4 ATxmega16D4 - * ATxmega32C3 ATxmega32C3 ATxmega32C3 ATxmega32D3 ATxmega32D3 ATxmega32D3 ATxmega32A4 ATxmega32A4 - * ATxmega32A4 ATxmega32A4U ATxmega32A4U ATxmega32A4U ATxmega32C4 ATxmega32C4 ATxmega32C4 - * ATxmega32D4 ATxmega32D4 ATxmega32D4 ATxmega32E5 ATxmega32E5 ATxmega32E5 ATxmega64A1 ATxmega64A1 - * ATxmega64A1 ATxmega64A1U ATxmega64A1U ATxmega64A1U ATxmega64B1 ATxmega64B1 ATxmega64B1 - * ATxmega64A3 ATxmega64A3 ATxmega64A3 ATxmega64A3U ATxmega64A3U ATxmega64A3U ATxmega64B3 - * ATxmega64B3 ATxmega64B3 ATxmega64C3 ATxmega64C3 ATxmega64C3 ATxmega64D3 ATxmega64D3 ATxmega64D3 - * ATxmega64A4U ATxmega64A4U ATxmega64A4U ATxmega64D4 ATxmega64D4 ATxmega64D4 ATxmega128A1 - * ATxmega128A1 ATxmega128A1 ATxmega128A1revD ATxmega128A1revD ATxmega128A1revD ATxmega128A1U - * ATxmega128A1U ATxmega128A1U ATxmega128B1 ATxmega128B1 ATxmega128B1 ATxmega128B3 ATxmega128B3 - * ATxmega128B3 ATxmega128C3 ATxmega128C3 ATxmega128C3 ATxmega128D3 ATxmega128D3 ATxmega128D3 - * ATxmega128A4U ATxmega128A4U ATxmega128A4U ATxmega128D4 ATxmega128D4 ATxmega128D4 ATxmega192A3 - * ATxmega192A3 ATxmega192A3 ATxmega192A3U ATxmega192A3U ATxmega192A3U ATxmega192C3 ATxmega192C3 - * ATxmega192C3 ATxmega192D3 ATxmega192D3 ATxmega192D3 ATxmega256A3 ATxmega256A3 ATxmega256A3 - * ATxmega256A3B ATxmega256A3B ATxmega256A3B ATxmega256A3BU ATxmega256A3BU ATxmega256A3BU - * ATxmega256A3U ATxmega256A3U ATxmega256A3U ATxmega256C3 ATxmega256C3 ATxmega256C3 ATxmega256D3 - * ATxmega256D3 ATxmega256D3 ATxmega384C3 ATxmega384C3 ATxmega384C3 ATxmega384D3 ATxmega384D3 - * ATxmega384D3 + * ATxmega64A1 ATxmega64A1 ATxmega64A1 ATxmega128A1 ATxmega128A1 ATxmega128A1 ATxmega128A1revD + * ATxmega128A1revD ATxmega128A1revD ATxmega192A1 ATxmega192A1 ATxmega192A1 ATxmega256A1 + * ATxmega256A1 ATxmega256A1 ATxmega64A1U ATxmega64A1U ATxmega64A1U ATxmega128A1U ATxmega128A1U + * ATxmega128A1U ATxmega64A3 ATxmega64A3 ATxmega64A3 ATxmega128A3 ATxmega128A3 ATxmega128A3 + * ATxmega192A3 ATxmega192A3 ATxmega192A3 ATxmega256A3 ATxmega256A3 ATxmega256A3 ATxmega256A3B + * ATxmega256A3B ATxmega256A3B ATxmega64A3U ATxmega64A3U ATxmega64A3U ATxmega128A3U ATxmega128A3U + * ATxmega128A3U ATxmega192A3U ATxmega192A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3BU + * ATxmega256A3BU ATxmega256A3U ATxmega256A3U ATxmega256A3U ATxmega16A4 ATxmega16A4 ATxmega16A4 + * ATxmega32A4 ATxmega32A4 ATxmega32A4 ATxmega64A4 ATxmega64A4 ATxmega64A4 ATxmega128A4 + * ATxmega128A4 ATxmega128A4 ATxmega16A4U ATxmega16A4U ATxmega16A4U ATxmega32A4U ATxmega32A4U + * ATxmega32A4U ATxmega64A4U ATxmega64A4U ATxmega64A4U ATxmega128A4U ATxmega128A4U ATxmega128A4U + * ATxmega64B1 ATxmega64B1 ATxmega64B1 ATxmega128B1 ATxmega128B1 ATxmega128B1 ATxmega64B3 + * ATxmega64B3 ATxmega64B3 ATxmega128B3 ATxmega128B3 ATxmega128B3 ATxmega32C3 ATxmega32C3 + * ATxmega32C3 ATxmega64C3 ATxmega64C3 ATxmega64C3 ATxmega128C3 ATxmega128C3 ATxmega128C3 + * ATxmega192C3 ATxmega192C3 ATxmega192C3 ATxmega256C3 ATxmega256C3 ATxmega256C3 ATxmega384C3 + * ATxmega384C3 ATxmega384C3 ATxmega16C4 ATxmega16C4 ATxmega16C4 ATxmega32C4 ATxmega32C4 + * ATxmega32C4 ATxmega32D3 ATxmega32D3 ATxmega32D3 ATxmega64D3 ATxmega64D3 ATxmega64D3 + * ATxmega128D3 ATxmega128D3 ATxmega128D3 ATxmega192D3 ATxmega192D3 ATxmega192D3 ATxmega256D3 + * ATxmega256D3 ATxmega256D3 ATxmega384D3 ATxmega384D3 ATxmega384D3 ATxmega16D4 ATxmega16D4 + * ATxmega16D4 ATxmega32D4 ATxmega32D4 ATxmega32D4 ATxmega64D4 ATxmega64D4 ATxmega64D4 + * ATxmega128D4 ATxmega128D4 ATxmega128D4 ATxmega8E5 ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 + * ATxmega16E5 ATxmega32E5 ATxmega32E5 ATxmega32E5 */ -static const Configvalue _values_blbb_atxmega16e5[4] = { +static const Configvalue _values_blbb_atxmega64a1[4] = { {0, "rwlock", "read and write not allowed"}, {1, "rlock", "read not allowed"}, {2, "wlock", "write not allowed"}, @@ -11567,27 +11581,39 @@ static const Configvalue _values_blbb_atxmega16e5[4] = { }; /* - * ATxmega128A3U ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32C3 ATxmega32D3 ATxmega32A4U - * ATxmega32C4 ATxmega32D4 ATxmega64A1U ATxmega64B1 ATxmega64A3U ATxmega64B3 ATxmega64C3 - * ATxmega64D3 ATxmega64A4U ATxmega64D4 ATxmega128A1U ATxmega128B1 ATxmega128B3 ATxmega128C3 - * ATxmega128D3 ATxmega128A4U ATxmega128D4 ATxmega192A3U ATxmega192C3 ATxmega192D3 ATxmega256A3BU - * ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 ATxmega384D3 + * ATxmega64A1U ATxmega128A1U ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3U + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega64B1 ATxmega128B1 ATxmega64B3 + * ATxmega128B3 ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 + * ATxmega16C4 ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 */ -static const Configvalue _values_toscsel_atxmega128a3u[2] = { +static const Configvalue _values_toscsel_atxmega64a1u[2] = { {0, "alternate", "TOSC1/TOSC2 on separate pins"}, {1, "xtal", "TOSC1/TOSC2 shared with XTAL1/XTAL2"}, }; +// ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 ATxmega32E5 ATxmega32E5 +static const Configvalue _values_fdact4_atxmega8e5[2] = { + {0, "gpio_from_value_fuse", "during reset and until a timer/counter compare channel is enabled the port pins are set to the VALUEn fuse bits"}, + {1, "default_io", "default I/O pin configuration"}, +}; + +// ATxmega8E5 ATxmega8E5 ATxmega16E5 ATxmega16E5 ATxmega32E5 ATxmega32E5 +static const Configvalue _values_fdact5_atxmega8e5[2] = { + {0, "gpio_from_value_fuse", "during reset and until a timer/counter compare channel is enabled the port pins are set to the VALUEn fuse bits"}, + {1, "default_io", "default I/O pin configuration"}, +}; + /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 - * AVR32LA28 AVR32LA32 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 */ -static const Configvalue _values_wdtperiod_attiny204[12] = { +static const Configvalue _values_wdtperiod_attiny202[12] = { {0x00, "t_off", "watchdog timer off"}, {0x01, "t_0s008", "8 cycles (8 ms)"}, {0x02, "t_0s016", "16 cycles (16 ms)"}, @@ -11603,17 +11629,17 @@ static const Configvalue _values_wdtperiod_attiny204[12] = { }; /* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16DD20 AVR16DU20 AVR16EB20 AVR16DD28 - * AVR16DU28 AVR16EA28 AVR16EB28 AVR16DD32 AVR16DU32 AVR16EA32 AVR16EB32 AVR16EA48 AVR32DU14 - * AVR32EB14 AVR32DD20 AVR32DU20 AVR32EB20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 - * AVR32EA28 AVR32EB28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 - * AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 AVR64DA28S AVR64DB28 - * AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 AVR64DU32 AVR64EA32 - * AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 - * AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S - * AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 */ -static const Configvalue _values_wdtperiod_avr32dd14[12] = { +static const Configvalue _values_wdtperiod_avr32da28[12] = { {0x00, "t_off", "watchdog timer off"}, {0x01, "t_0s008", "8 cycles (8 ms)"}, {0x02, "t_0s016", "16 cycles (16 ms)"}, @@ -11645,15 +11671,15 @@ static const Configvalue _values_wdtperiod_avr32sd20[12] = { }; /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 - * AVR32LA28 AVR32LA32 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 */ -static const Configvalue _values_wdtwindow_attiny204[12] = { +static const Configvalue _values_wdtwindow_attiny202[12] = { {0x00, "t_off", "window mode off"}, {0x01, "t_0s008", "8 cycles (8 ms)"}, {0x02, "t_0s016", "16 cycles (16 ms)"}, @@ -11669,17 +11695,17 @@ static const Configvalue _values_wdtwindow_attiny204[12] = { }; /* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16DD20 AVR16DU20 AVR16EB20 AVR16DD28 - * AVR16DU28 AVR16EA28 AVR16EB28 AVR16DD32 AVR16DU32 AVR16EA32 AVR16EB32 AVR16EA48 AVR32DU14 - * AVR32EB14 AVR32DD20 AVR32DU20 AVR32EB20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 - * AVR32EA28 AVR32EB28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 - * AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 AVR64DA28S AVR64DB28 - * AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 AVR64DU32 AVR64EA32 - * AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 - * AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S - * AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 */ -static const Configvalue _values_wdtwindow_avr32dd14[12] = { +static const Configvalue _values_wdtwindow_avr32da28[12] = { {0x00, "t_off", "window mode off"}, {0x01, "t_0s008", "8 cycles (8 ms)"}, {0x02, "t_0s016", "16 cycles (16 ms)"}, @@ -11711,46 +11737,46 @@ static const Configvalue _values_wdtwindow_avr32sd20[12] = { }; /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 */ -static const Configvalue _values_bodsleep_attiny204[3] = { +static const Configvalue _values_bodsleep_attiny202[3] = { {0, "bod_disabled", "brownout detection disabled"}, {1, "bod_enabled", "brownout detection enabled"}, {2, "bod_sampled", "brownout detection in sampled mode"}, }; /* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 AVR16DD20 AVR16DU20 AVR16EB20 - * AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 AVR16DD32 AVR16DU32 AVR16EA32 - * AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 AVR32DD20 AVR32DU20 AVR32EB20 - * AVR32LA20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 AVR32EA28 AVR32EB28 - * AVR32LA28 AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 - * AVR32LA32 AVR32SD32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 - * AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 - * AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 - * AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 - * AVR128DA64 AVR128DA64S AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_bodsleep_avr32dd14[3] = { +static const Configvalue _values_bodsleep_avr32da28[3] = { {0, "bod_disabled", "brownout detection disabled"}, {1, "bod_continuous", "brownout detection enabled in continuous mode"}, {2, "bod_sampled", "brownout detection in sampled mode"}, }; /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 */ -static const Configvalue _values_bodactive_attiny204[4] = { +static const Configvalue _values_bodactive_attiny202[4] = { {0, "bod_disabled", "brownout detection disabled"}, {1, "bod_enabled", "brownout detection enabled"}, {2, "bod_sampled", "brownout detection in sampled mode"}, @@ -11758,18 +11784,18 @@ static const Configvalue _values_bodactive_attiny204[4] = { }; /* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 AVR16DD20 AVR16DU20 AVR16EB20 - * AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 AVR16DD32 AVR16DU32 AVR16EA32 - * AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 AVR32DD20 AVR32DU20 AVR32EB20 - * AVR32LA20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 AVR32EA28 AVR32EB28 - * AVR32LA28 AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 - * AVR32LA32 AVR32SD32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 - * AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 - * AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 - * AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 - * AVR128DA64 AVR128DA64S AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_bodactive_avr32dd14[4] = { +static const Configvalue _values_bodactive_avr32da28[4] = { {0, "bod_disabled", "brownout detection disabled"}, {1, "bod_continuous", "brownout detection enabled in continuous mode"}, {2, "bod_sampled", "brownout detection in sampled mode"}, @@ -11777,172 +11803,172 @@ static const Configvalue _values_bodactive_avr32dd14[4] = { }; /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 */ -static const Configvalue _values_bodsampfreq_attiny204[2] = { +static const Configvalue _values_bodsampfreq_attiny202[2] = { {0, "bod_1khz", "1 kHz sampling frequency"}, {1, "bod_125hz", "125 Hz sampling frequency"}, }; /* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 AVR16DD20 AVR16DU20 AVR16EB20 - * AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 AVR16DD32 AVR16DU32 AVR16EA32 - * AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 AVR32DD20 AVR32DU20 AVR32EB20 - * AVR32LA20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 AVR32EA28 AVR32EB28 - * AVR32LA28 AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 - * AVR32LA32 AVR32SD32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 - * AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 - * AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 - * AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 - * AVR128DA64 AVR128DA64S AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_bodsampfreq_avr32dd14[2] = { +static const Configvalue _values_bodsampfreq_avr32da28[2] = { {0, "bod_128hz", "128 Hz sampling frequency"}, {1, "bod_32hz", "32 Hz sampling frequency"}, }; /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 ATtiny807 - * ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 ATtiny1607 - * ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 ATtiny3224 - * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 - * ATmega4808 ATmega4809 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny417 ATtiny814 + * ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 ATtiny426 + * ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 ATtiny3226 + * ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 ATmega4808 + * ATmega4809 */ -static const Configvalue _values_freqsel_attiny204[2] = { +static const Configvalue _values_freqsel_attiny202[2] = { {1, "fcpu_16mhz", "internal clock running at 16 MHz"}, {2, "fcpu_20mhz", "internal clock running at 20 MHz"}, }; -/* - * AVR64EA48 AVR16EB14 AVR16LA14 AVR16EB20 AVR16LA20 AVR16EA28 AVR16EB28 AVR16LA28 AVR16EA32 - * AVR16EB32 AVR16LA32 AVR16EA48 AVR32EB14 AVR32LA14 AVR32EB20 AVR32LA20 AVR32EA28 AVR32EB28 - * AVR32LA28 AVR32EA32 AVR32EB32 AVR32LA32 AVR32EA48 AVR64EA28 AVR64EA32 - */ -static const Configvalue _values_freqsel_avr64ea48[2] = { - {0, "fcpu_20mhz", "OSCHF running at 20 MHz"}, - {1, "fcpu_16mhz", "OSCHF running at 16 MHz"}, -}; - // ATtiny416auto static const Configvalue _values_freqsel_attiny416auto[1] = { {1, "fcpu_16mhz", "internal clock running at 16 MHz"}, }; /* - * ATtiny204 ATtiny1624 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 - * ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 ATtiny804 ATtiny806 - * ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 ATtiny1604 ATtiny1606 - * ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 ATtiny3216 ATtiny3217 - * ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 - * ATmega3209 ATmega4808 ATmega4809 + * AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 + * AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 AVR16LA14 + * AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 */ -static const Configvalue _values_osclock_attiny204[2] = { +static const Configvalue _values_freqsel_avr16ea28[2] = { + {0, "fcpu_20mhz", "OSCHF running at 20 MHz"}, + {1, "fcpu_16mhz", "OSCHF running at 16 MHz"}, +}; + +/* + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 + */ +static const Configvalue _values_osclock_attiny202[2] = { {0, "olock_disabled", "oscillator lock disabled"}, {1, "olock_enabled", "oscillator lock enabled"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpa_attiny204[2] = { +static const Configvalue _values_cmpa_attiny202[2] = { {0, "v_0", "compare A default output value 0"}, {1, "v_1", "compare A default output value 1"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpb_attiny204[2] = { +static const Configvalue _values_cmpb_attiny202[2] = { {0, "v_0", "compare B default output value 0"}, {1, "v_1", "compare B default output value 1"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpc_attiny204[2] = { +static const Configvalue _values_cmpc_attiny202[2] = { {0, "v_0", "compare C default output value 0"}, {1, "v_1", "compare C default output value 1"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpd_attiny204[2] = { +static const Configvalue _values_cmpd_attiny202[2] = { {0, "v_0", "compare D default output value 0"}, {1, "v_1", "compare D default output value 1"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpaen_attiny204[2] = { +static const Configvalue _values_cmpaen_attiny202[2] = { {0, "cpa_disabled", "compare A output disabled"}, {1, "cpa_enabled", "compare A output enabled"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpben_attiny204[2] = { +static const Configvalue _values_cmpben_attiny202[2] = { {0, "cpb_disabled", "compare B output disabled"}, {1, "cpb_enabled", "compare B output enabled"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpcen_attiny204[2] = { +static const Configvalue _values_cmpcen_attiny202[2] = { {0, "cpc_disabled", "compare C output disabled"}, {1, "cpc_enabled", "compare C output enabled"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 * ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 * ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_cmpden_attiny204[2] = { +static const Configvalue _values_cmpden_attiny202[2] = { {0, "cpd_disabled", "compare D output disabled"}, {1, "cpd_enabled", "compare D output enabled"}, }; /* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 - * ATtiny416 ATtiny416auto ATtiny417 ATtiny804 ATtiny806 ATtiny807 ATtiny814 ATtiny816 ATtiny817 - * ATtiny1604 ATtiny1606 ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 */ -static const Configvalue _values_rstpincfg_attiny204[3] = { +static const Configvalue _values_rstpincfg_attiny202[3] = { {0, "gpio", "GPIO mode"}, {1, "updi", "UPDI mode"}, {2, "rst", "reset mode"}, }; /* - * ATtiny1624 ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 + * ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 * ATtiny3224 ATtiny3226 ATtiny3227 */ -static const Configvalue _values_rstpincfg_attiny1624[4] = { +static const Configvalue _values_rstpincfg_attiny424[4] = { {0, "gpio", "GPIO mode"}, {1, "updi", "UPDI mode"}, {2, "rst", "reset mode"}, @@ -11950,21 +11976,32 @@ static const Configvalue _values_rstpincfg_attiny1624[4] = { }; /* - * AVR32DD14 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 ATmega4808 ATmega4809 - * AVR16DD14 AVR16DU14 AVR16DD20 AVR16DU20 AVR16DD28 AVR16DU28 AVR16DD32 AVR16DU32 AVR32DU14 - * AVR32DD20 AVR32DU20 AVR32DD28 AVR32DU28 AVR32DD32 AVR32DU32 AVR64DD14 AVR64DD20 AVR64DD28 - * AVR64DU28 AVR64DD32 AVR64DU32 + * ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 ATmega4808 ATmega4809 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 */ -static const Configvalue _values_rstpincfg_avr32dd14[2] = { +static const Configvalue _values_rstpincfg_atmega808[2] = { {0, "gpio", "GPIO mode"}, {1, "rst", "reset mode"}, }; /* - * AVR64EA48 AVR16EB14 AVR16EB20 AVR16EA28 AVR16EB28 AVR16EA32 AVR16EB32 AVR16EA48 AVR32EB14 - * AVR32EB20 AVR32EA28 AVR32EB28 AVR32EA32 AVR32EB32 AVR32EA48 AVR64EA28 AVR64EA32 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 */ -static const Configvalue _values_rstpincfg_avr64ea48[2] = { +static const Configvalue _values_rstpincfg_avr32da28[2] = { + {0, "gpio", "GPIO mode"}, + {2, "rst", "reset mode"}, +}; + +/* + * AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 + * AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 + */ +static const Configvalue _values_rstpincfg_avr16ea28[2] = { {0, "none", "no external reset"}, {1, "reset", "PF6 configured as reset pin"}, }; @@ -11976,33 +12013,22 @@ static const Configvalue _values_rstpincfg_avr16la14[2] = { }; /* - * AVR32DA28 AVR32DA28S AVR32DB28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DA48 AVR32DA48S AVR32DB48 - * AVR64DA28 AVR64DA28S AVR64DB28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DA48 AVR64DA48S AVR64DB48 - * AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S - * AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S AVR128DB64 + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 + * ATtiny1606 ATtiny1607 ATtiny212 ATtiny214 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 + * ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 ATtiny424 + * ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 ATtiny3224 + * ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 + * ATmega4808 ATmega4809 AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 + * AVR64DA28S AVR64DA32 AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 + * AVR128DA28S AVR128DA32 AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 + * AVR32DB32 AVR32DB48 AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 + * AVR128DB64 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 + * AVR64DD14 AVR64DD20 AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 + * AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 + * AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 + * AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 */ -static const Configvalue _values_rstpincfg_avr32da28[2] = { - {0, "gpio", "GPIO mode"}, - {2, "rst", "reset mode"}, -}; - -/* - * ATtiny204 ATtiny1624 AVR32DD14 AVR64EA48 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 - * ATtiny406 ATtiny412 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny424 ATtiny426 ATtiny427 - * ATtiny804 ATtiny806 ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny824 ATtiny826 ATtiny827 - * ATtiny1604 ATtiny1606 ATtiny1607 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny1626 ATtiny1627 - * ATtiny3216 ATtiny3217 ATtiny3224 ATtiny3226 ATtiny3227 ATmega808 ATmega809 ATmega1608 - * ATmega1609 ATmega3208 ATmega3209 ATmega4808 ATmega4809 AVR16DD14 AVR16DU14 AVR16EB14 AVR16DD20 - * AVR16DU20 AVR16EB20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16DD32 AVR16DU32 AVR16EA32 - * AVR16EB32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32DD20 AVR32DU20 AVR32EB20 AVR32DA28 AVR32DA28S - * AVR32DB28 AVR32DD28 AVR32DU28 AVR32EA28 AVR32EB28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 - * AVR32DU32 AVR32EA32 AVR32EB32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 - * AVR64DA28 AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 - * AVR64DD32 AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 - * AVR128DA28 AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S - * AVR128DB48 AVR128DA64 AVR128DA64S AVR128DB64 - */ -static const Configvalue _values_crcsrc_attiny204[4] = { +static const Configvalue _values_crcsrc_attiny202[4] = { {0, "flash", "CRC of entire flash (boot, application code and application data)"}, {1, "boot", "CRC of boot section"}, {2, "bootapp", "CRC of application code and boot sections"}, @@ -12010,100 +12036,58 @@ static const Configvalue _values_crcsrc_attiny204[4] = { }; /* - * ATtiny1624 ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 + * ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 * ATtiny3224 ATtiny3226 ATtiny3227 */ -static const Configvalue _values_toutdis_attiny1624[2] = { +static const Configvalue _values_toutdis_attiny424[2] = { {0, "to_disabled", "timeout disabled"}, {1, "to_enabled", "timeout enabled"}, }; /* - * AVR32DD14 AVR16DD14 AVR16DU14 AVR16DD20 AVR16DU20 AVR16DD28 AVR16DU28 AVR16DD32 AVR16DU32 - * AVR32DU14 AVR32DD20 AVR32DU20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 AVR32DA32 - * AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32DA48 AVR32DA48S AVR32DB48 AVR64DD14 AVR64DD20 - * AVR64DA28 AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 - * AVR64DU32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S - * AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 - * AVR128DA64S AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 */ -static const Configvalue _values_clksel_avr32dd14[2] = { +static const Configvalue _values_clksel_avr32da28[2] = { {0, "oschf", "1-32 MHz internal oscillator"}, {1, "osc32k", "32.768 kHz internal oscillator"}, }; /* - * AVR32DD14 AVR16DD14 AVR16DU14 AVR16DD20 AVR16DU20 AVR16DD28 AVR16DU28 AVR16DD32 AVR16DU32 - * AVR32DU14 AVR32DD20 AVR32DU20 AVR32DD28 AVR32DU28 AVR32DD32 AVR32DU32 AVR64DD14 AVR64DD20 - * AVR64DD28 AVR64DU28 AVR64DD32 AVR64DU32 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_updipincfg_avr32dd14[2] = { - {0, "gpio", "GPIO mode"}, - {1, "updi", "UPDI mode"}, -}; - -/* - * AVR64EA48 AVR16EB14 AVR16EB20 AVR16EA28 AVR16EB28 AVR16EA32 AVR16EB32 AVR16EA48 AVR32EB14 - * AVR32EB20 AVR32EA28 AVR32EB28 AVR32EA32 AVR32EB32 AVR32EA48 AVR64EA28 AVR64EA32 - */ -static const Configvalue _values_updipincfg_avr64ea48[2] = { - {0, "gpio", "PF7 configured as GPIO pin"}, - {1, "updi", "PF7 configured as UPDI pin"}, -}; - -// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 -static const Configvalue _values_updipincfg_avr16la14[2] = { - {0, "gpio", "PF7 configures as GPIO pin"}, - {1, "updi", "PF7 configures as UPDI pin"}, -}; - -/* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 AVR16DD20 AVR16DU20 AVR16EB20 - * AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 AVR16DD32 AVR16DU32 AVR16EA32 - * AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 AVR32DD20 AVR32DU20 AVR32EB20 - * AVR32LA20 AVR32SD20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 AVR32EA28 AVR32EB28 - * AVR32LA28 AVR32SD28 AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 - * AVR32LA32 AVR32SD32 AVR32DA48 AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 - * AVR64DA28S AVR64DB28 AVR64DD28 AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 - * AVR64DU32 AVR64EA32 AVR64DA48 AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 - * AVR128DA28S AVR128DB28 AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 - * AVR128DA64 AVR128DA64S AVR128DB64 - */ -static const Configvalue _values_crcsel_avr32dd14[2] = { +static const Configvalue _values_crcsel_avr32da28[2] = { {0, "crc16", "enable CRC16"}, {1, "crc32", "enable CRC32"}, }; /* - * AVR32DD14 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD20 AVR32DB28 AVR32DD28 AVR32DB32 - * AVR32DD32 AVR32DB48 AVR64DD14 AVR64DD20 AVR64DB28 AVR64DD28 AVR64DB32 AVR64DD32 AVR64DB48 - * AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 + * AVR32DA28 AVR32DA28S AVR32DA32 AVR32DA32S AVR32DA48 AVR32DA48S AVR64DA28 AVR64DA28S AVR64DA32 + * AVR64DA32S AVR64DA48 AVR64DA48S AVR64DA64 AVR64DA64S AVR128DA28 AVR128DA28S AVR128DA32 + * AVR128DA32S AVR128DA48 AVR128DA48S AVR128DA64 AVR128DA64S AVR32DB28 AVR32DB32 AVR32DB48 + * AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 AVR128DB48 AVR128DB64 AVR16DD14 + * AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 AVR64DD20 + * AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 + * AVR32DU32 AVR64DU28 AVR64DU32 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 + * AVR64EA28 AVR64EA32 AVR64EA48 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 + * AVR32EB28 AVR32EB32 AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 + * AVR32LA32 */ -static const Configvalue _values_mvsyscfg_avr32dd14[2] = { - {1, "dual", "device used in a dual supply configuration"}, - {2, "single", "device used in a single supply configuration"}, -}; - -// AVR32SD20 AVR32SD28 AVR32SD32 -static const Configvalue _values_mvsyscfg_avr32sd20[3] = { - {0, "reserved", "Reserved"}, - {1, "dual", "device used in a dual supply configuration"}, - {2, "single", "device used in a single supply configuration"}, -}; - -/* - * AVR32DD14 AVR64EA48 AVR16DD14 AVR16DU14 AVR16EB14 AVR16LA14 AVR16DD20 AVR16DU20 AVR16EB20 - * AVR16LA20 AVR16DD28 AVR16DU28 AVR16EA28 AVR16EB28 AVR16LA28 AVR16DD32 AVR16DU32 AVR16EA32 - * AVR16EB32 AVR16LA32 AVR16EA48 AVR32DU14 AVR32EB14 AVR32LA14 AVR32DD20 AVR32DU20 AVR32EB20 - * AVR32LA20 AVR32DA28 AVR32DA28S AVR32DB28 AVR32DD28 AVR32DU28 AVR32EA28 AVR32EB28 AVR32LA28 - * AVR32DA32 AVR32DA32S AVR32DB32 AVR32DD32 AVR32DU32 AVR32EA32 AVR32EB32 AVR32LA32 AVR32DA48 - * AVR32DA48S AVR32DB48 AVR32EA48 AVR64DD14 AVR64DD20 AVR64DA28 AVR64DA28S AVR64DB28 AVR64DD28 - * AVR64DU28 AVR64EA28 AVR64DA32 AVR64DA32S AVR64DB32 AVR64DD32 AVR64DU32 AVR64EA32 AVR64DA48 - * AVR64DA48S AVR64DB48 AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA28 AVR128DA28S AVR128DB28 - * AVR128DA32 AVR128DA32S AVR128DB32 AVR128DA48 AVR128DA48S AVR128DB48 AVR128DA64 AVR128DA64S - * AVR128DB64 - */ -static const Configvalue _values_key_avr32dd14[2] = { +static const Configvalue _values_key_avr32da28[2] = { {0x5cc5c55c, "nolock", "no locks"}, {0xa33a3aa3, "rwlock", "read and write not allowed"}, }; @@ -12114,49 +12098,13 @@ static const Configvalue _values_key_avr32sd20[2] = { {0x5cc5c55c, "nolock", "no locks"}, }; -// ATmega103comp ATmega64 ATmega64A ATmega128 ATmegaS128 ATmega128A -static const Configvalue _values_m103c_atmega103comp[2] = { - {0, "c103_enabled", "ATmega103 compatibility mode enabled"}, - {1, "c103_disabled", "ATmega103 compatibility mode disabled"}, -}; - -// ATmega161comp ATmega162 -static const Configvalue _values_m161c_atmega161comp[2] = { - {0, "c161_enabled", "ATmega161 compatibility mode enabled"}, - {1, "c161_disabled", "ATmega161 compatibility mode disabled"}, -}; - -// AT90S8535comp ATmega8535 -static const Configvalue _values_s8535c_at90s8535comp[2] = { - {0, "c8535_enabled", "AT90S4434/8535 compatibility mode enabled"}, - {1, "c8535_disabled", "AT90S4434/8535 compatibility mode disabled"}, -}; - /* - * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32SD20 AVR32DU28 AVR32SD28 - * AVR32DU32 AVR32SD32 AVR64DU28 AVR64DU32 + * AVR32DA28S AVR32DA32S AVR32DA48S AVR64DA28S AVR64DA32S AVR64DA48S AVR64DA64S AVR128DA28S + * AVR128DA32S AVR128DA48S AVR128DA64S AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 + * AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 + * AVR32EB20 AVR32EB28 AVR32EB32 AVR32SD20 AVR32SD28 AVR32SD32 */ -static const Configvalue _values_browsave_avr16du14[2] = { - {0, "br_erased", "BOOTROW is erased during chip erase"}, - {1, "br_preserved", "BOOTROW is preserved during chip erase"}, -}; - -/* - * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 - * AVR64DU32 - */ -static const Configvalue _values_usbsink_avr16du14[2] = { - {0, "disable", "USB VREG cannot sink current"}, - {1, "enable", "USB VREG can sink current"}, -}; - -/* - * AVR16DU14 AVR16EB14 AVR16DU20 AVR16EB20 AVR16DU28 AVR16EB28 AVR16DU32 AVR16EB32 AVR32DU14 - * AVR32EB14 AVR32DU20 AVR32EB20 AVR32SD20 AVR32DA28S AVR32DU28 AVR32EB28 AVR32SD28 AVR32DA32S - * AVR32DU32 AVR32EB32 AVR32SD32 AVR32DA48S AVR64DA28S AVR64DU28 AVR64DA32S AVR64DU32 AVR64DA48S - * AVR64DA64S AVR128DA28S AVR128DA32S AVR128DA48S AVR128DA64S - */ -static const Configvalue _values_nvmlevel_avr16du14[2] = { +static const Configvalue _values_nvmlevel_avr32da28s[2] = { {2, "nvmaccdis", "NVM access through UPDI disabled"}, {3, "basic", "UPDI and UPDI pins working normally"}, }; @@ -12168,12 +12116,12 @@ static const Configvalue _values_nvmlevel_avr16la14[2] = { }; /* - * AVR16DU14 AVR16EB14 AVR16DU20 AVR16EB20 AVR16DU28 AVR16EB28 AVR16DU32 AVR16EB32 AVR32DU14 - * AVR32EB14 AVR32DU20 AVR32EB20 AVR32DA28S AVR32DU28 AVR32EB28 AVR32DA32S AVR32DU32 AVR32EB32 - * AVR32DA48S AVR64DA28S AVR64DU28 AVR64DA32S AVR64DU32 AVR64DA48S AVR64DA64S AVR128DA28S - * AVR128DA32S AVR128DA48S AVR128DA64S + * AVR32DA28S AVR32DA32S AVR32DA48S AVR64DA28S AVR64DA32S AVR64DA48S AVR64DA64S AVR128DA28S + * AVR128DA32S AVR128DA48S AVR128DA64S AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 + * AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 + * AVR32EB20 AVR32EB28 AVR32EB32 */ -static const Configvalue _values_nvmkey_avr16du14[2] = { +static const Configvalue _values_nvmkey_avr32da28s[2] = { {0x00, "notact", "not active"}, {0xb45, "nvmact", "NVM protection active"}, }; @@ -12191,8 +12139,68 @@ static const Configvalue _values_nvmkey_avr32sd20[2] = { }; /* - * AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32SD20 AVR32LA28 AVR32SD28 - * AVR32LA32 AVR32SD32 + * AVR32DB28 AVR32DB32 AVR32DB48 AVR64DB28 AVR64DB32 AVR64DB48 AVR64DB64 AVR128DB28 AVR128DB32 + * AVR128DB48 AVR128DB64 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 + * AVR32DD32 AVR64DD14 AVR64DD20 AVR64DD28 AVR64DD32 + */ +static const Configvalue _values_mvsyscfg_avr32db28[2] = { + {1, "dual", "device used in a dual supply configuration"}, + {2, "single", "device used in a single supply configuration"}, +}; + +// AVR32SD20 AVR32SD28 AVR32SD32 +static const Configvalue _values_mvsyscfg_avr32sd20[3] = { + {0, "reserved", "Reserved"}, + {1, "dual", "device used in a dual supply configuration"}, + {2, "single", "device used in a single supply configuration"}, +}; + +/* + * AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 + * AVR64DD20 AVR64DD28 AVR64DD32 AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 + * AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 + */ +static const Configvalue _values_updipincfg_avr16dd14[2] = { + {0, "gpio", "GPIO mode"}, + {1, "updi", "UPDI mode"}, +}; + +/* + * AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 + * AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 + */ +static const Configvalue _values_updipincfg_avr16ea28[2] = { + {0, "gpio", "PF7 configured as GPIO pin"}, + {1, "updi", "PF7 configured as UPDI pin"}, +}; + +// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 +static const Configvalue _values_updipincfg_avr16la14[2] = { + {0, "gpio", "PF7 configures as GPIO pin"}, + {1, "updi", "PF7 configures as UPDI pin"}, +}; + +/* + * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 + * AVR64DU32 AVR32SD20 AVR32SD28 AVR32SD32 + */ +static const Configvalue _values_browsave_avr16du14[2] = { + {0, "br_erased", "BOOTROW is erased during chip erase"}, + {1, "br_preserved", "BOOTROW is preserved during chip erase"}, +}; + +/* + * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 + * AVR64DU32 + */ +static const Configvalue _values_usbsink_avr16du14[2] = { + {0, "disable", "USB VREG cannot sink current"}, + {1, "enable", "USB VREG can sink current"}, +}; + +/* + * AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 AVR32SD20 + * AVR32SD28 AVR32SD32 */ static const Configvalue _values_crcboot_avr16la14[2] = { {0, "cb_no", "No CRC scan of boot section during reset"}, @@ -12210,604 +12218,382 @@ static const Configvalue _values_wdtmon_avr32sd20[4] = { // Configuration tables -// ATmega328 ATmega328P ATA6614Q -const Configitem cfgtab_atmega328[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega328, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// ATtiny4 ATtiny5 ATtiny9 ATtiny10 +const Configitem cfgtab_attiny4[4] = { + {"rstdisbl", 2, _values_rstdisbl_attiny4, "fuse", 0, 0x01, 0, 1, "reset configuration"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, + {"ckout", 2, _values_ckout_attiny4, "fuse", 0, 0x04, 2, 1, "clock output"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; -// ATmega16M1 -const Configitem cfgtab_atmega16m1[17] = { - {"sut_cksel", 53, _values_sut_cksel_atmega16m1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"pscrvb", 2, _values_pscrvb_atmega16m1, "efuse", 2, 0x08, 3, 1, "PSC0UTnB reset value"}, - {"pscrva", 2, _values_pscrva_atmega16m1, "efuse", 2, 0x10, 4, 1, "PSCOUTnA reset value"}, - {"pscrb", 2, _values_pscrb_atmega16m1, "efuse", 2, 0x20, 5, 1, "PSC reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// ATtiny20 +const Configitem cfgtab_attiny20[5] = { + {"rstdisbl", 2, _values_rstdisbl_attiny4, "fuse", 0, 0x01, 0, 1, "reset configuration"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, + {"ckout", 2, _values_ckout_attiny4, "fuse", 0, 0x04, 2, 1, "clock output"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "fuse", 0, 0x70, 4, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; -// ATmega16HVA2 -const Configitem cfgtab_atmega16hva2[9] = { - {"sut", 8, _values_sut_atmega16hva2, "lfuse", 0, 0x07, 0, -1, "startup time"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "lfuse", 0, 0x08, 3, -1, "self programming"}, - {"dwen", 2, _values_dwen_atmega328, "lfuse", 0, 0x10, 4, -1, "debugWIRE"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, -1, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, -1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, -1, "watchdog timer"}, - {"cksel", 2, _values_cksel_atmega16hva2, "hfuse", 1, 0x03, 0, -1, "oscillator"}, - {"compmode", 2, _values_compmode_atmega16hva2, "hfuse", 1, 0x04, 2, -1, "compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATmega32HVBrevB -const Configitem cfgtab_atmega32hvbrevb[12] = { - {"cksel", 1, _values_cksel_atmega32hvbrevb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, - {"sut", 8, _values_sut_atmega32hvbrevb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, - {"duvrdinit", 2, _values_duvrdinit_atmega32hvbrevb, "hfuse", 1, 0x10, 4, 0, "DUVR mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega64HVE -const Configitem cfgtab_atmega64hve[13] = { - {"cksel", 1, _values_cksel_atmega64hve, "lfuse", 0, 0x01, 0, -1, "oscillator"}, - {"sut", 4, _values_sut_atmega64hve, "lfuse", 0, 0x06, 1, -1, "startup time"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x08, 3, -1, "clock prescaled"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x10, 4, -1, "brownout detection"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, -1, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, -1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, -1, "watchdog timer"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, -1, "debugWIRE"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega328PB -const Configitem cfgtab_atmega328pb[15] = { - {"sut_cksel", 47, _values_sut_cksel_atmega328pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"cfd", 2, _values_cfd_atmega328pb, "efuse", 2, 0x08, 3, 0, "clock failure detection"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega8515 -const Configitem cfgtab_atmega8515[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x40, 6, 1, "watchdog timer"}, - {"s8515c", 2, _values_s8515c_atmega8515, "hfuse", 1, 0x80, 7, 1, "AT90S4414/8515 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// ATtiny40 +const Configitem cfgtab_attiny40[5] = { + {"rstdisbl", 2, _values_rstdisbl_attiny40, "fuse", 0, 0x01, 0, 1, "reset configuration"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, + {"ckout", 2, _values_ckout_attiny40, "fuse", 0, 0x04, 2, 1, "clock output"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "fuse", 0, 0x70, 4, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATtiny102 ATtiny104 const Configitem cfgtab_attiny102[5] = { {"rstdisbl", 2, _values_rstdisbl_attiny102, "fuse", 0, 0x01, 0, 1, "reset configuration"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, {"ckout", 2, _values_ckout_attiny102, "fuse", 0, 0x04, 2, 1, "clock output"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "fuse", 0, 0x08, 3, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "fuse", 0, 0x08, 3, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; -// ATtiny28 -const Configitem cfgtab_attiny28[3] = { - {"cksel", 16, _values_cksel_attiny28, "fuse", 0, 0x0f, 0, 0x02, "clock source"}, - {"intcap", 2, _values_intcap_attiny28, "fuse", 0, 0x10, 4, 1, "internal load capacitors between XTAL1/XTAL2 and GND"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, +// AT90S1200 +const Configitem cfgtab_at90s1200[3] = { + {"rcen", 2, _values_rcen_at90s1200, "fuse", 0, 0x01, 0, 1, "clock source"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, }; -// ATtiny441 ATtiny841 -const Configitem cfgtab_attiny441[14] = { - {"sut_cksel", 17, _values_sut_cksel_attiny441, "lfuse", 0, 0x1f, 0, 0x02, "clock source"}, - {"ckout", 2, _values_ckout_attiny441, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_attiny441, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_attiny441, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"bodact", 3, _values_bodact_attiny441, "efuse", 2, 0x06, 1, 3, "brownout detection in active/idle mode"}, - {"bodpd", 3, _values_bodpd_attiny441, "efuse", 2, 0x18, 3, 3, "brownout detection in power-down mode"}, - {"ulposcsel", 5, _values_ulposcsel_attiny441, "efuse", 2, 0xe0, 5, 7, "frequency for internal ultra-low-power oscillator"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, +// AT90S2313 AT90S4414 AT90S4434 AT90S8515 AT90S8535 +const Configitem cfgtab_at90s2313[3] = { + {"fstrt", 2, _values_fstrt_at90s2313, "fuse", 0, 0x01, 0, 1, "startup time"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, }; -// AT90PWM2 AT90PWM3 -const Configitem cfgtab_at90pwm2[18] = { - {"sut_cksel", 42, _values_sut_cksel_at90pwm2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"pscrv", 2, _values_pscrv_at90pwm2, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, - {"psc0rb", 2, _values_psc0rb_at90pwm2, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, - {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, - {"psc2rb", 2, _values_psc2rb_at90pwm2, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// AT90S2323 +const Configitem cfgtab_at90s2323[3] = { + {"fstrt", 2, _values_fstrt_at90s2313, "fuse", 0, 0x01, 0, 0, "startup time"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, +}; + +// AT90S2333 +const Configitem cfgtab_at90s2333[5] = { + {"sut_cksel", 8, _values_sut_cksel_at90s2333, "fuse", 0, 0x07, 0, -1, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "fuse", 0, 0x08, 3, -1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "fuse", 0, 0x10, 4, -1, "brownout detection trigger level"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, -1, "serial programming"}, + {"lb", 3, _values_lb_at90s2333, "lock", 0, 0x06, 1, -1, "lock bits"}, +}; + +// AT90S2343 +const Configitem cfgtab_at90s2343[3] = { + {"rcen", 2, _values_rcen_at90s1200, "fuse", 0, 0x01, 0, 0, "clock source"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, +}; + +// AT90S4433 +const Configitem cfgtab_at90s4433[5] = { + {"sut_cksel", 8, _values_sut_cksel_at90s2333, "fuse", 0, 0x07, 0, 2, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "fuse", 0, 0x08, 3, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "fuse", 0, 0x10, 4, 1, "brownout detection trigger level"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, +}; + +// AT90S8515comp +const Configitem cfgtab_at90s8515comp[13] = { + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, -1, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, -1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, -1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, -1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x40, 6, -1, "watchdog timer"}, + {"s8515c", 2, _values_s8515c_at90s8515comp, "hfuse", 1, 0x80, 7, -1, "AT90S4414/8515 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90S8535comp +const Configitem cfgtab_at90s8535comp[13] = { + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, -1, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, -1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, -1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, -1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x40, 6, -1, "watchdog timer"}, + {"s8535c", 2, _values_s8535c_at90s8535comp, "hfuse", 1, 0x80, 7, -1, "AT90S4434/8535 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90CAN32 +const Configitem cfgtab_at90can32[15] = { + {"sut_cksel", 38, _values_sut_cksel_at90can32, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"ta0sel", 2, _values_ta0sel_at90can32, "efuse", 2, 0x01, 0, 1, "reserved for factory tests"}, + {"bodlevel", 8, _values_bodlevel_at90can32, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90CAN64 +const Configitem cfgtab_at90can64[15] = { + {"sut_cksel", 38, _values_sut_cksel_at90can32, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"ta0sel", 2, _values_ta0sel_at90can32, "efuse", 2, 0x01, 0, 1, "reserved for factory tests"}, + {"bodlevel", 8, _values_bodlevel_at90can32, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90CAN128 +const Configitem cfgtab_at90can128[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"ta0sel", 2, _values_ta0sel_at90can32, "efuse", 2, 0x01, 0, 1, "reserved for factory tests"}, + {"bodlevel", 8, _values_bodlevel_at90can32, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90PWM1 +const Configitem cfgtab_at90pwm1[17] = { + {"sut_cksel", 42, _values_sut_cksel_at90pwm1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"pscrv", 2, _values_pscrv_at90pwm1, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, + {"psc0rb", 2, _values_psc0rb_at90pwm1, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, + {"psc2rb", 2, _values_psc2rb_at90pwm1, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // AT90PWM81 AT90PWM161 const Configitem cfgtab_at90pwm81[19] = { {"sut_cksel", 56, _values_sut_cksel_at90pwm81, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, {"ckout", 2, _values_ckout_at90pwm81, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, {"bodlevel", 8, _values_bodlevel_at90pwm81, "efuse", 2, 0x07, 0, 5, "brownout detection trigger level"}, {"pscinrb", 2, _values_pscinrb_at90pwm81, "efuse", 2, 0x08, 3, 1, "PSC2 and PSC0 input reset behavior"}, - {"pscrv", 2, _values_pscrv_at90pwm2, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, - {"psc0rb", 2, _values_psc0rb_at90pwm2, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, + {"pscrv", 2, _values_pscrv_at90pwm1, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, + {"psc0rb", 2, _values_psc0rb_at90pwm1, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, {"psc2rba", 2, _values_psc2rba_at90pwm81, "efuse", 2, 0x40, 6, 1, "PSC2 reset behavior for 22 and 23"}, - {"psc2rb", 2, _values_psc2rb_at90pwm2, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"psc2rb", 2, _values_psc2rb_at90pwm1, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// AT90CAN128 -const Configitem cfgtab_at90can128[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"ta0sel", 2, _values_ta0sel_at90can128, "efuse", 2, 0x01, 0, 1, "reserved for factory tests"}, - {"bodlevel", 8, _values_bodlevel_at90can128, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// AT90PWM2 AT90PWM3 +const Configitem cfgtab_at90pwm2[18] = { + {"sut_cksel", 42, _values_sut_cksel_at90pwm1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"pscrv", 2, _values_pscrv_at90pwm1, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, + {"psc0rb", 2, _values_psc0rb_at90pwm1, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, + {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, + {"psc2rb", 2, _values_psc2rb_at90pwm1, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// AT90USB162 ATmega16U2 AT90USB82 -const Configitem cfgtab_at90usb162[15] = { +// AT90PWM2B AT90PWM3B +const Configitem cfgtab_at90pwm2b[18] = { + {"sut_cksel", 53, _values_sut_cksel_at90pwm2b, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"pscrv", 2, _values_pscrv_at90pwm1, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, + {"psc0rb", 2, _values_psc0rb_at90pwm1, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, + {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, + {"psc2rb", 2, _values_psc2rb_at90pwm1, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90PWM216 +const Configitem cfgtab_at90pwm216[18] = { + {"sut_cksel", 42, _values_sut_cksel_at90pwm1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"pscrv", 2, _values_pscrv_at90pwm1, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, + {"psc0rb", 2, _values_psc0rb_at90pwm1, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, + {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, + {"psc2rb", 2, _values_psc2rb_at90pwm1, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90PWM316 +const Configitem cfgtab_at90pwm316[18] = { + {"sut_cksel", 53, _values_sut_cksel_at90pwm2b, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"pscrv", 2, _values_pscrv_at90pwm1, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, + {"psc0rb", 2, _values_psc0rb_at90pwm1, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, + {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, + {"psc2rb", 2, _values_psc2rb_at90pwm1, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// AT90USB82 AT90USB162 ATmega16U2 +const Configitem cfgtab_at90usb82[15] = { {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"rstdisbl", 2, _values_rstdisbl_at90usb162, "hfuse", 1, 0x40, 6, 1, "reset configuration"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, - {"bodlevel", 8, _values_bodlevel_at90usb162, "efuse", 2, 0x07, 0, 4, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 0, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"rstdisbl", 2, _values_rstdisbl_at90usb82, "hfuse", 1, 0x40, 6, 1, "reset configuration"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, + {"bodlevel", 8, _values_bodlevel_at90usb82, "efuse", 2, 0x07, 0, 4, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 0, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// AT90S1200 -const Configitem cfgtab_at90s1200[3] = { - {"rcen", 2, _values_rcen_at90s1200, "fuse", 0, 0x01, 0, 1, "clock source"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, +// AT90USB646 AT90USB647 +const Configitem cfgtab_at90usb646[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90usb646, "hfuse", 1, 0x06, 1, 1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_at90usb646, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 0, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// AT90S2313 AT90S4414 AT90S4434 AT90S8515 AT90S8535 -const Configitem cfgtab_at90s2313[3] = { - {"fstrt", 2, _values_fstrt_at90s2313, "fuse", 0, 0x01, 0, 1, "startup time"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, +// AT90USB1286 AT90USB1287 +const Configitem cfgtab_at90usb1286[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_at90usb646, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 0, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// ATA5700M322 ATA5702M322 -const Configitem cfgtab_ata5700m322[9] = { - {"pcee1", 2, _values_pcee1_ata5700m322, "fuse", 0, 0x01, 0, 1, "protect customer EEPROM section"}, - {"eeacc", 2, _values_eeacc_ata5700m322, "fuse", 0, 0x02, 1, 1, "EEPROM access control"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse", 0, 0x04, 2, 1, "reset address"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckstart", 2, _values_ckstart_ata5700m322, "fuse", 0, 0x80, 7, 1, "MRC during reset startup phase"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATA5781 ATA5782 ATA5783 ATA5831 ATA5832 ATA5833 -const Configitem cfgtab_ata5781[11] = { - {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, - {"rstdisbl", 2, _values_rstdisbl_ata5781, "fuse", 0, 0x02, 1, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse", 0, 0x04, 2, 1, "reset address"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"ap", 4, _values_ap_atmega328, "lock", 0, 0x0c, 2, 3, "application protection"}, - {"blp", 4, _values_blp_atmega328, "lock", 0, 0x30, 4, 3, "boot loader protection"}, -}; - -// ATA5790 ATA5791 -const Configitem cfgtab_ata5790[11] = { - {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, - {"_32oen", 2, _values__32oen_ata5790, "fuse", 0, 0x02, 1, 0, "32 kHz oscillator"}, - {"reserved", 1, _values_reserved_ata5790, "fuse", 0, 0x04, 2, 0, "bit must be programmed"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 0, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "fuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATA6285 ATA6286 -const Configitem cfgtab_ata6285[17] = { - {"tsrdi", 2, _values_tsrdi_ata6285, "lfuse", 0, 0x01, 0, 1, "temperature shutdown reset"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x02, 1, 0, "brownout detection"}, - {"frcfs", 2, _values_frcfs_ata6285, "lfuse", 0, 0x04, 2, 0, "fast RC oscillator frequency"}, - {"wdrcon", 2, _values_wdrcon_ata6285, "lfuse", 0, 0x08, 3, 0, "watchdog RC oscillator"}, - {"sut_cksel", 3, _values_sut_cksel_ata6285, "lfuse", 0, 0x30, 4, 2, "clock source"}, - {"ckout", 2, _values_ckout_ata6285, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_ata6285, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"eelock", 2, _values_eelock_ata6285, "hfuse", 1, 0x80, 7, 1, "Upper EEPROM"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATxmega16E5 ATxmega8E5 ATxmega32E5 -const Configitem cfgtab_atxmega16e5[17] = { - {"wdper", 11, _values_wdper_atxmega16e5, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdwper", 11, _values_wdwper_atxmega16e5, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodpd", 3, _values_bodpd_atxmega16e5, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse2", 2, 0x40, 6, 1, "reset address"}, - {"wdlock", 2, _values_wdlock_atxmega16e5, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, - {"startuptime", 3, _values_startuptime_atxmega16e5, "fuse4", 4, 0x0c, 2, 3, "startup time"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atxmega16e5, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, - {"bodact", 3, _values_bodact_atxmega16e5, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"value", 0, NULL, "fuse6", 6, 0x3f, 0, 0x3f, "port pin value"}, - {"fdact4", 2, _values_fdact4_atxmega16e5, "fuse6", 6, 0x40, 6, 1, "fault detection action on TC4"}, - {"fdact5", 2, _values_fdact5_atxmega16e5, "fuse6", 6, 0x80, 7, 1, "fault detection action on TC5"}, - {"lb", 3, _values_lb_atxmega16e5, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blbat", 4, _values_blbat_atxmega16e5, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, - {"blba", 4, _values_blba_atxmega16e5, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, - {"blbb", 4, _values_blbb_atxmega16e5, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, -}; - -/* - * ATxmega192A1 ATxmega256A1 ATxmega128A3 ATxmega64A1 ATxmega64A3 ATxmega128A1 ATxmega128A1revD - * ATxmega192A3 ATxmega256A3 ATxmega256A3B - */ -const Configitem cfgtab_atxmega192a1[16] = { - {"jtaguserid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, - {"wdper", 11, _values_wdper_atxmega16e5, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdwper", 11, _values_wdwper_atxmega16e5, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodpd", 3, _values_bodpd_atxmega16e5, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse2", 2, 0x40, 6, 1, "reset address"}, - {"jtagen", 2, _values_jtagen_at90can128, "fuse4", 4, 0x01, 0, 0, "JTAG interface"}, - {"wdlock", 2, _values_wdlock_atxmega16e5, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, - {"startuptime", 3, _values_startuptime_atxmega16e5, "fuse4", 4, 0x0c, 2, 3, "startup time"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atxmega192a1, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, - {"bodact", 3, _values_bodact_atxmega16e5, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"lb", 3, _values_lb_atxmega16e5, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blbat", 4, _values_blbat_atxmega16e5, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, - {"blba", 4, _values_blba_atxmega16e5, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, - {"blbb", 4, _values_blbb_atxmega16e5, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, -}; - -/* - * ATxmega128A3U ATxmega16A4U ATxmega32A4U ATxmega64A1U ATxmega64A3U ATxmega64A4U ATxmega128A1U - * ATxmega128A4U ATxmega192A3U ATxmega256A3BU ATxmega256A3U - */ -const Configitem cfgtab_atxmega128a3u[17] = { - {"jtaguid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, - {"wdper", 11, _values_wdper_atxmega16e5, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdwper", 11, _values_wdwper_atxmega16e5, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodpd", 3, _values_bodpd_atxmega16e5, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, - {"toscsel", 2, _values_toscsel_atxmega128a3u, "fuse2", 2, 0x20, 5, 1, "timer oscillator pin location"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse2", 2, 0x40, 6, 1, "reset address"}, - {"jtagen", 2, _values_jtagen_at90can128, "fuse4", 4, 0x01, 0, 0, "JTAG interface"}, - {"wdlock", 2, _values_wdlock_atxmega16e5, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, - {"startuptime", 3, _values_startuptime_atxmega16e5, "fuse4", 4, 0x0c, 2, 3, "startup time"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atxmega16e5, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, - {"bodact", 3, _values_bodact_atxmega16e5, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"lb", 3, _values_lb_atxmega16e5, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blbat", 4, _values_blbat_atxmega16e5, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, - {"blba", 4, _values_blba_atxmega16e5, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, - {"blbb", 4, _values_blbb_atxmega16e5, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, -}; - -// ATxmega64A4 ATxmega128A4 ATxmega16A4 ATxmega32A4 -const Configitem cfgtab_atxmega64a4[16] = { - {"jtaguserid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, - {"wdper", 11, _values_wdper_atxmega16e5, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdwper", 11, _values_wdwper_atxmega16e5, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodpd", 3, _values_bodpd_atxmega16e5, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse2", 2, 0x40, 6, 1, "reset address"}, - {"jtagen", 2, _values_jtagen_at90can128, "fuse4", 4, 0x01, 0, 0, "JTAG interface"}, - {"wdlock", 2, _values_wdlock_atxmega16e5, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, - {"startuptime", 3, _values_startuptime_atxmega16e5, "fuse4", 4, 0x0c, 2, 3, "startup time"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atxmega64a4, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, - {"bodact", 3, _values_bodact_atxmega16e5, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"lb", 3, _values_lb_atxmega16e5, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blbat", 4, _values_blbat_atxmega16e5, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, - {"blba", 4, _values_blba_atxmega16e5, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, - {"blbb", 4, _values_blbb_atxmega16e5, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, -}; - -/* - * ATtiny204 ATtiny202 ATtiny212 ATtiny214 ATtiny402 ATtiny404 ATtiny406 ATtiny412 ATtiny414 - * ATtiny416 ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 - * ATtiny3217 - */ -const Configitem cfgtab_attiny204[23] = { - {"wdtperiod", 12, _values_wdtperiod_attiny204, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_attiny204, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_attiny204, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_attiny204, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_attiny204, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 3, _values_bodlevel_attiny204, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_attiny204, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, - {"osclock", 2, _values_osclock_attiny204, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, - {"cmpa", 2, _values_cmpa_attiny204, "tcd0cfg", 4, 0x01, 0, 0, "compare A default output value"}, - {"cmpb", 2, _values_cmpb_attiny204, "tcd0cfg", 4, 0x02, 1, 0, "compare B default output value"}, - {"cmpc", 2, _values_cmpc_attiny204, "tcd0cfg", 4, 0x04, 2, 0, "compare C default output value"}, - {"cmpd", 2, _values_cmpd_attiny204, "tcd0cfg", 4, 0x08, 3, 0, "compare D default output value"}, - {"cmpaen", 2, _values_cmpaen_attiny204, "tcd0cfg", 4, 0x10, 4, 0, "compare A output"}, - {"cmpben", 2, _values_cmpben_attiny204, "tcd0cfg", 4, 0x20, 5, 0, "compare B output"}, - {"cmpcen", 2, _values_cmpcen_attiny204, "tcd0cfg", 4, 0x40, 6, 0, "compare C output"}, - {"cmpden", 2, _values_cmpden_attiny204, "tcd0cfg", 4, 0x80, 7, 0, "compare D output"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 3, _values_rstpincfg_attiny204, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, - {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, - {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, - {"lb", 2, _values_lb_attiny204, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, -}; - -/* - * ATtiny1624 ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 - * ATtiny3224 ATtiny3226 ATtiny3227 - */ -const Configitem cfgtab_attiny1624[16] = { - {"wdtperiod", 12, _values_wdtperiod_attiny204, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_attiny204, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_attiny204, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_attiny204, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_attiny204, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 3, _values_bodlevel_attiny204, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_attiny204, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, - {"osclock", 2, _values_osclock_attiny204, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 4, _values_rstpincfg_attiny1624, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, - {"toutdis", 2, _values_toutdis_attiny1624, "syscfg0", 5, 0x10, 4, 1, "timeout"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, - {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, - {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, - {"lb", 2, _values_lb_attiny204, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, -}; - -/* - * AVR32DD14 AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 - * AVR64DD20 AVR64DD28 AVR64DD32 - */ -const Configitem cfgtab_avr32dd14[17] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr32dd14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"clksel", 2, _values_clksel_avr32dd14, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 2, _values_rstpincfg_avr32dd14, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, - {"updipincfg", 2, _values_updipincfg_avr32dd14, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 0, "startup time"}, - {"mvsyscfg", 2, _values_mvsyscfg_avr32dd14, "syscfg1", 6, 0x18, 3, 1, "MVIO system configuration"}, - {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, - {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, -}; - -// AVR64EA48 AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 -const Configitem cfgtab_avr64ea48[16] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr64ea48, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_avr64ea48, "osccfg", 2, 0x08, 3, 0, "HF oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 2, _values_rstpincfg_avr64ea48, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, - {"updipincfg", 2, _values_updipincfg_avr64ea48, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, - {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, - {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, -}; - -// ATmega103comp -const Configitem cfgtab_atmega103comp[15] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, -1, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, -1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, -1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, -1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, - {"wdton", 2, _values_wdton_atmega328, "efuse", 2, 0x01, 0, -1, "watchdog timer"}, - {"m103c", 2, _values_m103c_atmega103comp, "efuse", 2, 0x02, 1, -1, "ATmega103 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90SCR100H AT90SCR100 -const Configitem cfgtab_at90scr100h[13] = { - {"sut_cksel", 14, _values_sut_cksel_at90scr100h, "lfuse", 0, 0x39, 0, -1, "clock source"}, +// AT90SCR100 AT90SCR100H +const Configitem cfgtab_at90scr100[13] = { + {"sut_cksel", 14, _values_sut_cksel_at90scr100, "lfuse", 0, 0x39, 0, -1, "clock source"}, {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, -1, "clock output"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, - {"boden", 2, _values_boden_at90scr100h, "efuse", 2, 0x01, 0, -1, "brownout detection"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega161comp -const Configitem cfgtab_atmega161comp[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, -1, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, -1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, -1, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, - {"bodlevel", 5, _values_bodlevel_atmega161comp, "efuse", 2, 0x0e, 1, -1, "brownout detection trigger level"}, - {"m161c", 2, _values_m161c_atmega161comp, "efuse", 2, 0x10, 4, -1, "ATmega161 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90S8535comp -const Configitem cfgtab_at90s8535comp[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, -1, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, -1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, -1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, -1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x40, 6, -1, "watchdog timer"}, - {"s8535c", 2, _values_s8535c_at90s8535comp, "hfuse", 1, 0x80, 7, -1, "AT90S4434/8535 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATtiny4 ATtiny5 ATtiny9 ATtiny10 -const Configitem cfgtab_attiny4[4] = { - {"rstdisbl", 2, _values_rstdisbl_attiny441, "fuse", 0, 0x01, 0, 1, "reset configuration"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, - {"ckout", 2, _values_ckout_attiny441, "fuse", 0, 0x04, 2, 1, "clock output"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATtiny20 -const Configitem cfgtab_attiny20[5] = { - {"rstdisbl", 2, _values_rstdisbl_attiny441, "fuse", 0, 0x01, 0, 1, "reset configuration"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, - {"ckout", 2, _values_ckout_attiny441, "fuse", 0, 0x04, 2, 1, "clock output"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "fuse", 0, 0x70, 4, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATtiny40 -const Configitem cfgtab_attiny40[5] = { - {"rstdisbl", 2, _values_rstdisbl_attiny40, "fuse", 0, 0x01, 0, 1, "reset configuration"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x02, 1, 1, "watchdog timer"}, - {"ckout", 2, _values_ckout_attiny40, "fuse", 0, 0x04, 2, 1, "clock output"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "fuse", 0, 0x70, 4, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, + {"boden", 2, _values_boden_at90scr100, "efuse", 2, 0x01, 0, -1, "brownout detection"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATtiny11 @@ -12815,1514 +12601,1597 @@ const Configitem cfgtab_attiny11[4] = { {"cksel", 5, _values_cksel_attiny11, "fuse", 0, 0x07, 0, 4, "clock source"}, {"rstdisbl", 2, _values_rstdisbl_attiny11, "fuse", 0, 0x08, 3, 0, "reset configuration"}, {"fstrt", 2, _values_fstrt_at90s2313, "fuse", 0, 0x10, 4, 1, "startup time"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, }; // ATtiny12 const Configitem cfgtab_attiny12[6] = { - {"cksel", 16, _values_cksel_attiny28, "fuse", 0, 0x0f, 0, 0x02, "clock source"}, + {"cksel", 16, _values_cksel_attiny12, "fuse", 0, 0x0f, 0, 0x02, "clock source"}, {"rstdisbl", 2, _values_rstdisbl_attiny11, "fuse", 0, 0x10, 4, 1, "reset configuration"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"boden", 2, _values_boden_atmega64hve, "fuse", 0, 0x40, 6, 1, "brownout detection"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"boden", 2, _values_boden_at90s2333, "fuse", 0, 0x40, 6, 1, "brownout detection"}, {"bodlevel", 2, _values_bodlevel_attiny12, "fuse", 0, 0x80, 7, 0, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, -}; - -// ATtiny13 ATtiny13A -const Configitem cfgtab_attiny13[10] = { - {"sut_cksel", 12, _values_sut_cksel_attiny13, "lfuse", 0, 0x0f, 0, 0x0a, "clock source"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x10, 4, 0, "clock prescaled"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x20, 5, 1, "watchdog timer"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x80, 7, 0, "serial programming"}, - {"rstdisbl", 2, _values_rstdisbl_attiny11, "hfuse", 1, 0x01, 0, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_attiny13, "hfuse", 1, 0x06, 1, 3, "brownout detection trigger level"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "hfuse", 1, 0x10, 4, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATtiny15 -const Configitem cfgtab_attiny15[6] = { - {"cksel", 4, _values_cksel_attiny15, "fuse", 0, 0x03, 0, 0, "clock source"}, - {"rstdisbl", 2, _values_rstdisbl_attiny11, "fuse", 0, 0x10, 4, 1, "reset configuration"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"boden", 2, _values_boden_atmega64hve, "fuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "fuse", 0, 0x80, 7, 0, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, }; // ATtiny22 const Configitem cfgtab_attiny22[3] = { {"cksel", 2, _values_cksel_at90s1200, "fuse", 0, 0x01, 0, -1, "clock source"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, -1, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, -1, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, }; -// ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A -const Configitem cfgtab_attiny24[11] = { - {"sut_cksel", 44, _values_sut_cksel_attiny24, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_attiny441, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_attiny441, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATtiny25 ATtiny45 ATtiny85 -const Configitem cfgtab_attiny25[11] = { - {"sut_cksel", 51, _values_sut_cksel_attiny25, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_attiny25, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_attiny11, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATtiny26 -const Configitem cfgtab_attiny26[8] = { - {"ckopt", 2, _values_ckopt_attiny26, "lfuse", 0, 0x40, 6, 1, "internal capacitors on XTAL1 and XTAL2"}, - {"sut_cksel", 62, _values_sut_cksel_attiny26, "lfuse", 0, 0xbf, 0, 0xa1, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "hfuse", 1, 0x01, 0, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "hfuse", 1, 0x02, 1, 1, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x04, 2, 1, "EEPROM after chip erase"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x08, 3, 0, "serial programming"}, - {"rstdisbl", 2, _values_rstdisbl_attiny26, "hfuse", 1, 0x10, 4, 1, "reset configuration"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, +// ATtiny13 ATtiny13A +const Configitem cfgtab_attiny13[10] = { + {"sut_cksel", 12, _values_sut_cksel_attiny13, "lfuse", 0, 0x0f, 0, 0x0a, "clock source"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x10, 4, 0, "clock prescaled"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x20, 5, 1, "watchdog timer"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x80, 7, 0, "serial programming"}, + {"rstdisbl", 2, _values_rstdisbl_attiny11, "hfuse", 1, 0x01, 0, 1, "reset configuration"}, + {"bodlevel", 4, _values_bodlevel_attiny13, "hfuse", 1, 0x06, 1, 3, "brownout detection trigger level"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "hfuse", 1, 0x10, 4, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATtiny43U const Configitem cfgtab_attiny43u[11] = { {"sut_cksel", 48, _values_sut_cksel_attiny43u, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, {"ckout", 2, _values_ckout_attiny43u, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, {"bodlevel", 8, _values_bodlevel_at90pwm81, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, {"rstdisbl", 2, _values_rstdisbl_attiny43u, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; -// ATtiny48 ATtiny88 -const Configitem cfgtab_attiny48[11] = { - {"sut_cksel", 9, _values_sut_cksel_attiny48, "lfuse", 0, 0x3f, 0, 0x2e, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, +// ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A +const Configitem cfgtab_attiny24[11] = { + {"sut_cksel", 44, _values_sut_cksel_attiny24, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny4, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny4, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATtiny15 +const Configitem cfgtab_attiny15[6] = { + {"cksel", 4, _values_cksel_attiny15, "fuse", 0, 0x03, 0, 0, "clock source"}, + {"rstdisbl", 2, _values_rstdisbl_attiny11, "fuse", 0, 0x10, 4, 1, "reset configuration"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"boden", 2, _values_boden_at90s2333, "fuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "fuse", 0, 0x80, 7, 0, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, +}; + +// ATtiny25 ATtiny45 ATtiny85 +const Configitem cfgtab_attiny25[11] = { + {"sut_cksel", 51, _values_sut_cksel_attiny25, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny25, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny11, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATtiny26 +const Configitem cfgtab_attiny26[8] = { + {"ckopt", 2, _values_ckopt_attiny26, "lfuse", 0, 0x40, 6, 1, "internal capacitors on XTAL1 and XTAL2"}, + {"sut_cksel", 62, _values_sut_cksel_attiny26, "lfuse", 0, 0xbf, 0, 0xa1, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "hfuse", 1, 0x01, 0, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "hfuse", 1, 0x02, 1, 1, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x04, 2, 1, "EEPROM after chip erase"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x08, 3, 0, "serial programming"}, + {"rstdisbl", 2, _values_rstdisbl_attiny26, "hfuse", 1, 0x10, 4, 1, "reset configuration"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATtiny87 ATtiny167 ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 const Configitem cfgtab_attiny87[11] = { {"sut_cksel", 44, _values_sut_cksel_attiny87, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, {"ckout", 2, _values_ckout_attiny87, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, {"bodlevel", 8, _values_bodlevel_at90pwm81, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, {"rstdisbl", 2, _values_rstdisbl_attiny26, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; -// ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A -const Configitem cfgtab_attiny261[11] = { - {"sut_cksel", 48, _values_sut_cksel_attiny43u, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_attiny87, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 8, _values_bodlevel_at90pwm81, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_attiny26, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, +// ATtiny28 +const Configitem cfgtab_attiny28[3] = { + {"cksel", 16, _values_cksel_attiny12, "fuse", 0, 0x0f, 0, 0x02, "clock source"}, + {"intcap", 2, _values_intcap_attiny28, "fuse", 0, 0x10, 4, 1, "internal load capacitors between XTAL1/XTAL2 and GND"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, +}; + +// ATtiny48 ATtiny88 +const Configitem cfgtab_attiny48[11] = { + {"sut_cksel", 9, _values_sut_cksel_attiny48, "lfuse", 0, 0x3f, 0, 0x2e, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATtiny828 ATtiny828R const Configitem cfgtab_attiny828[16] = { {"sut_cksel", 16, _values_sut_cksel_attiny828, "lfuse", 0, 0x33, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_ata6285, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"ckout", 2, _values_ckout_attiny828, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, {"rstdisbl", 2, _values_rstdisbl_attiny828, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "efuse", 2, 0x06, 1, 3, "boot section size"}, - {"bodact", 3, _values_bodact_attiny441, "efuse", 2, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"bodpd", 3, _values_bodpd_attiny441, "efuse", 2, 0xc0, 6, 3, "brownout detection in power-down mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "efuse", 2, 0x06, 1, 3, "boot section size"}, + {"bodact", 3, _values_bodact_attiny828, "efuse", 2, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"bodpd", 3, _values_bodpd_attiny828, "efuse", 2, 0xc0, 6, 3, "brownout detection in power-down mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATtiny1634 ATtiny1634R const Configitem cfgtab_attiny1634[13] = { {"sut_cksel", 15, _values_sut_cksel_attiny1634, "lfuse", 0, 0x1f, 0, 0x02, "clock source"}, {"ckout", 2, _values_ckout_attiny40, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_attiny441, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny1634, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, {"rstdisbl", 2, _values_rstdisbl_attiny40, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"bodact", 3, _values_bodact_attiny441, "efuse", 2, 0x06, 1, 3, "brownout detection in active/idle mode"}, - {"bodpd", 3, _values_bodpd_attiny441, "efuse", 2, 0x18, 3, 3, "brownout detection in power-down mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"bodact", 3, _values_bodact_attiny828, "efuse", 2, 0x06, 1, 3, "brownout detection in active/idle mode"}, + {"bodpd", 3, _values_bodpd_attiny828, "efuse", 2, 0x18, 3, 3, "brownout detection in power-down mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATtiny441 ATtiny841 +const Configitem cfgtab_attiny441[14] = { + {"sut_cksel", 17, _values_sut_cksel_attiny441, "lfuse", 0, 0x1f, 0, 0x02, "clock source"}, + {"ckout", 2, _values_ckout_attiny4, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny1634, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny4, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"bodact", 3, _values_bodact_attiny828, "efuse", 2, 0x06, 1, 3, "brownout detection in active/idle mode"}, + {"bodpd", 3, _values_bodpd_attiny828, "efuse", 2, 0x18, 3, 3, "brownout detection in power-down mode"}, + {"ulposcsel", 5, _values_ulposcsel_attiny441, "efuse", 2, 0xe0, 5, 7, "frequency for internal ultra-low-power oscillator"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A +const Configitem cfgtab_attiny261[11] = { + {"sut_cksel", 48, _values_sut_cksel_attiny43u, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny87, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 8, _values_bodlevel_at90pwm81, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny26, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATtiny2313 const Configitem cfgtab_attiny2313[11] = { {"sut_cksel", 44, _values_sut_cksel_attiny2313, "lfuse", 0, 0x3f, 0, 0x24, "clock source"}, {"ckout", 2, _values_ckout_attiny2313, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, {"rstdisbl", 2, _values_rstdisbl_attiny102, "hfuse", 1, 0x01, 0, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x0e, 1, 7, "brownout detection trigger level"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x40, 6, 1, "EEPROM after chip erase"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x0e, 1, 7, "brownout detection trigger level"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x40, 6, 1, "EEPROM after chip erase"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATtiny2313A ATtiny4313 const Configitem cfgtab_attiny2313a[11] = { {"sut_cksel", 44, _values_sut_cksel_attiny2313, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, {"ckout", 2, _values_ckout_attiny2313, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, {"rstdisbl", 2, _values_rstdisbl_attiny102, "hfuse", 1, 0x01, 0, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x0e, 1, 7, "brownout detection trigger level"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x40, 6, 1, "EEPROM after chip erase"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x0e, 1, 7, "brownout detection trigger level"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x40, 6, 1, "EEPROM after chip erase"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; // ATmega8 ATmega8A const Configitem cfgtab_atmega8[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x40, 6, 1, "watchdog timer"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega8HVA ATmega16HVA -const Configitem cfgtab_atmega8hva[7] = { - {"sut", 8, _values_sut_atmega16hva2, "fuse", 0, 0x07, 0, 7, "startup time"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "fuse", 0, 0x08, 3, 1, "self programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x10, 4, 1, "debugWIRE"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATmega8U2 -const Configitem cfgtab_atmega8u2[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8u2, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"rstdisbl", 2, _values_rstdisbl_at90usb162, "hfuse", 1, 0x40, 6, 1, "reset configuration"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, - {"bodlevel", 8, _values_bodlevel_at90usb162, "efuse", 2, 0x07, 0, 4, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 0, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x40, 6, 1, "watchdog timer"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega16 ATmega16A const Configitem cfgtab_atmega16[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega16HVB -const Configitem cfgtab_atmega16hvb[12] = { - {"cksel", 1, _values_cksel_atmega32hvbrevb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, - {"sut", 8, _values_sut_atmega32hvbrevb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "hfuse", 1, 0x10, 4, 0, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega16HVBrevB -const Configitem cfgtab_atmega16hvbrevb[12] = { - {"cksel", 1, _values_cksel_atmega32hvbrevb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, - {"sut", 8, _values_sut_atmega32hvbrevb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, - {"duvrdinit", 2, _values_duvrdinit_atmega32hvbrevb, "hfuse", 1, 0x10, 4, 0, "DUVR mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega16U4 -const Configitem cfgtab_atmega16u4[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x12, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega16u4, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 1, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega32 ATmega32A const Configitem cfgtab_atmega32[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega32HVB -const Configitem cfgtab_atmega32hvb[12] = { - {"cksel", 1, _values_cksel_atmega32hvbrevb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, - {"sut", 8, _values_sut_atmega32hvbrevb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "hfuse", 1, 0x10, 4, 0, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega32C1 ATmega32M1 -const Configitem cfgtab_atmega32c1[17] = { - {"sut_cksel", 53, _values_sut_cksel_atmega16m1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"pscrvb", 2, _values_pscrvb_atmega16m1, "efuse", 2, 0x08, 3, 1, "PSC0UTnB reset value"}, - {"pscrva", 2, _values_pscrva_atmega16m1, "efuse", 2, 0x10, 4, 1, "PSCOUTnA reset value"}, - {"pscrb", 2, _values_pscrb_atmega16m1, "efuse", 2, 0x20, 5, 1, "PSC reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega32U2 -const Configitem cfgtab_atmega32u2[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"rstdisbl", 2, _values_rstdisbl_at90usb162, "hfuse", 1, 0x40, 6, 1, "reset configuration"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, - {"bodlevel", 8, _values_bodlevel_at90usb162, "efuse", 2, 0x07, 0, 4, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 0, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega32U4 -const Configitem cfgtab_atmega32u4[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x12, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega16u4, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 1, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega32U6 -const Configitem cfgtab_atmega32u6[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, -1, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, -1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, -1, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega16u4, "efuse", 2, 0x07, 0, -1, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, -1, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega48 ATmega48A ATmega48P ATmega48PA -const Configitem cfgtab_atmega48[11] = { - {"sut_cksel", 55, _values_sut_cksel_atmega328, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, -}; - -// ATmega48PB -const Configitem cfgtab_atmega48pb[11] = { - {"sut_cksel", 47, _values_sut_cksel_atmega328pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"selfprgen", 2, _values_selfprgen_atmega16hva2, "efuse", 2, 0x01, 0, 1, "self programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega64 ATmega64A const Configitem cfgtab_atmega64[15] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"wdton", 2, _values_wdton_atmega328, "efuse", 2, 0x01, 0, 1, "watchdog timer"}, - {"m103c", 2, _values_m103c_atmega103comp, "efuse", 2, 0x02, 1, 0, "ATmega103 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"wdton", 2, _values_wdton_attiny4, "efuse", 2, 0x01, 0, 1, "watchdog timer"}, + {"m103c", 2, _values_m103c_atmega64, "efuse", 2, 0x02, 1, 0, "ATmega103 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// ATmega64C1 ATmegaS64M1 ATmega64M1 -const Configitem cfgtab_atmega64c1[17] = { - {"sut_cksel", 53, _values_sut_cksel_atmega16m1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"pscrvb", 2, _values_pscrvb_atmega16m1, "efuse", 2, 0x08, 3, 1, "PSC0UTnB reset value"}, - {"pscrva", 2, _values_pscrva_atmega16m1, "efuse", 2, 0x10, 4, 1, "PSCOUTnA reset value"}, - {"pscrb", 2, _values_pscrb_atmega16m1, "efuse", 2, 0x20, 5, 1, "PSC reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega64HVE2 ATmega32HVE2 -const Configitem cfgtab_atmega64hve2[13] = { - {"cksel", 1, _values_cksel_atmega64hve, "lfuse", 0, 0x01, 0, 1, "oscillator"}, - {"sut", 4, _values_sut_atmega64hve, "lfuse", 0, 0x06, 1, 3, "startup time"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x08, 3, 0, "clock prescaled"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x10, 4, 1, "brownout detection"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, 0, "serial programming"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega64RFR2 ATmega644RFR2 -const Configitem cfgtab_atmega64rfr2[14] = { - {"sut_cksel", 49, _values_sut_cksel_atmega64rfr2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega64rfr2, "efuse", 2, 0x07, 0, 6, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega88 ATmega88A ATmega88P ATmega88PA ATA6612C -const Configitem cfgtab_atmega88[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega328, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega88PB -const Configitem cfgtab_atmega88pb[14] = { - {"sut_cksel", 47, _values_sut_cksel_atmega328pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega103 -const Configitem cfgtab_atmega103[4] = { - {"cksel", 4, _values_cksel_atmega103, "fuse", 0, 0x03, 0, 3, "clock source"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, -}; - -// ATmega128 ATmegaS128 ATmega128A +// ATmega128 ATmega128A ATmegaS128 const Configitem cfgtab_atmega128[15] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"wdton", 2, _values_wdton_atmega328, "efuse", 2, 0x01, 0, 1, "watchdog timer"}, - {"m103c", 2, _values_m103c_atmega103comp, "efuse", 2, 0x02, 1, 0, "ATmega103 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"wdton", 2, _values_wdton_attiny4, "efuse", 2, 0x01, 0, 1, "watchdog timer"}, + {"m103c", 2, _values_m103c_atmega64, "efuse", 2, 0x02, 1, 0, "ATmega103 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega640 +const Configitem cfgtab_atmega640[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega1280 ATmega1281 +const Configitem cfgtab_atmega1280[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega2560 ATmega2561 +const Configitem cfgtab_atmega2560[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega2560, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32C1 ATmega32M1 +const Configitem cfgtab_atmega32c1[17] = { + {"sut_cksel", 53, _values_sut_cksel_at90pwm2b, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"pscrvb", 2, _values_pscrvb_atmega32c1, "efuse", 2, 0x08, 3, 1, "PSC0UTnB reset value"}, + {"pscrva", 2, _values_pscrva_atmega32c1, "efuse", 2, 0x10, 4, 1, "PSCOUTnA reset value"}, + {"pscrb", 2, _values_pscrb_atmega32c1, "efuse", 2, 0x20, 5, 1, "PSC reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega64C1 ATmega64M1 ATmegaS64M1 +const Configitem cfgtab_atmega64c1[17] = { + {"sut_cksel", 53, _values_sut_cksel_at90pwm2b, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"pscrvb", 2, _values_pscrvb_atmega32c1, "efuse", 2, 0x08, 3, 1, "PSC0UTnB reset value"}, + {"pscrva", 2, _values_pscrva_atmega32c1, "efuse", 2, 0x10, 4, 1, "PSCOUTnA reset value"}, + {"pscrb", 2, _values_pscrb_atmega32c1, "efuse", 2, 0x20, 5, 1, "PSC reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega16M1 +const Configitem cfgtab_atmega16m1[17] = { + {"sut_cksel", 53, _values_sut_cksel_at90pwm2b, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_at90pwm1, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_at90pwm1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_at90pwm1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"pscrvb", 2, _values_pscrvb_atmega32c1, "efuse", 2, 0x08, 3, 1, "PSC0UTnB reset value"}, + {"pscrva", 2, _values_pscrva_atmega32c1, "efuse", 2, 0x10, 4, 1, "PSCOUTnA reset value"}, + {"pscrb", 2, _values_pscrb_atmega32c1, "efuse", 2, 0x20, 5, 1, "PSC reset behavior"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega128RFA1 const Configitem cfgtab_atmega128rfa1[14] = { {"sut_cksel", 17, _values_sut_cksel_atmega128rfa1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega64rfr2, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_atmega128rfa1, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega64RFR2 ATmega644RFR2 +const Configitem cfgtab_atmega64rfr2[14] = { + {"sut_cksel", 49, _values_sut_cksel_atmega64rfr2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_atmega128rfa1, "efuse", 2, 0x07, 0, 6, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega128RFR2 ATmega1284RFR2 const Configitem cfgtab_atmega128rfr2[14] = { {"sut_cksel", 49, _values_sut_cksel_atmega64rfr2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega64rfr2, "efuse", 2, 0x07, 0, 6, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_atmega128rfa1, "efuse", 2, 0x07, 0, 6, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega256RFR2 ATmega2564RFR2 +const Configitem cfgtab_atmega256rfr2[14] = { + {"sut_cksel", 49, _values_sut_cksel_atmega64rfr2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega2560, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_atmega128rfa1, "efuse", 2, 0x07, 0, 6, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega8U2 +const Configitem cfgtab_atmega8u2[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega8u2, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"rstdisbl", 2, _values_rstdisbl_at90usb82, "hfuse", 1, 0x40, 6, 1, "reset configuration"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, + {"bodlevel", 8, _values_bodlevel_at90usb82, "efuse", 2, 0x07, 0, 4, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 0, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32U2 +const Configitem cfgtab_atmega32u2[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"rstdisbl", 2, _values_rstdisbl_at90usb82, "hfuse", 1, 0x40, 6, 1, "reset configuration"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x80, 7, 1, "debugWIRE"}, + {"bodlevel", 8, _values_bodlevel_at90usb82, "efuse", 2, 0x07, 0, 4, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 0, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega16U4 +const Configitem cfgtab_atmega16u4[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x12, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_at90usb646, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 1, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32U4 +const Configitem cfgtab_atmega32u4[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x12, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_at90usb646, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, 1, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32U6 +const Configitem cfgtab_atmega32u6[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, -1, "clock source"}, + {"ckout", 2, _values_ckout_at90can32, "lfuse", 0, 0x40, 6, -1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, -1, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, + {"bodlevel", 8, _values_bodlevel_at90usb646, "efuse", 2, 0x07, 0, -1, "brownout detection trigger level"}, + {"hwbe", 2, _values_hwbe_at90usb82, "efuse", 2, 0x08, 3, -1, "hardware boot"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega161 const Configitem cfgtab_atmega161[7] = { {"cksel", 8, _values_cksel_atmega161, "fuse", 0, 0x07, 0, 2, "clock source"}, {"sut", 2, _values_sut_atmega161, "fuse", 0, 0x10, 4, 1, "startup time"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse", 0, 0x40, 6, 1, "reset address"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse", 0, 0x40, 6, 1, "reset address"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega161comp +const Configitem cfgtab_atmega161comp[15] = { + {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, -1, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, -1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, -1, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, + {"bodlevel", 5, _values_bodlevel_atmega161comp, "efuse", 2, 0x0e, 1, -1, "brownout detection trigger level"}, + {"m161c", 2, _values_m161c_atmega161comp, "efuse", 2, 0x10, 4, -1, "ATmega161 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega162 const Configitem cfgtab_atmega162[15] = { {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, {"bodlevel", 5, _values_bodlevel_atmega161comp, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, {"m161c", 2, _values_m161c_atmega161comp, "efuse", 2, 0x10, 4, 1, "ATmega161 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega163 const Configitem cfgtab_atmega163[9] = { {"cksel", 16, _values_cksel_atmega163, "lfuse", 0, 0x0f, 0, 0x0f, "clock source"}, - {"spien", 2, _values_spien_atmega328, "lfuse", 0, 0x20, 5, 0, "serial programming"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, 3, "boot section size"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega164A ATmega164P ATmega164PA -const Configitem cfgtab_atmega164a[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega165 ATmega169 -const Configitem cfgtab_atmega165[15] = { - {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "efuse", 2, 0x01, 0, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega165A ATmega165P ATmega165PA ATmega169A ATmega169P ATmega169PA -const Configitem cfgtab_atmega165a[15] = { - {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"rstdisbl", 2, _values_rstdisbl_atmega165a, "efuse", 2, 0x01, 0, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega168 ATmega168A ATmega168P ATmega168PA ATA6613C -const Configitem cfgtab_atmega168[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega328, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega168PB -const Configitem cfgtab_atmega168pb[14] = { - {"sut_cksel", 47, _values_sut_cksel_atmega328pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega328, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega328, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega161comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega256RFR2 ATmega2564RFR2 -const Configitem cfgtab_atmega256rfr2[14] = { - {"sut_cksel", 49, _values_sut_cksel_atmega64rfr2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega256rfr2, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega64rfr2, "efuse", 2, 0x07, 0, 6, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, 0, "serial programming"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, 3, "boot section size"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega323 const Configitem cfgtab_atmega323[12] = { {"cksel", 16, _values_cksel_atmega163, "lfuse", 0, 0x0f, 0, 0x02, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 3, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 3, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega164A ATmega164P ATmega164PA +const Configitem cfgtab_atmega164a[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega324A ATmega324P ATmega324PA const Configitem cfgtab_atmega324a[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega644 ATmega644A ATmega644P ATmega644PA +const Configitem cfgtab_atmega644[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega1284 ATmega1284P +const Configitem cfgtab_atmega1284[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega640, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega324PB const Configitem cfgtab_atmega324pb[15] = { - {"sut_cksel", 47, _values_sut_cksel_atmega328pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"sut_cksel", 47, _values_sut_cksel_atmega324pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"cfd", 2, _values_cfd_atmega328pb, "efuse", 2, 0x08, 3, 0, "clock failure detection"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"cfd", 2, _values_cfd_atmega324pb, "efuse", 2, 0x08, 3, 0, "clock failure detection"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega165 ATmega169 +const Configitem cfgtab_atmega165[15] = { + {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "efuse", 2, 0x01, 0, 1, "reset configuration"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega165A ATmega165P ATmega165PA ATmega169A ATmega169P ATmega169PA +const Configitem cfgtab_atmega165a[15] = { + {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165a, "efuse", 2, 0x01, 0, 1, "reset configuration"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; /* - * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega329 ATmega329A ATmega329P ATmega329PA - * ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A ATmega3290P ATmega3290PA + * ATmega325 ATmega325A ATmega325P ATmega325PA ATmega3250 ATmega3250A ATmega3250P ATmega3250PA + * ATmega329 ATmega329A ATmega329P ATmega329PA ATmega3290 ATmega3290A ATmega3290P ATmega3290PA */ const Configitem cfgtab_atmega325[15] = { {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega328, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, {"rstdisbl", 2, _values_rstdisbl_atmega165a, "efuse", 2, 0x01, 0, 1, "reset configuration"}, {"bodlevel", 4, _values_bodlevel_attiny13, "efuse", 2, 0x06, 1, 3, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +/* + * ATmega645 ATmega645A ATmega645P ATmega6450 ATmega6450A ATmega6450P ATmega649 ATmega649A + * ATmega649P ATmega6490 ATmega6490A ATmega6490P + */ +const Configitem cfgtab_atmega645[15] = { + {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_atmega640, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165a, "efuse", 2, 0x01, 0, 1, "reset configuration"}, + {"bodlevel", 4, _values_bodlevel_attiny13, "efuse", 2, 0x06, 1, 3, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega8515 +const Configitem cfgtab_atmega8515[13] = { + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x40, 6, 1, "watchdog timer"}, + {"s8515c", 2, _values_s8515c_at90s8515comp, "hfuse", 1, 0x80, 7, 1, "AT90S4414/8515 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega8535 +const Configitem cfgtab_atmega8535[13] = { + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x40, 6, 1, "watchdog timer"}, + {"s8535c", 2, _values_s8535c_at90s8535comp, "hfuse", 1, 0x80, 7, 1, "AT90S4434/8535 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega48 ATmega48A ATmega48P ATmega48PA +const Configitem cfgtab_atmega48[11] = { + {"sut_cksel", 55, _values_sut_cksel_atmega48, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATmega88 ATmega88A ATmega88P ATmega88PA ATA6612C +const Configitem cfgtab_atmega88[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega48, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega168 ATmega168A ATmega168P ATmega168PA ATA6613C +const Configitem cfgtab_atmega168[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega48, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega328 ATmega328P ATA6614Q +const Configitem cfgtab_atmega328[14] = { + {"sut_cksel", 55, _values_sut_cksel_atmega48, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega48PB +const Configitem cfgtab_atmega48pb[11] = { + {"sut_cksel", 47, _values_sut_cksel_atmega324pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "efuse", 2, 0x01, 0, 1, "self programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATmega88PB +const Configitem cfgtab_atmega88pb[14] = { + {"sut_cksel", 47, _values_sut_cksel_atmega324pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90s8515comp, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega168PB +const Configitem cfgtab_atmega168pb[14] = { + {"sut_cksel", 47, _values_sut_cksel_atmega324pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "efuse", 2, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega16, "efuse", 2, 0x06, 1, 0, "boot section size"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega328PB +const Configitem cfgtab_atmega328pb[15] = { + {"sut_cksel", 47, _values_sut_cksel_atmega324pb, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, + {"ckout", 2, _values_ckout_attiny48, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"rstdisbl", 2, _values_rstdisbl_attiny48, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, + {"bodlevel", 4, _values_bodlevel_attiny20, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, + {"cfd", 2, _values_cfd_atmega324pb, "efuse", 2, 0x08, 3, 0, "clock failure detection"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega103 +const Configitem cfgtab_atmega103[4] = { + {"cksel", 4, _values_cksel_atmega103, "fuse", 0, 0x03, 0, 3, "clock source"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x06, 1, 3, "lock bits"}, +}; + +// ATmega103comp +const Configitem cfgtab_atmega103comp[15] = { + {"sut_cksel", 58, _values_sut_cksel_at90s8515comp, "lfuse", 0, 0x3f, 0, -1, "clock source"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x40, 6, -1, "brownout detection"}, + {"bodlevel", 2, _values_bodlevel_at90s2333, "lfuse", 0, 0x80, 7, -1, "brownout detection trigger level"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"ckopt", 2, _values_ckopt_at90s8515comp, "hfuse", 1, 0x10, 4, -1, "oscillator swing"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x40, 6, -1, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x80, 7, -1, "on-chip debug"}, + {"wdton", 2, _values_wdton_attiny4, "efuse", 2, 0x01, 0, -1, "watchdog timer"}, + {"m103c", 2, _values_m103c_atmega64, "efuse", 2, 0x02, 1, -1, "ATmega103 compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega8HVA ATmega16HVA +const Configitem cfgtab_atmega8hva[7] = { + {"sut", 8, _values_sut_atmega8hva, "fuse", 0, 0x07, 0, 7, "startup time"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "fuse", 0, 0x08, 3, 1, "self programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x10, 4, 1, "debugWIRE"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATmega16HVA2 +const Configitem cfgtab_atmega16hva2[9] = { + {"sut", 8, _values_sut_atmega8hva, "lfuse", 0, 0x07, 0, -1, "startup time"}, + {"selfprgen", 2, _values_selfprgen_attiny102, "lfuse", 0, 0x08, 3, -1, "self programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "lfuse", 0, 0x10, 4, -1, "debugWIRE"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, -1, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, -1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, -1, "watchdog timer"}, + {"cksel", 2, _values_cksel_atmega16hva2, "hfuse", 1, 0x03, 0, -1, "oscillator"}, + {"compmode", 2, _values_compmode_atmega16hva2, "hfuse", 1, 0x04, 2, -1, "compatibility mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, +}; + +// ATmega16HVB +const Configitem cfgtab_atmega16hvb[12] = { + {"cksel", 1, _values_cksel_atmega16hvb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, + {"sut", 8, _values_sut_atmega16hvb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "hfuse", 1, 0x10, 4, 0, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega16HVBrevB +const Configitem cfgtab_atmega16hvbrevb[12] = { + {"cksel", 1, _values_cksel_atmega16hvb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, + {"sut", 8, _values_sut_atmega16hvb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90pwm216, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, + {"duvrdinit", 2, _values_duvrdinit_atmega16hvbrevb, "hfuse", 1, 0x10, 4, 0, "DUVR mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32HVB +const Configitem cfgtab_atmega32hvb[12] = { + {"cksel", 1, _values_cksel_atmega16hvb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, + {"sut", 8, _values_sut_atmega16hvb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "hfuse", 1, 0x10, 4, 0, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32HVBrevB +const Configitem cfgtab_atmega32hvbrevb[12] = { + {"cksel", 1, _values_cksel_atmega16hvb, "lfuse", 0, 0x03, 0, 1, "oscillator"}, + {"sut", 8, _values_sut_atmega16hvb, "lfuse", 0, 0x1c, 2, 7, "startup time"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_atmega32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, + {"duvrdinit", 2, _values_duvrdinit_atmega16hvbrevb, "hfuse", 1, 0x10, 4, 0, "DUVR mode"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega64HVE +const Configitem cfgtab_atmega64hve[13] = { + {"cksel", 1, _values_cksel_atmega64hve, "lfuse", 0, 0x01, 0, -1, "oscillator"}, + {"sut", 4, _values_sut_atmega64hve, "lfuse", 0, 0x06, 1, -1, "startup time"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x08, 3, -1, "clock prescaled"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x10, 4, -1, "brownout detection"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, -1, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, -1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, -1, "watchdog timer"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, -1, "boot section size"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, -1, "debugWIRE"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATmega32HVE2 ATmega64HVE2 +const Configitem cfgtab_atmega32hve2[13] = { + {"cksel", 1, _values_cksel_atmega64hve, "lfuse", 0, 0x01, 0, 1, "oscillator"}, + {"sut", 4, _values_sut_atmega64hve, "lfuse", 0, 0x06, 1, 3, "startup time"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x08, 3, 0, "clock prescaled"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x10, 4, 1, "brownout detection"}, + {"spien", 2, _values_spien_at90s1200, "lfuse", 0, 0x20, 5, 0, "serial programming"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_at90can64, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x08, 3, 1, "debugWIRE"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATmega406 const Configitem cfgtab_atmega406[10] = { {"sut_cksel", 6, _values_sut_cksel_atmega406, "lfuse", 0, 0x07, 0, 5, "clock source"}, - {"bootrst", 2, _values_bootrst_atmega328, "lfuse", 0, 0x08, 3, 1, "reset address"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "lfuse", 0, 0x08, 3, 1, "reset address"}, {"bootsz", 4, _values_bootsz_atmega406, "lfuse", 0, 0x30, 4, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x01, 0, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x02, 1, 1, "on-chip debug"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"eesave", 2, _values_eesave_at90s8515comp, "lfuse", 0, 0x40, 6, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "lfuse", 0, 0x80, 7, 1, "watchdog timer"}, + {"jtagen", 2, _values_jtagen_at90can32, "hfuse", 1, 0x01, 0, 0, "JTAG interface"}, + {"ocden", 2, _values_ocden_at90can32, "hfuse", 1, 0x02, 1, 1, "on-chip debug"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; -// ATmega640 -const Configitem cfgtab_atmega640[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// ATA5700M322 ATA5702M322 +const Configitem cfgtab_ata5700m322[9] = { + {"pcee1", 2, _values_pcee1_ata5700m322, "fuse", 0, 0x01, 0, 1, "protect customer EEPROM section"}, + {"eeacc", 2, _values_eeacc_ata5700m322, "fuse", 0, 0x02, 1, 1, "EEPROM access control"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse", 0, 0x04, 2, 1, "reset address"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckstart", 2, _values_ckstart_ata5700m322, "fuse", 0, 0x80, 7, 1, "MRC during reset startup phase"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, }; -// ATmega644 ATmega644A ATmega644P ATmega644PA -const Configitem cfgtab_atmega644[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -/* - * ATmega645 ATmega645A ATmega645P ATmega649 ATmega649A ATmega649P ATmega6450 ATmega6450A - * ATmega6450P ATmega6490 ATmega6490A ATmega6490P - */ -const Configitem cfgtab_atmega645[15] = { - {"sut_cksel", 44, _values_sut_cksel_atmega165, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"rstdisbl", 2, _values_rstdisbl_atmega165a, "efuse", 2, 0x01, 0, 1, "reset configuration"}, - {"bodlevel", 4, _values_bodlevel_attiny13, "efuse", 2, 0x06, 1, 3, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega1280 ATmega1281 -const Configitem cfgtab_atmega1280[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega1284 ATmega1284P -const Configitem cfgtab_atmega1284[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_attiny102, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega2560 ATmega2561 -const Configitem cfgtab_atmega2560[14] = { - {"sut_cksel", 55, _values_sut_cksel_atmega164a, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega64rfr2, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega256rfr2, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 4, _values_bodlevel_atmega328, "efuse", 2, 0x07, 0, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// ATmega8535 -const Configitem cfgtab_atmega8535[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, 0x21, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, 1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, 1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x40, 6, 1, "watchdog timer"}, - {"s8535c", 2, _values_s8535c_at90s8535comp, "hfuse", 1, 0x80, 7, 1, "AT90S4434/8535 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90PWM1 -const Configitem cfgtab_at90pwm1[17] = { - {"sut_cksel", 42, _values_sut_cksel_at90pwm2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"pscrv", 2, _values_pscrv_at90pwm2, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, - {"psc0rb", 2, _values_psc0rb_at90pwm2, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, - {"psc2rb", 2, _values_psc2rb_at90pwm2, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90PWM2B AT90PWM3B -const Configitem cfgtab_at90pwm2b[18] = { - {"sut_cksel", 53, _values_sut_cksel_atmega16m1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"pscrv", 2, _values_pscrv_at90pwm2, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, - {"psc0rb", 2, _values_psc0rb_at90pwm2, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, - {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, - {"psc2rb", 2, _values_psc2rb_at90pwm2, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90CAN32 -const Configitem cfgtab_at90can32[15] = { - {"sut_cksel", 38, _values_sut_cksel_at90can32, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90can32, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"ta0sel", 2, _values_ta0sel_at90can128, "efuse", 2, 0x01, 0, 1, "reserved for factory tests"}, - {"bodlevel", 8, _values_bodlevel_at90can128, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90CAN64 -const Configitem cfgtab_at90can64[15] = { - {"sut_cksel", 38, _values_sut_cksel_at90can32, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega64hve, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"ta0sel", 2, _values_ta0sel_at90can128, "efuse", 2, 0x01, 0, 1, "reserved for factory tests"}, - {"bodlevel", 8, _values_bodlevel_at90can128, "efuse", 2, 0x0e, 1, 7, "brownout detection trigger level"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90PWM216 -const Configitem cfgtab_at90pwm216[18] = { - {"sut_cksel", 42, _values_sut_cksel_at90pwm2, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"pscrv", 2, _values_pscrv_at90pwm2, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, - {"psc0rb", 2, _values_psc0rb_at90pwm2, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, - {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, - {"psc2rb", 2, _values_psc2rb_at90pwm2, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90PWM316 -const Configitem cfgtab_at90pwm316[18] = { - {"sut_cksel", 53, _values_sut_cksel_atmega16m1, "lfuse", 0, 0x3f, 0, 0x22, "clock source"}, - {"ckout", 2, _values_ckout_atmega16m1, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bodlevel", 8, _values_bodlevel_atmega16m1, "hfuse", 1, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, - {"rstdisbl", 2, _values_rstdisbl_atmega16m1, "hfuse", 1, 0x80, 7, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "efuse", 2, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega16m1, "efuse", 2, 0x06, 1, 0, "boot section size"}, - {"pscrv", 2, _values_pscrv_at90pwm2, "efuse", 2, 0x10, 4, 1, "PSCOUT reset value"}, - {"psc0rb", 2, _values_psc0rb_at90pwm2, "efuse", 2, 0x20, 5, 1, "PSC0 reset behavior"}, - {"psc1rb", 2, _values_psc1rb_at90pwm2, "efuse", 2, 0x40, 6, 1, "PSC1 reset behavior"}, - {"psc2rb", 2, _values_psc2rb_at90pwm2, "efuse", 2, 0x80, 7, 1, "PSC2 reset behavior"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90USB646 AT90USB647 -const Configitem cfgtab_at90usb646[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90usb646, "hfuse", 1, 0x06, 1, 1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega16u4, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 0, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90USB1286 AT90USB1287 -const Configitem cfgtab_at90usb1286[15] = { - {"sut_cksel", 50, _values_sut_cksel_at90can128, "lfuse", 0, 0x3f, 0, 0x1e, "clock source"}, - {"ckout", 2, _values_ckout_at90can128, "lfuse", 0, 0x40, 6, 1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, 1, "reset address"}, - {"bootsz", 4, _values_bootsz_at90can128, "hfuse", 1, 0x06, 1, 0, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, 0, "serial programming"}, - {"jtagen", 2, _values_jtagen_at90can128, "hfuse", 1, 0x40, 6, 0, "JTAG interface"}, - {"ocden", 2, _values_ocden_at90can128, "hfuse", 1, 0x80, 7, 1, "on-chip debug"}, - {"bodlevel", 8, _values_bodlevel_atmega16u4, "efuse", 2, 0x07, 0, 3, "brownout detection trigger level"}, - {"hwbe", 2, _values_hwbe_at90usb162, "efuse", 2, 0x08, 3, 0, "hardware boot"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, -}; - -// AT90S2323 -const Configitem cfgtab_at90s2323[3] = { - {"fstrt", 2, _values_fstrt_at90s2313, "fuse", 0, 0x01, 0, 0, "startup time"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, -}; - -// AT90S2333 -const Configitem cfgtab_at90s2333[5] = { - {"sut_cksel", 8, _values_sut_cksel_at90s2333, "fuse", 0, 0x07, 0, -1, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "fuse", 0, 0x08, 3, -1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "fuse", 0, 0x10, 4, -1, "brownout detection trigger level"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, -1, "serial programming"}, - {"lb", 3, _values_lb_at90s2333, "lock", 0, 0x06, 1, -1, "lock bits"}, -}; - -// AT90S2343 -const Configitem cfgtab_at90s2343[3] = { - {"rcen", 2, _values_rcen_at90s1200, "fuse", 0, 0x01, 0, 0, "clock source"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, -}; - -// AT90S4433 -const Configitem cfgtab_at90s4433[5] = { - {"sut_cksel", 8, _values_sut_cksel_at90s2333, "fuse", 0, 0x07, 0, 2, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "fuse", 0, 0x08, 3, 1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "fuse", 0, 0x10, 4, 1, "brownout detection trigger level"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x06, 1, 3, "lock bits"}, -}; - -// AT90S8515comp -const Configitem cfgtab_at90s8515comp[13] = { - {"sut_cksel", 58, _values_sut_cksel_atmega8515, "lfuse", 0, 0x3f, 0, -1, "clock source"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x40, 6, -1, "brownout detection"}, - {"bodlevel", 2, _values_bodlevel_atmega8515, "lfuse", 0, 0x80, 7, -1, "brownout detection trigger level"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, - {"bootsz", 4, _values_bootsz_atmega8515, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"ckopt", 2, _values_ckopt_atmega8515, "hfuse", 1, 0x10, 4, -1, "oscillator swing"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x40, 6, -1, "watchdog timer"}, - {"s8515c", 2, _values_s8515c_atmega8515, "hfuse", 1, 0x80, 7, -1, "AT90S4414/8515 compatibility mode"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +// ATA5781 ATA5782 ATA5783 ATA5831 ATA5832 ATA5833 +const Configitem cfgtab_ata5781[11] = { + {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, + {"rstdisbl", 2, _values_rstdisbl_ata5781, "fuse", 0, 0x02, 1, 1, "reset configuration"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse", 0, 0x04, 2, 1, "reset address"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"ap", 4, _values_ap_at90s8515comp, "lock", 0, 0x0c, 2, 3, "application protection"}, + {"blp", 4, _values_blp_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot loader protection"}, }; // ATA5787 const Configitem cfgtab_ata5787[11] = { {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, {"rstdisbl", 2, _values_rstdisbl_ata5787, "fuse", 0, 0x02, 1, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse", 0, 0x04, 2, 1, "reset address"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse", 0, 0x04, 2, 1, "reset address"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATA5790 ATA5791 +const Configitem cfgtab_ata5790[11] = { + {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, + {"_32oen", 2, _values__32oen_ata5790, "fuse", 0, 0x02, 1, 0, "32 kHz oscillator"}, + {"reserved", 1, _values_reserved_ata5790, "fuse", 0, 0x04, 2, 0, "bit must be programmed"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 0, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "fuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATA5790N ATA5795 const Configitem cfgtab_ata5790n[10] = { {"_32oen", 2, _values__32oen_ata5790, "fuse", 0, 0x02, 1, 0, "32 kHz oscillator"}, {"reserved", 1, _values_reserved_ata5790, "fuse", 0, 0x04, 2, 0, "bit must be programmed"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 0, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "fuse", 0, 0x80, 7, 0, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 0, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "fuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATA5835 const Configitem cfgtab_ata5835[11] = { {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, {"rstdisbl", 2, _values_rstdisbl_ata5781, "fuse", 0, 0x02, 1, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse", 0, 0x04, 2, 1, "reset address"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse", 0, 0x04, 2, 1, "reset address"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, +}; + +// ATA6285 ATA6286 +const Configitem cfgtab_ata6285[17] = { + {"tsrdi", 2, _values_tsrdi_ata6285, "lfuse", 0, 0x01, 0, 1, "temperature shutdown reset"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x02, 1, 0, "brownout detection"}, + {"frcfs", 2, _values_frcfs_ata6285, "lfuse", 0, 0x04, 2, 0, "fast RC oscillator frequency"}, + {"wdrcon", 2, _values_wdrcon_ata6285, "lfuse", 0, 0x08, 3, 0, "watchdog RC oscillator"}, + {"sut_cksel", 3, _values_sut_cksel_ata6285, "lfuse", 0, 0x30, 4, 2, "clock source"}, + {"ckout", 2, _values_ckout_attiny828, "lfuse", 0, 0x40, 6, 1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, 0, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, 1, "reset address"}, + {"bootsz", 4, _values_bootsz_ata6285, "hfuse", 1, 0x06, 1, 0, "boot section size"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, 1, "debugWIRE"}, + {"eelock", 2, _values_eelock_ata6285, "hfuse", 1, 0x80, 7, 1, "Upper EEPROM"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATA6289 const Configitem cfgtab_ata6289[17] = { {"tsrdi", 2, _values_tsrdi_ata6285, "lfuse", 0, 0x01, 0, -1, "temperature shutdown reset"}, - {"boden", 2, _values_boden_atmega64hve, "lfuse", 0, 0x02, 1, -1, "brownout detection"}, + {"boden", 2, _values_boden_at90s2333, "lfuse", 0, 0x02, 1, -1, "brownout detection"}, {"frcfs", 2, _values_frcfs_ata6285, "lfuse", 0, 0x04, 2, -1, "fast RC oscillator frequency"}, {"wdrcon", 2, _values_wdrcon_ata6285, "lfuse", 0, 0x08, 3, -1, "watchdog RC oscillator"}, {"sut_cksel", 3, _values_sut_cksel_ata6285, "lfuse", 0, 0x30, 4, -1, "clock source"}, - {"ckout", 2, _values_ckout_ata6285, "lfuse", 0, 0x40, 6, -1, "clock output"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "lfuse", 0, 0x80, 7, -1, "clock prescaled"}, - {"bootrst", 2, _values_bootrst_atmega328, "hfuse", 1, 0x01, 0, -1, "reset address"}, + {"ckout", 2, _values_ckout_attiny828, "lfuse", 0, 0x40, 6, -1, "clock output"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "lfuse", 0, 0x80, 7, -1, "clock prescaled"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "hfuse", 1, 0x01, 0, -1, "reset address"}, {"bootsz", 4, _values_bootsz_ata6285, "hfuse", 1, 0x06, 1, -1, "boot section size"}, - {"eesave", 2, _values_eesave_atmega328, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "hfuse", 1, 0x20, 5, -1, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "hfuse", 1, 0x40, 6, -1, "debugWIRE"}, + {"eesave", 2, _values_eesave_at90s8515comp, "hfuse", 1, 0x08, 3, -1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "hfuse", 1, 0x10, 4, -1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "hfuse", 1, 0x20, 5, -1, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "hfuse", 1, 0x40, 6, -1, "debugWIRE"}, {"eelock", 2, _values_eelock_ata6285, "hfuse", 1, 0x80, 7, -1, "Upper EEPROM"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blb0", 4, _values_blb0_atmega328, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, - {"blb1", 4, _values_blb1_atmega328, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blb0", 4, _values_blb0_at90s8515comp, "lock", 0, 0x0c, 2, 3, "boot lock bits: application section"}, + {"blb1", 4, _values_blb1_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot lock bits: boot section"}, }; // ATA8210 ATA8215 ATA8510 ATA8515 const Configitem cfgtab_ata8210[11] = { {"extclken", 2, _values_extclken_ata5781, "fuse", 0, 0x01, 0, 1, "external clock"}, {"rstdisbl", 2, _values_rstdisbl_ata5787, "fuse", 0, 0x02, 1, 1, "reset configuration"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse", 0, 0x04, 2, 1, "reset address"}, - {"eesave", 2, _values_eesave_atmega328, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, - {"wdton", 2, _values_wdton_atmega328, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, - {"spien", 2, _values_spien_atmega328, "fuse", 0, 0x20, 5, 0, "serial programming"}, - {"dwen", 2, _values_dwen_atmega328, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, - {"ckdiv8", 2, _values_ckdiv8_atmega328, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, - {"lb", 3, _values_lb_atmega328, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"ap", 4, _values_ap_atmega328, "lock", 0, 0x0c, 2, 3, "application protection"}, - {"blp", 4, _values_blp_atmega328, "lock", 0, 0x30, 4, 3, "boot loader protection"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse", 0, 0x04, 2, 1, "reset address"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse", 0, 0x08, 3, 1, "EEPROM after chip erase"}, + {"wdton", 2, _values_wdton_attiny4, "fuse", 0, 0x10, 4, 1, "watchdog timer"}, + {"spien", 2, _values_spien_at90s1200, "fuse", 0, 0x20, 5, 0, "serial programming"}, + {"dwen", 2, _values_dwen_at90pwm1, "fuse", 0, 0x40, 6, 1, "debugWIRE"}, + {"ckdiv8", 2, _values_ckdiv8_at90can32, "fuse", 0, 0x80, 7, 1, "clock prescaled"}, + {"lb", 3, _values_lb_attiny4, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"ap", 4, _values_ap_at90s8515comp, "lock", 0, 0x0c, 2, 3, "application protection"}, + {"blp", 4, _values_blp_at90s8515comp, "lock", 0, 0x30, 4, 3, "boot loader protection"}, }; /* - * ATxmega16C4 ATxmega16D4 ATxmega32C3 ATxmega32D3 ATxmega32C4 ATxmega32D4 ATxmega64C3 ATxmega64D3 - * ATxmega64D4 ATxmega128C3 ATxmega128D3 ATxmega128D4 ATxmega192C3 ATxmega192D3 ATxmega256C3 - * ATxmega256D3 ATxmega384C3 ATxmega384D3 + * ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 ATxmega64A3 ATxmega128A3 + * ATxmega192A3 ATxmega256A3 ATxmega256A3B */ -const Configitem cfgtab_atxmega16c4[15] = { - {"wdper", 11, _values_wdper_atxmega16e5, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdwper", 11, _values_wdwper_atxmega16e5, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodpd", 3, _values_bodpd_atxmega16e5, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, - {"toscsel", 2, _values_toscsel_atxmega128a3u, "fuse2", 2, 0x20, 5, 1, "timer oscillator pin location"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse2", 2, 0x40, 6, 1, "reset address"}, - {"wdlock", 2, _values_wdlock_atxmega16e5, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, - {"startuptime", 3, _values_startuptime_atxmega16e5, "fuse4", 4, 0x0c, 2, 3, "startup time"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atxmega16e5, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, - {"bodact", 3, _values_bodact_atxmega16e5, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"lb", 3, _values_lb_atxmega16e5, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blbat", 4, _values_blbat_atxmega16e5, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, - {"blba", 4, _values_blba_atxmega16e5, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, - {"blbb", 4, _values_blbb_atxmega16e5, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, +const Configitem cfgtab_atxmega64a1[16] = { + {"jtaguserid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, + {"wdper", 11, _values_wdper_atxmega64a1, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdwper", 11, _values_wdwper_atxmega64a1, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodpd", 3, _values_bodpd_atxmega64a1, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse2", 2, 0x40, 6, 1, "reset address"}, + {"jtagen", 2, _values_jtagen_at90can32, "fuse4", 4, 0x01, 0, 0, "JTAG interface"}, + {"wdlock", 2, _values_wdlock_atxmega64a1, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, + {"startuptime", 3, _values_startuptime_atxmega64a1, "fuse4", 4, 0x0c, 2, 3, "startup time"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_atxmega64a1, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, + {"bodact", 3, _values_bodact_atxmega64a1, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"lb", 3, _values_lb_atxmega64a1, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blbat", 4, _values_blbat_atxmega64a1, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, + {"blba", 4, _values_blba_atxmega64a1, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, + {"blbb", 4, _values_blbb_atxmega64a1, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, }; -// ATxmega64B1 ATxmega64B3 ATxmega128B1 ATxmega128B3 +/* + * ATxmega64A1U ATxmega128A1U ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3BU ATxmega256A3U + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U + */ +const Configitem cfgtab_atxmega64a1u[17] = { + {"jtaguid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, + {"wdper", 11, _values_wdper_atxmega64a1, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdwper", 11, _values_wdwper_atxmega64a1, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodpd", 3, _values_bodpd_atxmega64a1, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, + {"toscsel", 2, _values_toscsel_atxmega64a1u, "fuse2", 2, 0x20, 5, 1, "timer oscillator pin location"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse2", 2, 0x40, 6, 1, "reset address"}, + {"jtagen", 2, _values_jtagen_at90can32, "fuse4", 4, 0x01, 0, 0, "JTAG interface"}, + {"wdlock", 2, _values_wdlock_atxmega64a1, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, + {"startuptime", 3, _values_startuptime_atxmega64a1, "fuse4", 4, 0x0c, 2, 3, "startup time"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_atxmega64a1u, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, + {"bodact", 3, _values_bodact_atxmega64a1, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"lb", 3, _values_lb_atxmega64a1, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blbat", 4, _values_blbat_atxmega64a1, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, + {"blba", 4, _values_blba_atxmega64a1, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, + {"blbb", 4, _values_blbb_atxmega64a1, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, +}; + +// ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 +const Configitem cfgtab_atxmega16a4[16] = { + {"jtaguserid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, + {"wdper", 11, _values_wdper_atxmega64a1, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdwper", 11, _values_wdwper_atxmega64a1, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodpd", 3, _values_bodpd_atxmega64a1, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse2", 2, 0x40, 6, 1, "reset address"}, + {"jtagen", 2, _values_jtagen_at90can32, "fuse4", 4, 0x01, 0, 0, "JTAG interface"}, + {"wdlock", 2, _values_wdlock_atxmega64a1, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, + {"startuptime", 3, _values_startuptime_atxmega64a1, "fuse4", 4, 0x0c, 2, 3, "startup time"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_atxmega16a4, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, + {"bodact", 3, _values_bodact_atxmega64a1, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"lb", 3, _values_lb_atxmega64a1, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blbat", 4, _values_blbat_atxmega64a1, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, + {"blba", 4, _values_blba_atxmega64a1, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, + {"blbb", 4, _values_blbb_atxmega64a1, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, +}; + +// ATxmega64B1 ATxmega128B1 ATxmega64B3 ATxmega128B3 const Configitem cfgtab_atxmega64b1[17] = { {"jtaguserid", 0, NULL, "fuse0", 0, 0xff, 0, 0xff, "JTAG User ID"}, - {"wdper", 11, _values_wdper_atxmega16e5, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdwper", 11, _values_wdwper_atxmega16e5, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodpd", 3, _values_bodpd_atxmega16e5, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, - {"toscsel", 2, _values_toscsel_atxmega128a3u, "fuse2", 2, 0x20, 5, 1, "timer oscillator pin location"}, - {"bootrst", 2, _values_bootrst_atmega328, "fuse2", 2, 0x40, 6, 1, "reset address"}, - {"jtagen", 2, _values_jtagen_at90can128, "fuse4", 4, 0x01, 0, 1, "JTAG interface"}, - {"wdlock", 2, _values_wdlock_atxmega16e5, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, - {"startuptime", 3, _values_startuptime_atxmega16e5, "fuse4", 4, 0x0c, 2, 3, "startup time"}, - {"rstdisbl", 2, _values_rstdisbl_atxmega16e5, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, - {"bodlevel", 8, _values_bodlevel_atxmega16e5, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, - {"eesave", 2, _values_eesave_atmega328, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, - {"bodact", 3, _values_bodact_atxmega16e5, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, - {"lb", 3, _values_lb_atxmega16e5, "lock", 0, 0x03, 0, 3, "lock bits"}, - {"blbat", 4, _values_blbat_atxmega16e5, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, - {"blba", 4, _values_blba_atxmega16e5, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, - {"blbb", 4, _values_blbb_atxmega16e5, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, + {"wdper", 11, _values_wdper_atxmega64a1, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdwper", 11, _values_wdwper_atxmega64a1, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodpd", 3, _values_bodpd_atxmega64a1, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, + {"toscsel", 2, _values_toscsel_atxmega64a1u, "fuse2", 2, 0x20, 5, 1, "timer oscillator pin location"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse2", 2, 0x40, 6, 1, "reset address"}, + {"jtagen", 2, _values_jtagen_at90can32, "fuse4", 4, 0x01, 0, 1, "JTAG interface"}, + {"wdlock", 2, _values_wdlock_atxmega64a1, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, + {"startuptime", 3, _values_startuptime_atxmega64a1, "fuse4", 4, 0x0c, 2, 3, "startup time"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_atxmega64a1u, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, + {"bodact", 3, _values_bodact_atxmega64a1, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"lb", 3, _values_lb_atxmega64a1, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blbat", 4, _values_blbat_atxmega64a1, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, + {"blba", 4, _values_blba_atxmega64a1, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, + {"blbb", 4, _values_blbb_atxmega64a1, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, }; -// ATtiny416auto -const Configitem cfgtab_attiny416auto[23] = { - {"wdtperiod", 12, _values_wdtperiod_attiny204, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_attiny204, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_attiny204, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_attiny204, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_attiny204, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 2, _values_bodlevel_attiny416auto, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 1, _values_freqsel_attiny416auto, "osccfg", 2, 0x03, 0, 1, "oscillator frequency"}, - {"osclock", 2, _values_osclock_attiny204, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, - {"cmpa", 2, _values_cmpa_attiny204, "tcd0cfg", 4, 0x01, 0, 0, "compare A default output value"}, - {"cmpb", 2, _values_cmpb_attiny204, "tcd0cfg", 4, 0x02, 1, 0, "compare B default output value"}, - {"cmpc", 2, _values_cmpc_attiny204, "tcd0cfg", 4, 0x04, 2, 0, "compare C default output value"}, - {"cmpd", 2, _values_cmpd_attiny204, "tcd0cfg", 4, 0x08, 3, 0, "compare D default output value"}, - {"cmpaen", 2, _values_cmpaen_attiny204, "tcd0cfg", 4, 0x10, 4, 0, "compare A output"}, - {"cmpben", 2, _values_cmpben_attiny204, "tcd0cfg", 4, 0x20, 5, 0, "compare B output"}, - {"cmpcen", 2, _values_cmpcen_attiny204, "tcd0cfg", 4, 0x40, 6, 0, "compare C output"}, - {"cmpden", 2, _values_cmpden_attiny204, "tcd0cfg", 4, 0x80, 7, 0, "compare D output"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 3, _values_rstpincfg_attiny204, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, +/* + * ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 ATxmega16C4 + * ATxmega32C4 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 ATxmega384D3 + * ATxmega16D4 ATxmega32D4 ATxmega64D4 ATxmega128D4 + */ +const Configitem cfgtab_atxmega32c3[15] = { + {"wdper", 11, _values_wdper_atxmega64a1, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdwper", 11, _values_wdwper_atxmega64a1, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodpd", 3, _values_bodpd_atxmega64a1, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, + {"toscsel", 2, _values_toscsel_atxmega64a1u, "fuse2", 2, 0x20, 5, 1, "timer oscillator pin location"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse2", 2, 0x40, 6, 1, "reset address"}, + {"wdlock", 2, _values_wdlock_atxmega64a1, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, + {"startuptime", 3, _values_startuptime_atxmega64a1, "fuse4", 4, 0x0c, 2, 3, "startup time"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_atxmega64a1u, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, + {"bodact", 3, _values_bodact_atxmega64a1, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"lb", 3, _values_lb_atxmega64a1, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blbat", 4, _values_blbat_atxmega64a1, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, + {"blba", 4, _values_blba_atxmega64a1, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, + {"blbb", 4, _values_blbb_atxmega64a1, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, +}; + +// ATxmega8E5 ATxmega16E5 ATxmega32E5 +const Configitem cfgtab_atxmega8e5[17] = { + {"wdper", 11, _values_wdper_atxmega64a1, "fuse1", 1, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdwper", 11, _values_wdwper_atxmega64a1, "fuse1", 1, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodpd", 3, _values_bodpd_atxmega64a1, "fuse2", 2, 0x03, 0, 3, "brownout detection in power-down mode"}, + {"bootrst", 2, _values_bootrst_at90s8515comp, "fuse2", 2, 0x40, 6, 1, "reset address"}, + {"wdlock", 2, _values_wdlock_atxmega64a1, "fuse4", 4, 0x02, 1, 1, "watchdog timer"}, + {"startuptime", 3, _values_startuptime_atxmega64a1, "fuse4", 4, 0x0c, 2, 3, "startup time"}, + {"rstdisbl", 2, _values_rstdisbl_atmega165, "fuse4", 4, 0x10, 4, 1, "reset configuration"}, + {"bodlevel", 8, _values_bodlevel_atxmega64a1u, "fuse5", 5, 0x07, 0, 7, "brownout detection trigger level"}, + {"eesave", 2, _values_eesave_at90s8515comp, "fuse5", 5, 0x08, 3, 1, "EEPROM after chip erase"}, + {"bodact", 3, _values_bodact_atxmega64a1, "fuse5", 5, 0x30, 4, 3, "brownout detection in active/idle mode"}, + {"value", 0, NULL, "fuse6", 6, 0x3f, 0, 0x3f, "port pin value"}, + {"fdact4", 2, _values_fdact4_atxmega8e5, "fuse6", 6, 0x40, 6, 1, "fault detection action on TC4"}, + {"fdact5", 2, _values_fdact5_atxmega8e5, "fuse6", 6, 0x80, 7, 1, "fault detection action on TC5"}, + {"lb", 3, _values_lb_atxmega64a1, "lock", 0, 0x03, 0, 3, "lock bits"}, + {"blbat", 4, _values_blbat_atxmega64a1, "lock", 0, 0x0c, 2, 3, "boot lock bits: application table"}, + {"blba", 4, _values_blba_atxmega64a1, "lock", 0, 0x30, 4, 3, "boot lock bits: application section"}, + {"blbb", 4, _values_blbb_atxmega64a1, "lock", 0, 0xc0, 6, 3, "boot lock bits: boot section"}, +}; + +/* + * ATtiny202 ATtiny204 ATtiny402 ATtiny404 ATtiny406 ATtiny212 ATtiny214 ATtiny412 ATtiny414 + * ATtiny416 ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 ATtiny1616 ATtiny1617 ATtiny3216 + * ATtiny3217 + */ +const Configitem cfgtab_attiny202[23] = { + {"wdtperiod", 12, _values_wdtperiod_attiny202, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_attiny202, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_attiny202, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_attiny202, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_attiny202, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 3, _values_bodlevel_attiny202, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_attiny202, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, + {"osclock", 2, _values_osclock_attiny202, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, + {"cmpa", 2, _values_cmpa_attiny202, "tcd0cfg", 4, 0x01, 0, 0, "compare A default output value"}, + {"cmpb", 2, _values_cmpb_attiny202, "tcd0cfg", 4, 0x02, 1, 0, "compare B default output value"}, + {"cmpc", 2, _values_cmpc_attiny202, "tcd0cfg", 4, 0x04, 2, 0, "compare C default output value"}, + {"cmpd", 2, _values_cmpd_attiny202, "tcd0cfg", 4, 0x08, 3, 0, "compare D default output value"}, + {"cmpaen", 2, _values_cmpaen_attiny202, "tcd0cfg", 4, 0x10, 4, 0, "compare A output"}, + {"cmpben", 2, _values_cmpben_attiny202, "tcd0cfg", 4, 0x20, 5, 0, "compare B output"}, + {"cmpcen", 2, _values_cmpcen_attiny202, "tcd0cfg", 4, 0x40, 6, 0, "compare C output"}, + {"cmpden", 2, _values_cmpden_attiny202, "tcd0cfg", 4, 0x80, 7, 0, "compare D output"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 3, _values_rstpincfg_attiny202, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, - {"lb", 2, _values_lb_attiny204, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, + {"lb", 2, _values_lb_attiny202, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, }; // ATtiny804 ATtiny806 ATtiny807 ATtiny1604 ATtiny1606 ATtiny1607 const Configitem cfgtab_attiny804[15] = { - {"wdtperiod", 12, _values_wdtperiod_attiny204, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_attiny204, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_attiny204, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_attiny204, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_attiny204, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 3, _values_bodlevel_attiny204, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_attiny204, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, - {"osclock", 2, _values_osclock_attiny204, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 3, _values_rstpincfg_attiny204, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"wdtperiod", 12, _values_wdtperiod_attiny202, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_attiny202, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_attiny202, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_attiny202, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_attiny202, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 3, _values_bodlevel_attiny202, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_attiny202, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, + {"osclock", 2, _values_osclock_attiny202, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 3, _values_rstpincfg_attiny202, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, - {"lb", 2, _values_lb_attiny204, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, + {"lb", 2, _values_lb_attiny202, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, +}; + +// ATtiny416auto +const Configitem cfgtab_attiny416auto[23] = { + {"wdtperiod", 12, _values_wdtperiod_attiny202, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_attiny202, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_attiny202, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_attiny202, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_attiny202, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 2, _values_bodlevel_attiny416auto, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 1, _values_freqsel_attiny416auto, "osccfg", 2, 0x03, 0, 1, "oscillator frequency"}, + {"osclock", 2, _values_osclock_attiny202, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, + {"cmpa", 2, _values_cmpa_attiny202, "tcd0cfg", 4, 0x01, 0, 0, "compare A default output value"}, + {"cmpb", 2, _values_cmpb_attiny202, "tcd0cfg", 4, 0x02, 1, 0, "compare B default output value"}, + {"cmpc", 2, _values_cmpc_attiny202, "tcd0cfg", 4, 0x04, 2, 0, "compare C default output value"}, + {"cmpd", 2, _values_cmpd_attiny202, "tcd0cfg", 4, 0x08, 3, 0, "compare D default output value"}, + {"cmpaen", 2, _values_cmpaen_attiny202, "tcd0cfg", 4, 0x10, 4, 0, "compare A output"}, + {"cmpben", 2, _values_cmpben_attiny202, "tcd0cfg", 4, 0x20, 5, 0, "compare B output"}, + {"cmpcen", 2, _values_cmpcen_attiny202, "tcd0cfg", 4, 0x40, 6, 0, "compare C output"}, + {"cmpden", 2, _values_cmpden_attiny202, "tcd0cfg", 4, 0x80, 7, 0, "compare D output"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 3, _values_rstpincfg_attiny202, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, + {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, + {"lb", 2, _values_lb_attiny202, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, +}; + +/* + * ATtiny424 ATtiny426 ATtiny427 ATtiny824 ATtiny826 ATtiny827 ATtiny1624 ATtiny1626 ATtiny1627 + * ATtiny3224 ATtiny3226 ATtiny3227 + */ +const Configitem cfgtab_attiny424[16] = { + {"wdtperiod", 12, _values_wdtperiod_attiny202, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_attiny202, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_attiny202, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_attiny202, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_attiny202, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 3, _values_bodlevel_attiny202, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_attiny202, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, + {"osclock", 2, _values_osclock_attiny202, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 4, _values_rstpincfg_attiny424, "syscfg0", 5, 0x0c, 2, 1, "reset pin configuration"}, + {"toutdis", 2, _values_toutdis_attiny424, "syscfg0", 5, 0x10, 4, 1, "timeout"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, + {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, + {"lb", 2, _values_lb_attiny202, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, }; // ATmega808 ATmega809 ATmega1608 ATmega1609 ATmega3208 ATmega3209 ATmega4808 ATmega4809 const Configitem cfgtab_atmega808[15] = { - {"wdtperiod", 12, _values_wdtperiod_attiny204, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_attiny204, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_attiny204, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_attiny204, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_attiny204, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 3, _values_bodlevel_attiny204, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_attiny204, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, - {"osclock", 2, _values_osclock_attiny204, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 2, _values_rstpincfg_avr32dd14, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"wdtperiod", 12, _values_wdtperiod_attiny202, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_attiny202, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_attiny202, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_attiny202, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_attiny202, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 3, _values_bodlevel_attiny202, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_attiny202, "osccfg", 2, 0x03, 0, 2, "oscillator frequency"}, + {"osclock", 2, _values_osclock_attiny202, "osccfg", 2, 0x80, 7, 0, "oscillator lock"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 2, _values_rstpincfg_atmega808, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, {"append", 0, NULL, "append", 7, 0xff, 0, 0x00, "application code section end [# of blocks]"}, {"bootend", 0, NULL, "bootend", 8, 0xff, 0, 0x00, "boot section end [# of blocks]"}, - {"lb", 2, _values_lb_attiny204, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, -}; - -/* - * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 - * AVR64DU32 - */ -const Configitem cfgtab_avr16du14[20] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr32dd14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"clksel", 2, _values_clksel_avr32dd14, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"browsave", 2, _values_browsave_avr16du14, "syscfg0", 5, 0x02, 1, 0, "BOOTROW after chip erase"}, - {"rstpincfg", 2, _values_rstpincfg_avr32dd14, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, - {"updipincfg", 2, _values_updipincfg_avr32dd14, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 0, "startup time"}, - {"usbsink", 2, _values_usbsink_avr16du14, "syscfg1", 6, 0x08, 3, 1, "USB Voltage Regulator Current Sink Enable"}, - {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, - {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"nvmlevel", 2, _values_nvmlevel_avr16du14, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, - {"nvmkey", 2, _values_nvmkey_avr16du14, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, -}; - -// AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 -const Configitem cfgtab_avr16eb14[18] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr64ea48, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_avr64ea48, "osccfg", 2, 0x08, 3, 0, "HF oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"rstpincfg", 2, _values_rstpincfg_avr64ea48, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, - {"updipincfg", 2, _values_updipincfg_avr64ea48, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, - {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, - {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"nvmlevel", 2, _values_nvmlevel_avr16du14, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, - {"nvmkey", 2, _values_nvmkey_avr16du14, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, -}; - -// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 -const Configitem cfgtab_avr16la14[20] = { - {"wdtperiod", 12, _values_wdtperiod_attiny204, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_attiny204, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr16la14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"freqsel", 2, _values_freqsel_avr64ea48, "osccfg", 2, 0x08, 3, 0, "HF oscillator frequency"}, - {"rstpincfg", 2, _values_rstpincfg_avr16la14, "pincfg", 3, 0x01, 0, 0, "Reset Pin Configuration select"}, - {"updipincfg", 2, _values_updipincfg_avr16la14, "pincfg", 3, 0x02, 1, 0, "UPDI Pin Configuration select"}, - {"cpumon", 0, NULL, "hvmoncfg", 4, 0x01, 0, 0, "CPU Monitor"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"bootrowsave", 0, NULL, "syscfg0", 5, 0x02, 1, 0, "BOOTROW Save"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x40, 6, 0, "CRC select"}, - {"crcboot", 2, _values_crcboot_avr16la14, "syscfg0", 5, 0x80, 7, 0, "CRC of boot section during reset"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 7, "startup time"}, - {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, - {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"nvmlevel", 2, _values_nvmlevel_avr16la14, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, - {"nvmkey", 2, _values_nvmkey_avr16la14, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, -}; - -// AVR32SD20 AVR32SD28 AVR32SD32 -const Configitem cfgtab_avr32sd20[18] = { - {"wdtperiod", 12, _values_wdtperiod_avr32sd20, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32sd20, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr32dd14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, - {"browsave", 2, _values_browsave_avr16du14, "syscfg0", 5, 0x02, 1, 0, "BOOTROW after chip erase"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x40, 6, 0, "CRC select"}, - {"crcboot", 2, _values_crcboot_avr16la14, "syscfg0", 5, 0x80, 7, 0, "CRC of boot section during reset"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 0, "startup time"}, - {"mvsyscfg", 3, _values_mvsyscfg_avr32sd20, "syscfg1", 6, 0x18, 3, 1, "MVIO system configuration"}, - {"wdtmon", 4, _values_wdtmon_avr32sd20, "syscfg1", 6, 0xc0, 6, 1, "WDT Monitor Configuration"}, - {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, - {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"nvmlevel", 2, _values_nvmlevel_avr16du14, "pdicfg", 10, 0x03, 0, 3, "Protection Level select"}, - {"nvmkey", 2, _values_nvmkey_avr32sd20, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM Protection Activation Key select"}, - {"key", 2, _values_key_avr32sd20, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, + {"lb", 2, _values_lb_attiny202, "lock", 0, 0xff, 0, 0xc5, "lock bits"}, }; /* @@ -14330,21 +14199,21 @@ const Configitem cfgtab_avr32sd20[18] = { * AVR128DA48 AVR128DA64 */ const Configitem cfgtab_avr32da28[15] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr32dd14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"clksel", 2, _values_clksel_avr32dd14, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr32da28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"clksel", 2, _values_clksel_avr32da28, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, {"rstpincfg", 2, _values_rstpincfg_avr32da28, "syscfg0", 5, 0x0c, 2, 0, "reset pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 0, "startup time"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 0, "startup time"}, {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, }; /* @@ -14352,23 +14221,23 @@ const Configitem cfgtab_avr32da28[15] = { * AVR128DA32S AVR128DA48S AVR128DA64S */ const Configitem cfgtab_avr32da28s[17] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr32dd14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"clksel", 2, _values_clksel_avr32dd14, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr32da28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"clksel", 2, _values_clksel_avr32da28, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, {"rstpincfg", 2, _values_rstpincfg_avr32da28, "syscfg0", 5, 0x0c, 2, 0, "reset pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 0, "startup time"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 0, "startup time"}, {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"nvmlevel", 2, _values_nvmlevel_avr16du14, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, - {"nvmkey", 2, _values_nvmkey_avr16du14, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, + {"nvmlevel", 2, _values_nvmlevel_avr32da28s, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, + {"nvmkey", 2, _values_nvmkey_avr32da28s, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, }; /* @@ -14376,53 +14245,2500 @@ const Configitem cfgtab_avr32da28s[17] = { * AVR128DB48 AVR128DB64 */ const Configitem cfgtab_avr32db28[16] = { - {"wdtperiod", 12, _values_wdtperiod_avr32dd14, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, - {"wdtwindow", 12, _values_wdtwindow_avr32dd14, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, - {"bodsleep", 3, _values_bodsleep_avr32dd14, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, - {"bodactive", 4, _values_bodactive_avr32dd14, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, - {"bodsampfreq", 2, _values_bodsampfreq_avr32dd14, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, - {"bodlevel", 4, _values_bodlevel_avr32dd14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, - {"clksel", 2, _values_clksel_avr32dd14, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, - {"eesave", 2, _values_eesave_attiny204, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr32da28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"clksel", 2, _values_clksel_avr32da28, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, {"rstpincfg", 2, _values_rstpincfg_avr32da28, "syscfg0", 5, 0x0c, 2, 0, "reset pin configuration"}, - {"crcsel", 2, _values_crcsel_avr32dd14, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, - {"crcsrc", 4, _values_crcsrc_attiny204, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, - {"sut", 8, _values_sut_attiny204, "syscfg1", 6, 0x07, 0, 0, "startup time"}, - {"mvsyscfg", 2, _values_mvsyscfg_avr32dd14, "syscfg1", 6, 0x18, 3, 1, "MVIO system configuration"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 0, "startup time"}, + {"mvsyscfg", 2, _values_mvsyscfg_avr32db28, "syscfg1", 6, 0x18, 3, 1, "MVIO system configuration"}, {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, - {"key", 2, _values_key_avr32dd14, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, +}; + +/* + * AVR16DD14 AVR16DD20 AVR16DD28 AVR16DD32 AVR32DD14 AVR32DD20 AVR32DD28 AVR32DD32 AVR64DD14 + * AVR64DD20 AVR64DD28 AVR64DD32 + */ +const Configitem cfgtab_avr16dd14[17] = { + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr32da28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"clksel", 2, _values_clksel_avr32da28, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 2, _values_rstpincfg_atmega808, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, + {"updipincfg", 2, _values_updipincfg_avr16dd14, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 0, "startup time"}, + {"mvsyscfg", 2, _values_mvsyscfg_avr32db28, "syscfg1", 6, 0x18, 3, 1, "MVIO system configuration"}, + {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, + {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, +}; + +/* + * AVR16DU14 AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU14 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 + * AVR64DU32 + */ +const Configitem cfgtab_avr16du14[20] = { + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr32da28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"clksel", 2, _values_clksel_avr32da28, "osccfg", 2, 0x07, 0, 0, "oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"browsave", 2, _values_browsave_avr16du14, "syscfg0", 5, 0x02, 1, 0, "BOOTROW after chip erase"}, + {"rstpincfg", 2, _values_rstpincfg_atmega808, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, + {"updipincfg", 2, _values_updipincfg_avr16dd14, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 0, "startup time"}, + {"usbsink", 2, _values_usbsink_avr16du14, "syscfg1", 6, 0x08, 3, 1, "USB Voltage Regulator Current Sink Enable"}, + {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, + {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, + {"nvmlevel", 2, _values_nvmlevel_avr32da28s, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, + {"nvmkey", 2, _values_nvmkey_avr32da28s, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, +}; + +// AVR16EA28 AVR16EA32 AVR16EA48 AVR32EA28 AVR32EA32 AVR32EA48 AVR64EA28 AVR64EA32 AVR64EA48 +const Configitem cfgtab_avr16ea28[16] = { + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr16ea28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_avr16ea28, "osccfg", 2, 0x08, 3, 0, "HF oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 2, _values_rstpincfg_avr16ea28, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, + {"updipincfg", 2, _values_updipincfg_avr16ea28, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, + {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, +}; + +// AVR16EB14 AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB14 AVR32EB20 AVR32EB28 AVR32EB32 +const Configitem cfgtab_avr16eb14[18] = { + {"wdtperiod", 12, _values_wdtperiod_avr32da28, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32da28, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr16ea28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_avr16ea28, "osccfg", 2, 0x08, 3, 0, "HF oscillator frequency"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"rstpincfg", 2, _values_rstpincfg_avr16ea28, "syscfg0", 5, 0x08, 3, 0, "reset pin configuration"}, + {"updipincfg", 2, _values_updipincfg_avr16ea28, "syscfg0", 5, 0x10, 4, 1, "UPDI pin configuration"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x20, 5, 0, "CRC select"}, + {"crcsrc", 4, _values_crcsrc_attiny202, "syscfg0", 5, 0xc0, 6, 3, "CRC source"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, + {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, + {"nvmlevel", 2, _values_nvmlevel_avr32da28s, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, + {"nvmkey", 2, _values_nvmkey_avr32da28s, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, +}; + +// AVR16LA14 AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA14 AVR32LA20 AVR32LA28 AVR32LA32 +const Configitem cfgtab_avr16la14[20] = { + {"wdtperiod", 12, _values_wdtperiod_attiny202, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_attiny202, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr16la14, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"freqsel", 2, _values_freqsel_avr16ea28, "osccfg", 2, 0x08, 3, 0, "HF oscillator frequency"}, + {"rstpincfg", 2, _values_rstpincfg_avr16la14, "pincfg", 3, 0x01, 0, 0, "Reset Pin Configuration select"}, + {"updipincfg", 2, _values_updipincfg_avr16la14, "pincfg", 3, 0x02, 1, 0, "UPDI Pin Configuration select"}, + {"cpumon", 0, NULL, "hvmoncfg", 4, 0x01, 0, 0, "CPU Monitor"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"bootrowsave", 0, NULL, "syscfg0", 5, 0x02, 1, 0, "BOOTROW Save"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x40, 6, 0, "CRC select"}, + {"crcboot", 2, _values_crcboot_avr16la14, "syscfg0", 5, 0x80, 7, 0, "CRC of boot section during reset"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 7, "startup time"}, + {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, + {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, + {"nvmlevel", 2, _values_nvmlevel_avr16la14, "pdicfg", 10, 0x03, 0, 3, "NVM protection level"}, + {"nvmkey", 2, _values_nvmkey_avr16la14, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM protection activation key"}, + {"key", 2, _values_key_avr32da28, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, +}; + +// AVR32SD20 AVR32SD28 AVR32SD32 +const Configitem cfgtab_avr32sd20[18] = { + {"wdtperiod", 12, _values_wdtperiod_avr32sd20, "wdtcfg", 0, 0x0f, 0, 0x00, "watchdog timeout period"}, + {"wdtwindow", 12, _values_wdtwindow_avr32sd20, "wdtcfg", 0, 0xf0, 4, 0x00, "watchdog window timeout period"}, + {"bodsleep", 3, _values_bodsleep_avr32da28, "bodcfg", 1, 0x03, 0, 0, "brownout detection in sleep mode"}, + {"bodactive", 4, _values_bodactive_avr32da28, "bodcfg", 1, 0x0c, 2, 0, "brownout detection in active/idle mode"}, + {"bodsampfreq", 2, _values_bodsampfreq_avr32da28, "bodcfg", 1, 0x10, 4, 0, "brownout detection sampling frequency"}, + {"bodlevel", 4, _values_bodlevel_avr32da28, "bodcfg", 1, 0xe0, 5, 0, "brownout detection level"}, + {"eesave", 2, _values_eesave_attiny202, "syscfg0", 5, 0x01, 0, 0, "EEPROM after chip erase"}, + {"browsave", 2, _values_browsave_avr16du14, "syscfg0", 5, 0x02, 1, 0, "BOOTROW after chip erase"}, + {"crcsel", 2, _values_crcsel_avr32da28, "syscfg0", 5, 0x40, 6, 0, "CRC select"}, + {"crcboot", 2, _values_crcboot_avr16la14, "syscfg0", 5, 0x80, 7, 0, "CRC of boot section during reset"}, + {"sut", 8, _values_sut_attiny202, "syscfg1", 6, 0x07, 0, 0, "startup time"}, + {"mvsyscfg", 3, _values_mvsyscfg_avr32sd20, "syscfg1", 6, 0x18, 3, 1, "MVIO system configuration"}, + {"wdtmon", 4, _values_wdtmon_avr32sd20, "syscfg1", 6, 0xc0, 6, 1, "WDT Monitor Configuration"}, + {"codesize", 0, NULL, "codesize", 7, 0xff, 0, 0x00, "code section size [# of blocks]"}, + {"bootsize", 0, NULL, "bootsize", 8, 0xff, 0, 0x00, "boot section size [# of blocks]"}, + {"nvmlevel", 2, _values_nvmlevel_avr32da28s, "pdicfg", 10, 0x03, 0, 3, "Protection Level select"}, + {"nvmkey", 2, _values_nvmkey_avr32sd20, "pdicfg", 10, 0xfff0, 4, 0x00, "NVM Protection Activation Key select"}, + {"key", 2, _values_key_avr32sd20, "lock", 0, 0xffffffff, 0, 0x5cc5c55c, "lock key"}, }; // I/O Register files -// ATmega328 ATmega328P -const Register_file rgftab_atmega328[81] = { // I/O memory [0, 223] + 32 +// ATtiny4 ATtiny9 +const Register_file rgftab_attiny4[36] = { // I/O memory [0, 63] + {"portb.pinb", 0x00, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x01, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x02, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x03, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"portb.portcr", 0x0c, 1, -1, -1, "port control register"}, + {"exint.pcmsk", 0x10, 1, -1, -1, "pin change interrupt mask register"}, + {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, + {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, + {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, + {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"ac.acsr", 0x1f, 1, -1, -1, "analog comparator control and status register"}, + {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, + {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, + {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, + {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, + {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny5 ATtiny10 +const Register_file rgftab_attiny5[41] = { // I/O memory [0, 63] + {"portb.pinb", 0x00, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x01, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x02, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x03, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"portb.portcr", 0x0c, 1, -1, -1, "port control register"}, + {"exint.pcmsk", 0x10, 1, -1, -1, "pin change interrupt mask register"}, + {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, + {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, + {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, + {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.adcl", 0x19, 1, 0xff, -1, "ADC data register low byte"}, + {"adc.admux", 0x1b, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x1c, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x1d, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsr", 0x1f, 1, -1, -1, "analog comparator control and status register"}, + {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, + {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, + {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, + {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, + {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny20 +const Register_file rgftab_attiny20[61] = { // I/O memory [0, 63] + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"porta.portcr", 0x08, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x08, 1, -1, -1, "port control register"}, + {"exint.pcmsk0", 0x09, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x0a, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.gifr", 0x0b, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x0c, 1, -1, -1, "general interrupt mask register"}, + {"adc.didr0", 0x0d, 1, -1, -1, "digital input disable register 0"}, + {"adc.adc", 0x0e, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.admux", 0x10, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x11, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x12, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsrb", 0x13, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x14, 1, -1, -1, "analog comparator control and status register A"}, + {"tc0.ocr0b", 0x15, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x16, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0", 0x17, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x18, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x19, 1, -1, -1, "T/C 0 control register A"}, + {"tc1.icr1", 0x1a, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x1c, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x1e, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x20, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tccr1b", 0x23, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x24, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, + {"tc0.gtccr", 0x27, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x27, 1, -1, -1, "general T/C control register"}, + {"twi.twsd", 0x28, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x29, 1, 0xff, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x2a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x2b, 1, 0xff, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x2c, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x2d, 1, -1, -1, "TWI peripheral control register A"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"spi.spsr", 0x2f, 1, -1, -1, "SPI status register"}, + {"spi.spcr", 0x30, 1, -1, -1, "SPI control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.mcucr", 0x3a, 1, 0xdf, -1, "MCU control register"}, + {"exint.mcucr", 0x3a, 1, -1, -1, "MCU control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny40 +const Register_file rgftab_attiny40[63] = { // I/O memory [0, 63] + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"porta.portcr", 0x08, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x08, 1, -1, -1, "port control register"}, + {"portc.portcr", 0x08, 1, -1, -1, "port control register"}, + {"exint.pcmsk0", 0x09, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x0a, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.gifr", 0x0b, 1, 0x71, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x0c, 1, 0x71, -1, "general interrupt mask register"}, + {"adc.didr0", 0x0d, 1, -1, -1, "digital input disable register 0"}, + {"adc.adc", 0x0e, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.admux", 0x10, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x11, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x12, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsrb", 0x13, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x14, 1, -1, -1, "analog comparator control and status register A"}, + {"tc0.ocr0b", 0x15, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x16, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0", 0x17, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x18, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x19, 1, -1, -1, "T/C 0 control register A"}, + {"exint.pcmsk2", 0x1a, 1, -1, -1, "pin change interrupt mask register 2"}, + {"portc.pinc", 0x1b, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x1c, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x1d, 1, 0x3f, -1, "port C data register"}, + {"portc.puec", 0x1e, 1, 0x3f, -1, "PORT C pull-up enable control register"}, + {"cpu.ramdr", 0x1f, 1, 0xff, -1, "RAM data register"}, + {"cpu.ramar", 0x20, 1, 0xff, -1, "RAM address register"}, + {"tc0.ocr1b", 0x21, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc0.ocr1a", 0x22, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc0.tcnt1l", 0x23, 1, 0xff, -1, "timer/counter 1 low byte"}, + {"tc0.tccr1a", 0x24, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, + {"tc0.tcnt1h", 0x27, 1, 0xff, -1, "timer/counter 1 high byte"}, + {"twi.twsd", 0x28, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x29, 1, 0xff, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x2a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x2b, 1, 0xff, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x2c, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x2d, 1, -1, -1, "TWI peripheral control register A"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"spi.spsr", 0x2f, 1, -1, -1, "SPI status register"}, + {"spi.spcr", 0x30, 1, -1, -1, "SPI control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.mcucr", 0x3a, 1, 0xdf, -1, "MCU control register"}, + {"exint.mcucr", 0x3a, 1, -1, -1, "MCU control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny102 ATtiny104 +const Register_file rgftab_attiny102[55] = { // I/O memory [0, 63] + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"usart.udr", 0x08, 1, 0xff, -1, "USART I/O data register"}, + {"usart.ubrr", 0x09, 2, 0x0fff, -1, "USART baud rate register (16 bits)"}, + {"usart.ucsrd", 0x0b, 1, -1, -1, "USART control and status register D"}, + {"usart.ucsrc", 0x0c, 1, -1, -1, "USART control and status register C"}, + {"usart.ucsrb", 0x0d, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0e, 1, -1, -1, "USART control and status register A"}, + {"exint.pcmsk0", 0x0f, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x10, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, + {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, + {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, + {"porta.portcr", 0x16, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x16, 1, -1, -1, "port control register"}, + {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, + {"adc.adcl", 0x19, 1, 0xff, -1, "ADC data register low byte"}, + {"adc.adch", 0x1a, 1, 0xff, -1, "ADC data register high byte"}, + {"adc.admux", 0x1b, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.adcsrb", 0x1c, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x1d, 1, -1, -1, "ADC control and status register A"}, + {"ac.acsrb", 0x1e, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x1f, 1, -1, -1, "analog comparator control and status register A"}, + {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, + {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, + {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, + {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, + {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, + {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, + {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, + {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, + {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, + {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, + {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, + {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, + {"cpu.ccp", 0x3c, 1, -1, -1, "configuration change protection register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// AT90CAN32 AT90CAN64 AT90CAN128 +const Register_file rgftab_at90can32[137] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, 0xff, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x7f, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, 0xff, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x7f, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, 0xff, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x7f, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, -1, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, -1, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, 0xff, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, -1, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, -1, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, -1, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, -1, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// AT90PWM1 +const Register_file rgftab_at90pwm1[92] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, 0x9f, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, -1, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, 0x0fff, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM81 +const Register_file rgftab_at90pwm81[84] = { // I/O memory [0, 223] + 32 + {"ac.acsr", 0x00, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.timsk1", 0x01, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc1.tifr1", 0x02, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x07, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x08, 1, -1, -1, "ADC multiplexer selection register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"psc0.pim0", 0x0f, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc0.pifr0", 0x10, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pcnf0", 0x11, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0x12, 1, -1, -1, "PSC 0 control register"}, + {"psc2.pim2", 0x13, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"psc2.pifr2", 0x14, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pcnf2", 0x15, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0x16, 1, -1, -1, "PSC 2 control register"}, + {"spi.spcr", 0x17, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x18, 1, -1, -1, "SPI status register"}, + {"cpu.gpior0", 0x19, 1, -1, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x1a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1b, 1, -1, -1, "general purpose I/O register 2"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, -1, -1, "EEPROM address register (16 bits)"}, + {"exint.eifr", 0x20, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x21, 1, -1, -1, "external interrupt mask register"}, + {"psc0.ocr0sb", 0x22, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0x24, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc2.ocr2sb", 0x26, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0x28, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc0.ocr0ra", 0x2a, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"adc.adc", 0x2c, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"psc2.ocr2ra", 0x2e, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"spi.spdr", 0x36, 1, -1, -1, "SPI data register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"dac.dac", 0x38, 2, 0xffff, -1, "DAC data register (16 bits)"}, + {"tc1.tcnt1", 0x3a, 2, -1, -1, "timer/counter 1 (16 bits)"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"psc0.ocr0sa", 0x40, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.pfrc0a", 0x42, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0x43, 1, -1, -1, "PSC 0 input B control register"}, + {"psc2.ocr2sa", 0x44, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.pfrc2a", 0x46, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0x47, 1, -1, -1, "PSC 2 input B control register"}, + {"psc0.picr0", 0x48, 2, -1, -1, "PSC 0 input capture register (16 bits)"}, + {"psc0.psoc0", 0x4a, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc2.picr2", 0x4c, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, + {"psc2.psoc2", 0x4e, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0x4f, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.pcnfe2", 0x50, 1, -1, -1, "PSC 2 enhanced configuration register"}, + {"psc2.pasdly2", 0x51, 1, -1, -1, "analog synchronization delay register"}, + {"dac.dacon", 0x56, 1, -1, -1, "DAC control register"}, + {"adc.didr0", 0x57, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x58, 1, -1, -1, "digital input disable register 1"}, + {"adc.amp0csr", 0x59, 1, -1, -1, "amplifier 0 control and status register"}, + {"ac.ac1econ", 0x5a, 1, -1, -1, "analog comparator 1 extended control register"}, + {"ac.ac2econ", 0x5b, 1, -1, -1, "analog comparator 2 extended control register"}, + {"ac.ac3econ", 0x5c, 1, -1, -1, "analog comparator 3 extended control register"}, + {"ac.ac1con", 0x5d, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x5e, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x5f, 1, -1, -1, "analog comparator 3 control register"}, + {"cpu.bgcrr", 0x60, 1, -1, -1, "bandgap resistor calibration register"}, + {"cpu.bgccr", 0x61, 1, -1, -1, "bandgap current calibration register"}, + {"wdt.wdtcsr", 0x62, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x63, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x64, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x65, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x66, 1, -1, -1, "power reduction register"}, + {"cpu.pllcsr", 0x67, 1, -1, -1, "PLL control and status register"}, + {"cpu.osccal", 0x68, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x69, 1, -1, -1, "external interrupt control register A"}, + {"tc1.tccr1b", 0x6a, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.icr1", 0x6c, 2, -1, -1, "T/C 1 input capture register (16 bits)"}, +}; + +// AT90PWM161 +const Register_file rgftab_at90pwm161[86] = { // I/O memory [0, 223] + 32 + {"ac.acsr", 0x00, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.timsk1", 0x01, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc1.tifr1", 0x02, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x07, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x08, 1, -1, -1, "ADC multiplexer selection register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"psc0.pim0", 0x0f, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc0.pifr0", 0x10, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pcnf0", 0x11, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0x12, 1, -1, -1, "PSC 0 control register"}, + {"psc2.pim2", 0x13, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"psc2.pifr2", 0x14, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pcnf2", 0x15, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0x16, 1, -1, -1, "PSC 2 control register"}, + {"spi.spcr", 0x17, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x18, 1, -1, -1, "SPI status register"}, + {"cpu.gpior0", 0x19, 1, -1, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x1a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1b, 1, -1, -1, "general purpose I/O register 2"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.eifr", 0x20, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x21, 1, -1, -1, "external interrupt mask register"}, + {"psc0.ocr0sb", 0x22, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0x24, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc2.ocr2sb", 0x26, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0x28, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc0.ocr0ra", 0x2a, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"adc.adc", 0x2c, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"psc2.ocr2ra", 0x2e, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"spi.spdr", 0x36, 1, 0xff, -1, "SPI data register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"dac.dacl", 0x38, 1, -1, -1, "DAC data register low byte"}, + {"dac.dach", 0x39, 1, -1, -1, "DAC data register high byte"}, + {"tc1.tcnt1", 0x3a, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"psc0.ocr0sa", 0x40, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.pfrc0a", 0x42, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0x43, 1, -1, -1, "PSC 0 input B control register"}, + {"psc2.ocr2sa", 0x44, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.pfrc2a", 0x46, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0x47, 1, -1, -1, "PSC 2 input B control register"}, + {"psc0.picr0", 0x48, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc0.psoc0", 0x4a, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc2.picr2l", 0x4c, 1, 0xff, -1, "PSC 2 input capture register low byte"}, + {"psc2.picr2h", 0x4d, 1, -1, -1, "PSC 2 input capture register high byte"}, + {"psc2.psoc2", 0x4e, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0x4f, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.pcnfe2", 0x50, 1, -1, -1, "PSC 2 enhanced configuration register"}, + {"psc2.pasdly2", 0x51, 1, 0xff, -1, "analog synchronization delay register"}, + {"dac.dacon", 0x56, 1, -1, -1, "DAC control register"}, + {"adc.didr0", 0x57, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x58, 1, -1, -1, "digital input disable register 1"}, + {"adc.amp0csr", 0x59, 1, -1, -1, "amplifier 0 control and status register"}, + {"ac.ac1econ", 0x5a, 1, -1, -1, "analog comparator 1 extended control register"}, + {"ac.ac2econ", 0x5b, 1, -1, -1, "analog comparator 2 extended control register"}, + {"ac.ac3econ", 0x5c, 1, -1, -1, "analog comparator 3 extended control register"}, + {"ac.ac1con", 0x5d, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x5e, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x5f, 1, -1, -1, "analog comparator 3 control register"}, + {"cpu.bgcrr", 0x60, 1, -1, -1, "bandgap resistor calibration register"}, + {"cpu.bgccr", 0x61, 1, -1, -1, "bandgap current calibration register"}, + {"wdt.wdtcsr", 0x62, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x63, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x64, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x65, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x66, 1, -1, -1, "power reduction register"}, + {"cpu.pllcsr", 0x67, 1, -1, -1, "PLL control and status register"}, + {"cpu.osccal", 0x68, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x69, 1, -1, -1, "external interrupt control register A"}, + {"tc1.tccr1b", 0x6a, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.icr1", 0x6c, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, +}; + +// AT90PWM2B +const Register_file rgftab_at90pwm2b[100] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM216 +const Register_file rgftab_at90pwm216[102] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, 0x8f, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrrl", 0xa4, 1, -1, -1, "USART baud rate register low byte"}, + {"usart.ubrrh", 0xa5, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrrl", 0xac, 1, -1, -1, "manchester receiver baud rate register low byte"}, + {"eusart.mubrrh", 0xad, 1, -1, -1, "manchester receiver baud rate register high byte"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, 0x8fff, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM3 +const Register_file rgftab_at90pwm3[115] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, -1, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, -1, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, + {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x0fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.ocr1sa", 0xc2, 2, 0x0fff, -1, "T/C 1 output compare SA register (16 bits)"}, + {"psc1.ocr1ra", 0xc4, 2, 0x0fff, -1, "T/C 1 output compare RA register (16 bits)"}, + {"psc1.ocr1sb", 0xc6, 2, 0x0fff, -1, "T/C 1 output compare SB register (16 bits)"}, + {"psc1.ocr1rb", 0xc8, 2, 0xffff, -1, "T/C 1 output compare RB register (16 bits)"}, + {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, 0x0fff, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM3B +const Register_file rgftab_at90pwm3b[115] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, -1, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, -1, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, + {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.ocr1sa", 0xc2, 2, -1, -1, "T/C 1 output compare SA register (16 bits)"}, + {"psc1.ocr1ra", 0xc4, 2, -1, -1, "T/C 1 output compare RA register (16 bits)"}, + {"psc1.ocr1sb", 0xc6, 2, -1, -1, "T/C 1 output compare SB register (16 bits)"}, + {"psc1.ocr1rb", 0xc8, 2, -1, -1, "T/C 1 output compare RB register (16 bits)"}, + {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, -1, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90PWM316 +const Register_file rgftab_at90pwm316[117] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, 0x8f, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, + {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, + {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, + {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, + {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, + {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, + {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ubrrl", 0xa4, 1, -1, -1, "USART baud rate register low byte"}, + {"usart.ubrrh", 0xa5, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, + {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, + {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, + {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, + {"eusart.mubrrl", 0xac, 1, -1, -1, "manchester receiver baud rate register low byte"}, + {"eusart.mubrrh", 0xad, 1, -1, -1, "manchester receiver baud rate register high byte"}, + {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, + {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, + {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, + {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, + {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, + {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, + {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, + {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, + {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, + {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, + {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, + {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, + {"psc1.ocr1sa", 0xc2, 2, 0x0fff, -1, "T/C 1 output compare SA register (16 bits)"}, + {"psc1.ocr1ra", 0xc4, 2, 0x0fff, -1, "T/C 1 output compare RA register (16 bits)"}, + {"psc1.ocr1sb", 0xc6, 2, 0x0fff, -1, "T/C 1 output compare SB register (16 bits)"}, + {"psc1.ocr1rb", 0xc8, 2, 0xffff, -1, "T/C 1 output compare RB register (16 bits)"}, + {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, + {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, + {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, + {"psc1.picr1", 0xce, 2, 0x8fff, -1, "PSC 1 input capture register (16 bits)"}, + {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, + {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, + {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, + {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, + {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, + {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, + {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, + {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, + {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, + {"psc2.picr2", 0xde, 2, 0x8fff, -1, "PSC 2 input capture register (16 bits)"}, +}; + +// AT90USB82 AT90USB162 +const Register_file rgftab_at90usb82[92] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, -1, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, -1, -1, "port C data register"}, {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"wdt.wdtckd", 0x42, 1, -1, -1, "watchdog timer clock divider register"}, + {"usb_device.regcr", 0x43, 1, -1, -1, "regulator control register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"cpu.clksel0", 0xb0, 1, -1, -1, "clock selection register 0"}, + {"cpu.clksel1", 0xb1, 1, -1, -1, "clock selection register 1"}, + {"cpu.clksta", 0xb2, 1, -1, -1, "clock status register"}, + {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.ueint", 0xd4, 1, 0x1f, -1, "USB endpoint number interrupt register"}, + {"ps2.ps2con", 0xda, 1, -1, -1, "PS 2 pad enable register"}, + {"ps2.upoe", 0xdb, 1, -1, -1, "USB software output enable register"}, +}; + +// AT90USB646 AT90USB647 AT90USB1287 +const Register_file rgftab_at90usb646[157] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"usb_host.uhcon", 0x7e, 1, -1, -1, "UHCON register"}, + {"usb_host.uhint", 0x7f, 1, -1, -1, "UHINT register"}, + {"usb_host.uhien", 0x80, 1, -1, -1, "UHIEN register"}, + {"usb_host.uhaddr", 0x81, 1, 0x7f, -1, "USB host address register"}, + {"usb_host.uhfnum", 0x82, 2, 0x07ff, -1, "UHFNUM register (16 bits)"}, + {"usb_host.uhflen", 0x84, 1, 0xff, -1, "UHFLEN register"}, + {"usb_host.upinrqx", 0x85, 1, 0xff, -1, "UPINRQX register"}, + {"usb_host.upintx", 0x86, 1, -1, -1, "UPINTX register"}, + {"usb_host.upnum", 0x87, 1, 0x07, -1, "UPNUM register"}, + {"usb_host.uprst", 0x88, 1, -1, -1, "UPRST register"}, + {"usb_host.upconx", 0x89, 1, -1, -1, "UPCONX register"}, + {"usb_host.upcfg0x", 0x8a, 1, -1, -1, "UPCFG0X register"}, + {"usb_host.upcfg1x", 0x8b, 1, -1, -1, "UPCFG1X register"}, + {"usb_host.upstax", 0x8c, 1, -1, -1, "UPSTAX register"}, + {"usb_host.upcfg2x", 0x8d, 1, 0xff, -1, "UPCFG2X register"}, + {"usb_host.upienx", 0x8e, 1, -1, -1, "UPIENX register"}, + {"usb_host.updatx", 0x8f, 1, 0xff, -1, "UPDATX register"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usb_global.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, + {"usb_global.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_global.usbsta", 0xb9, 1, -1, -1, "USB status register"}, + {"usb_global.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, + {"usb_global.otgcon", 0xbd, 1, -1, -1, "OTGCON register"}, + {"usb_global.otgien", 0xbe, 1, -1, -1, "OTGIEN register"}, + {"usb_global.otgint", 0xbf, 1, -1, -1, "OTGINT register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, + {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, + {"usb_host.uperrx", 0xd5, 1, -1, -1, "UPERRX register"}, + {"usb_host.upbclx", 0xd6, 1, 0xff, -1, "UPBCLX register"}, + {"usb_host.upbchx", 0xd7, 1, 0x07, -1, "UPBCHX register"}, + {"usb_host.upint", 0xd8, 1, 0x7f, -1, "UPINT register"}, + {"usb_global.otgtcon", 0xd9, 1, -1, -1, "OTGTCON register"}, +}; + +// AT90USB1286 +const Register_file rgftab_at90usb1286[132] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usb_global.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, + {"usb_global.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_global.usbsta", 0xb9, 1, -1, -1, "USB status register"}, + {"usb_global.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, + {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, +}; + +// ATtiny11 +const Register_file rgftab_attiny11[14] = { // I/O memory [0, 63] + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x1f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny12 +const Register_file rgftab_attiny12[18] = { // I/O memory [0, 63] + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny13 +const Register_file rgftab_attiny13[35] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc0.gtccr", 0x28, 1, -1, -1, "general T/C control register"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.dwdr", 0x2e, 1, 0xff, -1, "debugWIRE data register"}, + {"tc0.tccr0a", 0x2f, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny13A +const Register_file rgftab_attiny13a[37] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.prr", 0x25, 1, -1, -1, "power reduction register"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc0.gtccr", 0x28, 1, -1, -1, "general T/C control register"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.dwdr", 0x2e, 1, 0xff, -1, "debugWIRE data register"}, + {"tc0.tccr0a", 0x2f, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.bodcr", 0x30, 1, -1, -1, "BOD control register"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny43U +const Register_file rgftab_attiny43u[54] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"exint.pcmsk1", 0x20, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2c, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2d, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny24 ATtiny24A +const Register_file rgftab_attiny24[55] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny44 ATtiny44A +const Register_file rgftab_attiny44[55] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny84 ATtiny84A +const Register_file rgftab_attiny84[55] = { // I/O memory [0, 63] + 32 + {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, + {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny15 +const Register_file rgftab_attiny15[28] = { // I/O memory [0, 63] + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsr", 0x06, 1, -1, -1, "ADC control and status register"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.sfior", 0x2c, 1, -1, -1, "special function I/O register"}, + {"tc1.ocr1b", 0x2d, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny25 +const Register_file rgftab_attiny25[55] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"cpu.gpior0", 0x11, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x12, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x13, 1, 0xff, -1, "general purpose I/O register 2"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.prr", 0x20, 1, -1, -1, "power reduction register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.dwdr", 0x22, 1, 0xff, -1, "debugWIRE data register"}, + {"tc1.dtps", 0x23, 1, -1, -1, "dead-time prescaler register"}, + {"tc1.dt1b", 0x24, 1, -1, -1, "T/C 1 dead-time register B"}, + {"tc1.dt1a", 0x25, 1, -1, -1, "T/C 1 dead-time register A"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x27, 1, -1, -1, "PLL control and status register"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x29, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tccr0a", 0x2a, 1, -1, -1, "T/C 0 control register A"}, + {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc0.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.ocr1c", 0x2d, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny45 ATtiny85 +const Register_file rgftab_attiny45[55] = { // I/O memory [0, 63] + 32 + {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"cpu.gpior0", 0x11, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x12, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x13, 1, 0xff, -1, "general purpose I/O register 2"}, + {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, + {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, + {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.prr", 0x20, 1, -1, -1, "power reduction register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"cpu.dwdr", 0x22, 1, 0xff, -1, "debugWIRE data register"}, + {"tc1.dtps", 0x23, 1, -1, -1, "dead-time prescaler register"}, + {"tc1.dt1b", 0x24, 1, -1, -1, "T/C 1 dead-time register B"}, + {"tc1.dt1a", 0x25, 1, -1, -1, "T/C 1 dead-time register A"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x27, 1, -1, -1, "PLL control and status register"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x29, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tccr0a", 0x2a, 1, -1, -1, "T/C 0 control register A"}, + {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc0.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, + {"tc1.ocr1c", 0x2d, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny26 +const Register_file rgftab_attiny26[37] = { // I/O memory [0, 63] + 32 + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsr", 0x06, 1, -1, -1, "ADC control and status register"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 1, 0xff, -1, "stack pointer"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny87 ATtiny167 +const Register_file rgftab_attiny87[80] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, + {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, +}; + +// ATtiny28 +const Register_file rgftab_attiny28[20] = { // I/O memory [0, 63] + 32 + {"cpu.osccal", 0x00, 1, 0xff, -1, "oscillator calibration register"}, + {"watchdog.wdtcr", 0x01, 1, -1, -1, "watchdog timer control register"}, + {"modulator.modcr", 0x02, 1, -1, -1, "modulation control register"}, + {"timer_counter_0.tcnt0", 0x03, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.tccr0", 0x04, 1, -1, -1, "T/C 0 control register"}, + {"external_interrupt.ifr", 0x05, 1, -1, -1, "interrupt flag register"}, + {"timer_counter_0.ifr", 0x05, 1, -1, -1, "interrupt flag register"}, + {"cpu.icr", 0x06, 1, -1, -1, "interrupt control register"}, + {"external_interrupt.icr", 0x06, 1, -1, -1, "interrupt control register"}, + {"timer_counter_0.icr", 0x06, 1, -1, -1, "interrupt control register"}, + {"cpu.mcucs", 0x07, 1, -1, -1, "MCU control and status register"}, + {"analog_comparator.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"porta.pina", 0x19, 1, 0x0b, -1, "port A input register"}, + {"porta.pacr", 0x1a, 1, 0x0f, -1, "port A control register"}, + {"porta.porta", 0x1b, 1, 0x0f, -1, "port A data register"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny48 +const Register_file rgftab_attiny48[74] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porta.pina", 0x0c, 1, 0x0f, -1, "port A input register"}, + {"porta.ddra", 0x0d, 1, 0x0f, -1, "port A data direction register"}, + {"porta.porta", 0x0e, 1, 0x0f, -1, "port A data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0x3f, -1, "EEPROM address register low byte"}, {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, @@ -14436,7 +16752,8 @@ const Register_file rgftab_atmega328[81] = { // I/O memory [0, 223] + 32 {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sph", 0x3e, 1, 0x01, -1, "stack pointer high byte"}, {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, @@ -14444,18 +16761,19 @@ const Register_file rgftab_atmega328[81] = { // I/O memory [0, 223] + 32 {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk3", 0x4a, 1, -1, -1, "pin change interrupt mask register 3"}, {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, @@ -14463,23 +16781,2022 @@ const Register_file rgftab_atmega328[81] = { // I/O memory [0, 223] + 32 {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"twi.twhsr", 0x9e, 1, -1, -1, "TWHSR register"}, +}; + +// ATtiny88 +const Register_file rgftab_attiny88[74] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porta.pina", 0x0c, 1, 0x0f, -1, "port A input register"}, + {"porta.ddra", 0x0d, 1, 0x0f, -1, "port A data direction register"}, + {"porta.porta", 0x0e, 1, 0x0f, -1, "port A data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0x3f, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sph", 0x3e, 1, 0x03, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk3", 0x4a, 1, -1, -1, "pin change interrupt mask register 3"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twhsr", 0x9e, 1, -1, -1, "TWHSR register"}, +}; + +// ATtiny828 +const Register_file rgftab_attiny828[94] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"portb.pinb", 0x04, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x05, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x06, 1, 0xff, -1, "port B data register"}, + {"portb.pueb", 0x07, 1, 0xff, -1, "PORT B pull-up enable control register"}, + {"portc.pinc", 0x08, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x09, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x0a, 1, 0xff, -1, "port C data register"}, + {"portc.puec", 0x0b, 1, 0xff, -1, "PORT C pull-up enable control register"}, + {"portd.pind", 0x0c, 1, 0x0f, -1, "port D input register"}, + {"portd.ddrd", 0x0d, 1, 0x0f, -1, "port D data direction register"}, + {"portd.portd", 0x0e, 1, 0x0f, -1, "port D data register"}, + {"portd.pued", 0x0f, 1, 0x0f, -1, "PORT D pull-up enable control register"}, + {"portc.phde", 0x14, 1, -1, -1, "port high drive enable register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 1, 0xff, -1, "EEPROM address register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x30, 1, -1, -1, "analog comparator control and status register A"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.ccp", 0x36, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal0", 0x46, 1, 0xff, -1, "oscillator calibration register 8 MHz"}, + {"cpu.osccal1", 0x47, 1, 0x03, -1, "oscillator calibration register 32 kHz"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admuxa", 0x5c, 1, -1, -1, "ADC multiplexer selection register A"}, + {"adc.admuxb", 0x5d, 1, -1, -1, "ADC multiplexer selection register B"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"twi.twscra", 0x98, 1, -1, -1, "TWI peripheral control register A"}, + {"twi.twscrb", 0x99, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twssra", 0x9a, 1, -1, -1, "TWI peripheral status register A"}, + {"twi.twsam", 0x9b, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x9c, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twsd", 0x9d, 1, -1, -1, "TWI peripheral data register"}, + {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, + {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, + {"usart.ucsrd", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart.ubrr", 0xa4, 2, 0x0fff, -1, "USART baud rate register (16 bits)"}, + {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, + {"adc.didr2", 0xbe, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr3", 0xbf, 1, -1, -1, "digital input disable register 3"}, + {"tocpm.tocpmcoe", 0xc2, 1, -1, -1, "timer output compare pin mux channel output enable register"}, + {"tocpm.tocpmsa0", 0xc8, 1, -1, -1, "timer output compare pin mux selection 0 register"}, + {"tocpm.tocpmsa1", 0xc9, 1, -1, -1, "timer output compare pin mux selection 1 register"}, + {"cpu.osctcal0a", 0xd0, 1, 0xff, -1, "oscillator temperature calibration register A"}, + {"cpu.osctcal0b", 0xd1, 1, 0xff, -1, "oscillator temperature calibration register B"}, +}; + +// ATtiny1634 +const Register_file rgftab_attiny1634[89] = { // I/O memory [0, 223] + 32 + {"adc.adc", 0x00, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsrb", 0x02, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x03, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x04, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsrb", 0x05, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsra", 0x06, 1, -1, -1, "analog comparator control and status register A"}, + {"portc.pinc", 0x07, 1, 0x3f, -1, "port C input register"}, + {"portc.ddrc", 0x08, 1, 0x3f, -1, "port C data direction register"}, + {"portc.portc", 0x09, 1, 0x3f, -1, "port C data register"}, + {"portc.puec", 0x0a, 1, -1, -1, "PORT C pull-up enable control register"}, + {"portb.pinb", 0x0b, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x0c, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x0d, 1, 0x0f, -1, "port B data register"}, + {"portb.pueb", 0x0e, 1, -1, -1, "PORT B pull-up enable control register"}, + {"porta.pina", 0x0f, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x10, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x11, 1, 0xff, -1, "port A data register"}, + {"porta.puea", 0x12, 1, -1, -1, "PORT A pull-up enable control register"}, + {"porta.portcr", 0x13, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x13, 1, -1, -1, "port control register"}, + {"portc.portcr", 0x13, 1, -1, -1, "port control register"}, + {"cpu.gpior0", 0x14, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x15, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x16, 1, 0xff, -1, "general purpose I/O register 2"}, + {"tc0.ocr0b", 0x17, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x18, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0", 0x19, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x1a, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tccr0a", 0x1b, 1, -1, -1, "T/C 0 control register A"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart0.udr0", 0x20, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart0.ubrr0", 0x21, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.ucsr0d", 0x23, 1, -1, -1, "USART control and status register D"}, + {"usart0.ucsr0c", 0x24, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0b", 0x25, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x26, 1, -1, -1, "USART 0 control and status register A"}, + {"exint.pcmsk0", 0x27, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x28, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x29, 1, -1, -1, "pin change interrupt mask register 2"}, + {"usi.usicr", 0x2a, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x2b, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x2c, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x2d, 1, 0xff, -1, "USI buffer register"}, + {"cpu.ccp", 0x2f, 1, 0xff, -1, "configuration change protection register"}, + {"wdt.wdtcsr", 0x30, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clksr", 0x32, 1, -1, -1, "clock setting register"}, + {"cpu.clkpr", 0x33, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x34, 1, -1, -1, "power reduction register"}, + {"cpu.mcusr", 0x35, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x36, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x39, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x39, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x3a, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x3a, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3b, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3c, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"adc.didr0", 0x40, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x41, 1, -1, -1, "digital input disable register 1"}, + {"adc.didr2", 0x42, 1, -1, -1, "digital input disable register 2"}, + {"cpu.osccal0", 0x43, 1, 0xff, -1, "oscillator calibration 0 register"}, + {"cpu.osctcal0a", 0x44, 1, 0xff, -1, "oscillator temperature calibration register A"}, + {"cpu.osctcal0b", 0x45, 1, 0xff, -1, "oscillator temperature calibration register B"}, + {"cpu.osccal1", 0x46, 1, 0x03, -1, "oscillator calibration 1 register"}, + {"tc0.gtccr", 0x47, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x47, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x48, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x4a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x4c, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x4e, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1c", 0x50, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tccr1b", 0x51, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x52, 1, -1, -1, "T/C 1 control register A"}, + {"usart1.udr1", 0x53, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ubrr1", 0x54, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.ucsr1d", 0x56, 1, -1, -1, "USART control and status register D"}, + {"usart1.ucsr1c", 0x57, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1b", 0x58, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x59, 1, -1, -1, "USART 1 control and status register A"}, + {"twi.twsd", 0x5a, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x5b, 1, 0xff, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x5c, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x5d, 1, -1, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x5e, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x5f, 1, -1, -1, "TWI peripheral control register A"}, +}; + +// ATtiny441 ATtiny841 +const Register_file rgftab_attiny441[101] = { // I/O memory [0, 223] + 32 + {"adc.adcsrb", 0x04, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsra", 0x05, 1, -1, -1, "ADC control and status register A"}, + {"adc.adc", 0x06, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.admuxb", 0x08, 1, -1, -1, "ADC multiplexer selection register B"}, + {"adc.admuxa", 0x09, 1, -1, -1, "ADC multiplexer selection register A"}, + {"ac.acsr0a", 0x0a, 1, -1, -1, "analog comparator 0 control and status register A"}, + {"ac.acsr0b", 0x0b, 1, -1, -1, "analog comparator 0 control and status register B"}, + {"ac.acsr1a", 0x0c, 1, -1, -1, "analog comparator 1 control and status register A"}, + {"ac.acsr1b", 0x0d, 1, -1, -1, "analog comparator 1 control and status register B"}, + {"tc1.tifr1", 0x0e, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc1.timsk1", 0x0f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.tifr2", 0x10, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc2.timsk2", 0x11, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, + {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"adc.didr0", 0x40, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x41, 1, -1, -1, "digital input disable register 1"}, + {"portb.pueb", 0x42, 1, 0x0f, -1, "PORT B pull-up enable control register"}, + {"porta.puea", 0x43, 1, 0xff, -1, "PORT A pull-up enable control register"}, + {"porta.portcr", 0x44, 1, -1, -1, "port control register"}, + {"portb.portcr", 0x44, 1, -1, -1, "port control register"}, + {"spi.remap", 0x45, 1, -1, -1, "remap port pins register"}, + {"usart0.remap", 0x45, 1, -1, -1, "remap port pins register"}, + {"tocpm.tocpmcoe", 0x46, 1, -1, -1, "timer output compare pin mux channel output enable register"}, + {"tocpm.tocpmsa0", 0x47, 1, -1, -1, "timer output compare pin mux selection 0 register"}, + {"tocpm.tocpmsa1", 0x48, 1, -1, -1, "timer output compare pin mux selection 1 register"}, + {"porta.phde", 0x4a, 1, -1, -1, "port high drive enable register"}, + {"cpu.prr", 0x50, 1, -1, -1, "power reduction register"}, + {"cpu.ccp", 0x51, 1, 0xff, -1, "configuration change protection register"}, + {"cpu.clkcr", 0x52, 1, -1, -1, "clock control register"}, + {"cpu.clkpr", 0x53, 1, -1, -1, "clock prescaler register"}, + {"cpu.osccal0", 0x54, 1, 0xff, -1, "oscillator calibration register 8 MHz"}, + {"cpu.osctcal0a", 0x55, 1, 0xff, -1, "oscillator temperature calibration register A"}, + {"cpu.osctcal0b", 0x56, 1, 0xff, -1, "oscillator temperature calibration register B"}, + {"cpu.osccal1", 0x57, 1, 0x03, -1, "oscillator calibration register 32 kHz"}, + {"usart0.udr0", 0x60, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart0.ubrr0", 0x61, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.ucsr0d", 0x63, 1, -1, -1, "USART control and status register D"}, + {"usart0.ucsr0c", 0x64, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0b", 0x65, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x66, 1, -1, -1, "USART 0 control and status register A"}, + {"usart1.udr1", 0x70, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ubrr1", 0x71, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.ucsr1d", 0x73, 1, -1, -1, "USART control and status register D"}, + {"usart1.ucsr1c", 0x74, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1b", 0x75, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x76, 1, -1, -1, "USART 1 control and status register A"}, + {"twi.twsd", 0x80, 1, -1, -1, "TWI peripheral data register"}, + {"twi.twsam", 0x81, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twsa", 0x82, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twssra", 0x83, 1, -1, -1, "TWI peripheral status register A"}, + {"twi.twscrb", 0x84, 1, -1, -1, "TWI peripheral control register B"}, + {"twi.twscra", 0x85, 1, -1, -1, "TWI peripheral control register A"}, + {"spi.spdr", 0x90, 1, 0xff, -1, "SPI data register"}, + {"spi.spsr", 0x91, 1, -1, -1, "SPI status register"}, + {"spi.spcr", 0x92, 1, -1, -1, "SPI control register"}, + {"tc2.icr2", 0xa0, 2, 0xffff, -1, "T/C 2 input capture register (16 bits)"}, + {"tc2.ocr2b", 0xa2, 2, 0xffff, -1, "T/C 2 output compare register B (16 bits)"}, + {"tc2.ocr2a", 0xa4, 2, 0xffff, -1, "T/C 2 output compare register A (16 bits)"}, + {"tc2.tcnt2", 0xa6, 2, 0xffff, -1, "timer/counter 2 (16 bits)"}, + {"tc2.tccr2c", 0xa8, 1, -1, -1, "T/C 2 control register C"}, + {"tc2.tccr2b", 0xa9, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tccr2a", 0xaa, 1, -1, -1, "T/C 2 control register A"}, +}; + +// ATtiny261 ATtiny261A +const Register_file rgftab_attiny261[63] = { // I/O memory [0, 63] + 32 + {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, + {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, + {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, + {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, + {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, + {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, + {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny461 ATtiny461A +const Register_file rgftab_attiny461[63] = { // I/O memory [0, 63] + 32 + {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, + {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, + {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, + {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, + {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, + {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, + {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny861 ATtiny861A +const Register_file rgftab_attiny861[63] = { // I/O memory [0, 63] + 32 + {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, + {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, + {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, + {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, + {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, + {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, + {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, + {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, + {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, + {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, + {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, + {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny2313 +const Register_file rgftab_attiny2313[54] = { // I/O memory [0, 63] + 32 + {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, + {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"cpu.pcmsk", 0x20, 1, 0xff, -1, "pin change interrupt mask register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x3a, 1, -1, -1, "external interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny2313A +const Register_file rgftab_attiny2313a[58] = { // I/O memory [0, 63] + 32 + {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, + {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, + {"exint.pcmsk1", 0x04, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x05, 1, -1, -1, "pin change interrupt mask register 2"}, + {"cpu.prr", 0x06, 1, -1, -1, "power reduction register"}, + {"cpu.bodcr", 0x07, 1, -1, -1, "BOD control register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"exint.pcmsk0", 0x20, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATtiny4313 +const Register_file rgftab_attiny4313[58] = { // I/O memory [0, 63] + 32 + {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, + {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, + {"exint.pcmsk1", 0x04, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x05, 1, -1, -1, "pin change interrupt mask register 2"}, + {"cpu.prr", 0x06, 1, -1, -1, "power reduction register"}, + {"cpu.bodcr", 0x07, 1, -1, -1, "BOD control register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, + {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, + {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, + {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, + {"exint.pcmsk0", 0x20, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, + {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, + {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, + {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega8 ATmega8A +const Register_file rgftab_atmega8[61] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0x7f, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega16 +const Register_file rgftab_atmega16[70] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega16A +const Register_file rgftab_atmega16a[70] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x8f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega32 +const Register_file rgftab_atmega32[68] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, 0x07, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega32A +const Register_file rgftab_atmega32a[66] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, 0xff, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, 0x07, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega64 ATmega64A +const Register_file rgftab_atmega64[103] = { // I/O memory [0, 223] + 32 + {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, + {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, + {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, + {"cpu.xdiv", 0x3c, 1, -1, -1, "XTAL divide control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, + {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, + {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, + {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, + {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, + {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, + {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, + {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, + {"adc.adcsrb", 0x6e, 1, -1, -1, "ADC control and status register B"}, + {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, + {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, +}; + +// ATmega128 ATmegaS128 +const Register_file rgftab_atmega128[103] = { // I/O memory [0, 223] + 32 + {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, + {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, + {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.xdiv", 0x3c, 1, -1, -1, "XTAL divide control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, + {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, + {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, + {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, + {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, + {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, + {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, + {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, + {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, + {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, +}; + +// ATmega128A +const Register_file rgftab_atmega128a[103] = { // I/O memory [0, 223] + 32 + {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, + {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, + {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.xdiv", 0x3c, 1, 0xff, -1, "XTAL divide control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, + {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, + {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, + {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, + {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, + {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, + {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, + {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, + {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, + {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, + {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, +}; + +// ATmega640 +const Register_file rgftab_atmega640[160] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart2.ucsr2a", 0x0b0, 1, -1, -1, "USART control and status register A"}, + {"usart2.ucsr2b", 0x0b1, 1, -1, -1, "USART control and status register B"}, + {"usart2.ucsr2c", 0x0b2, 1, -1, -1, "USART control and status register C"}, + {"usart2.ubrr2", 0x0b4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, + {"usart2.udr2", 0x0b6, 1, 0xff, -1, "USART 2 I/O data register"}, + {"porth.pinh", 0x0e0, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0x0e1, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0x0e2, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0x0e3, 1, 0xff, -1, "PORT J input register"}, + {"portj.ddrj", 0x0e4, 1, 0xff, -1, "PORT J data direction register"}, + {"portj.portj", 0x0e5, 1, 0xff, -1, "PORT J data register"}, + {"portk.pink", 0x0e6, 1, 0xff, -1, "PORT K input register"}, + {"portk.ddrk", 0x0e7, 1, 0xff, -1, "PORT K data direction register"}, + {"portk.portk", 0x0e8, 1, 0xff, -1, "PORT K data register"}, + {"portl.pinl", 0x0e9, 1, 0xff, -1, "PORT L input register"}, + {"portl.ddrl", 0x0ea, 1, 0xff, -1, "PORT L data direction register"}, + {"portl.portl", 0x0eb, 1, 0xff, -1, "PORT L data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"usart3.ucsr3a", 0x110, 1, -1, -1, "USART control and status register A"}, + {"usart3.ucsr3b", 0x111, 1, -1, -1, "USART control and status register B"}, + {"usart3.ucsr3c", 0x112, 1, -1, -1, "USART control and status register C"}, + {"usart3.ubrr3", 0x114, 2, 0x0fff, -1, "USART 3 baud rate register (16 bits)"}, + {"usart3.udr3", 0x116, 1, 0xff, -1, "USART 3 I/O data register"}, +}; + +// ATmega1280 ATmega2560 +const Register_file rgftab_atmega1280[161] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart2.ucsr2a", 0x0b0, 1, -1, -1, "USART control and status register A"}, + {"usart2.ucsr2b", 0x0b1, 1, -1, -1, "USART control and status register B"}, + {"usart2.ucsr2c", 0x0b2, 1, -1, -1, "USART control and status register C"}, + {"usart2.ubrr2", 0x0b4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, + {"usart2.udr2", 0x0b6, 1, 0xff, -1, "USART 2 I/O data register"}, + {"porth.pinh", 0x0e0, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0x0e1, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0x0e2, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0x0e3, 1, 0xff, -1, "PORT J input register"}, + {"portj.ddrj", 0x0e4, 1, 0xff, -1, "PORT J data direction register"}, + {"portj.portj", 0x0e5, 1, 0xff, -1, "PORT J data register"}, + {"portk.pink", 0x0e6, 1, 0xff, -1, "PORT K input register"}, + {"portk.ddrk", 0x0e7, 1, 0xff, -1, "PORT K data direction register"}, + {"portk.portk", 0x0e8, 1, 0xff, -1, "PORT K data register"}, + {"portl.pinl", 0x0e9, 1, 0xff, -1, "PORT L input register"}, + {"portl.ddrl", 0x0ea, 1, 0xff, -1, "PORT L data direction register"}, + {"portl.portl", 0x0eb, 1, 0xff, -1, "PORT L data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"usart3.ucsr3a", 0x110, 1, -1, -1, "USART control and status register A"}, + {"usart3.ucsr3b", 0x111, 1, -1, -1, "USART control and status register B"}, + {"usart3.ucsr3c", 0x112, 1, -1, -1, "USART control and status register C"}, + {"usart3.ubrr3", 0x114, 2, 0x0fff, -1, "USART 3 baud rate register (16 bits)"}, + {"usart3.udr3", 0x116, 1, 0xff, -1, "USART 3 I/O data register"}, +}; + +// ATmega32C1 +const Register_file rgftab_atmega32c1[117] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// ATmega64C1 +const Register_file rgftab_atmega64c1[122] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dacl", 0x71, 1, -1, -1, "DAC data register low byte"}, + {"dac.dach", 0x72, 1, -1, -1, "DAC data register high byte"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantiml", 0xc6, 1, 0xff, -1, "CAN timer low byte"}, + {"can.cantimh", 0xc7, 1, 0xff, -1, "CAN timer high byte"}, + {"can.canttcl", 0xc8, 1, 0xff, -1, "CAN TTC timer low byte"}, + {"can.canttch", 0xc9, 1, 0xff, -1, "CAN TTC timer high byte"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstml", 0xd8, 1, 0xff, -1, "CAN time stamp register low byte"}, + {"can.canstmh", 0xd9, 1, 0xff, -1, "CAN time stamp register high byte"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, }; // ATmega16M1 ATmega32M1 @@ -14622,19 +18939,3489 @@ const Register_file rgftab_atmega16m1[136] = { // I/O memory [0, 223] + 32 {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, }; -// ATmega32HVBrevB ATmega16HVB ATmega16HVBrevB ATmega32HVB -const Register_file rgftab_atmega32hvbrevb[91] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0x0f, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0x0f, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0x0f, -1, "port A data register"}, +// ATmega64M1 ATmegaS64M1 +const Register_file rgftab_atmega64m1[136] = { // I/O memory [0, 223] + 32 {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x1f, -1, "port C input register"}, - {"portc.portc", 0x08, 1, 0x3f, -1, "port C data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.osicsr", 0x17, 1, -1, -1, "oscillator sampling interface control and status register"}, + {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, + {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, + {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, + {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, + {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, + {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, + {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, + {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, + {"psc.pocr0sa", 0x80, 2, 0x0fff, -1, "PSC module 0 output compare SA register (16 bits)"}, + {"psc.pocr0ra", 0x82, 2, 0x0fff, -1, "PSC module 0 output compare RA register (16 bits)"}, + {"psc.pocr0sb", 0x84, 2, 0x0fff, -1, "PSC module 0 output compare SB register (16 bits)"}, + {"psc.pocr1sa", 0x86, 2, 0x0fff, -1, "PSC module 1 output compare SA register (16 bits)"}, + {"psc.pocr1ra", 0x88, 2, 0x0fff, -1, "PSC module 1 output compare RA register (16 bits)"}, + {"psc.pocr1sb", 0x8a, 2, 0x0fff, -1, "PSC module 1 output compare SB register (16 bits)"}, + {"psc.pocr2sa", 0x8c, 2, 0x0fff, -1, "PSC module 2 output compare SA register (16 bits)"}, + {"psc.pocr2ra", 0x8e, 2, 0x0fff, -1, "PSC module 2 output compare RA register (16 bits)"}, + {"psc.pocr2sb", 0x90, 2, 0x0fff, -1, "PSC module 2 output compare SB register (16 bits)"}, + {"psc.pocr_rb", 0x92, 2, 0x0fff, -1, "PSC output compare RB register (16 bits)"}, + {"psc.psync", 0x94, 1, -1, -1, "PSC synchro configuration register"}, + {"psc.pcnf", 0x95, 1, -1, -1, "PSC configuration register"}, + {"psc.poc", 0x96, 1, -1, -1, "PSC output configuration register"}, + {"psc.pctl", 0x97, 1, -1, -1, "PSC control register"}, + {"psc.pmic0", 0x98, 1, -1, -1, "PSC module 0 input control register"}, + {"psc.pmic1", 0x99, 1, -1, -1, "PSC module 1 input control register"}, + {"psc.pmic2", 0x9a, 1, -1, -1, "PSC module 2 input control register"}, + {"psc.pim", 0x9b, 1, -1, -1, "PSC interrupt mask register"}, + {"psc.pifr", 0x9c, 1, -1, -1, "PSC interrupt flag register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, + {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, + {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, + {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, + {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, + {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, + {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, + {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, + {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, + {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, + {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, + {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, + {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, + {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, + {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, + {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, + {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, + {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, + {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, + {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, + {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, + {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, + {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, + {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, + {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, + {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, + {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, + {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, + {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, + {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, + {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, + {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, + {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, +}; + +// ATmega128RFA1 +const Register_file rgftab_atmega128rfa1[237] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega64RFR2 ATmega644RFR2 +const Register_file rgftab_atmega64rfr2[269] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega128RFR2 ATmega1284RFR2 +const Register_file rgftab_atmega128rfr2[270] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega256RFR2 +const Register_file rgftab_atmega256rfr2[271] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega8U2 ATmega16U2 ATmega32U2 +const Register_file rgftab_atmega8u2[92] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, -1, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, -1, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"wdt.wdtckd", 0x42, 1, -1, -1, "watchdog timer clock divider register"}, + {"usb_device.regcr", 0x43, 1, -1, -1, "regulator control register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ac.acmux", 0x5d, 1, -1, -1, "analog comparator input multiplexer register"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"cpu.clksel0", 0xb0, 1, -1, -1, "clock selection register 0"}, + {"cpu.clksel1", 0xb1, 1, -1, -1, "clock selection register 1"}, + {"cpu.clksta", 0xb2, 1, -1, -1, "clock status register"}, + {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.ueint", 0xd4, 1, 0x1f, -1, "USB endpoint number interrupt register"}, + {"usb_device.upoe", 0xdb, 1, -1, -1, "USB software output enable register"}, +}; + +// ATmega16U4 ATmega32U4 +const Register_file rgftab_atmega16u4[139] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xc0, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xc0, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xc0, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x44, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x44, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x44, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xf3, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xf3, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xf3, -1, "port F data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"pll.pllfrq", 0x32, 1, -1, -1, "PLL frequency control register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"cpu.rcctrl", 0x47, 1, -1, -1, "oscillator control register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x5d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"tc4.tcnt4", 0x9e, 1, 0xff, -1, "timer/counter 4"}, + {"tc4.tc4h", 0x9f, 1, 0x07, -1, "timer/counter 4 high byte"}, + {"tc4.tccr4a", 0xa0, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0xa1, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0xa2, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tccr4d", 0xa3, 1, -1, -1, "T/C 4 control register D"}, + {"tc4.tccr4e", 0xa4, 1, -1, -1, "T/C 4 control register E"}, + {"cpu.clksel0", 0xa5, 1, -1, -1, "clock selection register 0"}, + {"cpu.clksel1", 0xa6, 1, -1, -1, "clock selection register 1"}, + {"cpu.clksta", 0xa7, 1, -1, -1, "clock status register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"tc4.ocr4a", 0xaf, 1, 0xff, -1, "T/C 4 output compare register A"}, + {"tc4.ocr4b", 0xb0, 1, 0xff, -1, "T/C 4 output compare register B"}, + {"tc4.ocr4c", 0xb1, 1, 0xff, -1, "T/C 4 output compare register C"}, + {"tc4.ocr4d", 0xb2, 1, 0xff, -1, "T/C 4 output compare register D"}, + {"tc4.dt4", 0xb4, 1, -1, -1, "T/C 4 dead-time register"}, + {"usb_device.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, + {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, + {"usb_device.usbsta", 0xb9, 1, -1, -1, "USB status register"}, + {"usb_device.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, + {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, + {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, + {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, + {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, + {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, + {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, + {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, + {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, + {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, + {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, + {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, + {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, + {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, + {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, + {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, + {"usb_device.uedatx", 0xd1, 1, -1, -1, "USB data endpoint register"}, + {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, + {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, + {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, +}; + +// ATmega1281 +const Register_file rgftab_atmega1281[138] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, +}; + +// ATmega2561 +const Register_file rgftab_atmega2561[139] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, + {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, +}; + +// ATmega162 +const Register_file rgftab_atmega162[79] = { // I/O memory [0, 223] + 32 + {"usart1.ubrr1l", 0x00, 1, 0xff, -1, "USART 1 baud rate register low byte"}, + {"usart1.ucsr1b", 0x01, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1a", 0x02, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.udr1", 0x03, 1, 0xff, -1, "USART 1 I/O data register"}, + {"cpu.osccal", 0x04, 1, 0x7f, -1, "oscillator calibration register"}, + {"jtag.ocdr", 0x04, 1, -1, -1, "on-chip debug register"}, + {"porte.pine", 0x05, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x06, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x07, 1, 0x07, -1, "port E data register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, + {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart0.ubrr0h", 0x20, 1, 0x8f, -1, "USART 0 baud rate register high byte"}, + {"usart0.ucsr0c", 0x20, 1, -1, -1, "USART 0 control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.ocr2", 0x22, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x23, 1, 0xff, -1, "timer/counter 2"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc2.assr", 0x26, 1, -1, -1, "asynchronous status register"}, + {"tc2.tccr2", 0x27, 1, -1, -1, "T/C 2 control register"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, + {"exint.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, + {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"usart1.ubrr1h", 0x3c, 1, 0x8f, -1, "USART 1 baud rate register high byte"}, + {"usart1.ucsr1c", 0x3c, 1, -1, -1, "USART control and status register C"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, + {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, + {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, +}; + +// ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA +const Register_file rgftab_atmega164a[96] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"spi.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, +}; + +// ATmega644 +const Register_file rgftab_atmega644[88] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega644A ATmega644P ATmega644PA +const Register_file rgftab_atmega644a[93] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, +}; + +// ATmega1284 ATmega1284P +const Register_file rgftab_atmega1284[104] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, +}; + +// ATmega324PB +const Register_file rgftab_atmega324pb[134] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x7f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x7f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x7f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi0.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi0.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi0.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cfd.xfdcsr", 0x42, 1, -1, -1, "XOSC failure detection control and status register"}, + {"cpu.prr2", 0x43, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, + {"exint.pcmsk4", 0x55, 1, -1, -1, "pin change interrupt mask register 4"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc4.tccr4a", 0x80, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x81, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x82, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x84, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x86, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x88, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x8a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"spi1.spcr1", 0x8c, 1, -1, -1, "SPI control register"}, + {"spi1.spsr1", 0x8d, 1, -1, -1, "SPI status register"}, + {"spi1.spdr1", 0x8e, 1, 0xff, -1, "SPI data register"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi0.twbr0", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi0.twsr0", 0x99, 1, -1, -1, "TWI status register"}, + {"twi0.twar0", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi0.twdr0", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi0.twcr0", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi0.twamr0", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, + {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"usart2.ucsr2a", 0xb0, 1, -1, -1, "USART control and status register A"}, + {"usart2.ucsr2b", 0xb1, 1, -1, -1, "USART control and status register B"}, + {"usart2.ucsr2c", 0xb2, 1, -1, -1, "USART control and status register C"}, + {"usart2.ucsr2d", 0xb3, 1, -1, -1, "USART control and status register D"}, + {"usart2.ubrr2", 0xb4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, + {"usart2.udr2", 0xb6, 1, 0xff, -1, "USART 2 I/O data register"}, + {"twi1.twbr1", 0xb8, 1, 0xff, -1, "TWI bit rate register"}, + {"twi1.twsr1", 0xb9, 1, -1, -1, "TWI status register"}, + {"twi1.twar1", 0xba, 1, -1, -1, "TWI peripheral address register"}, + {"twi1.twdr1", 0xbb, 1, 0xff, -1, "TWI data register"}, + {"twi1.twcr1", 0xbc, 1, -1, -1, "TWI control register"}, + {"twi1.twamr1", 0xbd, 1, -1, -1, "TWI peripheral address mask register"}, +}; + +// ATmega2564RFR2 +const Register_file rgftab_atmega2564rfr2[271] = { // I/O memory [0, 479] + 32 + {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, + {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, + {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, + {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, + {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, + {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, + {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, + {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, + {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, + {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, + {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, + {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, + {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, + {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, + {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, + {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, + {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, + {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, + {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, + {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, + {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, + {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, + {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, + {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, + {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, + {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, + {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, + {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, + {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, + {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, + {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, + {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, + {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, + {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, + {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, + {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, + {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, + {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, + {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, + {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, + {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, + {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, + {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, + {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, + {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, + {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, + {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, + {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, + {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, + {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, + {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, + {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, + {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, + {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, + {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, + {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, + {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, + {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, + {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, + {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, + {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, + {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, + {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, + {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, + {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, + {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, + {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, + {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, + {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, + {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, + {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, + {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, + {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, + {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, + {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, + {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, + {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, + {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, + {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, + {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, + {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, + {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, + {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, + {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, + {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, + {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, + {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, + {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, + {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, + {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, + {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, + {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, + {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, + {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, + {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, + {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, + {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, + {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, + {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, + {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, + {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, + {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, + {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, + {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, + {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, + {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, + {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, + {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, + {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, + {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, + {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, + {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, + {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, + {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, + {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, + {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, + {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, + {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, + {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, + {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, + {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, + {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, + {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, + {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, + {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, + {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, + {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, + {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, + {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, + {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, + {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, + {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, + {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, + {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, + {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, + {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, + {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, + {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, + {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, + {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, + {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, + {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, + {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, + {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, + {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, + {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, + {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, + {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, + {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, + {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, + {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, + {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, + {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, + {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, + {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, + {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, + {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, + {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, + {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, + {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, + {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, + {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, + {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, + {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, + {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, + {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, + {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, + {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, + {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, + {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, + {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, + {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, + {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, + {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, + {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, + {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, + {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, + {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, +}; + +// ATmega165A ATmega165P ATmega165PA +const Register_file rgftab_atmega165a[86] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega325 ATmega325A ATmega325P ATmega325PA +const Register_file rgftab_atmega325[86] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega645 ATmega645A ATmega645P +const Register_file rgftab_atmega645[86] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega3250 ATmega3250A ATmega3250P ATmega3250PA +const Register_file rgftab_atmega3250[94] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, +}; + +// ATmega6450 ATmega6450A ATmega6450P +const Register_file rgftab_atmega6450[94] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, +}; + +// ATmega8515 +const Register_file rgftab_atmega8515[52] = { // I/O memory [0, 63] + 32 + {"cpu.osccal", 0x04, 1, 0xff, -1, "oscillator calibration register"}, + {"porte.pine", 0x05, 1, 0x07, -1, "port E input register"}, + {"porte.ddre", 0x06, 1, 0x07, -1, "port E data direction register"}, + {"porte.porte", 0x07, 1, 0x07, -1, "port E data register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, + {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega8535 +const Register_file rgftab_atmega8535[67] = { // I/O memory [0, 63] + 32 + {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, + {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, + {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, + {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, + {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, + {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, + {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, + {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, + {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, + {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, + {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, + {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, + {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, + {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"usart.ubrrh", 0x20, 1, -1, -1, "USART baud rate register high byte"}, + {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, + {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, + {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, + {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, + {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, + {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, + {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, + {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, + {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, + {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, + {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, + {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, + {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, + {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, + {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, + {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, +}; + +// ATmega48 ATmega48P +const Register_file rgftab_atmega48[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega48A ATmega48PA +const Register_file rgftab_atmega48a[82] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"eeprom.eearh", 0x22, 1, 0x03, -1, "EEPROM address register high byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA +const Register_file rgftab_atmega88[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega328 ATmega328P +const Register_file rgftab_atmega328[81] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, @@ -14644,77 +22431,264 @@ const Register_file rgftab_atmega32hvbrevb[91] = { // I/O memory [0, 223] + 32 {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, - {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0x0f, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, - {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, - {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, - {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"twi.twbcsr", 0x9e, 1, -1, -1, "TWI bus control and status register"}, - {"voltage_regulator.rocr", 0xa8, 1, -1, -1, "regulator operating condition register"}, - {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, - {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, - {"bandgap.bgcsr", 0xb2, 1, -1, -1, "bandgap control and status register"}, - {"charger_detect.chgdcsr", 0xb4, 1, -1, -1, "charger detect control and status register"}, - {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadic", 0xc4, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, - {"coulomb_counter.cadcsra", 0xc6, 1, -1, -1, "CC-ADC control and status register A"}, - {"coulomb_counter.cadcsrb", 0xc7, 1, -1, -1, "CC-ADC control and status register B"}, - {"coulomb_counter.cadcsrc", 0xc8, 1, -1, -1, "CC-ADC control and status register C"}, - {"coulomb_counter.cadrcc", 0xc9, 1, 0xff, -1, "CC-ADC regular charge current register"}, - {"coulomb_counter.cadrdc", 0xca, 1, 0xff, -1, "CC-ADC regular discharge current register"}, - {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, - {"cell_balancing.cbcr", 0xd1, 1, -1, -1, "cell balancing control register"}, - {"battery_protection.bpimsk", 0xd2, 1, -1, -1, "battery protection interrupt mask register"}, - {"battery_protection.bpifr", 0xd3, 1, -1, -1, "battery protection interrupt flag register"}, - {"battery_protection.bpscd", 0xd5, 1, 0xff, -1, "battery protection short-circuit detection level register"}, - {"battery_protection.bpdocd", 0xd6, 1, 0xff, -1, "battery protection discharge-over-current detection level register"}, - {"battery_protection.bpcocd", 0xd7, 1, 0xff, -1, "battery protection charge-over-current detection level register"}, - {"battery_protection.bpdhcd", 0xd8, 1, 0xff, -1, "battery protection discharge-high-current detection level register"}, - {"battery_protection.bpchcd", 0xd9, 1, 0xff, -1, "battery protection charge-high-current detection level register"}, - {"battery_protection.bpsctr", 0xda, 1, 0x7f, -1, "battery protection short-current timing register"}, - {"battery_protection.bpoctr", 0xdb, 1, 0x3f, -1, "battery protection over-current timing register"}, - {"battery_protection.bphctr", 0xdc, 1, 0x3f, -1, "battery protection short-current timing register"}, - {"battery_protection.bpcr", 0xdd, 1, -1, -1, "battery protection control register"}, - {"battery_protection.bpplr", 0xde, 1, -1, -1, "battery protection parameter lock register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, +}; + +// ATmega48PB +const Register_file rgftab_atmega48pb[95] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"deviceid.devid0", 0xd0, 1, -1, -1, "device ID byte 0"}, + {"deviceid.devid1", 0xd1, 1, -1, -1, "device ID byte 1"}, + {"deviceid.devid2", 0xd2, 1, -1, -1, "device ID byte 2"}, + {"deviceid.devid3", 0xd3, 1, -1, -1, "device ID byte 3"}, + {"deviceid.devid4", 0xd4, 1, -1, -1, "device ID byte 4"}, + {"deviceid.devid5", 0xd5, 1, -1, -1, "device ID byte 5"}, + {"deviceid.devid6", 0xd6, 1, -1, -1, "device ID byte 6"}, + {"deviceid.devid7", 0xd7, 1, -1, -1, "device ID byte 7"}, + {"deviceid.devid8", 0xd8, 1, -1, -1, "device ID byte 8"}, +}; + +// ATmega88PB ATmega168PB +const Register_file rgftab_atmega88pb[95] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"deviceid.devid0", 0xd0, 1, -1, -1, "device ID byte 0"}, + {"deviceid.devid1", 0xd1, 1, -1, -1, "device ID byte 1"}, + {"deviceid.devid2", 0xd2, 1, -1, -1, "device ID byte 2"}, + {"deviceid.devid3", 0xd3, 1, -1, -1, "device ID byte 3"}, + {"deviceid.devid4", 0xd4, 1, -1, -1, "device ID byte 4"}, + {"deviceid.devid5", 0xd5, 1, -1, -1, "device ID byte 5"}, + {"deviceid.devid6", 0xd6, 1, -1, -1, "device ID byte 6"}, + {"deviceid.devid7", 0xd7, 1, -1, -1, "device ID byte 7"}, + {"deviceid.devid8", 0xd8, 1, -1, -1, "device ID byte 8"}, }; // ATmega328PB @@ -14846,340 +22820,8 @@ const Register_file rgftab_atmega328pb[125] = { // I/O memory [0, 223] + 32 {"twi1.twamr1", 0xbd, 1, -1, -1, "TWI peripheral address mask register"}, }; -// ATmega8515 -const Register_file rgftab_atmega8515[52] = { // I/O memory [0, 63] + 32 - {"cpu.osccal", 0x04, 1, 0xff, -1, "oscillator calibration register"}, - {"porte.pine", 0x05, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x06, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x07, 1, 0x07, -1, "port E data register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, -1, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, - {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny102 ATtiny104 -const Register_file rgftab_attiny102[55] = { // I/O memory [0, 63] - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, - {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, - {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, - {"usart.udr", 0x08, 1, 0xff, -1, "USART I/O data register"}, - {"usart.ubrr", 0x09, 2, 0x0fff, -1, "USART baud rate register (16 bits)"}, - {"usart.ucsrd", 0x0b, 1, -1, -1, "USART control and status register D"}, - {"usart.ucsrc", 0x0c, 1, -1, -1, "USART control and status register C"}, - {"usart.ucsrb", 0x0d, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0e, 1, -1, -1, "USART control and status register A"}, - {"exint.pcmsk0", 0x0f, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x10, 1, 0x0f, -1, "pin change interrupt mask register 1"}, - {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, - {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, - {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, - {"porta.portcr", 0x16, 1, -1, -1, "port control register"}, - {"portb.portcr", 0x16, 1, -1, -1, "port control register"}, - {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, - {"adc.adcl", 0x19, 1, 0xff, -1, "ADC data register low byte"}, - {"adc.adch", 0x1a, 1, 0xff, -1, "ADC data register high byte"}, - {"adc.admux", 0x1b, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.adcsrb", 0x1c, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsra", 0x1d, 1, -1, -1, "ADC control and status register A"}, - {"ac.acsrb", 0x1e, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsra", 0x1f, 1, -1, -1, "analog comparator control and status register A"}, - {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, - {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, - {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, - {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, - {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, - {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, - {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, - {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, - {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, - {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, - {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, - {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, - {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, - {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, - {"cpu.ccp", 0x3c, 1, -1, -1, "configuration change protection register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny28 -const Register_file rgftab_attiny28[20] = { // I/O memory [0, 63] + 32 - {"cpu.osccal", 0x00, 1, 0xff, -1, "oscillator calibration register"}, - {"watchdog.wdtcr", 0x01, 1, -1, -1, "watchdog timer control register"}, - {"modulator.modcr", 0x02, 1, -1, -1, "modulation control register"}, - {"timer_counter_0.tcnt0", 0x03, 1, 0xff, -1, "timer/counter 0"}, - {"timer_counter_0.tccr0", 0x04, 1, -1, -1, "T/C 0 control register"}, - {"external_interrupt.ifr", 0x05, 1, -1, -1, "interrupt flag register"}, - {"timer_counter_0.ifr", 0x05, 1, -1, -1, "interrupt flag register"}, - {"cpu.icr", 0x06, 1, -1, -1, "interrupt control register"}, - {"external_interrupt.icr", 0x06, 1, -1, -1, "interrupt control register"}, - {"timer_counter_0.icr", 0x06, 1, -1, -1, "interrupt control register"}, - {"cpu.mcucs", 0x07, 1, -1, -1, "MCU control and status register"}, - {"analog_comparator.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"porta.pina", 0x19, 1, 0x0b, -1, "port A input register"}, - {"porta.pacr", 0x1a, 1, 0x0f, -1, "port A control register"}, - {"porta.porta", 0x1b, 1, 0x0f, -1, "port A data register"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny441 ATtiny841 -const Register_file rgftab_attiny441[101] = { // I/O memory [0, 223] + 32 - {"adc.adcsrb", 0x04, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsra", 0x05, 1, -1, -1, "ADC control and status register A"}, - {"adc.adc", 0x06, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.admuxb", 0x08, 1, -1, -1, "ADC multiplexer selection register B"}, - {"adc.admuxa", 0x09, 1, -1, -1, "ADC multiplexer selection register A"}, - {"ac.acsr0a", 0x0a, 1, -1, -1, "analog comparator 0 control and status register A"}, - {"ac.acsr0b", 0x0b, 1, -1, -1, "analog comparator 0 control and status register B"}, - {"ac.acsr1a", 0x0c, 1, -1, -1, "analog comparator 1 control and status register A"}, - {"ac.acsr1b", 0x0d, 1, -1, -1, "analog comparator 1 control and status register B"}, - {"tc1.tifr1", 0x0e, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc1.timsk1", 0x0f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.tifr2", 0x10, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc2.timsk2", 0x11, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, - {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"adc.didr0", 0x40, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x41, 1, -1, -1, "digital input disable register 1"}, - {"portb.pueb", 0x42, 1, 0x0f, -1, "PORT B pull-up enable control register"}, - {"porta.puea", 0x43, 1, 0xff, -1, "PORT A pull-up enable control register"}, - {"porta.portcr", 0x44, 1, -1, -1, "port control register"}, - {"portb.portcr", 0x44, 1, -1, -1, "port control register"}, - {"spi.remap", 0x45, 1, -1, -1, "remap port pins register"}, - {"usart0.remap", 0x45, 1, -1, -1, "remap port pins register"}, - {"tocpm.tocpmcoe", 0x46, 1, -1, -1, "timer output compare pin mux channel output enable register"}, - {"tocpm.tocpmsa0", 0x47, 1, -1, -1, "timer output compare pin mux selection 0 register"}, - {"tocpm.tocpmsa1", 0x48, 1, -1, -1, "timer output compare pin mux selection 1 register"}, - {"porta.phde", 0x4a, 1, -1, -1, "port high drive enable register"}, - {"cpu.prr", 0x50, 1, -1, -1, "power reduction register"}, - {"cpu.ccp", 0x51, 1, 0xff, -1, "configuration change protection register"}, - {"cpu.clkcr", 0x52, 1, -1, -1, "clock control register"}, - {"cpu.clkpr", 0x53, 1, -1, -1, "clock prescaler register"}, - {"cpu.osccal0", 0x54, 1, 0xff, -1, "oscillator calibration register 8 MHz"}, - {"cpu.osctcal0a", 0x55, 1, 0xff, -1, "oscillator temperature calibration register A"}, - {"cpu.osctcal0b", 0x56, 1, 0xff, -1, "oscillator temperature calibration register B"}, - {"cpu.osccal1", 0x57, 1, 0x03, -1, "oscillator calibration register 32 kHz"}, - {"usart0.udr0", 0x60, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart0.ubrr0", 0x61, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.ucsr0d", 0x63, 1, -1, -1, "USART control and status register D"}, - {"usart0.ucsr0c", 0x64, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ucsr0b", 0x65, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0a", 0x66, 1, -1, -1, "USART 0 control and status register A"}, - {"usart1.udr1", 0x70, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart1.ubrr1", 0x71, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.ucsr1d", 0x73, 1, -1, -1, "USART control and status register D"}, - {"usart1.ucsr1c", 0x74, 1, -1, -1, "USART control and status register C"}, - {"usart1.ucsr1b", 0x75, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1a", 0x76, 1, -1, -1, "USART 1 control and status register A"}, - {"twi.twsd", 0x80, 1, -1, -1, "TWI peripheral data register"}, - {"twi.twsam", 0x81, 1, -1, -1, "TWI peripheral address mask register"}, - {"twi.twsa", 0x82, 1, 0xff, -1, "TWI peripheral address register"}, - {"twi.twssra", 0x83, 1, -1, -1, "TWI peripheral status register A"}, - {"twi.twscrb", 0x84, 1, -1, -1, "TWI peripheral control register B"}, - {"twi.twscra", 0x85, 1, -1, -1, "TWI peripheral control register A"}, - {"spi.spdr", 0x90, 1, 0xff, -1, "SPI data register"}, - {"spi.spsr", 0x91, 1, -1, -1, "SPI status register"}, - {"spi.spcr", 0x92, 1, -1, -1, "SPI control register"}, - {"tc2.icr2", 0xa0, 2, 0xffff, -1, "T/C 2 input capture register (16 bits)"}, - {"tc2.ocr2b", 0xa2, 2, 0xffff, -1, "T/C 2 output compare register B (16 bits)"}, - {"tc2.ocr2a", 0xa4, 2, 0xffff, -1, "T/C 2 output compare register A (16 bits)"}, - {"tc2.tcnt2", 0xa6, 2, 0xffff, -1, "timer/counter 2 (16 bits)"}, - {"tc2.tccr2c", 0xa8, 1, -1, -1, "T/C 2 control register C"}, - {"tc2.tccr2b", 0xa9, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tccr2a", 0xaa, 1, -1, -1, "T/C 2 control register A"}, -}; - -// AT90PWM81 -const Register_file rgftab_at90pwm81[84] = { // I/O memory [0, 223] + 32 - {"ac.acsr", 0x00, 1, -1, -1, "analog comparator control and status register"}, - {"tc1.timsk1", 0x01, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc1.tifr1", 0x02, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x07, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x08, 1, -1, -1, "ADC multiplexer selection register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"psc0.pim0", 0x0f, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc0.pifr0", 0x10, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pcnf0", 0x11, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0x12, 1, -1, -1, "PSC 0 control register"}, - {"psc2.pim2", 0x13, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"psc2.pifr2", 0x14, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pcnf2", 0x15, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0x16, 1, -1, -1, "PSC 2 control register"}, - {"spi.spcr", 0x17, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x18, 1, -1, -1, "SPI status register"}, - {"cpu.gpior0", 0x19, 1, -1, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x1a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1b, 1, -1, -1, "general purpose I/O register 2"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, -1, -1, "EEPROM address register (16 bits)"}, - {"exint.eifr", 0x20, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x21, 1, -1, -1, "external interrupt mask register"}, - {"psc0.ocr0sb", 0x22, 2, -1, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0x24, 2, -1, -1, "output compare 0 RB register (16 bits)"}, - {"psc2.ocr2sb", 0x26, 2, -1, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0x28, 2, -1, -1, "output compare 2 RB register (16 bits)"}, - {"psc0.ocr0ra", 0x2a, 2, -1, -1, "output compare 0 RA register (16 bits)"}, - {"adc.adc", 0x2c, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"psc2.ocr2ra", 0x2e, 2, -1, -1, "output compare 2 RA register (16 bits)"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"spi.spdr", 0x36, 1, -1, -1, "SPI data register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"dac.dac", 0x38, 2, 0xffff, -1, "DAC data register (16 bits)"}, - {"tc1.tcnt1", 0x3a, 2, -1, -1, "timer/counter 1 (16 bits)"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"psc0.ocr0sa", 0x40, 2, -1, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.pfrc0a", 0x42, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0x43, 1, -1, -1, "PSC 0 input B control register"}, - {"psc2.ocr2sa", 0x44, 2, -1, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.pfrc2a", 0x46, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0x47, 1, -1, -1, "PSC 2 input B control register"}, - {"psc0.picr0", 0x48, 2, -1, -1, "PSC 0 input capture register (16 bits)"}, - {"psc0.psoc0", 0x4a, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc2.picr2", 0x4c, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, - {"psc2.psoc2", 0x4e, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0x4f, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.pcnfe2", 0x50, 1, -1, -1, "PSC 2 enhanced configuration register"}, - {"psc2.pasdly2", 0x51, 1, -1, -1, "analog synchronization delay register"}, - {"dac.dacon", 0x56, 1, -1, -1, "DAC control register"}, - {"adc.didr0", 0x57, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x58, 1, -1, -1, "digital input disable register 1"}, - {"adc.amp0csr", 0x59, 1, -1, -1, "amplifier 0 control and status register"}, - {"ac.ac1econ", 0x5a, 1, -1, -1, "analog comparator 1 extended control register"}, - {"ac.ac2econ", 0x5b, 1, -1, -1, "analog comparator 2 extended control register"}, - {"ac.ac3econ", 0x5c, 1, -1, -1, "analog comparator 3 extended control register"}, - {"ac.ac1con", 0x5d, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x5e, 1, -1, -1, "analog comparator 2 control register"}, - {"ac.ac3con", 0x5f, 1, -1, -1, "analog comparator 3 control register"}, - {"cpu.bgcrr", 0x60, 1, -1, -1, "bandgap resistor calibration register"}, - {"cpu.bgccr", 0x61, 1, -1, -1, "bandgap current calibration register"}, - {"wdt.wdtcsr", 0x62, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x63, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkcsr", 0x64, 1, -1, -1, "clock control and status register"}, - {"cpu.clkselr", 0x65, 1, -1, -1, "clock selection register"}, - {"cpu.prr", 0x66, 1, -1, -1, "power reduction register"}, - {"cpu.pllcsr", 0x67, 1, -1, -1, "PLL control and status register"}, - {"cpu.osccal", 0x68, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x69, 1, -1, -1, "external interrupt control register A"}, - {"tc1.tccr1b", 0x6a, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.icr1", 0x6c, 2, -1, -1, "T/C 1 input capture register (16 bits)"}, -}; - -// AT90CAN128 AT90CAN32 AT90CAN64 -const Register_file rgftab_at90can128[137] = { // I/O memory [0, 223] + 32 +// ATmega169A ATmega169P ATmega169PA +const Register_file rgftab_atmega169a[106] = { // I/O memory [0, 223] + 32 {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, @@ -15198,26 +22840,25 @@ const Register_file rgftab_at90can128[137] = { // I/O memory [0, 223] + 32 {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x1f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x3f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x3f, -1, "port G data register"}, {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, @@ -15229,20 +22870,18 @@ const Register_file rgftab_at90can128[137] = { // I/O memory [0, 223] + 32 {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, + {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, @@ -15257,123 +22896,108 @@ const Register_file rgftab_at90can128[137] = { // I/O memory [0, 223] + 32 {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, - {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, - {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, - {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, - {"can.canen2", 0xbc, 1, 0xff, -1, "CAN enable MOb register 2"}, - {"can.canen1", 0xbd, 1, 0x7f, -1, "CAN enable MOb register 1"}, - {"can.canie2", 0xbe, 1, 0xff, -1, "CAN enable interrupt MOb register 2"}, - {"can.canie1", 0xbf, 1, 0x7f, -1, "CAN enable interrupt MOb register 1"}, - {"can.cansit2", 0xc0, 1, 0xff, -1, "CAN status interrupt MOb register 2"}, - {"can.cansit1", 0xc1, 1, 0x7f, -1, "CAN status interrupt MOb register 1"}, - {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, - {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, - {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, - {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, - {"can.cantim", 0xc6, 2, -1, -1, "CAN timer (16 bits)"}, - {"can.canttc", 0xc8, 2, -1, -1, "CAN TTC timer (16 bits)"}, - {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, - {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, - {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, - {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, - {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, - {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, - {"can.canidt4", 0xd0, 1, 0xff, -1, "CAN identifier tag register 4"}, - {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, - {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, - {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, - {"can.canidm4", 0xd4, 1, -1, -1, "CAN identifier mask register 4"}, - {"can.canidm3", 0xd5, 1, -1, -1, "CAN identifier mask register 3"}, - {"can.canidm2", 0xd6, 1, -1, -1, "CAN identifier mask register 2"}, - {"can.canidm1", 0xd7, 1, -1, -1, "CAN identifier mask register 1"}, - {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, - {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, }; -// AT90USB162 AT90USB82 -const Register_file rgftab_at90usb162[92] = { // I/O memory [0, 223] + 32 +// ATmega329 +const Register_file rgftab_atmega329[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, -1, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, -1, -1, "port C data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"wdt.wdtckd", 0x42, 1, -1, -1, "watchdog timer clock divider register"}, - {"usb_device.regcr", 0x43, 1, -1, -1, "regulator control register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, @@ -15382,37 +23006,1289 @@ const Register_file rgftab_at90usb162[92] = { // I/O memory [0, 223] + 32 {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"cpu.clksel0", 0xb0, 1, -1, -1, "clock selection register 0"}, - {"cpu.clksel1", 0xb1, 1, -1, -1, "clock selection register 1"}, - {"cpu.clksta", 0xb2, 1, -1, -1, "clock status register"}, - {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, - {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, - {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, - {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, - {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, - {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, - {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, - {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, - {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, - {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, - {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, - {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, - {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, - {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, - {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, - {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, - {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, - {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, - {"usb_device.ueint", 0xd4, 1, 0x1f, -1, "USB endpoint number interrupt register"}, - {"ps2.ps2con", 0xda, 1, -1, -1, "PS 2 pad enable register"}, - {"ps2.upoe", 0xdb, 1, -1, -1, "USB software output enable register"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega329A ATmega329PA +const Register_file rgftab_atmega329a[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega329P +const Register_file rgftab_atmega329p[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega649 ATmega649A ATmega649P +const Register_file rgftab_atmega649[106] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, +}; + +// ATmega3290 ATmega3290A +const Register_file rgftab_atmega3290[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr04", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr09", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega3290P +const Register_file rgftab_atmega3290p[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr03", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr04", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr08", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr09", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega3290PA +const Register_file rgftab_atmega3290pa[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr4", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr9", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega6490 ATmega6490A ATmega6490P +const Register_file rgftab_atmega6490[118] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, + {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, + {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, + {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, + {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, + {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, + {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, + {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, + {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, + {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, + {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, + {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, + {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, + {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, + {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, + {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, + {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, + {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, + {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, + {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, + {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, + {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, + {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, + {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, + {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, + {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, + {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, + {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, + {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, + {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, + {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, + {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, + {"lcd.lcddr3", 0xcf, 1, 0xff, -1, "LCD data register 3"}, + {"lcd.lcddr4", 0xd0, 1, 0xff, -1, "LCD data register 4"}, + {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, + {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, + {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, + {"lcd.lcddr8", 0xd4, 1, 0xff, -1, "LCD data register 8"}, + {"lcd.lcddr9", 0xd5, 1, 0xff, -1, "LCD data register 9"}, + {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, + {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, + {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, + {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, + {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, + {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, + {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, + {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, + {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, + {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, +}; + +// ATmega8HVA ATmega16HVA +const Register_file rgftab_atmega8hva[74] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0x03, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0x03, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0x03, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0x0f, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0x0f, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0x0f, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x01, -1, "port C input register"}, + {"portc.portc", 0x08, 1, 0x01, -1, "port C data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.osicsr", 0x17, 1, -1, -1, "oscillator sampling interface control and status register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 1, 0xff, -1, "EEPROM address register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, + {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, + {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, + {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"voltage_regulator.rocr", 0xa8, 1, -1, -1, "regulator operating condition register"}, + {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, + {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, + {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadcsra", 0xc4, 1, -1, -1, "CC-ADC control and status register A"}, + {"coulomb_counter.cadcsrb", 0xc5, 1, -1, -1, "CC-ADC control and status register B"}, + {"coulomb_counter.cadrc", 0xc6, 1, 0xff, -1, "CC-ADC regular current register"}, + {"coulomb_counter.cadic", 0xc8, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, + {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, + {"battery_protection.bpimsk", 0xd2, 1, -1, -1, "battery protection interrupt mask register"}, + {"battery_protection.bpifr", 0xd3, 1, -1, -1, "battery protection interrupt flag register"}, + {"battery_protection.bpscd", 0xd5, 1, 0xff, -1, "battery protection short-circuit detection level register"}, + {"battery_protection.bpdocd", 0xd6, 1, 0xff, -1, "battery protection discharge-over-current detection level register"}, + {"battery_protection.bpcocd", 0xd7, 1, 0xff, -1, "battery protection charge-over-current detection level register"}, + {"battery_protection.bpdhcd", 0xd8, 1, 0xff, -1, "battery protection discharge-high-current detection level register"}, + {"battery_protection.bpchcd", 0xd9, 1, 0xff, -1, "battery protection charge-high-current detection level register"}, + {"battery_protection.bpsctr", 0xda, 1, 0x7f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpoctr", 0xdb, 1, 0x3f, -1, "battery protection over-current timing register"}, + {"battery_protection.bphctr", 0xdc, 1, 0x3f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpcr", 0xdd, 1, -1, -1, "battery protection control register"}, + {"battery_protection.bpplr", 0xde, 1, -1, -1, "battery protection parameter lock register"}, +}; + +// ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB +const Register_file rgftab_atmega16hvb[91] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0x0f, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0x0f, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0x0f, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x1f, -1, "port C input register"}, + {"portc.portc", 0x08, 1, 0x3f, -1, "port C data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"cpu.osicsr", 0x17, 1, -1, -1, "oscillator sampling interface control and status register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0x0f, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, + {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, + {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, + {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twbcsr", 0x9e, 1, -1, -1, "TWI bus control and status register"}, + {"voltage_regulator.rocr", 0xa8, 1, -1, -1, "regulator operating condition register"}, + {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, + {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, + {"bandgap.bgcsr", 0xb2, 1, -1, -1, "bandgap control and status register"}, + {"charger_detect.chgdcsr", 0xb4, 1, -1, -1, "charger detect control and status register"}, + {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadic", 0xc4, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, + {"coulomb_counter.cadcsra", 0xc6, 1, -1, -1, "CC-ADC control and status register A"}, + {"coulomb_counter.cadcsrb", 0xc7, 1, -1, -1, "CC-ADC control and status register B"}, + {"coulomb_counter.cadcsrc", 0xc8, 1, -1, -1, "CC-ADC control and status register C"}, + {"coulomb_counter.cadrcc", 0xc9, 1, 0xff, -1, "CC-ADC regular charge current register"}, + {"coulomb_counter.cadrdc", 0xca, 1, 0xff, -1, "CC-ADC regular discharge current register"}, + {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, + {"cell_balancing.cbcr", 0xd1, 1, -1, -1, "cell balancing control register"}, + {"battery_protection.bpimsk", 0xd2, 1, -1, -1, "battery protection interrupt mask register"}, + {"battery_protection.bpifr", 0xd3, 1, -1, -1, "battery protection interrupt flag register"}, + {"battery_protection.bpscd", 0xd5, 1, 0xff, -1, "battery protection short-circuit detection level register"}, + {"battery_protection.bpdocd", 0xd6, 1, 0xff, -1, "battery protection discharge-over-current detection level register"}, + {"battery_protection.bpcocd", 0xd7, 1, 0xff, -1, "battery protection charge-over-current detection level register"}, + {"battery_protection.bpdhcd", 0xd8, 1, 0xff, -1, "battery protection discharge-high-current detection level register"}, + {"battery_protection.bpchcd", 0xd9, 1, 0xff, -1, "battery protection charge-high-current detection level register"}, + {"battery_protection.bpsctr", 0xda, 1, 0x7f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpoctr", 0xdb, 1, 0x3f, -1, "battery protection over-current timing register"}, + {"battery_protection.bphctr", 0xdc, 1, 0x3f, -1, "battery protection short-current timing register"}, + {"battery_protection.bpcr", 0xdd, 1, -1, -1, "battery protection control register"}, + {"battery_protection.bpplr", 0xde, 1, -1, -1, "battery protection parameter lock register"}, +}; + +// ATmega64HVE2 +const Register_file rgftab_atmega64hve2[89] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0x03, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0x03, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0x03, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, + {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, + {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"wakeup_timer.wutcsr", 0x42, 1, -1, -1, "wake-up timer control and status register"}, + {"wdt.wdtclr", 0x43, 1, -1, -1, "watchdog timer configuration lock register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.sosccala", 0x46, 1, 0xff, -1, "slow oscillator calibration register A"}, + {"cpu.sosccalb", 0x47, 1, 0xff, -1, "oscillator calibration register B"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0x03, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, + {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, + {"linuart.lincr", 0xa0, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa1, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xa2, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xa3, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xa4, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xa5, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xa6, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xa7, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xa8, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xa9, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xaa, 1, -1, -1, "LIN data register"}, + {"bandgap.bgcsra", 0xb1, 1, -1, -1, "bandgap control and status register A"}, + {"bandgap.bgcrb", 0xb2, 1, -1, -1, "bandgap calibration register B"}, + {"bandgap.bgcra", 0xb3, 1, -1, -1, "bandgap calibration register A"}, + {"bandgap.bglr", 0xb4, 1, -1, -1, "band gap lock register"}, + {"cpu.pllcsr", 0xb8, 1, -1, -1, "PLL control and status register"}, + {"portb.pbov", 0xbc, 1, -1, -1, "port B override register"}, + {"adc.adscsra", 0xc0, 1, -1, -1, "ADC synchronization control and status register A"}, + {"adc.adscsrb", 0xc1, 1, -1, -1, "ADC synchronization control and status register B"}, + {"adc.adcra", 0xc2, 1, -1, -1, "ADC control register A"}, + {"adc.adcrb", 0xc3, 1, -1, -1, "ADC control register B"}, + {"adc.adcrc", 0xc4, 1, -1, -1, "ADC control register B"}, + {"adc.adcrd", 0xc5, 1, -1, -1, "ADC control register D"}, + {"adc.adcre", 0xc6, 1, -1, -1, "ADC control register E"}, + {"adc.adifr", 0xc7, 1, -1, -1, "ADC interrupt flag register"}, + {"adc.adimr", 0xc8, 1, -1, -1, "ADC interrupt mask register"}, + {"adc.cadrcl", 0xc9, 2, 0xffff, -1, "CC-ADC regulator current comparator threshold level register (16 bits)"}, + {"adc.cadic", 0xcb, 2, 0xffff, -1, "C-ADC instantaneous conversion result register (16 bits)"}, + {"adc.cadac0", 0xcd, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.cadac1", 0xce, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.cadac2", 0xcf, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.cadac3", 0xd0, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, + {"adc.vadic", 0xd1, 2, 0xffff, -1, "V-ADC instantaneous conversion result register (16 bits)"}, + {"adc.vadac0", 0xd3, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, + {"adc.vadac1", 0xd4, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, + {"adc.vadac2", 0xd5, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, + {"adc.vadac3", 0xd6, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, +}; + +// ATmega406 +const Register_file rgftab_atmega406[79] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.portc", 0x08, 1, 0x01, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0x03, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0x03, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0x03, -1, "port D data register"}, + {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, + {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, + {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, + {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, + {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, + {"wakeup_timer.wutcsr", 0x42, 1, -1, -1, "wake-up timer control and status register"}, + {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, + {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, + {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, + {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, + {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, + {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, + {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, + {"cpu.didr0", 0x5e, 1, 0x0f, -1, "digital input disable register 0"}, + {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"tc1.ocr1al", 0x68, 1, 0xff, -1, "output compare 1 register A low byte"}, + {"tc1.ocr1ah", 0x69, 1, 0xff, -1, "output compare 1 register A high byte"}, + {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, + {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, + {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, + {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, + {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, + {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, + {"twi.twbcsr", 0x9e, 1, -1, -1, "TWI bus control and status register"}, + {"cpu.ccsr", 0xa0, 1, -1, -1, "clock control and status register"}, + {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, + {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, + {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, + {"coulomb_counter.cadcsra", 0xc4, 1, -1, -1, "CC-ADC control and status register A"}, + {"coulomb_counter.cadcsrb", 0xc5, 1, -1, -1, "CC-ADC control and status register B"}, + {"coulomb_counter.cadrcc", 0xc6, 1, 0xff, -1, "CC-ADC regular charge current register"}, + {"coulomb_counter.cadrdc", 0xc7, 1, 0xff, -1, "CC-ADC regular discharge current register"}, + {"coulomb_counter.cadic", 0xc8, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, + {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, + {"cell_balancing.cbcr", 0xd1, 1, -1, -1, "cell balancing control register"}, + {"battery_protection.bpir", 0xd2, 1, -1, -1, "battery protection interrupt register"}, + {"battery_protection.bpduv", 0xd3, 1, -1, -1, "battery protection deep under voltage register"}, + {"battery_protection.bpscd", 0xd4, 1, -1, -1, "battery protection short-circuit detection level register"}, + {"battery_protection.bpocd", 0xd5, 1, -1, -1, "battery protection overcurrent detection level register"}, + {"battery_protection.cbptr", 0xd6, 1, -1, -1, "current battery protection timing register"}, + {"battery_protection.bpcr", 0xd7, 1, -1, -1, "battery protection control register"}, + {"battery_protection.bpplr", 0xd8, 1, -1, -1, "battery protection parameter lock register"}, +}; + +// ATA5272 ATA5505 +const Register_file rgftab_ata5272[80] = { // I/O memory [0, 223] + 32 + {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, + {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, + {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, + {"timer_counter_0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, + {"timer_counter_1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, + {"external_interrupt.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, + {"external_interrupt.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, + {"external_interrupt.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"timer_counter_0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, + {"timer_counter_0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, + {"timer_counter_0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, + {"timer_counter_0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, + {"timer_counter_0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"analog_comparator.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, + {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, + {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, + {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, + {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, + {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, + {"external_interrupt.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer_counter_0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, + {"timer_counter_1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, + {"ad_converter.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, + {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, + {"ad_converter.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, + {"ad_converter.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, + {"ad_converter.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, + {"analog_comparator.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, + {"ad_converter.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, + {"ad_converter.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, + {"ad_converter.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, + {"timer_counter_1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, + {"timer_counter_1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, + {"timer_counter_1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, + {"timer_counter_1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, + {"timer_counter_1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, + {"timer_counter_1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, + {"timer_counter_1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, + {"timer_counter_1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, + {"timer_counter_0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, + {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, + {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, + {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, + {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, + {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, + {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, + {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, + {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, + {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, + {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, + {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, + {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, + {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, + {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, + {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, + {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, }; // ATA5700M322 @@ -15756,6 +24632,388 @@ const Register_file rgftab_ata5700m322[337] = { // I/O memory [0, 479] + 32 {"tplf_cal.srccall", 0x1df, 1, -1, -1, "slow RC oscillator calibration register low byte"}, }; +// ATA5702M322 +const Register_file rgftab_ata5702m322[378] = { // I/O memory [0, 479] + 32 + {"gpioregs_dvcc.gpior0", 0x000, 1, 0xff, -1, "general purpose I/O register 0"}, + {"clk.prr1", 0x001, 1, -1, -1, "power reduction register 1"}, + {"clk.prr2", 0x002, 1, -1, -1, "power reduction register 2"}, + {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x006, 1, 0x07, -1, "port C input register"}, + {"portc.ddrc", 0x007, 1, 0x07, -1, "port C data direction register"}, + {"portc.portc", 0x008, 1, 0x07, -1, "port C data register"}, + {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, + {"lf_transponder.tpcr2", 0x00c, 1, -1, -1, "transponder control register 2"}, + {"lf_transponder.tpfr", 0x00d, 1, -1, -1, "transponder flag register"}, + {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, + {"txdsp.fscr", 0x00f, 1, -1, -1, "frequency synthesizer control register"}, + {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, + {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, + {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, + {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, + {"lf_timer.ltcmr", 0x015, 1, -1, -1, "LF timer control mode register"}, + {"eeprom.eecr2", 0x016, 1, -1, -1, "EEPROM control register 2"}, + {"lf_protocol_handler.phtcr", 0x017, 1, -1, -1, "PH telegram configuration register"}, + {"lf_fifo.ldffl", 0x018, 1, -1, -1, "LF data FIFO fill level register"}, + {"lf_fifo.ldfd", 0x019, 1, 0xff, -1, "LF data FIFO data register"}, + {"clk.prr0", 0x01a, 1, -1, -1, "power reduction register 0"}, + {"lf_protocol_handler.phfr", 0x01b, 1, -1, -1, "protocol handler flag register"}, + {"lf_receiver.lffr", 0x01c, 1, -1, -1, "LF flag register"}, + {"aes.aescr", 0x01d, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x01e, 1, -1, -1, "AES status register"}, + {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, + {"gpioregs_dvcc.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, + {"gpioregs_dvcc.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, + {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, + {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, + {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, + {"lf_fifo.ldfcksw", 0x029, 1, -1, -1, "LF data FIFO clock switch register"}, + {"sup.vmscr", 0x02a, 1, -1, -1, "voltage monitor status and control register"}, + {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, + {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, + {"lf_receiver.lfcr0", 0x02f, 1, -1, -1, "LF receiver control register 0"}, + {"lf_receiver.lfcr1", 0x030, 1, -1, -1, "LF receiver control register 1"}, + {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, + {"timer0_wdt.t0ifr", 0x032, 1, -1, -1, "timer 0 interrupt flag register"}, + {"cpu.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, + {"cpu.smcr", 0x038, 1, -1, -1, "sleep mode control register"}, + {"lf_transponder.tpsr", 0x039, 1, -1, -1, "transponder status register"}, + {"lf_receiver.lfcr2", 0x03a, 1, -1, -1, "LF receiver control register 2"}, + {"lf_receiver.lfcr3", 0x03b, 1, -1, -1, "LF receiver control register 3"}, + {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"txdsp.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, + {"txdsp.fsfcr", 0x041, 1, -1, -1, "frequency synthesizer filter control register"}, + {"txdsp.gacdiv", 0x042, 2, 0x1fff, -1, "Gauss clock divider register (16 bits)"}, + {"txdsp.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, + {"txdsp.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, + {"txdsp.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, + {"txdsp.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, + {"txdsp.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, + {"txdsp.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, + {"txdsp.bbte2", 0x04a, 1, -1, -1, "base band test enable 2 register"}, + {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, + {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, + {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, + {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, + {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, + {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, + {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, + {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, + {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, + {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, + {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, + {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, + {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, + {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, + {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, + {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, + {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, + {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, + {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, + {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, + {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, + {"timer5.t5temp", 0x069, 1, 0xff, -1, "timer 5 temp register"}, + {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, + {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, + {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, + {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, + {"tplf_cal.lfcalr1", 0x070, 1, -1, -1, "LF receiver calibration register 1"}, + {"tplf_cal.lfcalr2", 0x071, 1, -1, -1, "LF receiver calibration register 2"}, + {"tplf_cal.lfcalr3", 0x072, 1, -1, -1, "LF receiver calibration register 3"}, + {"tplf_cal.lfcalr4", 0x073, 1, -1, -1, "LF receiver calibration register 4"}, + {"tplf_cal.lfcalr5", 0x074, 1, -1, -1, "LF receiver calibration register 5"}, + {"tplf_cal.lfcalr6", 0x075, 1, -1, -1, "LF receiver calibration register 6"}, + {"tplf_cal.lfcalr7", 0x076, 1, 0xff, -1, "LF receiver calibration register 7"}, + {"tplf_cal.lfcalr8", 0x077, 1, 0x1f, -1, "LF receiver calibration register 8"}, + {"tplf_cal.lfcalr9", 0x078, 1, 0xff, -1, "LF receiver calibration register 9"}, + {"tplf_cal.lfcalr10", 0x079, 1, 0x7f, -1, "LF receiver calibration register 10"}, + {"tplf_cal.lfcalr11", 0x07a, 1, 0xff, -1, "LF receiver calibration register 11"}, + {"tplf_cal.lfcalr12", 0x07b, 1, 0xff, -1, "LF receiver calibration register 12"}, + {"tplf_cal.lfcalr13", 0x07c, 1, 0xff, -1, "LF receiver calibration register 13"}, + {"tplf_cal.lfcalr14", 0x07d, 1, 0x7f, -1, "LF receiver calibration register 14"}, + {"tplf_cal.lfcalr15", 0x07e, 1, 0xff, -1, "LF receiver calibration register 15"}, + {"tplf_cal.lfcalr16", 0x07f, 1, 0x1f, -1, "LF receiver calibration register 16"}, + {"tplf_cal.lfcalr17", 0x080, 1, 0x1f, -1, "LF receiver calibration register 17"}, + {"tplf_cal.lfcalr18", 0x081, 1, 0xff, -1, "LF receiver calibration register 18"}, + {"tplf_cal.lfcalr19", 0x082, 1, 0x7f, -1, "LF receiver calibration register 19"}, + {"tplf_cal.lfcalr20", 0x083, 1, 0xff, -1, "LF receiver calibration register 20"}, + {"tplf_cal.lfcalr21", 0x084, 1, 0xff, -1, "LF receiver calibration register 21"}, + {"tplf_cal.lfcalr22", 0x085, 1, 0xff, -1, "LF receiver calibration register 22"}, + {"tplf_cal.lfcalr23", 0x086, 1, 0x7f, -1, "LF receiver calibration register 23"}, + {"tplf_cal.lfcalr24", 0x087, 1, 0xff, -1, "LF receiver calibration register 24"}, + {"tplf_cal.lfcalr25", 0x088, 1, 0x1f, -1, "LF receiver calibration register 25"}, + {"tplf_cal.lfcalr26", 0x089, 1, 0x1f, -1, "LF receiver calibration register 26"}, + {"tplf_cal.lfcalr27", 0x08a, 1, 0xff, -1, "LF receiver calibration register 27"}, + {"tplf_cal.lfcalr28", 0x08b, 1, 0x7f, -1, "LF receiver calibration register 28"}, + {"tplf_cal.lfcalr29", 0x08c, 1, 0xff, -1, "LF receiver calibration register 29"}, + {"tplf_cal.lfcalr30", 0x08d, 1, 0xff, -1, "LF receiver calibration register 30"}, + {"tplf_cal.lfcalr31", 0x08e, 1, 0xff, -1, "LF receiver calibration register 31"}, + {"tplf_cal.lfcalr32", 0x08f, 1, 0x7f, -1, "LF receiver calibration register 32"}, + {"tplf_cal.lfcalr33", 0x090, 1, 0xff, -1, "LF receiver calibration register 33"}, + {"tplf_cal.lfcalr34", 0x091, 1, 0x1f, -1, "LF receiver calibration register 34"}, + {"tplf_cal.lfcalr35", 0x092, 1, 0xff, -1, "LF receiver calibration register 35"}, + {"tplf_cal.lfcalr36", 0x093, 1, 0x7f, -1, "LF receiver calibration register 36"}, + {"tplf_cal.lfcalr37", 0x094, 1, 0x3f, -1, "LF receiver calibration register 37"}, + {"tplf_cal.lfcalr38", 0x095, 1, 0x0f, -1, "LF receiver calibration register 38"}, + {"tplf_cal.lfcalr39", 0x096, 1, 0x0f, -1, "LF receiver calibration register 39"}, + {"tplf_cal.lfcalr40", 0x097, 1, 0x0f, -1, "LF receiver calibration register 40"}, + {"tplf_cal.lfcalr41", 0x098, 1, 0xff, -1, "LF receiver calibration register 41"}, + {"tplf_cal.lfcalr42", 0x099, 1, 0xff, -1, "LF receiver calibration register 42"}, + {"tplf_cal.lfcalr43", 0x09a, 1, 0xff, -1, "LF receiver calibration register 43"}, + {"tplf_cal.lfcalr44", 0x09b, 1, 0x3f, -1, "LF receiver calibration register 44"}, + {"tplf_cal.lfcalr45", 0x09c, 1, 0xff, -1, "LF receiver calibration register 45"}, + {"tplf_cal.lfcalr46", 0x09d, 1, 0xff, -1, "LF receiver calibration register 46"}, + {"tplf_cal.lfcalr47", 0x09e, 1, 0xff, -1, "LF receiver calibration register 47"}, + {"tplf_cal.lfcalr48", 0x09f, 1, 0x3f, -1, "LF receiver calibration register 48"}, + {"tplf_cal.lfcalr49", 0x0a0, 1, 0xff, -1, "LF receiver calibration register 49"}, + {"tplf_cal.lfcalr50", 0x0a1, 1, 0xff, -1, "LF receiver calibration register 50"}, + {"tplf_cal.lfcalr51", 0x0a2, 1, 0xff, -1, "LF receiver calibration register 51"}, + {"tplf_cal.lfcalr52", 0x0a3, 1, 0x3f, -1, "LF receiver calibration register 52"}, + {"tplf_cal.lfcalr53", 0x0a4, 1, 0xff, -1, "LF receiver calibration register 53"}, + {"clk.xfuse", 0x0a5, 1, -1, -1, "XFUSE register"}, + {"clk.mrccal", 0x0a6, 1, 0xfe, -1, "middle RC oscillator calibration register"}, + {"clk.frccal", 0x0a7, 1, 0x1f, -1, "fast RC oscillator calibration register"}, + {"sup.rctcal", 0x0a8, 1, -1, -1, "RC oscillator temperature compensation register"}, + {"clk.cmsr", 0x0a9, 1, -1, -1, "clock management status register"}, + {"clk.cmocr", 0x0aa, 1, -1, -1, "clock management override control register"}, + {"sup.supfr", 0x0ab, 1, -1, -1, "supply interrupt flag register"}, + {"sup.supcr", 0x0ac, 1, -1, -1, "supply control register"}, + {"sup.supca1", 0x0ad, 1, -1, -1, "supply calibration register 1"}, + {"sup.supca2", 0x0ae, 1, -1, -1, "supply calibration register 2"}, + {"sup.supca3", 0x0af, 1, -1, -1, "supply calibration register 3"}, + {"sup.supca4", 0x0b0, 1, -1, -1, "supply calibration register 4"}, + {"sup.calrdy", 0x0b1, 1, 0xff, -1, "calibration ready signature register"}, + {"dfifo.dfs", 0x0b2, 1, -1, -1, "data FIFO status register"}, + {"dfifo.dfl", 0x0b5, 1, -1, -1, "data FIFO fill level register"}, + {"dfifo.dfwp", 0x0b6, 1, 0x3f, -1, "data FIFO write pointer register"}, + {"dfifo.dfrp", 0x0b7, 1, 0x3f, -1, "data FIFO read pointer register"}, + {"dfifo.dfd", 0x0b8, 1, 0xff, -1, "data FIFO data register"}, + {"dfifo.dfi", 0x0b9, 1, -1, -1, "data FIFO interrupt mask register"}, + {"dfifo.dfc", 0x0ba, 1, -1, -1, "data FIFO configuration register"}, + {"sfifo.sfs", 0x0bb, 1, -1, -1, "support FIFO status register"}, + {"sfifo.sfl", 0x0bc, 1, -1, -1, "support FIFO fill level register"}, + {"sfifo.sfwp", 0x0bd, 1, 0x1f, -1, "support FIFO write pointer register"}, + {"sfifo.sfrp", 0x0be, 1, 0x1f, -1, "support FIFO read pointer register"}, + {"sfifo.sfd", 0x0bf, 1, 0xff, -1, "support FIFO data register"}, + {"sfifo.sfi", 0x0c0, 1, -1, -1, "support FIFO interrupt mask register"}, + {"sfifo.sfc", 0x0c1, 1, -1, -1, "support FIFO configuration register"}, + {"ssm.ssmcr", 0x0c2, 1, -1, -1, "sequencer state machine control register"}, + {"timer5.gtccr", 0x0c3, 1, -1, -1, "general T/C control register"}, + {"ssm.ssmfbr", 0x0c4, 1, -1, -1, "sequencer state machine filter bandwidth register"}, + {"ssm.ssmrr", 0x0c5, 1, -1, -1, "sequencer state machine run register"}, + {"ssm.ssmsr", 0x0c6, 1, -1, -1, "sequencer state machine status register"}, + {"ssm.ssmifr", 0x0c7, 1, -1, -1, "sequencer state machine interrupt flag register"}, + {"ssm.ssmimr", 0x0c8, 1, -1, -1, "sequencer state machine interrupt mask register"}, + {"ssm.msmstr", 0x0c9, 1, -1, -1, "master state machine state register"}, + {"ssm.ssmstr", 0x0ca, 1, -1, -1, "sequencer state machine state register"}, + {"vx_mode.vxmctrl", 0x0cb, 1, -1, -1, "VX mode control register"}, + {"ssm.msmcr1", 0x0cc, 1, -1, -1, "master state machine control register 1"}, + {"ssm.msmcr2", 0x0cd, 1, -1, -1, "master state machine control register 2"}, + {"ssm.msmcr3", 0x0ce, 1, -1, -1, "master state machine control register 3"}, + {"ssm.msmcr4", 0x0cf, 1, -1, -1, "master state machine control register 4"}, + {"spi2.sp2cr", 0x0d7, 1, -1, -1, "SPI 2 control register"}, + {"spi2.sp2dr", 0x0d8, 1, 0xff, -1, "SPI 2 data register"}, + {"spi2.sp2sr", 0x0d9, 1, -1, -1, "SPI 2 status register"}, + {"debug.trcid", 0x0dc, 2, 0xffff, -1, "trace ID register (16 bits)"}, + {"debug.trcdr", 0x0df, 1, 0xff, -1, "trace unit data register"}, + {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, + {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, + {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, + {"fe.felna", 0x0e3, 1, 0xff, -1, "reserved register"}, + {"fe.feat", 0x0e4, 1, -1, -1, "front-end antenna tuning register"}, + {"fe.fepac", 0x0e5, 1, -1, -1, "front-end power amplifier control register"}, + {"fe.fevct", 0x0e6, 1, 0x0f, -1, "front-end VCO tuning register"}, + {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, + {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, + {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, + {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, + {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, + {"fe.fealr", 0x0ec, 1, -1, -1, "front-end antenna level detector range register"}, + {"fe.feant", 0x0ed, 1, -1, -1, "front-end antenna register"}, + {"fe.febia", 0x0ee, 1, 0xff, -1, "reserved register"}, + {"clk.clkod", 0x0f5, 1, 0xff, -1, "clock output divider register"}, + {"clk.clkocr", 0x0f6, 1, -1, -1, "clock output control register"}, + {"fe.fete1", 0x0fc, 1, -1, -1, "front-end test enable register 1"}, + {"fe.fete2", 0x0fd, 1, -1, -1, "front-end test enable register 2"}, + {"fe.fete3", 0x0fe, 1, -1, -1, "front-end test enable register 3"}, + {"fe.fetd", 0x0ff, 1, 0xff, -1, "front-end test data register"}, + {"txm.tmfsm", 0x100, 1, -1, -1, "tx modulator finite state machine register"}, + {"txm.tmcrc", 0x101, 2, 0xffff, -1, "tx modulator CRC result register (16 bits)"}, + {"txm.tmcsb", 0x103, 1, 0xff, -1, "tx modulator CRC skip bit number register"}, + {"txm.tmci", 0x104, 2, 0xffff, -1, "tx modulator CRC init value register (16 bits)"}, + {"txm.tmcp", 0x106, 2, 0xffff, -1, "tx modulator CRC polynomial register (16 bits)"}, + {"txm.tmshr", 0x108, 1, 0xff, -1, "tx modulator shift register"}, + {"txm.tmtll", 0x109, 2, 0x0fff, -1, "tx modulator telegram length register (16 bits)"}, + {"txm.tmssc", 0x10b, 1, -1, -1, "tx modulator stop sequence configuration register"}, + {"txm.tmsr", 0x10c, 1, -1, -1, "tx modulator status register"}, + {"txm.tmcr2", 0x10d, 1, -1, -1, "tx modulator control register 2"}, + {"txm.tmcr1", 0x10e, 1, -1, -1, "tx modulator control register 1"}, + {"lf_receiver.lfdsr1", 0x110, 1, -1, -1, "LF decoder setting register 1"}, + {"lf_receiver.lfdsr2", 0x111, 1, -1, -1, "LF decoder setting register 2"}, + {"lf_receiver.lfdsr3", 0x112, 1, -1, -1, "LF decoder setting register 3"}, + {"lf_receiver.lfdsr4", 0x113, 1, -1, -1, "LF decoder setting register 4"}, + {"lf_receiver.lfdsr5", 0x114, 1, -1, -1, "LF decoder setting register 5"}, + {"lf_receiver.lfdsr6", 0x115, 1, -1, -1, "LF decoder setting register 6"}, + {"lf_receiver.lfdsr7", 0x116, 1, -1, -1, "LF decoder setting register 7"}, + {"lf_receiver.lfdsr8", 0x117, 1, -1, -1, "LF decoder setting register 8"}, + {"lf_receiver.lfdsr9", 0x118, 1, -1, -1, "LF decoder setting register 9"}, + {"lf_receiver.lfdsr10", 0x119, 1, -1, -1, "LF decoder setting register 10"}, + {"lf_receiver.lfdsr11", 0x11a, 1, -1, -1, "LF decoder setting register 11"}, + {"eeprom.eepr1", 0x11b, 1, -1, -1, "EEPROM protection register 1"}, + {"eeprom.eepr2", 0x11c, 1, -1, -1, "EEPROM protection register 2"}, + {"eeprom.eepr3", 0x11d, 1, -1, -1, "EEPROM protection register 3"}, + {"crc.crccr", 0x125, 1, -1, -1, "CRC control register"}, + {"crc.crcdor", 0x126, 1, 0xff, -1, "CRC data output register"}, + {"lf_receiver.lfsrctm", 0x131, 1, -1, -1, "LF receiver SRC tuning MSB register"}, + {"debounce.dbcr", 0x132, 1, -1, -1, "debounce control register"}, + {"debounce.dbtc", 0x133, 1, 0xff, -1, "debounce timer compare register"}, + {"debounce.dbenb", 0x134, 1, 0xff, -1, "debounce enable port B register"}, + {"debounce.dbenc", 0x135, 1, 0x07, -1, "debounce enable port C register"}, + {"debug.dbgsw", 0x136, 1, -1, -1, "debugging support switch register"}, + {"spi.sffr", 0x137, 1, -1, -1, "SPI FIFO fill status register"}, + {"spi.sfir", 0x138, 1, -1, -1, "SPI FIFO interrupt register"}, + {"timer2.t2ifr", 0x139, 1, -1, -1, "timer 2 interrupt flag register"}, + {"mem.pgmst", 0x13a, 1, -1, -1, "program memory status register"}, + {"mem.eest", 0x13b, 1, -1, -1, "EEPROM status register"}, + {"lf_receiver.lfsrctl", 0x13c, 1, -1, -1, "LF receiver SRC tuning LSB register"}, + {"int.pcifr", 0x141, 1, -1, -1, "pin change interrupt flag register"}, + {"timer0_wdt.t0cr", 0x142, 1, -1, -1, "timer 0 control register"}, + {"debounce.dbend", 0x144, 1, 0xff, -1, "debounce enable port D register"}, + {"lf_transponder.tpcr1", 0x145, 1, -1, -1, "transponder control register 1"}, + {"lf_transponder.tpimr", 0x146, 1, -1, -1, "transponder interrupt mask register"}, + {"lf_transponder.tpdcr1", 0x147, 1, -1, -1, "transponder decoder comparator register 1"}, + {"lf_transponder.tpdcr2", 0x148, 1, -1, -1, "transponder decoder comparator register 2"}, + {"lf_transponder.tpdcr3", 0x149, 1, -1, -1, "transponder decoder comparator register 3"}, + {"lf_transponder.tpdcr4", 0x14a, 1, -1, -1, "transponder decoder comparator register 4"}, + {"lf_transponder.tpdcr5", 0x14b, 1, -1, -1, "transponder decoder comparator register 5"}, + {"lf_transponder.tpecr1", 0x14c, 1, -1, -1, "transponder encoder comparator register 1"}, + {"lf_transponder.tpecr2", 0x14d, 1, -1, -1, "transponder encoder comparator register 2"}, + {"lf_transponder.tpecr3", 0x14e, 1, -1, -1, "transponder encoder comparator register 3"}, + {"lf_transponder.tpecr4", 0x14f, 1, -1, -1, "transponder encoder comparator register 4"}, + {"lf_transponder.tpecmr", 0x150, 1, -1, -1, "transponder encoder mode register"}, + {"lf_transponder.tpcr3", 0x151, 1, -1, -1, "transponder control register 3"}, + {"lf_transponder.tpcr4", 0x152, 1, -1, -1, "transponder control register 4"}, + {"lf_transponder.tpcr5", 0x153, 1, -1, -1, "transponder control register 5"}, + {"tplf_cal.tpcalr1", 0x155, 1, -1, -1, "transponder calibration register 1"}, + {"tplf_cal.tpcalr2", 0x156, 1, -1, -1, "transponder calibration register 2"}, + {"tplf_cal.tpcalr3", 0x157, 1, -1, -1, "transponder calibration register 3"}, + {"tplf_cal.tpcalr4", 0x158, 1, -1, -1, "transponder calibration register 4"}, + {"tplf_cal.tpcalr5", 0x159, 1, 0x0f, -1, "transponder calibration register 5"}, + {"tplf_cal.tpcalr6", 0x15a, 1, 0x1f, -1, "transponder calibration register 6"}, + {"tplf_cal.tpcalr7", 0x15b, 1, 0x07, -1, "transponder calibration register 7"}, + {"tplf_cal.tpcalr8", 0x15c, 1, 0x7f, -1, "transponder calibration register 8"}, + {"tplf_cal.tpcalr9", 0x15d, 1, 0xff, -1, "transponder calibration register 9"}, + {"tplf_cal.tpcalr10", 0x15e, 1, 0x7f, -1, "transponder calibration register 10"}, + {"aes.aesdpr", 0x15f, 1, 0x0f, -1, "AES data pointer register"}, + {"aes.aeskr", 0x160, 1, 0xff, -1, "AES key register"}, + {"aes.aesdr", 0x161, 1, 0xff, -1, "AES data register"}, + {"gpioregs_lfvcc.gpior3", 0x162, 1, 0xff, -1, "general purpose I/O register 3"}, + {"gpioregs_lfvcc.gpior4", 0x163, 1, 0xff, -1, "general purpose I/O register 4"}, + {"gpioregs_lfvcc.gpior5", 0x164, 1, 0xff, -1, "general purpose I/O register 5"}, + {"gpioregs_lfvcc.gpior6", 0x165, 1, 0xff, -1, "general purpose I/O register 6"}, + {"gpioregs_lfvcc.gpior7", 0x166, 1, 0xff, -1, "general purpose I/O register 7"}, + {"gpioregs_lfvcc.gpior8", 0x167, 1, 0xff, -1, "general purpose I/O register 8"}, + {"lf_protocol_handler.phbcrr", 0x168, 1, 0xff, -1, "protocol handler bit counter read register"}, + {"tplf_cal.lfcpr", 0x16e, 1, -1, -1, "LF receiver calibration protect register"}, + {"lf_receiver.lfimr", 0x16f, 1, -1, -1, "LF interrupt mask register"}, + {"lf_protocol_handler.phid0", 0x170, 4, 0xffffffff, -1, "PH ID 0 register (32 bits)"}, + {"lf_protocol_handler.phid0l", 0x174, 1, 0x3f, -1, "PH identifier 0 length register"}, + {"lf_protocol_handler.phid1", 0x175, 4, 0xffffffff, -1, "PH ID 1 register (32 bits)"}, + {"lf_protocol_handler.phid1l", 0x179, 1, 0x3f, -1, "PH identifier 1 length register"}, + {"lf_protocol_handler.phidfr", 0x17a, 1, 0xff, -1, "protocol handler ID frame register"}, + {"lf_receiver.lfsysy", 0x17b, 4, 0xffffffff, -1, "LF receiver synchronization symbols register (32 bits)"}, + {"lf_receiver.lfsyle", 0x17f, 1, -1, -1, "LF receiver synchronization length register"}, + {"lf_receiver.lfstop", 0x180, 1, -1, -1, "LF receiver stop bit register"}, + {"lf_timer.ltcor", 0x181, 1, 0xff, -1, "LF timer compare register"}, + {"timer1.t1ifr", 0x182, 1, -1, -1, "timer 1 interrupt flag register"}, + {"lf_protocol_handler.phtblr", 0x184, 1, 0xff, -1, "protocol handler telegram bit length register"}, + {"lf_protocol_handler.phdfr", 0x185, 1, 0xff, -1, "protocol handler data frame end register"}, + {"lf_timer.ltemr", 0x186, 1, -1, -1, "LF timer event mask register"}, + {"lf_receiver.lfqc3", 0x187, 1, -1, -1, "LF receiver channel 3 quality factor register"}, + {"lf_receiver.lfqc2", 0x188, 1, -1, -1, "LF receiver channel 2 quality factor register"}, + {"lf_receiver.lfqc1", 0x189, 1, -1, -1, "LF receiver channel 1 quality factor register"}, + {"twi2.tw2br", 0x18a, 1, 0xff, -1, "TWI 2 bit rate register"}, + {"twi2.tw2cr", 0x18b, 1, -1, -1, "TWI 2 control register"}, + {"twi2.tw2sr", 0x18c, 1, -1, -1, "TWI 2 status register"}, + {"twi2.tw2dr", 0x18d, 1, 0xff, -1, "TWI 2 data register"}, + {"twi2.tw2ar", 0x18e, 1, -1, -1, "TWI 2 peripheral address register"}, + {"twi2.tw2amr", 0x18f, 1, -1, -1, "TWI 2 address mask register"}, + {"lf_rssi.rscr", 0x190, 1, -1, -1, "RSSI control register"}, + {"lf_rssi.rssr", 0x191, 1, -1, -1, "RSSI status register"}, + {"lf_rssi.rsms1r", 0x192, 1, -1, -1, "RSSI measurement setting 1 register"}, + {"lf_rssi.rsms2r", 0x193, 1, -1, -1, "RSSI measurement setting 2 register"}, + {"lf_rssi.rsfr", 0x194, 1, -1, -1, "RSSI flag register"}, + {"lf_rssi.rscalib", 0x196, 1, -1, -1, "RSSI calibration register"}, + {"lf_rssi.rsdlyr", 0x197, 1, -1, -1, "RSSI delay register"}, + {"lf_rssi.rsres1l", 0x198, 1, -1, -1, "RSSI result 1 low byte register"}, + {"lf_rssi.rsres1h", 0x199, 1, -1, -1, "RSSI result 1 high byte register"}, + {"lf_rssi.rsres2l", 0x19a, 1, -1, -1, "RSSI result 2 low byte register"}, + {"lf_rssi.rsres2h", 0x19b, 1, -1, -1, "RSSI result 2 high byte register"}, + {"lf_rssi.rsres3l", 0x19c, 1, -1, -1, "RSSI result 3 low byte register"}, + {"lf_rssi.rsres3h", 0x19d, 1, -1, -1, "RSSI result 3 high byte register"}, + {"lf_rssi.rsres4l", 0x19e, 1, -1, -1, "RSSI result 4 low byte register"}, + {"lf_rssi.rsres4h", 0x19f, 1, -1, -1, "RSSI result 4 high byte register"}, + {"lf_rssi.rssrcr", 0x1a0, 1, -1, -1, "RSSI SRC calibration register"}, + {"lf_rssi.sd12rr", 0x1a1, 1, -1, -1, "sign detection channel 1 vs 2 result register"}, + {"lf_rssi.sd13rr", 0x1a2, 1, -1, -1, "sign detection channel 1 vs 3 result register"}, + {"lf_rssi.sd23rr", 0x1a3, 1, -1, -1, "sign detection channel 2 vs 3 result register"}, + {"lf_rssi.sd360r", 0x1a4, 1, -1, -1, "sign detection 360 degree result register"}, + {"lf_rssi.rsdbgr", 0x1a5, 1, -1, -1, "RSSI debug register"}, + {"lf_fifo.ldfs", 0x1b1, 1, -1, -1, "LF data FIFO status register"}, + {"timer4.t4ifr", 0x1b2, 1, -1, -1, "timer 4 interrupt flag register"}, + {"lf_fifo.ldfwp", 0x1b3, 1, -1, -1, "LF data FIFO write pointer register"}, + {"lf_fifo.ldfrp", 0x1b4, 1, -1, -1, "LF data FIFO read pointer register"}, + {"timer5.t5ifr", 0x1b5, 1, -1, -1, "timer 5 interrupt flag register"}, + {"lf_fifo.ldfim", 0x1b6, 1, -1, -1, "LF data FIFO interrupt mask register"}, + {"lf_fifo.ldfc", 0x1b7, 1, -1, -1, "LF data FIFO configuration register"}, + {"lf_protocol_handler.phimr", 0x1b8, 1, -1, -1, "protocol handler interrupt mask register"}, + {"lf_protocol_handler.phcrcr", 0x1b9, 1, -1, -1, "protocol handler CRC control register"}, + {"lf_protocol_handler.phcst", 0x1ba, 2, 0xffff, -1, "PH CRC start value register (16 bits)"}, + {"lf_protocol_handler.phcrp", 0x1bc, 2, 0xffff, -1, "PH CRC polynomial register (16 bits)"}, + {"lf_protocol_handler.phcsr", 0x1be, 2, 0xffff, -1, "PH CRC checksum register (16 bits)"}, + {"crc.crcdir", 0x1c0, 1, 0xff, -1, "CRC data input register"}, + {"timer3.t3ifr", 0x1c1, 1, -1, -1, "timer 3 interrupt flag register"}, + {"cpu.cmcr", 0x1c3, 1, -1, -1, "clock management control register"}, + {"cpu.cmimr", 0x1c4, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clpr", 0x1c5, 1, -1, -1, "clock prescaler register"}, + {"sup.vmcr", 0x1c6, 1, -1, -1, "voltage monitor control register"}, + {"debug.dbondr", 0x1c7, 1, -1, -1, "downbond test register"}, + {"sup.calrdylf", 0x1c8, 1, 0xff, -1, "calibration ready signature LFVCC register"}, + {"twi1.tw1br", 0x1c9, 1, 0xff, -1, "TWI 1 bit rate register"}, + {"twi1.tw1cr", 0x1ca, 1, -1, -1, "TWI 1 control register"}, + {"twi1.tw1sr", 0x1cb, 1, -1, -1, "TWI 1 status register"}, + {"twi1.tw1dr", 0x1cc, 1, 0xff, -1, "TWI 1 data register"}, + {"twi1.tw1ar", 0x1cd, 1, -1, -1, "TWI 1 peripheral address register"}, + {"twi1.tw1amr", 0x1ce, 1, -1, -1, "TWI 1 address mask register"}, + {"led.pdscr", 0x1cf, 1, -1, -1, "pad driver strength control register"}, + {"tmo.tmocr", 0x1d0, 1, -1, -1, "timer modulator output control register"}, + {"tplf_cal.srccal", 0x1d1, 1, -1, -1, "slow RC oscillator calibration register"}, + {"tplf_cal.srctcal", 0x1d2, 1, -1, -1, "slow RC oscillator temperature compensation register"}, + {"sup.supca5", 0x1d3, 1, -1, -1, "supply calibration register 5"}, + {"sup.supca6", 0x1d4, 1, -1, -1, "supply calibration register 6"}, + {"sup.supca7", 0x1d5, 1, -1, -1, "supply calibration register 7"}, + {"sup.supca8", 0x1d6, 1, -1, -1, "supply calibration register 8"}, + {"sup.supca9", 0x1d7, 1, -1, -1, "supply calibration register 9"}, + {"sup.supca10", 0x1d8, 1, 0x1f, -1, "supply calibration register 10"}, + {"tplf_cal.tpcalr11", 0x1d9, 1, -1, -1, "transponder calibration register 11"}, + {"tplf_cal.tpcalr12", 0x1da, 1, -1, -1, "transponder calibration register 12"}, + {"tplf_cal.tpcalr13", 0x1db, 1, 0xff, -1, "transponder calibration register 13"}, + {"sup.pmter", 0x1de, 1, 0xff, -1, "power management test enable register"}, + {"tplf_cal.srccall", 0x1df, 1, -1, -1, "slow RC oscillator calibration register low byte"}, +}; + // ATA5781 ATA5782 ATA5783 ATA8210 ATA8215 const Register_file rgftab_ata5781[262] = { // I/O memory [0, 479] + 32 {"clk.prr0", 0x001, 1, -1, -1, "power reduction register 0"}, @@ -16022,12827 +25280,6 @@ const Register_file rgftab_ata5781[262] = { // I/O memory [0, 479] + 32 {"rssib.rscom", 0x13f, 1, -1, -1, "RSSI compensation register"}, }; -// ATA5790 -const Register_file rgftab_ata5790[112] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"afe.tpcr", 0x0d, 1, -1, -1, "transponder control register"}, - {"afe.tpfr", 0x0e, 1, -1, -1, "transponder status and flag register"}, - {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, - {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, - {"timer_counter_2.t2cr", 0x11, 1, -1, -1, "timer 2 control register"}, - {"timer_counter_3.t3cr", 0x12, 1, -1, -1, "timer 3 control register"}, - {"aes.aescr", 0x13, 1, -1, -1, "AES control register"}, - {"aes.aessr", 0x14, 1, -1, -1, "AES status register"}, - {"mod.tmifr", 0x15, 1, -1, -1, "timer modulator interrupt flag register"}, - {"cpu.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, - {"vmon.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, - {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, - {"dddlfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, - {"timer_counter_0.t0ifr", 0x19, 1, -1, -1, "timer 0 interrupt flag register"}, - {"timer_counter_1.t1ifr", 0x1a, 1, -1, -1, "timer 1 interrupt flag register"}, - {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, - {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, - {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, - {"cpu.gpior", 0x1e, 1, 0xff, -1, "general purpose I/O register"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"eeprom.eepr", 0x23, 1, -1, -1, "EEPROM protection register"}, - {"eeprom.eeccr", 0x24, 1, -1, -1, "EEPROM error correction code register"}, - {"external_interrupt.pcicr", 0x26, 1, -1, -1, "pin change interrupt control register"}, - {"external_interrupt.eimsk", 0x27, 1, -1, -1, "external interrupt mask register"}, - {"mod.tmdr", 0x28, 1, 0xff, -1, "timer modulator data register"}, - {"aes.aesdr", 0x29, 1, 0xff, -1, "AES data register"}, - {"aes.aeskr", 0x2a, 1, -1, -1, "AES key register"}, - {"cpu.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, - {"vmon.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"dddlfrx.lfcr0", 0x2f, 1, -1, -1, "LF receiver control register 0"}, - {"dddlfrx.lfcr1", 0x30, 1, -1, -1, "LF receiver control register 1"}, - {"dddlfrx.lfrdb", 0x32, 1, 0xff, -1, "LF receiver data buffer register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"dddlfrx.lfsr", 0x36, 1, -1, -1, "LF status register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, - {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, - {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, - {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.prr0", 0x43, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x44, 1, -1, -1, "power reduction register 1"}, - {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, - {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, - {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, - {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, - {"irled.ldcr", 0x4d, 1, -1, -1, "LED driver control register"}, - {"timer_counter_2.t2cnt", 0x50, 1, 0xff, -1, "timer 2 counter"}, - {"timer_counter_2.t2cor", 0x51, 1, 0xff, -1, "timer 2 compare register"}, - {"timer_counter_2.t2mr", 0x53, 1, -1, -1, "timer 2 mode register"}, - {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, - {"timer_counter_3.t3cnt", 0x56, 1, 0xff, -1, "timer 3 counter"}, - {"timer_counter_3.t3cor", 0x57, 1, 0xff, -1, "timer 3 compare register"}, - {"timer_counter_3.t3icr", 0x58, 1, 0xff, -1, "timer 3 input capture register"}, - {"timer_counter_3.t3mra", 0x59, 1, -1, -1, "timer 3 mode register A"}, - {"timer_counter_3.t3mrb", 0x5a, 1, -1, -1, "timer 3 mode register B"}, - {"timer_counter_3.t3imr", 0x5b, 1, -1, -1, "timer 3 interrupt mask register"}, - {"mod.tmcr", 0x5d, 1, -1, -1, "timer modulator control register"}, - {"mod.tmmr", 0x5e, 1, -1, -1, "timer modulator mode register"}, - {"mod.tmimr", 0x5f, 1, -1, -1, "timer modulator interrupt mask register"}, - {"dddlfrx.lfimr", 0x62, 1, -1, -1, "LF interrupt mask register"}, - {"dddlfrx.lfcad", 0x63, 1, 0xff, -1, "LF clock adjustment data register"}, - {"dddlfrx.lfid00", 0x64, 1, 0xff, -1, "LF ID 0 data register byte 0"}, - {"dddlfrx.lfid01", 0x65, 1, 0xff, -1, "LF ID 0 data register byte 1"}, - {"dddlfrx.lfid02", 0x66, 1, 0xff, -1, "LF ID 0 data register byte 2"}, - {"dddlfrx.lfid03", 0x67, 1, 0xff, -1, "LF ID 0 data register byte 3"}, - {"dddlfrx.lfid10", 0x68, 1, 0xff, -1, "LF ID 1 data register byte 0"}, - {"dddlfrx.lfid11", 0x69, 1, 0xff, -1, "LF ID 1 data register byte 1"}, - {"dddlfrx.lfid12", 0x6a, 1, 0xff, -1, "LF ID 1 data register byte 2"}, - {"dddlfrx.lfid13", 0x6b, 1, 0xff, -1, "LF ID 1 data register byte 3"}, - {"dddlfrx.lfrd0", 0x6c, 1, 0xff, -1, "LF receive data register byte 0"}, - {"dddlfrx.lfrd1", 0x6d, 1, 0xff, -1, "LF receive data register byte 1"}, - {"dddlfrx.lfrd2", 0x6e, 1, 0xff, -1, "LF receive data register byte 2"}, - {"dddlfrx.lfrd3", 0x6f, 1, 0xff, -1, "LF receive data register byte 3"}, - {"dddlfrx.lfid0m", 0x70, 1, -1, -1, "LF identifier 0 mask register"}, - {"dddlfrx.lfid1m", 0x71, 1, -1, -1, "LF identifier 1 mask register"}, - {"dddlfrx.lfrdf", 0x72, 1, -1, -1, "LF receive data frame register"}, - {"dddlfrx.lfrsd1", 0x73, 1, 0xff, -1, "LF RSSI data register 1"}, - {"dddlfrx.lfrsd2", 0x74, 1, 0xff, -1, "LF RSSI data register 2"}, - {"dddlfrx.lfrsd3", 0x75, 1, 0xff, -1, "LF RSSI data register 3"}, - {"dddlfrx.lfcc1", 0x76, 1, 0x0f, -1, "LF channel capacity select register 1"}, - {"dddlfrx.lfcc2", 0x77, 1, 0x0f, -1, "LF channel capacity select register 2"}, - {"dddlfrx.lfcc3", 0x78, 1, 0x0f, -1, "LF channel capacity select register 3"}, - {"afe.tpimr", 0x7c, 1, -1, -1, "transponder interrupt mask register"}, - {"rtc_timer.rtccr", 0x7e, 1, -1, -1, "real-time clock control register"}, - {"rtc_timer.rtcdr", 0x7f, 1, 0xff, -1, "real time clock data register"}, - {"mod.tmmdr", 0x88, 1, 0x0f, -1, "timer modulator manchester data register"}, - {"mod.tmbdr", 0x89, 1, 0x0f, -1, "timer modulator biphase data register"}, - {"mod.tmtdr", 0x8a, 1, 0xff, -1, "timer modulator transmit data register"}, - {"mod.tmsr", 0x8b, 1, 0xff, -1, "timer modulator shift register"}, - {"crc.crcdr", 0x8d, 1, 0xff, -1, "CRC data register"}, - {"crc.crccr", 0x8e, 1, -1, -1, "CRC control register"}, - {"crc.crcsr", 0x8f, 1, -1, -1, "CRC status register"}, -}; - -// ATA6285 ATA6286 -const Register_file rgftab_ata6285[79] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x07, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x07, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x07, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, - {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, - {"timer_counter_2.t2cra", 0x11, 1, -1, -1, "timer 2 control register A"}, - {"timer_counter_2.t2crb", 0x12, 1, -1, -1, "timer 2 control register B"}, - {"timer_counter_3.t3cra", 0x14, 1, -1, -1, "timer 3 control register A"}, - {"cpu.vmcsr", 0x16, 1, -1, -1, "voltage monitor control and status register"}, - {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, - {"lfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, - {"sensor_interface.ssfr", 0x19, 1, -1, -1, "sensor status + flag register"}, - {"timer_counter_0.t10ifr", 0x1a, 1, -1, -1, "timer1/0 interrupt flag register"}, - {"timer_counter_1.t10ifr", 0x1a, 1, -1, -1, "timer1/0 interrupt flag register"}, - {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, - {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, - {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"external_interrupt.pcicr", 0x23, 1, -1, -1, "pin change interrupt control register"}, - {"external_interrupt.eimsk", 0x24, 1, -1, -1, "external interrupt mask register"}, - {"sensor_interface.svcr", 0x27, 1, 0x1f, -1, "sensor voltage control register"}, - {"sensor_interface.scr", 0x28, 1, -1, -1, "sensor control register"}, - {"sensor_interface.sccr", 0x29, 1, -1, -1, "sensor capacitor control register"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"timer_counter_2.t2mdr", 0x2f, 1, 0xff, -1, "timer 2 modulator data register"}, - {"lfrx.lfrr", 0x30, 1, 0x7f, -1, "LF RSSI data register"}, - {"lfrx.lfcdr", 0x32, 1, -1, -1, "LF receiver control und data register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"lfrx.lfrb", 0x36, 1, 0xff, -1, "LF receiver data buffer register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, - {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, - {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, - {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"sensor_interface.simsk", 0x41, 1, -1, -1, "sensor interrupt mask register"}, - {"sensor_interface.tscr", 0x44, 1, -1, -1, "temperature sensor control register"}, - {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, - {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, - {"sensor_interface.msvcal", 0x47, 1, 0xff, -1, "motion sensor voltage calibration register"}, - {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, - {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, - {"external_interrupt.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, - {"timer_counter_2.t2icrl", 0x4e, 1, 0xff, -1, "timer 2 input capture register low byte"}, - {"timer_counter_2.t2icr", 0x4f, 1, 0xff, -1, "timer 2 input capture register high byte"}, - {"timer_counter_2.t2cor", 0x50, 2, 0xffff, -1, "timer 2 compare register (16 bits)"}, - {"timer_counter_2.t2mra", 0x52, 1, -1, -1, "timer 2 mode register A"}, - {"timer_counter_2.t2mrb", 0x53, 1, -1, -1, "timer 2 mode register B"}, - {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, - {"timer_counter_3.t3icr", 0x56, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, - {"timer_counter_3.t3cora", 0x58, 2, 0xffff, -1, "timer 3 compare register A (16 bits)"}, - {"timer_counter_3.t3corb", 0x5a, 2, 0xffff, -1, "timer 3 compare register B (16 bits)"}, - {"timer_counter_3.t3mra", 0x5c, 1, -1, -1, "timer 3 mode register A"}, - {"timer_counter_3.t3mrb", 0x5d, 1, -1, -1, "timer 3 mode register B"}, - {"timer_counter_3.t3crb", 0x5e, 1, -1, -1, "timer 3 control register B"}, - {"timer_counter_3.t3imr", 0x5f, 1, -1, -1, "timer 3 interrupt mask register"}, - {"lfrx.lfimr", 0x61, 1, -1, -1, "LF interrupt mask register"}, - {"lfrx.lfrcr", 0x62, 1, -1, -1, "LF receiver control register"}, - {"lfrx.lfhcr", 0x63, 1, 0x7f, -1, "LF header compare register"}, - {"lfrx.lfidc", 0x64, 2, 0xffff, -1, "LF ID compare register (16 bits)"}, - {"lfrx.lfcal", 0x66, 2, 0xffff, -1, "LF calibration register (16 bits)"}, -}; - -// ATxmega16E5 ATxmega8E5 ATxmega32E5 -const Register_file rgftab_atxmega16e5[438] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"osc.rc8mcal", 0x057, 1, -1, -1, "internal 8 MHz RC oscillator calibration register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.wexlock", 0x099, 1, -1, -1, "WEX lock register"}, - {"mcu.faultlock", 0x09a, 1, -1, -1, "FAULT lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.clkout", 0x0b4, 1, -1, -1, "clock out register"}, - {"portcfg.acevout", 0x0b6, 1, -1, -1, "analog comparator and event out register"}, - {"portcfg.srlctrl", 0x0b7, 1, -1, -1, "slew rate limit control register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"edma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"edma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"edma.status", 0x104, 1, -1, -1, "status register"}, - {"edma.temp", 0x106, 1, -1, -1, "temporary register for 16-bit access"}, - {"edma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"edma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"edma.ch0.addrctrl", 0x112, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, - {"edma.ch0.destaddrctrl", 0x113, 1, -1, -1, "destination address control register for standard channels only"}, - {"edma.ch0.trigsrc", 0x114, 1, -1, -1, "channel trigger source register"}, - {"edma.ch0.trfcnt", 0x116, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, - {"edma.ch0.addr", 0x118, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, - {"edma.ch0.destaddr", 0x11c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, - {"edma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"edma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"edma.ch1.addrctrl", 0x122, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, - {"edma.ch1.destaddrctrl", 0x123, 1, -1, -1, "destination address control register for standard channels only"}, - {"edma.ch1.trigsrc", 0x124, 1, -1, -1, "channel trigger source register"}, - {"edma.ch1.trfcnt", 0x126, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, - {"edma.ch1.addr", 0x128, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, - {"edma.ch1.destaddr", 0x12c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, - {"edma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"edma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"edma.ch2.addrctrl", 0x132, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, - {"edma.ch2.destaddrctrl", 0x133, 1, -1, -1, "destination address control register for standard channels only"}, - {"edma.ch2.trigsrc", 0x134, 1, -1, -1, "channel trigger source register"}, - {"edma.ch2.trfcnt", 0x136, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, - {"edma.ch2.addr", 0x138, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, - {"edma.ch2.destaddr", 0x13c, 2, -1, -1, "channel destination address for standard channels only register (16 bits)"}, - {"edma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"edma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"edma.ch3.addrctrl", 0x142, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, - {"edma.ch3.destaddrctrl", 0x143, 1, -1, -1, "destination address control register for standard channels only"}, - {"edma.ch3.trigsrc", 0x144, 1, -1, -1, "channel trigger source register"}, - {"edma.ch3.trfcnt", 0x146, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, - {"edma.ch3.addr", 0x148, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, - {"edma.ch3.destaddr", 0x14c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"evsys.dfctrl", 0x192, 1, -1, -1, "digital filter control register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, - {"adca.cal", 0x20c, 1, -1, -1, "calibration register"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"adc.ch0.corrctrl", 0x227, 1, -1, -1, "correction control register"}, - {"adc.ch0.offsetcorr0", 0x228, 1, -1, -1, "offset correction register 0"}, - {"adc.ch0.offsetcorr1", 0x229, 1, -1, -1, "offset correction register 1"}, - {"adc.ch0.gaincorr0", 0x22a, 1, -1, -1, "gain correction register 0"}, - {"adc.ch0.gaincorr1", 0x22b, 1, -1, -1, "gain correction register 1"}, - {"adc.ch0.avgctrl", 0x22c, 1, -1, -1, "average control register"}, - {"daca.ctrla", 0x300, 1, -1, -1, "control register A"}, - {"daca.ctrlb", 0x301, 1, -1, -1, "control register B"}, - {"daca.ctrlc", 0x302, 1, -1, -1, "control register C"}, - {"daca.evctrl", 0x303, 1, -1, -1, "event control register"}, - {"daca.status", 0x305, 1, -1, -1, "status register"}, - {"daca.ch0gaincal", 0x308, 1, -1, -1, "gain calibration register"}, - {"daca.ch0offsetcal", 0x309, 1, -1, -1, "offset calibration register"}, - {"daca.ch1gaincal", 0x30a, 1, -1, -1, "gain calibration register"}, - {"daca.ch1offsetcal", 0x30b, 1, -1, -1, "offset calibration register"}, - {"daca.ch0data", 0x318, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"daca.ch1data", 0x31a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, - {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.calib", 0x406, 1, -1, -1, "calibration register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"xcl.ctrla", 0x460, 1, -1, -1, "control register A"}, - {"xcl.ctrlb", 0x461, 1, -1, -1, "control register B"}, - {"xcl.ctrlc", 0x462, 1, -1, -1, "control register C"}, - {"xcl.ctrld", 0x463, 1, -1, -1, "control register D"}, - {"xcl.ctrle", 0x464, 1, -1, -1, "control register E"}, - {"xcl.ctrlf", 0x465, 1, -1, -1, "control register F"}, - {"xcl.ctrlg", 0x466, 1, -1, -1, "control register G"}, - {"xcl.intctrl", 0x467, 1, -1, -1, "interrupt control register"}, - {"xcl.intflags", 0x468, 1, -1, -1, "interrupt flags register"}, - {"xcl.plc", 0x469, 1, -1, -1, "peripheral length control register"}, - {"xcl.cntl", 0x46a, 1, -1, -1, "counter low byte"}, - {"xcl.cnth", 0x46b, 1, -1, -1, "counter high byte"}, - {"xcl.cmpl", 0x46c, 1, -1, -1, "compare register low byte"}, - {"xcl.cmph", 0x46d, 1, -1, -1, "compare register high byte"}, - {"xcl.percaptl", 0x46e, 1, -1, -1, "period or capture register low byte"}, - {"xcl.percapth", 0x46f, 1, -1, -1, "period or capture register high byte"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x481, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x482, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x483, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x484, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x485, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x486, 1, -1, -1, "address register"}, - {"twi.host.data", 0x487, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x488, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x489, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x48a, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x48b, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x48c, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x48d, 1, -1, -1, "address mask register"}, - {"twi.timeout.tos", 0x48e, 1, -1, -1, "timeout status register"}, - {"twi.timeout.toconf", 0x48f, 1, -1, -1, "timeout configuration register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.intmask", 0x60a, 1, -1, -1, "port interrupt mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.intmask", 0x64a, 1, -1, -1, "port interrupt mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.intmask", 0x66a, 1, -1, -1, "port interrupt mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.intmask", 0x7ea, 1, -1, -1, "port interrupt mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc4.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc4.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc4.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc4.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc4.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc4.ctrlf", 0x805, 1, -1, -1, "control register F"}, - {"tcc4.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc4.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc4.ctrlgclr", 0x808, 1, -1, -1, "control register G clear"}, - {"tcc4.ctrlgset", 0x809, 1, -1, -1, "control register G set"}, - {"tcc4.ctrlhclr", 0x80a, 1, -1, -1, "control register H clear"}, - {"tcc4.ctrlhset", 0x80b, 1, -1, -1, "control register H set"}, - {"tcc4.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc4.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc4.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc4.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc4.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc4.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc4.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc4.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc4.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc4.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc4.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc4.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc4.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc5.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc5.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc5.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc5.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc5.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc5.ctrlf", 0x845, 1, -1, -1, "control register F"}, - {"tcc5.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc5.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc5.ctrlgclr", 0x848, 1, -1, -1, "control register G clear"}, - {"tcc5.ctrlgset", 0x849, 1, -1, -1, "control register G set"}, - {"tcc5.ctrlhclr", 0x84a, 1, -1, -1, "control register H clear"}, - {"tcc5.ctrlhset", 0x84b, 1, -1, -1, "control register H set"}, - {"tcc5.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc5.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc5.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc5.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc5.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc5.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc5.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc5.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc5.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"faultc4.ctrla", 0x880, 1, -1, -1, "control register A"}, - {"faultc4.ctrlb", 0x881, 1, -1, -1, "control register B"}, - {"faultc4.ctrlc", 0x882, 1, -1, -1, "control register C"}, - {"faultc4.ctrld", 0x883, 1, -1, -1, "control register D"}, - {"faultc4.ctrle", 0x884, 1, -1, -1, "control register E"}, - {"faultc4.status", 0x885, 1, -1, -1, "status register"}, - {"faultc4.ctrlgclr", 0x886, 1, -1, -1, "control register G clear"}, - {"faultc4.ctrlgset", 0x887, 1, -1, -1, "control register G set"}, - {"faultc5.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"faultc5.ctrlb", 0x891, 1, -1, -1, "control register B"}, - {"faultc5.ctrlc", 0x892, 1, -1, -1, "control register C"}, - {"faultc5.ctrld", 0x893, 1, -1, -1, "control register D"}, - {"faultc5.ctrle", 0x894, 1, -1, -1, "control register E"}, - {"faultc5.status", 0x895, 1, -1, -1, "status register"}, - {"faultc5.ctrlgclr", 0x896, 1, -1, -1, "control register G clear"}, - {"faultc5.ctrlgset", 0x897, 1, -1, -1, "control register G set"}, - {"wexc.ctrl", 0x8a0, 1, -1, -1, "control register"}, - {"wexc.dtboth", 0x8a1, 1, -1, -1, "dead-time both sides register"}, - {"wexc.dtls", 0x8a2, 1, -1, -1, "dead-time low side register"}, - {"wexc.dths", 0x8a3, 1, -1, -1, "dead-time high side register"}, - {"wexc.statusclr", 0x8a4, 1, -1, -1, "status clear register"}, - {"wexc.statusset", 0x8a5, 1, -1, -1, "status set register"}, - {"wexc.swap", 0x8a6, 1, -1, -1, "swap register"}, - {"wexc.pgo", 0x8a7, 1, -1, -1, "pattern generation override register"}, - {"wexc.pgv", 0x8a8, 1, -1, -1, "pattern generation value register"}, - {"wexc.swapbuf", 0x8aa, 1, -1, -1, "dead time low side buffer register"}, - {"wexc.pgobuf", 0x8ab, 1, -1, -1, "pattern generation overwrite buffer register"}, - {"wexc.pgvbuf", 0x8ac, 1, -1, -1, "pattern generation value buffer register"}, - {"wexc.outovdis", 0x8af, 1, -1, -1, "output override disable register"}, - {"hiresc.ctrla", 0x8b0, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8c0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8c1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8c2, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8c3, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8c4, 1, -1, -1, "control register C"}, - {"usartc0.ctrld", 0x8c5, 1, -1, -1, "control register D"}, - {"usartc0.baudctrla", 0x8c6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8c7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8e0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8e1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8e2, 1, -1, -1, "status register"}, - {"spic.data", 0x8e3, 1, -1, -1, "data register"}, - {"spic.ctrlb", 0x8e4, 1, -1, -1, "control register B"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd5.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd5.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd5.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd5.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd5.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd5.ctrlf", 0x945, 1, -1, -1, "control register F"}, - {"tcd5.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd5.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd5.ctrlgclr", 0x948, 1, -1, -1, "control register G clear"}, - {"tcd5.ctrlgset", 0x949, 1, -1, -1, "control register G set"}, - {"tcd5.ctrlhclr", 0x94a, 1, -1, -1, "control register H clear"}, - {"tcd5.ctrlhset", 0x94b, 1, -1, -1, "control register H set"}, - {"tcd5.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd5.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd5.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd5.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd5.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd5.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd5.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd5.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd5.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"usartd0.data", 0x9c0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9c1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9c2, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9c3, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9c4, 1, -1, -1, "control register C"}, - {"usartd0.ctrld", 0x9c5, 1, -1, -1, "control register D"}, - {"usartd0.baudctrla", 0x9c6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9c7, 1, -1, -1, "baud rate control register B"}, -}; - -// ATxmega128A3 ATxmega64A3 ATxmega192A3 ATxmega256A3 -const Register_file rgftab_atxmega128a3[680] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, - {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, - {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, - {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, - {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, - {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, - {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, - {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, - {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, - {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, - {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, - {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, - {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, - {"acb.status", 0x397, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, - {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, - {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, - {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, - {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, - {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, - {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, - {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, - {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, - {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, - {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, - {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, - {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, - {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, - {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, - {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, - {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, - {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, - {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, - {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, - {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, - {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, - {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, - {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, - {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, - {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, - {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, - {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, - {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, - {"awexe.status", 0xa84, 1, -1, -1, "status register"}, - {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, - {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, - {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, - {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, - {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, - {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, - {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, - {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, - {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, - {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, - {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, - {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, - {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, - {"spie.status", 0xac2, 1, -1, -1, "status register"}, - {"spie.data", 0xac3, 1, -1, -1, "data register"}, - {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, - {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, - {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, - {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, - {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, - {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, - {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, - {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, - {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, - {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, - {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, - {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, - {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, - {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, - {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, - {"usartf1.data", 0xbb0, 1, -1, -1, "data register"}, - {"usartf1.status", 0xbb1, 1, -1, -1, "status register"}, - {"usartf1.ctrla", 0xbb3, 1, -1, -1, "control register A"}, - {"usartf1.ctrlb", 0xbb4, 1, -1, -1, "control register B"}, - {"usartf1.ctrlc", 0xbb5, 1, -1, -1, "control register C"}, - {"usartf1.baudctrla", 0xbb6, 1, -1, -1, "baud rate control register A"}, - {"usartf1.baudctrlb", 0xbb7, 1, -1, -1, "baud rate control register B"}, - {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, - {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, - {"spif.status", 0xbc2, 1, -1, -1, "status register"}, - {"spif.data", 0xbc3, 1, -1, -1, "data register"}, -}; - -// ATxmega128A3U ATxmega64A3U ATxmega192A3U ATxmega256A3U -const Register_file rgftab_atxmega128a3u[792] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, - {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, - {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, - {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, - {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, - {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, - {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, - {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, - {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, - {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, - {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, - {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, - {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, - {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, - {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, - {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, - {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, - {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, - {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, - {"acb.status", 0x397, 1, -1, -1, "status register"}, - {"acb.currctrl", 0x398, 1, -1, -1, "current source control register"}, - {"acb.currcalib", 0x399, 1, -1, -1, "current source calibration register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, - {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, - {"usb.status", 0x4c2, 1, -1, -1, "status register"}, - {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, - {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, - {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, - {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, - {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, - {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, - {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, - {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, - {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, - {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, - {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, - {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, - {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, - {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, - {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, - {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, - {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, - {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, - {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, - {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, - {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, - {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, - {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, - {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, - {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, - {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, - {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, - {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, - {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, - {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, - {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, - {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, - {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, - {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, - {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, - {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, - {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, - {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, - {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, - {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, - {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, - {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, - {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, - {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, - {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, - {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, - {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, - {"awexe.status", 0xa84, 1, -1, -1, "status register"}, - {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, - {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, - {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, - {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, - {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, - {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, - {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, - {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, - {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, - {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, - {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, - {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, - {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, - {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, - {"spie.status", 0xac2, 1, -1, -1, "status register"}, - {"spie.data", 0xac3, 1, -1, -1, "data register"}, - {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, - {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, - {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, - {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, - {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, - {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, - {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, - {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, - {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, - {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, - {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, - {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, - {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, - {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, - {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, - {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, - {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, - {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, - {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, - {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, - {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, - {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, - {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, - {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, - {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, - {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, - {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, - {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, -}; - -// ATtiny204 ATtiny404 -const Register_file rgftab_attiny204[235] = { // I/O memory [0, 4351] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, - {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, - {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, - {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, - {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, - {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, - {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, - {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, - {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, - {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, - {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, - {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, - {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, - {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, - {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, - {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, - {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, - {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, - {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, - {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, - {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, - {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, - {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, - {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, - {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, - {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, - {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, - {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, - {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, - {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, - {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, - {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, - {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, - {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, - {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, - {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, - {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, - {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0824, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, -1, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, -}; - -// ATtiny1624 ATtiny424 ATtiny824 ATtiny3224 -const Register_file rgftab_attiny1624[307] = { // I/O memory [0, 4351] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, - {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, - {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, - {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, - {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, - {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, - {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, - {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"evsys.sweventa", 0x0180, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x01a8, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, - {"evsys.userusart0irda", 0x01ac, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x01ad, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x01ae, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x01af, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x01b0, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x01b1, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x01b2, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x01b3, 1, -1, 0x00, "user TCB 1 event register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e3, 1, -1, 0x00, "SPI route A register"}, - {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, - {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, - {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, - {"adc0.result", 0x0610, 4, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x0614, 2, -1, -1, "sample register (16 bits)"}, - {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, - {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, - {"adc0.temp2", 0x061a, 1, -1, -1, "temporary data register 2"}, - {"adc0.winlt", 0x061c, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x061e, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, - {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, - {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, - {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, - {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, - {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, - {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x08c2, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, -}; - -// AVR32DD14 AVR16DD14 AVR64DD14 -const Register_file rgftab_avr32dd14[390] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, - {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, - {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR64EA48 AVR16EA48 AVR32EA48 -const Register_file rgftab_avr64ea48[502] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, 0x00, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, 0x00, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, 0x00, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vporte.dir", 0x0010, 1, -1, 0x00, "data direction register"}, - {"vporte.out", 0x0011, 1, -1, 0x00, "I/O port output register"}, - {"vporte.in", 0x0012, 1, -1, 0x00, "I/O port input register"}, - {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutb", 0x022a, 1, -1, 0x00, "user EVOUT port B register"}, - {"evsys.userevsysevoutc", 0x022b, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022c, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoute", 0x022d, 1, -1, 0x00, "user EVOUT port E register"}, - {"evsys.userevsysevoutf", 0x022e, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022f, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0230, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0231, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x0232, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0233, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertca1cnta", 0x0234, 1, -1, 0x00, "user TCA 1 event A register"}, - {"evsys.usertca1cntb", 0x0235, 1, -1, 0x00, "user TCA 1 event B register"}, - {"evsys.usertcb0capt", 0x0236, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0237, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0238, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0239, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x023a, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x023b, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x023c, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x023d, 1, -1, 0x00, "user TCB 3 event register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portb.dir", 0x0420, 1, -1, 0x00, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, 0x00, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, 0x00, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, 0x00, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, 0x00, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, 0x00, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, 0x00, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, 0x00, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, 0x00, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, - {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, - {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, - {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, - {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portb.evgenctrla", 0x0438, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"porte.dir", 0x0480, 1, -1, 0x00, "data direction register"}, - {"porte.dirset", 0x0481, 1, -1, 0x00, "data direction set register"}, - {"porte.dirclr", 0x0482, 1, -1, 0x00, "data direction clear register"}, - {"porte.dirtgl", 0x0483, 1, -1, 0x00, "data direction toggle register"}, - {"porte.out", 0x0484, 1, -1, 0x00, "I/O port output register"}, - {"porte.outset", 0x0485, 1, -1, 0x00, "I/O port output set register"}, - {"porte.outclr", 0x0486, 1, -1, 0x00, "I/O port output clear register"}, - {"porte.outtgl", 0x0487, 1, -1, 0x00, "I/O port output toggle register"}, - {"porte.in", 0x0488, 1, -1, 0x00, "I/O port input register"}, - {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, - {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, - {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, - {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, - {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, - {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, - {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, - {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, - {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, - {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, - {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, - {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, - {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, - {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, - {"porte.evgenctrla", 0x0498, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, - {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, - {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, - {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, - {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, - {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, - {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, - {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, - {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, - {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, - {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, - {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, - {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, - {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, - {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, - {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, - {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, - {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, - {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, - {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, - {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, - {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, - {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, - {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, - {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, - {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, -}; - -// ATtiny4 ATtiny9 -const Register_file rgftab_attiny4[36] = { // I/O memory [0, 63] - {"portb.pinb", 0x00, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x01, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x02, 1, 0x0f, -1, "port B data register"}, - {"portb.pueb", 0x03, 1, 0x0f, -1, "PORT B pull-up enable control register"}, - {"portb.portcr", 0x0c, 1, -1, -1, "port control register"}, - {"exint.pcmsk", 0x10, 1, -1, -1, "pin change interrupt mask register"}, - {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, - {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, - {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, - {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, - {"ac.acsr", 0x1f, 1, -1, -1, "analog comparator control and status register"}, - {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, - {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, - {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, - {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, - {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, - {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, - {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, - {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, - {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, - {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, - {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, - {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, - {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, - {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, - {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny5 ATtiny10 -const Register_file rgftab_attiny5[41] = { // I/O memory [0, 63] - {"portb.pinb", 0x00, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x01, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x02, 1, 0x0f, -1, "port B data register"}, - {"portb.pueb", 0x03, 1, 0x0f, -1, "PORT B pull-up enable control register"}, - {"portb.portcr", 0x0c, 1, -1, -1, "port control register"}, - {"exint.pcmsk", 0x10, 1, -1, -1, "pin change interrupt mask register"}, - {"exint.pcifr", 0x11, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.pcicr", 0x12, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eimsk", 0x13, 1, -1, -1, "external interrupt mask register"}, - {"exint.eifr", 0x14, 1, -1, -1, "external interrupt flag register"}, - {"exint.eicra", 0x15, 1, -1, -1, "external interrupt control register A"}, - {"ac.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x17, 1, -1, -1, "digital input disable register 0"}, - {"adc.adcl", 0x19, 1, 0xff, -1, "ADC data register low byte"}, - {"adc.admux", 0x1b, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.adcsrb", 0x1c, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsra", 0x1d, 1, -1, -1, "ADC control and status register A"}, - {"ac.acsr", 0x1f, 1, -1, -1, "analog comparator control and status register"}, - {"tc0.icr0", 0x22, 2, 0xffff, -1, "input capture register (16 bits)"}, - {"tc0.ocr0b", 0x24, 2, 0xffff, -1, "T/C 0 output compare register B (16 bits)"}, - {"tc0.ocr0a", 0x26, 2, 0xffff, -1, "T/C 0 output compare register A (16 bits)"}, - {"tc0.tcnt0", 0x28, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, - {"tc0.tifr0", 0x2a, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x2b, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc0.tccr0c", 0x2c, 1, -1, -1, "T/C 0 control register C"}, - {"tc0.tccr0b", 0x2d, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tccr0a", 0x2e, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.gtccr", 0x2f, 1, -1, -1, "general T/C control register"}, - {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, - {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, - {"cpu.vlmcsr", 0x34, 1, -1, -1, "vcc level monitoring control and status register"}, - {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, - {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, - {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, - {"cpu.smcr", 0x3a, 1, -1, -1, "sleep mode control register"}, - {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, - {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny20 -const Register_file rgftab_attiny20[61] = { // I/O memory [0, 63] - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, - {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, - {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, - {"porta.portcr", 0x08, 1, -1, -1, "port control register"}, - {"portb.portcr", 0x08, 1, -1, -1, "port control register"}, - {"exint.pcmsk0", 0x09, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x0a, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.gifr", 0x0b, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x0c, 1, -1, -1, "general interrupt mask register"}, - {"adc.didr0", 0x0d, 1, -1, -1, "digital input disable register 0"}, - {"adc.adc", 0x0e, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.admux", 0x10, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.adcsrb", 0x11, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsra", 0x12, 1, -1, -1, "ADC control and status register A"}, - {"ac.acsrb", 0x13, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsra", 0x14, 1, -1, -1, "analog comparator control and status register A"}, - {"tc0.ocr0b", 0x15, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x16, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tcnt0", 0x17, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x18, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tccr0a", 0x19, 1, -1, -1, "T/C 0 control register A"}, - {"tc1.icr1", 0x1a, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x1c, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x1e, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x20, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tccr1b", 0x23, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x24, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, - {"tc0.gtccr", 0x27, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x27, 1, -1, -1, "general T/C control register"}, - {"twi.twsd", 0x28, 1, -1, -1, "TWI peripheral data register"}, - {"twi.twsam", 0x29, 1, 0xff, -1, "TWI peripheral address mask register"}, - {"twi.twsa", 0x2a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twssra", 0x2b, 1, 0xff, -1, "TWI peripheral status register A"}, - {"twi.twscrb", 0x2c, 1, -1, -1, "TWI peripheral control register B"}, - {"twi.twscra", 0x2d, 1, -1, -1, "TWI peripheral control register A"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"spi.spsr", 0x2f, 1, -1, -1, "SPI status register"}, - {"spi.spcr", 0x30, 1, -1, -1, "SPI control register"}, - {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, - {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, - {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, - {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, - {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, - {"cpu.mcucr", 0x3a, 1, 0xdf, -1, "MCU control register"}, - {"exint.mcucr", 0x3a, 1, -1, -1, "MCU control register"}, - {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, - {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny40 -const Register_file rgftab_attiny40[63] = { // I/O memory [0, 63] - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, - {"portb.pinb", 0x04, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x05, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x06, 1, 0x0f, -1, "port B data register"}, - {"portb.pueb", 0x07, 1, 0x0f, -1, "PORT B pull-up enable control register"}, - {"porta.portcr", 0x08, 1, -1, -1, "port control register"}, - {"portb.portcr", 0x08, 1, -1, -1, "port control register"}, - {"portc.portcr", 0x08, 1, -1, -1, "port control register"}, - {"exint.pcmsk0", 0x09, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x0a, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.gifr", 0x0b, 1, 0x71, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x0c, 1, 0x71, -1, "general interrupt mask register"}, - {"adc.didr0", 0x0d, 1, -1, -1, "digital input disable register 0"}, - {"adc.adc", 0x0e, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.admux", 0x10, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.adcsrb", 0x11, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsra", 0x12, 1, -1, -1, "ADC control and status register A"}, - {"ac.acsrb", 0x13, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsra", 0x14, 1, -1, -1, "analog comparator control and status register A"}, - {"tc0.ocr0b", 0x15, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x16, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tcnt0", 0x17, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x18, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tccr0a", 0x19, 1, -1, -1, "T/C 0 control register A"}, - {"exint.pcmsk2", 0x1a, 1, -1, -1, "pin change interrupt mask register 2"}, - {"portc.pinc", 0x1b, 1, 0x3f, -1, "port C input register"}, - {"portc.ddrc", 0x1c, 1, 0x3f, -1, "port C data direction register"}, - {"portc.portc", 0x1d, 1, 0x3f, -1, "port C data register"}, - {"portc.puec", 0x1e, 1, 0x3f, -1, "PORT C pull-up enable control register"}, - {"cpu.ramdr", 0x1f, 1, 0xff, -1, "RAM data register"}, - {"cpu.ramar", 0x20, 1, 0xff, -1, "RAM address register"}, - {"tc0.ocr1b", 0x21, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc0.ocr1a", 0x22, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc0.tcnt1l", 0x23, 1, 0xff, -1, "timer/counter 1 low byte"}, - {"tc0.tccr1a", 0x24, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tifr", 0x25, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x26, 1, -1, -1, "T/C interrupt mask register"}, - {"tc0.tcnt1h", 0x27, 1, 0xff, -1, "timer/counter 1 high byte"}, - {"twi.twsd", 0x28, 1, -1, -1, "TWI peripheral data register"}, - {"twi.twsam", 0x29, 1, 0xff, -1, "TWI peripheral address mask register"}, - {"twi.twsa", 0x2a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twssra", 0x2b, 1, 0xff, -1, "TWI peripheral status register A"}, - {"twi.twscrb", 0x2c, 1, -1, -1, "TWI peripheral control register B"}, - {"twi.twscra", 0x2d, 1, -1, -1, "TWI peripheral control register A"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"spi.spsr", 0x2f, 1, -1, -1, "SPI status register"}, - {"spi.spcr", 0x30, 1, -1, -1, "SPI control register"}, - {"wdt.wdtcsr", 0x31, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.nvmcsr", 0x32, 1, -1, -1, "non-volatile memory control and status register"}, - {"cpu.nvmcmd", 0x33, 1, 0x3f, -1, "non-volatile memory command register"}, - {"cpu.prr", 0x35, 1, -1, -1, "power reduction register"}, - {"cpu.clkpsr", 0x36, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkmsr", 0x37, 1, -1, -1, "clock main settings register"}, - {"cpu.osccal", 0x39, 1, 0xff, -1, "oscillator calibration register"}, - {"cpu.mcucr", 0x3a, 1, 0xdf, -1, "MCU control register"}, - {"exint.mcucr", 0x3a, 1, -1, -1, "MCU control register"}, - {"cpu.rstflr", 0x3b, 1, -1, -1, "reset flag register"}, - {"cpu.ccp", 0x3c, 1, 0xff, -1, "configuration change protection register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny11 -const Register_file rgftab_attiny11[14] = { // I/O memory [0, 63] - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x1f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny12 -const Register_file rgftab_attiny12[18] = { // I/O memory [0, 63] - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny13 -const Register_file rgftab_attiny13[35] = { // I/O memory [0, 63] + 32 - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc0.gtccr", 0x28, 1, -1, -1, "general T/C control register"}, - {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.dwdr", 0x2e, 1, 0xff, -1, "debugWIRE data register"}, - {"tc0.tccr0a", 0x2f, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny13A -const Register_file rgftab_attiny13a[37] = { // I/O memory [0, 63] + 32 - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"cpu.prr", 0x25, 1, -1, -1, "power reduction register"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc0.gtccr", 0x28, 1, -1, -1, "general T/C control register"}, - {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.dwdr", 0x2e, 1, 0xff, -1, "debugWIRE data register"}, - {"tc0.tccr0a", 0x2f, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.bodcr", 0x30, 1, -1, -1, "BOD control register"}, - {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny15 -const Register_file rgftab_attiny15[28] = { // I/O memory [0, 63] - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsr", 0x06, 1, -1, -1, "ADC control and status register"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x1f, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc1.sfior", 0x2c, 1, -1, -1, "special function I/O register"}, - {"tc1.ocr1b", 0x2d, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny24 ATtiny24A -const Register_file rgftab_attiny24[55] = { // I/O memory [0, 63] + 32 - {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, - {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, - {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny25 -const Register_file rgftab_attiny25[55] = { // I/O memory [0, 63] + 32 - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"cpu.gpior0", 0x11, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x12, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x13, 1, 0xff, -1, "general purpose I/O register 2"}, - {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"cpu.prr", 0x20, 1, -1, -1, "power reduction register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"cpu.dwdr", 0x22, 1, 0xff, -1, "debugWIRE data register"}, - {"tc1.dtps", 0x23, 1, -1, -1, "dead-time prescaler register"}, - {"tc1.dt1b", 0x24, 1, -1, -1, "T/C 1 dead-time register B"}, - {"tc1.dt1a", 0x25, 1, -1, -1, "T/C 1 dead-time register A"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"cpu.pllcsr", 0x27, 1, -1, -1, "PLL control and status register"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x29, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tccr0a", 0x2a, 1, -1, -1, "T/C 0 control register A"}, - {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc0.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, - {"tc1.ocr1c", 0x2d, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny26 -const Register_file rgftab_attiny26[37] = { // I/O memory [0, 63] + 32 - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsr", 0x06, 1, -1, -1, "ADC control and status register"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc1.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sp", 0x3d, 1, 0xff, -1, "stack pointer"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny43U -const Register_file rgftab_attiny43u[54] = { // I/O memory [0, 63] + 32 - {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, - {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x3f, -1, "EEPROM address register"}, - {"exint.pcmsk1", 0x20, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc1.ocr1a", 0x2c, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2d, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny44 ATtiny44A -const Register_file rgftab_attiny44[55] = { // I/O memory [0, 63] + 32 - {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, - {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, - {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny45 ATtiny85 -const Register_file rgftab_attiny45[55] = { // I/O memory [0, 63] + 32 - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"cpu.gpior0", 0x11, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x12, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x13, 1, 0xff, -1, "general purpose I/O register 2"}, - {"ac.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x14, 1, -1, -1, "digital input disable register 0"}, - {"exint.pcmsk", 0x15, 1, 0x3f, -1, "pin change interrupt mask register"}, - {"portb.pinb", 0x16, 1, 0x3f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x3f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x3f, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"cpu.prr", 0x20, 1, -1, -1, "power reduction register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"cpu.dwdr", 0x22, 1, 0xff, -1, "debugWIRE data register"}, - {"tc1.dtps", 0x23, 1, -1, -1, "dead-time prescaler register"}, - {"tc1.dt1b", 0x24, 1, -1, -1, "T/C 1 dead-time register B"}, - {"tc1.dt1a", 0x25, 1, -1, -1, "T/C 1 dead-time register A"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"cpu.pllcsr", 0x27, 1, -1, -1, "PLL control and status register"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x29, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tccr0a", 0x2a, 1, -1, -1, "T/C 0 control register A"}, - {"tc1.ocr1b", 0x2b, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc0.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x2c, 1, -1, -1, "general T/C control register"}, - {"tc1.ocr1c", 0x2d, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.ocr1a", 0x2e, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2f, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1", 0x30, 1, -1, -1, "T/C 1 control register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny48 -const Register_file rgftab_attiny48[74] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porta.pina", 0x0c, 1, 0x0f, -1, "port A input register"}, - {"porta.ddra", 0x0d, 1, 0x0f, -1, "port A data direction register"}, - {"porta.porta", 0x0e, 1, 0x0f, -1, "port A data register"}, - {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eearl", 0x21, 1, 0x3f, -1, "EEPROM address register low byte"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sph", 0x3e, 1, 0x01, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk3", 0x4a, 1, -1, -1, "pin change interrupt mask register 3"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"twi.twhsr", 0x9e, 1, -1, -1, "TWHSR register"}, -}; - -// ATtiny84 ATtiny84A -const Register_file rgftab_attiny84[55] = { // I/O memory [0, 63] + 32 - {"cpu.prr", 0x00, 1, -1, -1, "power reduction register"}, - {"ac.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr0", 0x01, 1, 0xff, -1, "digital input disable register 0"}, - {"ac.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, 0xff, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"tc1.tifr1", 0x0b, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc1.timsk1", 0x0c, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"exint.pcmsk0", 0x12, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0x0f, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"exint.pcmsk1", 0x20, 1, 0x0f, -1, "pin change interrupt mask register 1"}, - {"wdt.wdtcsr", 0x21, 1, -1, -1, "watchdog timer control and status register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr0", 0x38, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc0.timsk0", 0x39, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny87 ATtiny167 -const Register_file rgftab_attiny87[80] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, - {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, - {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, - {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, - {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, - {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, - {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, - {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, - {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, - {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, - {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, - {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, - {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, - {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, - {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, -}; - -// ATtiny88 -const Register_file rgftab_attiny88[74] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porta.pina", 0x0c, 1, 0x0f, -1, "port A input register"}, - {"porta.ddra", 0x0d, 1, 0x0f, -1, "port A data direction register"}, - {"porta.porta", 0x0e, 1, 0x0f, -1, "port A data register"}, - {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eearl", 0x21, 1, 0x3f, -1, "EEPROM address register low byte"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sph", 0x3e, 1, 0x03, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk3", 0x4a, 1, -1, -1, "pin change interrupt mask register 3"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"twi.twhsr", 0x9e, 1, -1, -1, "TWHSR register"}, -}; - -// ATtiny261 ATtiny261A -const Register_file rgftab_attiny261[63] = { // I/O memory [0, 63] + 32 - {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, - {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, - {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, - {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, - {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, - {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, - {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, - {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, - {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, - {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, - {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny461 ATtiny461A -const Register_file rgftab_attiny461[63] = { // I/O memory [0, 63] + 32 - {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, - {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, - {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, - {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, - {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, - {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, - {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, - {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, - {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, - {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, - {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sp", 0x3d, 2, 0x01ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny828 -const Register_file rgftab_attiny828[94] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"porta.puea", 0x03, 1, 0xff, -1, "PORT A pull-up enable control register"}, - {"portb.pinb", 0x04, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x05, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x06, 1, 0xff, -1, "port B data register"}, - {"portb.pueb", 0x07, 1, 0xff, -1, "PORT B pull-up enable control register"}, - {"portc.pinc", 0x08, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x09, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x0a, 1, 0xff, -1, "port C data register"}, - {"portc.puec", 0x0b, 1, 0xff, -1, "PORT C pull-up enable control register"}, - {"portd.pind", 0x0c, 1, 0x0f, -1, "port D input register"}, - {"portd.ddrd", 0x0d, 1, 0x0f, -1, "port D data direction register"}, - {"portd.portd", 0x0e, 1, 0x0f, -1, "port D data register"}, - {"portd.pued", 0x0f, 1, 0x0f, -1, "PORT D pull-up enable control register"}, - {"portc.phde", 0x14, 1, -1, -1, "port high drive enable register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 1, 0xff, -1, "EEPROM address register"}, - {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsra", 0x30, 1, -1, -1, "analog comparator control and status register A"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.ccp", 0x36, 1, 0xff, -1, "configuration change protection register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal0", 0x46, 1, 0xff, -1, "oscillator calibration register 8 MHz"}, - {"cpu.osccal1", 0x47, 1, 0x03, -1, "oscillator calibration register 32 kHz"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admuxa", 0x5c, 1, -1, -1, "ADC multiplexer selection register A"}, - {"adc.admuxb", 0x5d, 1, -1, -1, "ADC multiplexer selection register B"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"twi.twscra", 0x98, 1, -1, -1, "TWI peripheral control register A"}, - {"twi.twscrb", 0x99, 1, -1, -1, "TWI peripheral control register B"}, - {"twi.twssra", 0x9a, 1, -1, -1, "TWI peripheral status register A"}, - {"twi.twsam", 0x9b, 1, -1, -1, "TWI peripheral address mask register"}, - {"twi.twsa", 0x9c, 1, 0xff, -1, "TWI peripheral address register"}, - {"twi.twsd", 0x9d, 1, -1, -1, "TWI peripheral data register"}, - {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, - {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, - {"usart.ucsrd", 0xa3, 1, -1, -1, "USART control and status register D"}, - {"usart.ubrr", 0xa4, 2, 0x0fff, -1, "USART baud rate register (16 bits)"}, - {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, - {"adc.didr2", 0xbe, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr3", 0xbf, 1, -1, -1, "digital input disable register 3"}, - {"tocpm.tocpmcoe", 0xc2, 1, -1, -1, "timer output compare pin mux channel output enable register"}, - {"tocpm.tocpmsa0", 0xc8, 1, -1, -1, "timer output compare pin mux selection 0 register"}, - {"tocpm.tocpmsa1", 0xc9, 1, -1, -1, "timer output compare pin mux selection 1 register"}, - {"cpu.osctcal0a", 0xd0, 1, 0xff, -1, "oscillator temperature calibration register A"}, - {"cpu.osctcal0b", 0xd1, 1, 0xff, -1, "oscillator temperature calibration register B"}, -}; - -// ATtiny861 ATtiny861A -const Register_file rgftab_attiny861[63] = { // I/O memory [0, 63] + 32 - {"tc1.tccr1e", 0x00, 1, -1, -1, "T/C 1 control register E"}, - {"adc.didr0", 0x01, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x02, 1, -1, -1, "digital input disable register 1"}, - {"adc.adcsrb", 0x03, 1, -1, -1, "ADC control and status register B"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsra", 0x08, 1, -1, -1, "analog comparator control and status register A"}, - {"ac.acsrb", 0x09, 1, -1, -1, "analog comparator control and status register B"}, - {"cpu.gpior0", 0x0a, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x0b, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x0c, 1, 0xff, -1, "general purpose I/O register 2"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x10, 1, 0xff, -1, "USI buffer register"}, - {"usi.usipp", 0x11, 1, 0x01, -1, "USI pin position register"}, - {"tc0.ocr0b", 0x12, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x13, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tcnt0h", 0x14, 1, 0xff, -1, "timer/counter 0 high byte"}, - {"tc0.tccr0a", 0x15, 1, -1, -1, "T/C 0 control register A"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"cpu.dwdr", 0x20, 1, 0xff, -1, "debugWIRE data register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"exint.pcmsk1", 0x22, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk0", 0x23, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"tc1.dt1", 0x24, 1, -1, -1, "T/C 1 dead-time register"}, - {"tc1.tc1h", 0x25, 1, 0x03, -1, "timer/counter 1 high byte"}, - {"tc1.tccr1d", 0x26, 1, -1, -1, "T/C 1 control register D"}, - {"tc1.tccr1c", 0x27, 1, -1, -1, "T/C 1 control register C"}, - {"cpu.clkpr", 0x28, 1, -1, -1, "clock prescaler register"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"tc1.ocr1d", 0x2a, 1, 0xff, -1, "T/C 1 output compare register D"}, - {"tc1.ocr1c", 0x2b, 1, 0xff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.ocr1b", 0x2c, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"tc1.ocr1a", 0x2d, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.tcnt1", 0x2e, 1, 0xff, -1, "timer/counter 1"}, - {"tc1.tccr1b", 0x2f, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x30, 1, -1, -1, "T/C 1 control register A"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0l", 0x32, 1, 0xff, -1, "timer/counter 0 low byte"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.prr", 0x36, 1, -1, -1, "power reduction register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny1634 -const Register_file rgftab_attiny1634[89] = { // I/O memory [0, 223] + 32 - {"adc.adc", 0x00, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsrb", 0x02, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsra", 0x03, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x04, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsrb", 0x05, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsra", 0x06, 1, -1, -1, "analog comparator control and status register A"}, - {"portc.pinc", 0x07, 1, 0x3f, -1, "port C input register"}, - {"portc.ddrc", 0x08, 1, 0x3f, -1, "port C data direction register"}, - {"portc.portc", 0x09, 1, 0x3f, -1, "port C data register"}, - {"portc.puec", 0x0a, 1, -1, -1, "PORT C pull-up enable control register"}, - {"portb.pinb", 0x0b, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x0c, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x0d, 1, 0x0f, -1, "port B data register"}, - {"portb.pueb", 0x0e, 1, -1, -1, "PORT B pull-up enable control register"}, - {"porta.pina", 0x0f, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x10, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x11, 1, 0xff, -1, "port A data register"}, - {"porta.puea", 0x12, 1, -1, -1, "PORT A pull-up enable control register"}, - {"porta.portcr", 0x13, 1, -1, -1, "port control register"}, - {"portb.portcr", 0x13, 1, -1, -1, "port control register"}, - {"portc.portcr", 0x13, 1, -1, -1, "port control register"}, - {"cpu.gpior0", 0x14, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x15, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x16, 1, 0xff, -1, "general purpose I/O register 2"}, - {"tc0.ocr0b", 0x17, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"tc0.ocr0a", 0x18, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.tcnt0", 0x19, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x1a, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tccr0a", 0x1b, 1, -1, -1, "T/C 0 control register A"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart0.udr0", 0x20, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart0.ubrr0", 0x21, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.ucsr0d", 0x23, 1, -1, -1, "USART control and status register D"}, - {"usart0.ucsr0c", 0x24, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ucsr0b", 0x25, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0a", 0x26, 1, -1, -1, "USART 0 control and status register A"}, - {"exint.pcmsk0", 0x27, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x28, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x29, 1, -1, -1, "pin change interrupt mask register 2"}, - {"usi.usicr", 0x2a, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x2b, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x2c, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x2d, 1, 0xff, -1, "USI buffer register"}, - {"cpu.ccp", 0x2f, 1, 0xff, -1, "configuration change protection register"}, - {"wdt.wdtcsr", 0x30, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clksr", 0x32, 1, -1, -1, "clock setting register"}, - {"cpu.clkpr", 0x33, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x34, 1, -1, -1, "power reduction register"}, - {"cpu.mcusr", 0x35, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x36, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x39, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x39, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x3a, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x3a, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3b, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3c, 1, -1, -1, "general interrupt mask register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"adc.didr0", 0x40, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x41, 1, -1, -1, "digital input disable register 1"}, - {"adc.didr2", 0x42, 1, -1, -1, "digital input disable register 2"}, - {"cpu.osccal0", 0x43, 1, 0xff, -1, "oscillator calibration 0 register"}, - {"cpu.osctcal0a", 0x44, 1, 0xff, -1, "oscillator temperature calibration register A"}, - {"cpu.osctcal0b", 0x45, 1, 0xff, -1, "oscillator temperature calibration register B"}, - {"cpu.osccal1", 0x46, 1, 0x03, -1, "oscillator calibration 1 register"}, - {"tc0.gtccr", 0x47, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x47, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x48, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x4a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x4c, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x4e, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1c", 0x50, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tccr1b", 0x51, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x52, 1, -1, -1, "T/C 1 control register A"}, - {"usart1.udr1", 0x53, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart1.ubrr1", 0x54, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.ucsr1d", 0x56, 1, -1, -1, "USART control and status register D"}, - {"usart1.ucsr1c", 0x57, 1, -1, -1, "USART control and status register C"}, - {"usart1.ucsr1b", 0x58, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1a", 0x59, 1, -1, -1, "USART 1 control and status register A"}, - {"twi.twsd", 0x5a, 1, -1, -1, "TWI peripheral data register"}, - {"twi.twsam", 0x5b, 1, 0xff, -1, "TWI peripheral address mask register"}, - {"twi.twsa", 0x5c, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twssra", 0x5d, 1, -1, -1, "TWI peripheral status register A"}, - {"twi.twscrb", 0x5e, 1, -1, -1, "TWI peripheral control register B"}, - {"twi.twscra", 0x5f, 1, -1, -1, "TWI peripheral control register A"}, -}; - -// ATtiny2313 -const Register_file rgftab_attiny2313[54] = { // I/O memory [0, 63] + 32 - {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, - {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, - {"cpu.pcmsk", 0x20, 1, 0xff, -1, "pin change interrupt mask register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.eifr", 0x3a, 1, -1, -1, "external interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny2313A -const Register_file rgftab_attiny2313a[58] = { // I/O memory [0, 63] + 32 - {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, - {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, - {"exint.pcmsk1", 0x04, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x05, 1, -1, -1, "pin change interrupt mask register 2"}, - {"cpu.prr", 0x06, 1, -1, -1, "power reduction register"}, - {"cpu.bodcr", 0x07, 1, -1, -1, "BOD control register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, - {"exint.pcmsk0", 0x20, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.spl", 0x3d, 1, 0xff, -1, "stack pointer low byte"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATtiny4313 -const Register_file rgftab_attiny4313[58] = { // I/O memory [0, 63] + 32 - {"ac.didr", 0x01, 1, 0x03, -1, "digital input disable register"}, - {"usart.ubrrh", 0x02, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x03, 1, -1, -1, "USART control and status register C"}, - {"exint.pcmsk1", 0x04, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x05, 1, -1, -1, "pin change interrupt mask register 2"}, - {"cpu.prr", 0x06, 1, -1, -1, "power reduction register"}, - {"cpu.bodcr", 0x07, 1, -1, -1, "BOD control register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"usi.usicr", 0x0d, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x0e, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x0f, 1, 0xff, -1, "USI data register"}, - {"portd.pind", 0x10, 1, 0x7f, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0x7f, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0x7f, -1, "port D data register"}, - {"cpu.gpior0", 0x13, 1, 0xff, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x14, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x15, 1, 0xff, -1, "general purpose I/O register 2"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0x07, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0x07, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0x07, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 1, 0x7f, -1, "EEPROM address register"}, - {"exint.pcmsk0", 0x20, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc1.tccr1c", 0x22, 1, -1, -1, "T/C 1 control register C"}, - {"cpu.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"cpu.clkpr", 0x26, 1, -1, -1, "clock prescaler register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.tccr0a", 0x30, 1, -1, -1, "T/C 0 control register A"}, - {"cpu.osccal", 0x31, 1, 0x7f, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0b", 0x33, 1, -1, -1, "T/C 0 control register B"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.ocr0a", 0x36, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gimsk", 0x3b, 1, -1, -1, "general interrupt mask register"}, - {"tc0.ocr0b", 0x3c, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATmega8 ATmega8A -const Register_file rgftab_atmega8[61] = { // I/O memory [0, 63] + 32 - {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0x7f, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, - {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATmega8HVA ATmega16HVA -const Register_file rgftab_atmega8hva[74] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0x03, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0x03, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0x03, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0x0f, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0x0f, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0x0f, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x01, -1, "port C input register"}, - {"portc.portc", 0x08, 1, 0x01, -1, "port C data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.osicsr", 0x17, 1, -1, -1, "oscillator sampling interface control and status register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 1, 0xff, -1, "EEPROM address register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, - {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, - {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, - {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, - {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"voltage_regulator.rocr", 0xa8, 1, -1, -1, "regulator operating condition register"}, - {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, - {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, - {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadcsra", 0xc4, 1, -1, -1, "CC-ADC control and status register A"}, - {"coulomb_counter.cadcsrb", 0xc5, 1, -1, -1, "CC-ADC control and status register B"}, - {"coulomb_counter.cadrc", 0xc6, 1, 0xff, -1, "CC-ADC regular current register"}, - {"coulomb_counter.cadic", 0xc8, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, - {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, - {"battery_protection.bpimsk", 0xd2, 1, -1, -1, "battery protection interrupt mask register"}, - {"battery_protection.bpifr", 0xd3, 1, -1, -1, "battery protection interrupt flag register"}, - {"battery_protection.bpscd", 0xd5, 1, 0xff, -1, "battery protection short-circuit detection level register"}, - {"battery_protection.bpdocd", 0xd6, 1, 0xff, -1, "battery protection discharge-over-current detection level register"}, - {"battery_protection.bpcocd", 0xd7, 1, 0xff, -1, "battery protection charge-over-current detection level register"}, - {"battery_protection.bpdhcd", 0xd8, 1, 0xff, -1, "battery protection discharge-high-current detection level register"}, - {"battery_protection.bpchcd", 0xd9, 1, 0xff, -1, "battery protection charge-high-current detection level register"}, - {"battery_protection.bpsctr", 0xda, 1, 0x7f, -1, "battery protection short-current timing register"}, - {"battery_protection.bpoctr", 0xdb, 1, 0x3f, -1, "battery protection over-current timing register"}, - {"battery_protection.bphctr", 0xdc, 1, 0x3f, -1, "battery protection short-current timing register"}, - {"battery_protection.bpcr", 0xdd, 1, -1, -1, "battery protection control register"}, - {"battery_protection.bpplr", 0xde, 1, -1, -1, "battery protection parameter lock register"}, -}; - -// ATmega8U2 ATmega16U2 ATmega32U2 -const Register_file rgftab_atmega8u2[92] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, -1, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, -1, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, -1, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"wdt.wdtckd", 0x42, 1, -1, -1, "watchdog timer clock divider register"}, - {"usb_device.regcr", 0x43, 1, -1, -1, "regulator control register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"ac.acmux", 0x5d, 1, -1, -1, "analog comparator input multiplexer register"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"cpu.clksel0", 0xb0, 1, -1, -1, "clock selection register 0"}, - {"cpu.clksel1", 0xb1, 1, -1, -1, "clock selection register 1"}, - {"cpu.clksta", 0xb2, 1, -1, -1, "clock status register"}, - {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, - {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, - {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, - {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, - {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, - {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, - {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, - {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, - {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, - {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, - {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, - {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, - {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, - {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, - {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, - {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, - {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, - {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, - {"usb_device.ueint", 0xd4, 1, 0x1f, -1, "USB endpoint number interrupt register"}, - {"usb_device.upoe", 0xdb, 1, -1, -1, "USB software output enable register"}, -}; - -// ATmega16 -const Register_file rgftab_atmega16[70] = { // I/O memory [0, 63] + 32 - {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATmega16A -const Register_file rgftab_atmega16a[70] = { // I/O memory [0, 63] + 32 - {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, 0x8f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATmega16U4 ATmega32U4 -const Register_file rgftab_atmega16u4[139] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xc0, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xc0, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xc0, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x44, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x44, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x44, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xf3, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xf3, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xf3, -1, "port F data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"pll.pllfrq", 0x32, 1, -1, -1, "PLL frequency control register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"cpu.rcctrl", 0x47, 1, -1, -1, "oscillator control register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x5d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"tc4.tcnt4", 0x9e, 1, 0xff, -1, "timer/counter 4"}, - {"tc4.tc4h", 0x9f, 1, 0x07, -1, "timer/counter 4 high byte"}, - {"tc4.tccr4a", 0xa0, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0xa1, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0xa2, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tccr4d", 0xa3, 1, -1, -1, "T/C 4 control register D"}, - {"tc4.tccr4e", 0xa4, 1, -1, -1, "T/C 4 control register E"}, - {"cpu.clksel0", 0xa5, 1, -1, -1, "clock selection register 0"}, - {"cpu.clksel1", 0xa6, 1, -1, -1, "clock selection register 1"}, - {"cpu.clksta", 0xa7, 1, -1, -1, "clock status register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"tc4.ocr4a", 0xaf, 1, 0xff, -1, "T/C 4 output compare register A"}, - {"tc4.ocr4b", 0xb0, 1, 0xff, -1, "T/C 4 output compare register B"}, - {"tc4.ocr4c", 0xb1, 1, 0xff, -1, "T/C 4 output compare register C"}, - {"tc4.ocr4d", 0xb2, 1, 0xff, -1, "T/C 4 output compare register D"}, - {"tc4.dt4", 0xb4, 1, -1, -1, "T/C 4 dead-time register"}, - {"usb_device.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, - {"usb_device.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, - {"usb_device.usbsta", 0xb9, 1, -1, -1, "USB status register"}, - {"usb_device.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, - {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, - {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, - {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, - {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, - {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, - {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, - {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, - {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, - {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, - {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, - {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, - {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, - {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, - {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, - {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, - {"usb_device.uedatx", 0xd1, 1, -1, -1, "USB data endpoint register"}, - {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, - {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, - {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, -}; - -// ATmega32 -const Register_file rgftab_atmega32[68] = { // I/O memory [0, 63] + 32 - {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x02, 1, 0xff, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.sfior", 0x30, 1, 0x07, -1, "special function I/O register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"jtag.ocdr", 0x31, 1, -1, -1, "on-chip debug register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, - {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, - {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATmega32A -const Register_file rgftab_atmega32a[66] = { // I/O memory [0, 63] + 32 - {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x02, 1, 0xff, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, 0x0f, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"ac.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.sfior", 0x30, 1, 0x07, -1, "special function I/O register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, - {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, - {"cpu.sp", 0x3d, 2, 0x0fff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// ATmega32C1 -const Register_file rgftab_atmega32c1[117] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, - {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, - {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, - {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, - {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, - {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, - {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, - {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, - {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, - {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, - {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, - {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, - {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, - {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, - {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, - {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, - {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, - {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, - {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, - {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, - {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, - {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, - {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, - {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, - {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, - {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, - {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, - {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, - {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, - {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, - {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, - {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, - {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, - {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, - {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, - {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, - {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, - {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, - {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, - {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, - {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, - {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, - {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, - {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, - {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, -}; - -// ATmega48 ATmega48P -const Register_file rgftab_atmega48[81] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega48A ATmega48PA -const Register_file rgftab_atmega48a[82] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, - {"eeprom.eearh", 0x22, 1, 0x03, -1, "EEPROM address register high byte"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega48PB -const Register_file rgftab_atmega48pb[95] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eearl", 0x21, 1, 0xff, -1, "EEPROM address register low byte"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x03ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"deviceid.devid0", 0xd0, 1, -1, -1, "device ID byte 0"}, - {"deviceid.devid1", 0xd1, 1, -1, -1, "device ID byte 1"}, - {"deviceid.devid2", 0xd2, 1, -1, -1, "device ID byte 2"}, - {"deviceid.devid3", 0xd3, 1, -1, -1, "device ID byte 3"}, - {"deviceid.devid4", 0xd4, 1, -1, -1, "device ID byte 4"}, - {"deviceid.devid5", 0xd5, 1, -1, -1, "device ID byte 5"}, - {"deviceid.devid6", 0xd6, 1, -1, -1, "device ID byte 6"}, - {"deviceid.devid7", 0xd7, 1, -1, -1, "device ID byte 7"}, - {"deviceid.devid8", 0xd8, 1, -1, -1, "device ID byte 8"}, -}; - -// ATmega64 ATmega64A -const Register_file rgftab_atmega64[103] = { // I/O memory [0, 223] + 32 - {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, - {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, - {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, - {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, - {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, - {"cpu.xdiv", 0x3c, 1, -1, -1, "XTAL divide control register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, - {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, - {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, - {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, - {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, - {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, - {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, - {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, - {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, - {"adc.adcsrb", 0x6e, 1, -1, -1, "ADC control and status register B"}, - {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, - {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, - {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, - {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, - {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, -}; - -// ATmega64C1 -const Register_file rgftab_atmega64c1[122] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, - {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, - {"dac.dacl", 0x71, 1, -1, -1, "DAC data register low byte"}, - {"dac.dach", 0x72, 1, -1, -1, "DAC data register high byte"}, - {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, - {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, - {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, - {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, - {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, - {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, - {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, - {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, - {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, - {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, - {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, - {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, - {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, - {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, - {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, - {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, - {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, - {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, - {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, - {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, - {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, - {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, - {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, - {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, - {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, - {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, - {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, - {"can.cantiml", 0xc6, 1, 0xff, -1, "CAN timer low byte"}, - {"can.cantimh", 0xc7, 1, 0xff, -1, "CAN timer high byte"}, - {"can.canttcl", 0xc8, 1, 0xff, -1, "CAN TTC timer low byte"}, - {"can.canttch", 0xc9, 1, 0xff, -1, "CAN TTC timer high byte"}, - {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, - {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, - {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, - {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, - {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, - {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, - {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, - {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, - {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, - {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, - {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, - {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, - {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, - {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, - {"can.canstml", 0xd8, 1, 0xff, -1, "CAN time stamp register low byte"}, - {"can.canstmh", 0xd9, 1, 0xff, -1, "CAN time stamp register high byte"}, - {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, -}; - -// ATmegaS64M1 ATmega64M1 -const Register_file rgftab_atmegas64m1[136] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, - {"exint.pcmsk3", 0x4d, 1, -1, -1, "pin change interrupt mask register 3"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x55, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x56, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.amp2csr", 0x57, 1, -1, -1, "amplifier 2 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"dac.dacon", 0x70, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x71, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x74, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x75, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x76, 1, -1, -1, "analog comparator 2 control register"}, - {"ac.ac3con", 0x77, 1, -1, -1, "analog comparator 3 control register"}, - {"psc.pocr0sa", 0x80, 2, 0x0fff, -1, "PSC module 0 output compare SA register (16 bits)"}, - {"psc.pocr0ra", 0x82, 2, 0x0fff, -1, "PSC module 0 output compare RA register (16 bits)"}, - {"psc.pocr0sb", 0x84, 2, 0x0fff, -1, "PSC module 0 output compare SB register (16 bits)"}, - {"psc.pocr1sa", 0x86, 2, 0x0fff, -1, "PSC module 1 output compare SA register (16 bits)"}, - {"psc.pocr1ra", 0x88, 2, 0x0fff, -1, "PSC module 1 output compare RA register (16 bits)"}, - {"psc.pocr1sb", 0x8a, 2, 0x0fff, -1, "PSC module 1 output compare SB register (16 bits)"}, - {"psc.pocr2sa", 0x8c, 2, 0x0fff, -1, "PSC module 2 output compare SA register (16 bits)"}, - {"psc.pocr2ra", 0x8e, 2, 0x0fff, -1, "PSC module 2 output compare RA register (16 bits)"}, - {"psc.pocr2sb", 0x90, 2, 0x0fff, -1, "PSC module 2 output compare SB register (16 bits)"}, - {"psc.pocr_rb", 0x92, 2, 0x0fff, -1, "PSC output compare RB register (16 bits)"}, - {"psc.psync", 0x94, 1, -1, -1, "PSC synchro configuration register"}, - {"psc.pcnf", 0x95, 1, -1, -1, "PSC configuration register"}, - {"psc.poc", 0x96, 1, -1, -1, "PSC output configuration register"}, - {"psc.pctl", 0x97, 1, -1, -1, "PSC control register"}, - {"psc.pmic0", 0x98, 1, -1, -1, "PSC module 0 input control register"}, - {"psc.pmic1", 0x99, 1, -1, -1, "PSC module 1 input control register"}, - {"psc.pmic2", 0x9a, 1, -1, -1, "PSC module 2 input control register"}, - {"psc.pim", 0x9b, 1, -1, -1, "PSC interrupt mask register"}, - {"psc.pifr", 0x9c, 1, -1, -1, "PSC interrupt flag register"}, - {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, - {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, - {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, - {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, - {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, - {"linuart.linbrr", 0xad, 2, -1, -1, "LIN baud rate register (16 bits)"}, - {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, - {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, - {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, - {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, - {"can.cangcon", 0xb8, 1, -1, -1, "CAN general control register"}, - {"can.cangsta", 0xb9, 1, -1, -1, "CAN general status register"}, - {"can.cangit", 0xba, 1, -1, -1, "CAN general interrupt register"}, - {"can.cangie", 0xbb, 1, -1, -1, "CAN general interrupt enable register"}, - {"can.canen2", 0xbc, 1, -1, -1, "CAN enable MOb register 2"}, - {"can.canen1", 0xbd, 1, 0x00, -1, "CAN enable MOb register 1"}, - {"can.canie2", 0xbe, 1, -1, -1, "CAN enable interrupt MOb register 2"}, - {"can.canie1", 0xbf, 1, 0x00, -1, "CAN enable interrupt MOb register 1"}, - {"can.cansit2", 0xc0, 1, -1, -1, "CAN status interrupt MOb register 2"}, - {"can.cansit1", 0xc1, 1, 0x00, -1, "CAN status interrupt MOb register 1"}, - {"can.canbt1", 0xc2, 1, -1, -1, "CAN bit timing register 1"}, - {"can.canbt2", 0xc3, 1, -1, -1, "CAN bit timing register 2"}, - {"can.canbt3", 0xc4, 1, -1, -1, "CAN bit timing register 3"}, - {"can.cantcon", 0xc5, 1, 0xff, -1, "CAN timer control register"}, - {"can.cantim", 0xc6, 2, 0xffff, -1, "CAN timer (16 bits)"}, - {"can.canttc", 0xc8, 2, 0xffff, -1, "CAN TTC timer (16 bits)"}, - {"can.cantec", 0xca, 1, 0xff, -1, "CAN transmit error counter"}, - {"can.canrec", 0xcb, 1, 0xff, -1, "CAN receive error counter"}, - {"can.canhpmob", 0xcc, 1, -1, -1, "CAN highest priority MOb register"}, - {"can.canpage", 0xcd, 1, -1, -1, "CAN page MOb register"}, - {"can.canstmob", 0xce, 1, -1, -1, "CAN MOb status register"}, - {"can.cancdmob", 0xcf, 1, -1, -1, "MOb control and DLC register"}, - {"can.canidt4", 0xd0, 1, -1, -1, "CAN identifier tag register 4"}, - {"can.canidt3", 0xd1, 1, 0xff, -1, "CAN identifier tag register 3"}, - {"can.canidt2", 0xd2, 1, 0xff, -1, "CAN identifier tag register 2"}, - {"can.canidt1", 0xd3, 1, 0xff, -1, "CAN identifier tag register 1"}, - {"can.canidm4", 0xd4, 1, 0xfd, -1, "CAN identifier mask register 4"}, - {"can.canidm3", 0xd5, 1, 0xff, -1, "CAN identifier mask register 3"}, - {"can.canidm2", 0xd6, 1, 0xff, -1, "CAN identifier mask register 2"}, - {"can.canidm1", 0xd7, 1, 0xff, -1, "CAN identifier mask register 1"}, - {"can.canstm", 0xd8, 2, 0xffff, -1, "CAN time stamp register (16 bits)"}, - {"can.canmsg", 0xda, 1, 0xff, -1, "CAN message data register"}, -}; - -// ATmega64HVE2 -const Register_file rgftab_atmega64hve2[89] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0x03, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0x03, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0x03, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 2, 0xffff, -1, "timer/counter 0 (16 bits)"}, - {"tc0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x29, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"wakeup_timer.wutcsr", 0x42, 1, -1, -1, "wake-up timer control and status register"}, - {"wdt.wdtclr", 0x43, 1, -1, -1, "watchdog timer configuration lock register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.sosccala", 0x46, 1, 0xff, -1, "slow oscillator calibration register A"}, - {"cpu.sosccalb", 0x47, 1, 0xff, -1, "oscillator calibration register B"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0x03, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"cpu.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.ocr1a", 0x68, 1, 0xff, -1, "T/C 1 output compare register A"}, - {"tc1.ocr1b", 0x69, 1, 0xff, -1, "T/C 1 output compare register B"}, - {"linuart.lincr", 0xa0, 1, -1, -1, "LIN control register"}, - {"linuart.linsir", 0xa1, 1, -1, -1, "LIN status and interrupt register"}, - {"linuart.linenir", 0xa2, 1, -1, -1, "LIN enable interrupt register"}, - {"linuart.linerr", 0xa3, 1, -1, -1, "LIN error register"}, - {"linuart.linbtr", 0xa4, 1, -1, -1, "LIN bit timing register"}, - {"linuart.linbrrl", 0xa5, 1, -1, -1, "LIN baud rate low register low byte"}, - {"linuart.linbrrh", 0xa6, 1, -1, -1, "LIN baud rate high register high byte"}, - {"linuart.lindlr", 0xa7, 1, -1, -1, "LIN data length register"}, - {"linuart.linidr", 0xa8, 1, -1, -1, "LIN identifier register"}, - {"linuart.linsel", 0xa9, 1, -1, -1, "LIN data buffer selection register"}, - {"linuart.lindat", 0xaa, 1, -1, -1, "LIN data register"}, - {"bandgap.bgcsra", 0xb1, 1, -1, -1, "bandgap control and status register A"}, - {"bandgap.bgcrb", 0xb2, 1, -1, -1, "bandgap calibration register B"}, - {"bandgap.bgcra", 0xb3, 1, -1, -1, "bandgap calibration register A"}, - {"bandgap.bglr", 0xb4, 1, -1, -1, "band gap lock register"}, - {"cpu.pllcsr", 0xb8, 1, -1, -1, "PLL control and status register"}, - {"portb.pbov", 0xbc, 1, -1, -1, "port B override register"}, - {"adc.adscsra", 0xc0, 1, -1, -1, "ADC synchronization control and status register A"}, - {"adc.adscsrb", 0xc1, 1, -1, -1, "ADC synchronization control and status register B"}, - {"adc.adcra", 0xc2, 1, -1, -1, "ADC control register A"}, - {"adc.adcrb", 0xc3, 1, -1, -1, "ADC control register B"}, - {"adc.adcrc", 0xc4, 1, -1, -1, "ADC control register B"}, - {"adc.adcrd", 0xc5, 1, -1, -1, "ADC control register D"}, - {"adc.adcre", 0xc6, 1, -1, -1, "ADC control register E"}, - {"adc.adifr", 0xc7, 1, -1, -1, "ADC interrupt flag register"}, - {"adc.adimr", 0xc8, 1, -1, -1, "ADC interrupt mask register"}, - {"adc.cadrcl", 0xc9, 2, 0xffff, -1, "CC-ADC regulator current comparator threshold level register (16 bits)"}, - {"adc.cadic", 0xcb, 2, 0xffff, -1, "C-ADC instantaneous conversion result register (16 bits)"}, - {"adc.cadac0", 0xcd, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, - {"adc.cadac1", 0xce, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, - {"adc.cadac2", 0xcf, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, - {"adc.cadac3", 0xd0, 1, 0xff, -1, "C-ADC accumulated conversion result register"}, - {"adc.vadic", 0xd1, 2, 0xffff, -1, "V-ADC instantaneous conversion result register (16 bits)"}, - {"adc.vadac0", 0xd3, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, - {"adc.vadac1", 0xd4, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, - {"adc.vadac2", 0xd5, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, - {"adc.vadac3", 0xd6, 1, 0xff, -1, "V-ADC accumulated conversion result register"}, -}; - -// ATmega64RFR2 ATmega644RFR2 -const Register_file rgftab_atmega64rfr2[269] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, - {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, - {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, - {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, - {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, - {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, - {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, - {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, - {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, - {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, - {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, - {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, - {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, - {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, - {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, - {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, - {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, - {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, - {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, - {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, - {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, - {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, - {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, - {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, - {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, - {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, - {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, - {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, - {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, - {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, - {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, - {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, - {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, - {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, - {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, - {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, - {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, - {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, - {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, - {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, - {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, - {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, - {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, - {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, - {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, - {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, - {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, - {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, - {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, - {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, - {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, - {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, - {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, - {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, - {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, - {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, - {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, - {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, - {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, - {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, - {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, - {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, - {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, - {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, - {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, - {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, - {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, - {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, - {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, - {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, - {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, - {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, - {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, - {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, - {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, - {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, - {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, - {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, - {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, - {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, - {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, - {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, - {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, - {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, - {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, - {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, - {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, - {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, - {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, - {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, - {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, - {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, - {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, - {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, - {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, - {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, - {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, - {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, - {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, - {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, - {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, - {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, - {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, - {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, - {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, - {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, - {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, - {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, - {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, - {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, - {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, - {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, - {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, - {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, - {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, - {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, - {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, - {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, - {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, - {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, - {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, - {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, - {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, -}; - -// ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 ATmega168A ATmega168P ATmega168PA -const Register_file rgftab_atmega88[81] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega88PB ATmega168PB -const Register_file rgftab_atmega88pb[95] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0x7f, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0x7f, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0x7f, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x0f, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x0f, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x0f, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"deviceid.devid0", 0xd0, 1, -1, -1, "device ID byte 0"}, - {"deviceid.devid1", 0xd1, 1, -1, -1, "device ID byte 1"}, - {"deviceid.devid2", 0xd2, 1, -1, -1, "device ID byte 2"}, - {"deviceid.devid3", 0xd3, 1, -1, -1, "device ID byte 3"}, - {"deviceid.devid4", 0xd4, 1, -1, -1, "device ID byte 4"}, - {"deviceid.devid5", 0xd5, 1, -1, -1, "device ID byte 5"}, - {"deviceid.devid6", 0xd6, 1, -1, -1, "device ID byte 6"}, - {"deviceid.devid7", 0xd7, 1, -1, -1, "device ID byte 7"}, - {"deviceid.devid8", 0xd8, 1, -1, -1, "device ID byte 8"}, -}; - -// ATmega128 ATmegaS128 -const Register_file rgftab_atmega128[103] = { // I/O memory [0, 223] + 32 - {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, - {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, - {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, - {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, - {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, - {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, - {"cpu.xdiv", 0x3c, 1, -1, -1, "XTAL divide control register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, - {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, - {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, - {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, - {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, - {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, - {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, - {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, - {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, - {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, - {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, - {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, - {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, - {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, -}; - -// ATmega128A -const Register_file rgftab_atmega128a[103] = { // I/O memory [0, 223] + 32 - {"portf.pinf", 0x00, 1, 0xff, -1, "port F input register"}, - {"porte.pine", 0x01, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x02, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x03, 1, 0xff, -1, "port E data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, - {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"ac.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"misc.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc0.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc1.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"tc3.sfior", 0x20, 1, -1, -1, "special function I/O register"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"jtag.ocdr", 0x22, 1, -1, -1, "on-chip debug register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"tc0.assr", 0x30, 1, -1, -1, "asynchronous status register"}, - {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"tc0.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x36, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x37, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.eifr", 0x38, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x39, 1, -1, -1, "external interrupt mask register"}, - {"exint.eicrb", 0x3a, 1, -1, -1, "external interrupt control register B"}, - {"cpu.rampz", 0x3b, 1, -1, -1, "extended Z register"}, - {"cpu.xdiv", 0x3c, 1, 0xff, -1, "XTAL divide control register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"portf.ddrf", 0x41, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x42, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x43, 1, 0x1f, -1, "port G input register"}, - {"portg.ddrg", 0x44, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x45, 1, 0x1f, -1, "port G data register"}, - {"boot_load.spmcsr", 0x48, 1, -1, -1, "store program memory control and status register"}, - {"exint.eicra", 0x4a, 1, -1, -1, "external interrupt control register A"}, - {"cpu.xmcrb", 0x4c, 1, -1, -1, "external memory control register B"}, - {"cpu.xmcra", 0x4d, 1, -1, -1, "external memory control register A"}, - {"cpu.osccal", 0x4f, 1, 0xff, -1, "oscillator calibration register"}, - {"twi.twbr", 0x50, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x51, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x52, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x53, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x54, 1, -1, -1, "TWI control register"}, - {"tc1.ocr1c", 0x58, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc1.tccr1c", 0x5a, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc1.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3c", 0x62, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3c", 0x6c, 1, -1, -1, "T/C 3 control register C"}, - {"usart0.ubrr0h", 0x70, 1, 0x0f, -1, "USART 0 baud rate register high byte"}, - {"usart0.ucsr0c", 0x75, 1, -1, -1, "USART 0 control and status register C"}, - {"usart1.ubrr1h", 0x78, 1, 0x0f, -1, "USART 1 baud rate register high byte"}, - {"usart1.ubrr1l", 0x79, 1, 0xff, -1, "USART 1 baud rate register low byte"}, - {"usart1.ucsr1b", 0x7a, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1a", 0x7b, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.udr1", 0x7c, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart1.ucsr1c", 0x7d, 1, -1, -1, "USART control and status register C"}, -}; - -// ATmega128RFA1 -const Register_file rgftab_atmega128rfa1[237] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, - {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, - {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, - {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, - {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, - {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, - {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, - {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, - {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, - {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, - {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, - {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, - {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, - {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, - {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, - {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, - {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, - {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, - {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, - {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, - {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, - {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, - {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, - {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, - {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, - {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, - {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, - {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, - {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, - {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, - {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, - {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, - {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, - {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, - {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, - {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, - {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, - {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, - {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, - {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, - {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, - {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, - {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, - {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, - {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, - {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, - {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, - {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, - {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, - {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, - {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, - {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, - {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, - {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, - {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, - {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, - {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, - {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, - {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, - {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, - {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, - {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, - {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, - {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, - {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, - {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, - {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, - {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, - {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, - {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, - {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, - {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, - {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, - {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, - {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, - {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, - {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, - {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, - {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, - {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, - {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, - {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, - {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, - {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, - {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, - {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, - {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, - {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, - {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, - {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, - {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, -}; - -// ATmega128RFR2 ATmega1284RFR2 -const Register_file rgftab_atmega128rfr2[270] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, - {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, - {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, - {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, - {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, - {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, - {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, - {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, - {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, - {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, - {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, - {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, - {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, - {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, - {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, - {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, - {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, - {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, - {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, - {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, - {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, - {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, - {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, - {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, - {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, - {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, - {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, - {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, - {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, - {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, - {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, - {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, - {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, - {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, - {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, - {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, - {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, - {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, - {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, - {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, - {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, - {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, - {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, - {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, - {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, - {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, - {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, - {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, - {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, - {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, - {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, - {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, - {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, - {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, - {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, - {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, - {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, - {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, - {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, - {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, - {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, - {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, - {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, - {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, - {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, - {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, - {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, - {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, - {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, - {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, - {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, - {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, - {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, - {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, - {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, - {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, - {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, - {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, - {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, - {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, - {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, - {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, - {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, - {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, - {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, - {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, - {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, - {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, - {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, - {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, - {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, - {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, - {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, - {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, - {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, - {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, - {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, - {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, - {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, - {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, - {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, - {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, - {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, - {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, - {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, - {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, - {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, - {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, - {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, - {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, - {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, - {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, - {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, - {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, - {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, - {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, - {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, - {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, - {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, - {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, - {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, - {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, - {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, -}; - -// ATmega162 -const Register_file rgftab_atmega162[79] = { // I/O memory [0, 223] + 32 - {"usart1.ubrr1l", 0x00, 1, 0xff, -1, "USART 1 baud rate register low byte"}, - {"usart1.ucsr1b", 0x01, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1a", 0x02, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.udr1", 0x03, 1, 0xff, -1, "USART 1 I/O data register"}, - {"cpu.osccal", 0x04, 1, 0x7f, -1, "oscillator calibration register"}, - {"jtag.ocdr", 0x04, 1, -1, -1, "on-chip debug register"}, - {"porte.pine", 0x05, 1, 0x0f, -1, "port E input register"}, - {"porte.ddre", 0x06, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x07, 1, 0x07, -1, "port E data register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart0.ubrr0l", 0x09, 1, 0xff, -1, "USART 0 baud rate register low byte"}, - {"usart0.ucsr0b", 0x0a, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0a", 0x0b, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.udr0", 0x0c, 1, 0xff, -1, "USART 0 I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart0.ubrr0h", 0x20, 1, 0x8f, -1, "USART 0 baud rate register high byte"}, - {"usart0.ucsr0c", 0x20, 1, -1, -1, "USART 0 control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.ocr2", 0x22, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x23, 1, 0xff, -1, "timer/counter 2"}, - {"tc1.icr1", 0x24, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc2.assr", 0x26, 1, -1, -1, "asynchronous status register"}, - {"tc2.tccr2", 0x27, 1, -1, -1, "T/C 2 control register"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc0.ocr0", 0x31, 1, 0xff, -1, "T/C 0 output compare register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"jtag.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, - {"exint.emcucr", 0x36, 1, -1, -1, "extended MCU control register"}, - {"boot_load.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"usart1.ubrr1h", 0x3c, 1, 0x8f, -1, "USART 1 baud rate register high byte"}, - {"usart1.ucsr1c", 0x3c, 1, -1, -1, "USART control and status register C"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc3.etifr", 0x5c, 1, -1, -1, "extended T/C interrupt flag register"}, - {"tc3.etimsk", 0x5d, 1, -1, -1, "extended T/C interrupt mask register"}, - {"tc3.icr3", 0x60, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3b", 0x64, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3a", 0x66, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.tcnt3", 0x68, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.tccr3b", 0x6a, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3a", 0x6b, 1, -1, -1, "T/C 3 control register A"}, -}; - -// ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA -const Register_file rgftab_atmega164a[96] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"spi.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, -}; - -// ATmega165A ATmega165P ATmega165PA -const Register_file rgftab_atmega165a[86] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega169A ATmega169P ATmega169PA -const Register_file rgftab_atmega169a[106] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x3f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x3f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, - {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, - {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, -}; - -// ATmega256RFR2 -const Register_file rgftab_atmega256rfr2[271] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, - {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, - {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, - {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, - {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, - {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, - {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, - {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, - {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, - {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, - {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, - {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, - {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, - {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, - {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, - {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, - {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, - {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, - {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, - {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, - {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, - {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, - {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, - {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, - {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, - {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, - {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, - {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, - {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, - {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, - {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, - {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, - {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, - {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, - {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, - {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, - {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, - {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, - {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, - {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, - {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, - {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, - {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, - {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, - {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, - {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, - {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, - {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, - {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, - {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, - {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, - {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, - {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, - {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, - {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, - {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, - {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, - {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, - {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, - {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, - {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, - {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, - {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, - {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, - {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, - {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, - {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, - {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, - {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, - {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, - {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, - {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, - {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, - {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, - {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, - {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, - {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, - {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, - {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, - {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, - {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, - {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, - {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, - {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, - {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, - {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, - {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, - {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, - {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, - {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, - {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, - {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, - {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, - {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, - {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, - {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, - {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, - {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, - {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, - {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, - {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, - {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, - {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, - {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, - {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, - {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, - {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, - {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, - {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, - {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, - {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, - {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, - {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, - {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, - {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, - {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, - {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, - {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, - {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, - {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, - {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, - {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, - {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, -}; - -// ATmega324PB -const Register_file rgftab_atmega324pb[134] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x7f, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x7f, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x7f, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x19, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi0.spcr0", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi0.spsr0", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi0.spdr0", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsrb", 0x2f, 1, -1, -1, "analog comparator control and status register B"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cfd.xfdcsr", 0x42, 1, -1, -1, "XOSC failure detection control and status register"}, - {"cpu.prr2", 0x43, 1, -1, -1, "power reduction register 2"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x52, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, - {"exint.pcmsk4", 0x55, 1, -1, -1, "pin change interrupt mask register 4"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc4.tccr4a", 0x80, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x81, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x82, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x84, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x86, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x88, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x8a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"spi1.spcr1", 0x8c, 1, -1, -1, "SPI control register"}, - {"spi1.spsr1", 0x8d, 1, -1, -1, "SPI status register"}, - {"spi1.spdr1", 0x8e, 1, 0xff, -1, "SPI data register"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi0.twbr0", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi0.twsr0", 0x99, 1, -1, -1, "TWI status register"}, - {"twi0.twar0", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi0.twdr0", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi0.twcr0", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi0.twamr0", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ucsr0d", 0xa3, 1, -1, -1, "USART control and status register D"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ucsr1d", 0xab, 1, -1, -1, "USART control and status register D"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart2.ucsr2a", 0xb0, 1, -1, -1, "USART control and status register A"}, - {"usart2.ucsr2b", 0xb1, 1, -1, -1, "USART control and status register B"}, - {"usart2.ucsr2c", 0xb2, 1, -1, -1, "USART control and status register C"}, - {"usart2.ucsr2d", 0xb3, 1, -1, -1, "USART control and status register D"}, - {"usart2.ubrr2", 0xb4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, - {"usart2.udr2", 0xb6, 1, 0xff, -1, "USART 2 I/O data register"}, - {"twi1.twbr1", 0xb8, 1, 0xff, -1, "TWI bit rate register"}, - {"twi1.twsr1", 0xb9, 1, -1, -1, "TWI status register"}, - {"twi1.twar1", 0xba, 1, -1, -1, "TWI peripheral address register"}, - {"twi1.twdr1", 0xbb, 1, 0xff, -1, "TWI data register"}, - {"twi1.twcr1", 0xbc, 1, -1, -1, "TWI control register"}, - {"twi1.twamr1", 0xbd, 1, -1, -1, "TWI peripheral address mask register"}, -}; - -// ATmega325 ATmega325A ATmega325P ATmega325PA -const Register_file rgftab_atmega325[86] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega329 -const Register_file rgftab_atmega329[106] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, - {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr03", 0xcf, 1, 0x01, -1, "LCD data register 3"}, - {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr08", 0xd4, 1, 0x01, -1, "LCD data register 8"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, -}; - -// ATmega329A ATmega329PA -const Register_file rgftab_atmega329a[106] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, - {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr03", 0xcf, 1, 0x01, -1, "LCD data register 3"}, - {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr08", 0xd4, 1, 0x01, -1, "LCD data register 8"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, -}; - -// ATmega329P -const Register_file rgftab_atmega329p[106] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, - {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, - {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, -}; - -// ATmega406 -const Register_file rgftab_atmega406[79] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.portc", 0x08, 1, 0x01, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0x03, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0x03, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0x03, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"wakeup_timer.wutcsr", 0x42, 1, -1, -1, "wake-up timer control and status register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.fosccal", 0x46, 1, 0xff, -1, "fast oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.vadc", 0x58, 2, 0x0fff, -1, "VADC data register (16 bits)"}, - {"adc.vadcsr", 0x5a, 1, -1, -1, "VADC control and status register"}, - {"adc.vadmux", 0x5c, 1, -1, -1, "VADC multiplexer selection register"}, - {"cpu.didr0", 0x5e, 1, 0x0f, -1, "digital input disable register 0"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.ocr1al", 0x68, 1, 0xff, -1, "output compare 1 register A low byte"}, - {"tc1.ocr1ah", 0x69, 1, 0xff, -1, "output compare 1 register A high byte"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"twi.twbcsr", 0x9e, 1, -1, -1, "TWI bus control and status register"}, - {"cpu.ccsr", 0xa0, 1, -1, -1, "clock control and status register"}, - {"bandgap.bgccr", 0xb0, 1, -1, -1, "bandgap current calibration register"}, - {"bandgap.bgcrr", 0xb1, 1, 0xff, -1, "bandgap resistor calibration register"}, - {"coulomb_counter.cadac0", 0xc0, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac1", 0xc1, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac2", 0xc2, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadac3", 0xc3, 1, 0xff, -1, "ADC accumulate current register"}, - {"coulomb_counter.cadcsra", 0xc4, 1, -1, -1, "CC-ADC control and status register A"}, - {"coulomb_counter.cadcsrb", 0xc5, 1, -1, -1, "CC-ADC control and status register B"}, - {"coulomb_counter.cadrcc", 0xc6, 1, 0xff, -1, "CC-ADC regular charge current register"}, - {"coulomb_counter.cadrdc", 0xc7, 1, 0xff, -1, "CC-ADC regular discharge current register"}, - {"coulomb_counter.cadic", 0xc8, 2, 0xffff, -1, "CC-ADC instantaneous current register (16 bits)"}, - {"fet.fcsr", 0xd0, 1, -1, -1, "FET control and status register"}, - {"cell_balancing.cbcr", 0xd1, 1, -1, -1, "cell balancing control register"}, - {"battery_protection.bpir", 0xd2, 1, -1, -1, "battery protection interrupt register"}, - {"battery_protection.bpduv", 0xd3, 1, -1, -1, "battery protection deep under voltage register"}, - {"battery_protection.bpscd", 0xd4, 1, -1, -1, "battery protection short-circuit detection level register"}, - {"battery_protection.bpocd", 0xd5, 1, -1, -1, "battery protection overcurrent detection level register"}, - {"battery_protection.cbptr", 0xd6, 1, -1, -1, "current battery protection timing register"}, - {"battery_protection.bpcr", 0xd7, 1, -1, -1, "battery protection control register"}, - {"battery_protection.bpplr", 0xd8, 1, -1, -1, "battery protection parameter lock register"}, -}; - -// ATmega640 -const Register_file rgftab_atmega640[160] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart2.ucsr2a", 0x0b0, 1, -1, -1, "USART control and status register A"}, - {"usart2.ucsr2b", 0x0b1, 1, -1, -1, "USART control and status register B"}, - {"usart2.ucsr2c", 0x0b2, 1, -1, -1, "USART control and status register C"}, - {"usart2.ubrr2", 0x0b4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, - {"usart2.udr2", 0x0b6, 1, 0xff, -1, "USART 2 I/O data register"}, - {"porth.pinh", 0x0e0, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0x0e1, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0x0e2, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0x0e3, 1, 0xff, -1, "PORT J input register"}, - {"portj.ddrj", 0x0e4, 1, 0xff, -1, "PORT J data direction register"}, - {"portj.portj", 0x0e5, 1, 0xff, -1, "PORT J data register"}, - {"portk.pink", 0x0e6, 1, 0xff, -1, "PORT K input register"}, - {"portk.ddrk", 0x0e7, 1, 0xff, -1, "PORT K data direction register"}, - {"portk.portk", 0x0e8, 1, 0xff, -1, "PORT K data register"}, - {"portl.pinl", 0x0e9, 1, 0xff, -1, "PORT L input register"}, - {"portl.ddrl", 0x0ea, 1, 0xff, -1, "PORT L data direction register"}, - {"portl.portl", 0x0eb, 1, 0xff, -1, "PORT L data register"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"usart3.ucsr3a", 0x110, 1, -1, -1, "USART control and status register A"}, - {"usart3.ucsr3b", 0x111, 1, -1, -1, "USART control and status register B"}, - {"usart3.ucsr3c", 0x112, 1, -1, -1, "USART control and status register C"}, - {"usart3.ubrr3", 0x114, 2, 0x0fff, -1, "USART 3 baud rate register (16 bits)"}, - {"usart3.udr3", 0x116, 1, 0xff, -1, "USART 3 I/O data register"}, -}; - -// ATmega644 -const Register_file rgftab_atmega644[88] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega644A ATmega644P ATmega644PA -const Register_file rgftab_atmega644a[93] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x1fff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, -}; - -// ATmega645 ATmega645A ATmega645P -const Register_file rgftab_atmega645[86] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, -}; - -// ATmega649 ATmega649A ATmega649P -const Register_file rgftab_atmega649[106] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, - {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr3", 0xcf, 1, 0x01, -1, "LCD data register 3"}, - {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr8", 0xd4, 1, 0x01, -1, "LCD data register 8"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0x01, -1, "LCD data register 13"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0x01, -1, "LCD data register 18"}, -}; - -// ATmega1280 ATmega2560 -const Register_file rgftab_atmega1280[161] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usart2.ucsr2a", 0x0b0, 1, -1, -1, "USART control and status register A"}, - {"usart2.ucsr2b", 0x0b1, 1, -1, -1, "USART control and status register B"}, - {"usart2.ucsr2c", 0x0b2, 1, -1, -1, "USART control and status register C"}, - {"usart2.ubrr2", 0x0b4, 2, 0x0fff, -1, "USART 2 baud rate register (16 bits)"}, - {"usart2.udr2", 0x0b6, 1, 0xff, -1, "USART 2 I/O data register"}, - {"porth.pinh", 0x0e0, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0x0e1, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0x0e2, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0x0e3, 1, 0xff, -1, "PORT J input register"}, - {"portj.ddrj", 0x0e4, 1, 0xff, -1, "PORT J data direction register"}, - {"portj.portj", 0x0e5, 1, 0xff, -1, "PORT J data register"}, - {"portk.pink", 0x0e6, 1, 0xff, -1, "PORT K input register"}, - {"portk.ddrk", 0x0e7, 1, 0xff, -1, "PORT K data direction register"}, - {"portk.portk", 0x0e8, 1, 0xff, -1, "PORT K data register"}, - {"portl.pinl", 0x0e9, 1, 0xff, -1, "PORT L input register"}, - {"portl.ddrl", 0x0ea, 1, 0xff, -1, "PORT L data direction register"}, - {"portl.portl", 0x0eb, 1, 0xff, -1, "PORT L data register"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"usart3.ucsr3a", 0x110, 1, -1, -1, "USART control and status register A"}, - {"usart3.ucsr3b", 0x111, 1, -1, -1, "USART control and status register B"}, - {"usart3.ucsr3c", 0x112, 1, -1, -1, "USART control and status register C"}, - {"usart3.ubrr3", 0x114, 2, 0x0fff, -1, "USART 3 baud rate register (16 bits)"}, - {"usart3.udr3", 0x116, 1, 0xff, -1, "USART 3 I/O data register"}, -}; - -// ATmega1281 -const Register_file rgftab_atmega1281[138] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, -}; - -// ATmega1284 ATmega1284P -const Register_file rgftab_atmega1284[104] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, -1, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, -}; - -// ATmega2561 -const Register_file rgftab_atmega2561[139] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0x3f, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0x3f, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, 0x03, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"cpu.xmcra", 0x054, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x055, 1, -1, -1, "external memory control register B"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, -}; - -// ATmega2564RFR2 -const Register_file rgftab_atmega2564rfr2[271] = { // I/O memory [0, 479] + 32 - {"porta.pina", 0x000, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x001, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x002, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x00c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x00d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x00e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x00f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x010, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x011, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x012, 1, 0xff, -1, "port G input register"}, - {"portg.ddrg", 0x013, 1, 0xff, -1, "port G data direction register"}, - {"portg.portg", 0x014, 1, 0xff, -1, "port G data register"}, - {"tc0.tifr0", 0x015, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x016, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x017, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x018, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"tc4.tifr4", 0x019, 1, -1, -1, "T/C 4 interrupt flag register"}, - {"tc5.tifr5", 0x01a, 1, -1, -1, "T/C 5 interrupt flag register"}, - {"exint.pcifr", 0x01b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x01c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x01d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x01e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0xffff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x023, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x024, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x025, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x026, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x027, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x028, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"cpu.gpior1", 0x02a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x02b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x030, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x031, 1, -1, -1, "on-chip debug register"}, - {"cpu.smcr", 0x033, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x034, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"pwrctrl.mcucr", 0x035, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x03d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x040, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x041, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr2", 0x043, 1, -1, -1, "power reduction register 2"}, - {"cpu.prr0", 0x044, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x045, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x046, 1, -1, -1, "oscillator calibration register"}, - {"flash.bgcr", 0x047, 1, -1, -1, "bandgap calibration register"}, - {"exint.pcicr", 0x048, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x049, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x04a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x04b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x04c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x04d, 1, -1, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x04e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x04f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x050, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x051, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"tc4.timsk4", 0x052, 1, -1, -1, "T/C 4 interrupt mask register"}, - {"tc5.timsk5", 0x053, 1, -1, -1, "T/C 5 interrupt mask register"}, - {"flash.nemcr", 0x055, 1, -1, -1, "flash extended-mode control register"}, - {"adc.adcsrc", 0x057, 1, -1, -1, "ADC control and status register C"}, - {"adc.adc", 0x058, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x05a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x05b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x05c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr2", 0x05d, 1, -1, -1, "digital input disable register 2"}, - {"adc.didr0", 0x05e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x05f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x060, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x061, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x062, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x064, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x066, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x068, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x06a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x06c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x070, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x071, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x072, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x074, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x076, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x078, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x07a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x07c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc4.tccr4a", 0x080, 1, -1, -1, "T/C 4 control register A"}, - {"tc4.tccr4b", 0x081, 1, -1, -1, "T/C 4 control register B"}, - {"tc4.tccr4c", 0x082, 1, -1, -1, "T/C 4 control register C"}, - {"tc4.tcnt4", 0x084, 2, 0xffff, -1, "timer/counter 4 (16 bits)"}, - {"tc4.icr4", 0x086, 2, 0xffff, -1, "T/C 4 input capture register (16 bits)"}, - {"tc4.ocr4a", 0x088, 2, 0xffff, -1, "T/C 4 output compare register A (16 bits)"}, - {"tc4.ocr4b", 0x08a, 2, 0xffff, -1, "T/C 4 output compare register B (16 bits)"}, - {"tc4.ocr4c", 0x08c, 2, 0xffff, -1, "T/C 4 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x090, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x091, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x092, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x093, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x094, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x096, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x098, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x099, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x09a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x09b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x09c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x09d, 1, -1, -1, "TWI peripheral address mask register"}, - {"trx24.irq_mask1", 0x09e, 1, -1, -1, "transceiver interrupt enable register 1"}, - {"trx24.irq_status1", 0x09f, 1, -1, -1, "transceiver interrupt status register 1"}, - {"usart0.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0_spi.ucsr0a", 0x0a0, 1, -1, -1, "USART 0 HSPIM control and status register A"}, - {"usart0.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0_spi.ucsr0b", 0x0a1, 1, -1, -1, "USART 0 HSPIM control and status register B"}, - {"usart0.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0_spi.ucsr0c", 0x0a2, 1, -1, -1, "USART 0 HSPIM control and status register C"}, - {"usart0.ubrr0", 0x0a4, 2, 0xffff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0x0a6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"usart1.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1_spi.ucsr1a", 0x0a8, 1, -1, -1, "USART 1 HSPIM control and status register A"}, - {"usart1.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1_spi.ucsr1b", 0x0a9, 1, -1, -1, "USART 1 HSPIM control and status register B"}, - {"usart1.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1_spi.ucsr1c", 0x0aa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0x0ac, 2, 0xffff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0x0ae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"symcnt.scrstrll", 0x0b7, 1, -1, -1, "symbol counter received frame timestamp register LL byte"}, - {"symcnt.scrstrlh", 0x0b8, 1, -1, -1, "symbol counter received frame timestamp register LH byte"}, - {"symcnt.scrstrhl", 0x0b9, 1, -1, -1, "symbol counter received frame timestamp register HL byte"}, - {"symcnt.scrstrhh", 0x0ba, 1, -1, -1, "symbol counter received frame timestamp register HH byte"}, - {"symcnt.sccsr", 0x0bb, 1, -1, -1, "symbol counter compare source register"}, - {"symcnt.sccr0", 0x0bc, 1, -1, -1, "symbol counter control register 0"}, - {"symcnt.sccr1", 0x0bd, 1, -1, -1, "symbol counter control register 1"}, - {"symcnt.scsr", 0x0be, 1, -1, -1, "symbol counter status register"}, - {"symcnt.scirqm", 0x0bf, 1, -1, -1, "symbol counter interrupt mask register"}, - {"symcnt.scirqs", 0x0c0, 1, -1, -1, "symbol counter interrupt status register"}, - {"symcnt.sccntll", 0x0c1, 1, -1, -1, "symbol counter LL byte"}, - {"symcnt.sccntlh", 0x0c2, 1, -1, -1, "symbol counter LH byte"}, - {"symcnt.sccnthl", 0x0c3, 1, -1, -1, "symbol counter HL byte"}, - {"symcnt.sccnthh", 0x0c4, 1, -1, -1, "symbol counter HH byte"}, - {"symcnt.scbtsrll", 0x0c5, 1, -1, -1, "symbol counter beacon timestamp register LL byte"}, - {"symcnt.scbtsrlh", 0x0c6, 1, -1, -1, "symbol counter beacon timestamp register LH byte"}, - {"symcnt.scbtsrhl", 0x0c7, 1, -1, -1, "symbol counter beacon timestamp register HL byte"}, - {"symcnt.scbtsrhh", 0x0c8, 1, -1, -1, "symbol counter beacon timestamp register HH byte"}, - {"symcnt.sctsrll", 0x0c9, 1, -1, -1, "symbol counter frame timestamp register LL byte"}, - {"symcnt.sctsrlh", 0x0ca, 1, -1, -1, "symbol counter frame timestamp register LH byte"}, - {"symcnt.sctsrhl", 0x0cb, 1, -1, -1, "symbol counter frame timestamp register HL byte"}, - {"symcnt.sctsrhh", 0x0cc, 1, -1, -1, "symbol counter frame timestamp register HH byte"}, - {"symcnt.scocr3ll", 0x0cd, 1, -1, -1, "symbol counter output compare register 3 LL byte"}, - {"symcnt.scocr3lh", 0x0ce, 1, -1, -1, "symbol counter output compare register 3 LH byte"}, - {"symcnt.scocr3hl", 0x0cf, 1, -1, -1, "symbol counter output compare register 3 HL byte"}, - {"symcnt.scocr3hh", 0x0d0, 1, -1, -1, "symbol counter output compare register 3 HH byte"}, - {"symcnt.scocr2ll", 0x0d1, 1, -1, -1, "symbol counter output compare register 2 LL byte"}, - {"symcnt.scocr2lh", 0x0d2, 1, -1, -1, "symbol counter output compare register 2 LH byte"}, - {"symcnt.scocr2hl", 0x0d3, 1, -1, -1, "symbol counter output compare register 2 HL byte"}, - {"symcnt.scocr2hh", 0x0d4, 1, -1, -1, "symbol counter output compare register 2 HH byte"}, - {"symcnt.scocr1ll", 0x0d5, 1, -1, -1, "symbol counter output compare register 1 LL byte"}, - {"symcnt.scocr1lh", 0x0d6, 1, -1, -1, "symbol counter output compare register 1 LH byte"}, - {"symcnt.scocr1hl", 0x0d7, 1, -1, -1, "symbol counter output compare register 1 HL byte"}, - {"symcnt.scocr1hh", 0x0d8, 1, -1, -1, "symbol counter output compare register 1 HH byte"}, - {"symcnt.sctstrll", 0x0d9, 1, -1, -1, "symbol counter transmit frame timestamp register LL byte"}, - {"symcnt.sctstrlh", 0x0da, 1, -1, -1, "symbol counter transmit frame timestamp register LH byte"}, - {"symcnt.sctstrhl", 0x0db, 1, -1, -1, "symbol counter transmit frame timestamp register HL byte"}, - {"symcnt.sctstrhh", 0x0dc, 1, -1, -1, "symbol counter transmit frame timestamp register HH byte"}, - {"trx24.mafcr0", 0x0ec, 1, -1, -1, "multiple address filter configuration register 0"}, - {"trx24.mafcr1", 0x0ed, 1, -1, -1, "multiple address filter configuration register 1"}, - {"trx24.mafsa0l", 0x0ee, 1, -1, -1, "transceiver MAC short address register for frame filter 0 low byte"}, - {"trx24.mafsa0h", 0x0ef, 1, -1, -1, "transceiver MAC short address register for frame filter 0 high byte"}, - {"trx24.mafpa0l", 0x0f0, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 low byte"}, - {"trx24.mafpa0h", 0x0f1, 1, -1, -1, "transceiver personal area network ID register for frame filter 0 high byte"}, - {"trx24.mafsa1l", 0x0f2, 1, -1, -1, "transceiver MAC short address register for frame filter 1 low byte"}, - {"trx24.mafsa1h", 0x0f3, 1, -1, -1, "transceiver MAC short address register for frame filter 1 high byte"}, - {"trx24.mafpa1l", 0x0f4, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 low byte"}, - {"trx24.mafpa1h", 0x0f5, 1, -1, -1, "transceiver personal area network ID register for frame filter 1 high byte"}, - {"trx24.mafsa2l", 0x0f6, 1, -1, -1, "transceiver MAC short address register for frame filter 2 low byte"}, - {"trx24.mafsa2h", 0x0f7, 1, -1, -1, "transceiver MAC short address register for frame filter 2 high byte"}, - {"trx24.mafpa2l", 0x0f8, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 low byte"}, - {"trx24.mafpa2h", 0x0f9, 1, -1, -1, "transceiver personal area network ID register for frame filter 2 high byte"}, - {"trx24.mafsa3l", 0x0fa, 1, -1, -1, "transceiver MAC short address register for frame filter 3 low byte"}, - {"trx24.mafsa3h", 0x0fb, 1, -1, -1, "transceiver MAC short address register for frame filter 3 high byte"}, - {"trx24.mafpa3l", 0x0fc, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 low byte"}, - {"trx24.mafpa3h", 0x0fd, 1, -1, -1, "transceiver personal area network ID register for frame filter 3 high byte"}, - {"tc5.tccr5a", 0x100, 1, -1, -1, "T/C 5 control register A"}, - {"tc5.tccr5b", 0x101, 1, -1, -1, "T/C 5 control register B"}, - {"tc5.tccr5c", 0x102, 1, -1, -1, "T/C 5 control register C"}, - {"tc5.tcnt5", 0x104, 2, 0xffff, -1, "timer/counter 5 (16 bits)"}, - {"tc5.icr5", 0x106, 2, 0xffff, -1, "T/C 5 input capture register (16 bits)"}, - {"tc5.ocr5a", 0x108, 2, 0xffff, -1, "T/C 5 output compare register A (16 bits)"}, - {"tc5.ocr5b", 0x10a, 2, 0xffff, -1, "T/C 5 output compare register B (16 bits)"}, - {"tc5.ocr5c", 0x10c, 2, 0xffff, -1, "T/C 5 output compare register C (16 bits)"}, - {"pwrctrl.llcr", 0x10f, 1, -1, -1, "low leakage voltage regulator control register"}, - {"pwrctrl.lldrl", 0x110, 1, -1, -1, "low leakage voltage regulator data register low byte"}, - {"pwrctrl.lldrh", 0x111, 1, -1, -1, "low leakage voltage regulator data register high byte"}, - {"pwrctrl.drtram3", 0x112, 1, -1, -1, "data retention configuration register of SRAM 3"}, - {"pwrctrl.drtram2", 0x113, 1, -1, -1, "data retention configuration register of SRAM 2"}, - {"pwrctrl.drtram1", 0x114, 1, -1, -1, "data retention configuration register of SRAM 1"}, - {"pwrctrl.drtram0", 0x115, 1, -1, -1, "data retention configuration register of SRAM 0"}, - {"pwrctrl.dpds0", 0x116, 1, -1, -1, "port driver strength register 0"}, - {"pwrctrl.dpds1", 0x117, 1, -1, -1, "port driver strength register 1"}, - {"trx24.parcr", 0x118, 1, -1, -1, "power amplifier ramp up/down control register"}, - {"pwrctrl.trxpr", 0x119, 1, -1, -1, "transceiver pin register"}, - {"trx24.aes_ctrl", 0x11c, 1, -1, -1, "AES control register"}, - {"trx24.aes_status", 0x11d, 1, -1, -1, "AES status register"}, - {"trx24.aes_state", 0x11e, 1, -1, -1, "AES plain and cipher text buffer register"}, - {"trx24.aes_key", 0x11f, 1, -1, -1, "AES encryption and decryption key buffer register"}, - {"trx24.trx_status", 0x121, 1, -1, -1, "transceiver status register"}, - {"trx24.trx_state", 0x122, 1, -1, -1, "transceiver state control register"}, - {"trx24.trx_ctrl_0", 0x123, 1, -1, -1, "reserved register"}, - {"trx24.trx_ctrl_1", 0x124, 1, -1, -1, "transceiver control register 1"}, - {"trx24.phy_tx_pwr", 0x125, 1, -1, -1, "transceiver transmit power control register"}, - {"trx24.phy_rssi", 0x126, 1, -1, -1, "receiver signal strength indicator register"}, - {"trx24.phy_ed_level", 0x127, 1, -1, -1, "transceiver energy detection level register"}, - {"trx24.phy_cc_cca", 0x128, 1, -1, -1, "transceiver clear channel assessment control register"}, - {"trx24.cca_thres", 0x129, 1, -1, -1, "transceiver CCA threshold setting register"}, - {"trx24.rx_ctrl", 0x12a, 1, -1, -1, "transceiver receive control register"}, - {"trx24.sfd_value", 0x12b, 1, -1, -1, "start of frame delimiter value register"}, - {"trx24.trx_ctrl_2", 0x12c, 1, -1, -1, "transceiver control register 2"}, - {"trx24.ant_div", 0x12d, 1, -1, -1, "antenna diversity control register"}, - {"trx24.irq_mask", 0x12e, 1, -1, -1, "transceiver interrupt enable register"}, - {"trx24.irq_status", 0x12f, 1, -1, -1, "transceiver interrupt status register"}, - {"trx24.vreg_ctrl", 0x130, 1, -1, -1, "voltage regulator control and status register"}, - {"trx24.batmon", 0x131, 1, -1, -1, "battery monitor control and status register"}, - {"trx24.xosc_ctrl", 0x132, 1, -1, -1, "crystal oscillator control register"}, - {"trx24.cc_ctrl_0", 0x133, 1, -1, -1, "channel control register 0"}, - {"trx24.cc_ctrl_1", 0x134, 1, -1, -1, "channel control register 1"}, - {"trx24.rx_syn", 0x135, 1, -1, -1, "transceiver receiver sensitivity control register"}, - {"trx24.trx_rpc", 0x136, 1, -1, -1, "transceiver reduced power consumption control register"}, - {"trx24.xah_ctrl_1", 0x137, 1, -1, -1, "transceiver acknowledgment frame control register 1"}, - {"trx24.ftn_ctrl", 0x138, 1, -1, -1, "transceiver filter tuning control register"}, - {"trx24.pll_cf", 0x13a, 1, -1, -1, "transceiver center frequency calibration control register"}, - {"trx24.pll_dcu", 0x13b, 1, -1, -1, "transceiver delay cell calibration control register"}, - {"trx24.part_num", 0x13c, 1, -1, -1, "device identification register (part number)"}, - {"trx24.version_num", 0x13d, 1, -1, -1, "device identification register (version number)"}, - {"trx24.man_id_0", 0x13e, 1, -1, -1, "device manufacturer identification register low byte"}, - {"trx24.man_id_1", 0x13f, 1, -1, -1, "device manufacturer identification register high byte"}, - {"trx24.short_addr_0", 0x140, 1, -1, -1, "transceiver MAC short address register low byte"}, - {"trx24.short_addr_1", 0x141, 1, -1, -1, "transceiver MAC short address register high byte"}, - {"trx24.pan_id_0", 0x142, 1, -1, -1, "transceiver personal area network ID register low byte"}, - {"trx24.pan_id_1", 0x143, 1, -1, -1, "transceiver personal area network ID register high byte"}, - {"trx24.ieee_addr_0", 0x144, 1, -1, -1, "transceiver MAC IEEE address register 0"}, - {"trx24.ieee_addr_1", 0x145, 1, -1, -1, "transceiver MAC IEEE address register 1"}, - {"trx24.ieee_addr_2", 0x146, 1, -1, -1, "transceiver MAC IEEE address register 2"}, - {"trx24.ieee_addr_3", 0x147, 1, -1, -1, "transceiver MAC IEEE address register 3"}, - {"trx24.ieee_addr_4", 0x148, 1, -1, -1, "transceiver MAC IEEE address register 4"}, - {"trx24.ieee_addr_5", 0x149, 1, -1, -1, "transceiver MAC IEEE address register 5"}, - {"trx24.ieee_addr_6", 0x14a, 1, -1, -1, "transceiver MAC IEEE address register 6"}, - {"trx24.ieee_addr_7", 0x14b, 1, -1, -1, "transceiver MAC IEEE address register 7"}, - {"trx24.xah_ctrl_0", 0x14c, 1, -1, -1, "transceiver extended operating mode control register"}, - {"trx24.csma_seed_0", 0x14d, 1, -1, -1, "transceiver CSMA-CA random number generator seed register"}, - {"trx24.csma_seed_1", 0x14e, 1, -1, -1, "transceiver acknowledgment frame control register 2"}, - {"trx24.csma_be", 0x14f, 1, -1, -1, "transceiver CSMA-CA back-off exponent control register"}, - {"trx24.tst_ctrl_digi", 0x156, 1, -1, -1, "transceiver digital test control register"}, - {"trx24.tst_rx_length", 0x15b, 1, -1, -1, "transceiver received frame length register"}, - {"trx24.trxfbst", 0x160, 1, 0xff, -1, "start of frame buffer register"}, - {"trx24.trxfbend", 0x1df, 1, 0xff, -1, "end of frame buffer register"}, -}; - -// ATmega3250 ATmega3250A ATmega3250P ATmega3250PA -const Register_file rgftab_atmega3250[94] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, - {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, - {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, -}; - -// ATmega3290 ATmega3290A -const Register_file rgftab_atmega3290[118] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, - {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, - {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, - {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr03", 0xcf, 1, 0xff, -1, "LCD data register 3"}, - {"lcd.lcddr04", 0xd0, 1, 0xff, -1, "LCD data register 4"}, - {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr08", 0xd4, 1, 0xff, -1, "LCD data register 8"}, - {"lcd.lcddr09", 0xd5, 1, 0xff, -1, "LCD data register 9"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, - {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, - {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, -}; - -// ATmega3290P -const Register_file rgftab_atmega3290p[118] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, - {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, - {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, - {"lcd.lcddr00", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr01", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr02", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr03", 0xcf, 1, 0xff, -1, "LCD data register 3"}, - {"lcd.lcddr04", 0xd0, 1, 0xff, -1, "LCD data register 4"}, - {"lcd.lcddr05", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr06", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr07", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr08", 0xd4, 1, 0xff, -1, "LCD data register 8"}, - {"lcd.lcddr09", 0xd5, 1, 0xff, -1, "LCD data register 9"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, - {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, - {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, -}; - -// ATmega3290PA -const Register_file rgftab_atmega3290pa[118] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x03ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, - {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, - {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, -1, -1, "LCD contrast control register"}, - {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr3", 0xcf, 1, 0xff, -1, "LCD data register 3"}, - {"lcd.lcddr4", 0xd0, 1, 0xff, -1, "LCD data register 4"}, - {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr8", 0xd4, 1, 0xff, -1, "LCD data register 8"}, - {"lcd.lcddr9", 0xd5, 1, 0xff, -1, "LCD data register 9"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, - {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, - {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, -}; - -// ATmega6450 ATmega6450A ATmega6450P -const Register_file rgftab_atmega6450[94] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, - {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, - {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, -}; - -// ATmega6490 ATmega6490A ATmega6490P -const Register_file rgftab_atmega6490[118] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"portg.ping", 0x12, 1, 0x3f, -1, "port G input register"}, - {"portg.ddrg", 0x13, 1, 0x1f, -1, "port G data direction register"}, - {"portg.portg", 0x14, 1, 0x1f, -1, "port G data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x07ff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"exint.pcmsk1", 0x4c, 1, 0xff, -1, "pin change interrupt mask register 1"}, - {"exint.pcmsk2", 0x4d, 1, 0xff, -1, "pin change interrupt mask register 2"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"exint.pcmsk3", 0x53, 1, 0x7f, -1, "pin change interrupt mask register 3"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usart0.ucsr0a", 0xa0, 1, -1, -1, "USART 0 control and status register A"}, - {"usart0.ucsr0b", 0xa1, 1, -1, -1, "USART 0 control and status register B"}, - {"usart0.ucsr0c", 0xa2, 1, -1, -1, "USART 0 control and status register C"}, - {"usart0.ubrr0", 0xa4, 2, 0x0fff, -1, "USART 0 baud rate register (16 bits)"}, - {"usart0.udr0", 0xa6, 1, 0xff, -1, "USART 0 I/O data register"}, - {"porth.pinh", 0xb8, 1, 0xff, -1, "PORT H input register"}, - {"porth.ddrh", 0xb9, 1, 0xff, -1, "PORT H data direction register"}, - {"porth.porth", 0xba, 1, 0xff, -1, "PORT H data register"}, - {"portj.pinj", 0xbb, 1, 0x7f, -1, "PORT J input register"}, - {"portj.ddrj", 0xbc, 1, 0x7f, -1, "PORT J data direction register"}, - {"portj.portj", 0xbd, 1, 0x7f, -1, "PORT J data register"}, - {"lcd.lcdcra", 0xc4, 1, -1, -1, "LCD control register A"}, - {"lcd.lcdcrb", 0xc5, 1, -1, -1, "LCD control and status register B"}, - {"lcd.lcdfrr", 0xc6, 1, -1, -1, "LCD frame rate register"}, - {"lcd.lcdccr", 0xc7, 1, 0xef, -1, "LCD contrast control register"}, - {"lcd.lcddr0", 0xcc, 1, 0xff, -1, "LCD data register 0"}, - {"lcd.lcddr1", 0xcd, 1, 0xff, -1, "LCD data register 1"}, - {"lcd.lcddr2", 0xce, 1, 0xff, -1, "LCD data register 2"}, - {"lcd.lcddr3", 0xcf, 1, 0xff, -1, "LCD data register 3"}, - {"lcd.lcddr4", 0xd0, 1, 0xff, -1, "LCD data register 4"}, - {"lcd.lcddr5", 0xd1, 1, 0xff, -1, "LCD data register 5"}, - {"lcd.lcddr6", 0xd2, 1, 0xff, -1, "LCD data register 6"}, - {"lcd.lcddr7", 0xd3, 1, 0xff, -1, "LCD data register 7"}, - {"lcd.lcddr8", 0xd4, 1, 0xff, -1, "LCD data register 8"}, - {"lcd.lcddr9", 0xd5, 1, 0xff, -1, "LCD data register 9"}, - {"lcd.lcddr10", 0xd6, 1, 0xff, -1, "LCD data register 10"}, - {"lcd.lcddr11", 0xd7, 1, 0xff, -1, "LCD data register 11"}, - {"lcd.lcddr12", 0xd8, 1, 0xff, -1, "LCD data register 12"}, - {"lcd.lcddr13", 0xd9, 1, 0xff, -1, "LCD data register 13"}, - {"lcd.lcddr14", 0xda, 1, 0xff, -1, "LCD data register 14"}, - {"lcd.lcddr15", 0xdb, 1, 0xff, -1, "LCD data register 15"}, - {"lcd.lcddr16", 0xdc, 1, 0xff, -1, "LCD data register 16"}, - {"lcd.lcddr17", 0xdd, 1, 0xff, -1, "LCD data register 17"}, - {"lcd.lcddr18", 0xde, 1, 0xff, -1, "LCD data register 18"}, - {"lcd.lcddr19", 0xdf, 1, 0xff, -1, "LCD data register 19"}, -}; - -// ATmega8535 -const Register_file rgftab_atmega8535[67] = { // I/O memory [0, 63] + 32 - {"twi.twbr", 0x00, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x01, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x02, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x03, 1, 0xff, -1, "TWI data register"}, - {"adc.adc", 0x04, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.admux", 0x07, 1, -1, -1, "ADC multiplexer selection register"}, - {"ac.acsr", 0x08, 1, -1, -1, "analog comparator control and status register"}, - {"usart.ubrrl", 0x09, 1, 0xff, -1, "USART baud rate register low byte"}, - {"usart.ucsrb", 0x0a, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsra", 0x0b, 1, -1, -1, "USART control and status register A"}, - {"usart.udr", 0x0c, 1, 0xff, -1, "USART I/O data register"}, - {"spi.spcr", 0x0d, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x0e, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x0f, 1, 0xff, -1, "SPI data register"}, - {"portd.pind", 0x10, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x11, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x12, 1, 0xff, -1, "port D data register"}, - {"portc.pinc", 0x13, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x14, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x15, 1, 0xff, -1, "port C data register"}, - {"portb.pinb", 0x16, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x17, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x18, 1, 0xff, -1, "port B data register"}, - {"porta.pina", 0x19, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x1a, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x1b, 1, 0xff, -1, "port A data register"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"usart.ubrrh", 0x20, 1, -1, -1, "USART baud rate register high byte"}, - {"usart.ucsrc", 0x20, 1, -1, -1, "USART control and status register C"}, - {"wdt.wdtcr", 0x21, 1, -1, -1, "watchdog timer control register"}, - {"tc2.assr", 0x22, 1, -1, -1, "asynchronous status register"}, - {"tc2.ocr2", 0x23, 1, 0xff, -1, "T/C 2 output compare register"}, - {"tc2.tcnt2", 0x24, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.tccr2", 0x25, 1, -1, -1, "T/C 2 control register"}, - {"tc1.icr1", 0x26, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1b", 0x28, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1a", 0x2a, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.tcnt1", 0x2c, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.tccr1b", 0x2e, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1a", 0x2f, 1, -1, -1, "T/C 1 control register A"}, - {"adc.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc0.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"tc2.sfior", 0x30, 1, -1, -1, "special function I/O register"}, - {"cpu.osccal", 0x31, 1, 0xff, -1, "oscillator calibration register"}, - {"tc0.tcnt0", 0x32, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.tccr0", 0x33, 1, -1, -1, "T/C 0 control register"}, - {"cpu.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"exint.mcucsr", 0x34, 1, -1, -1, "MCU control and status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"exint.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"twi.twcr", 0x36, 1, -1, -1, "TWI control register"}, - {"cpu.spmcr", 0x37, 1, -1, -1, "store program memory control register"}, - {"tc0.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc1.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc2.tifr", 0x38, 1, -1, -1, "T/C interrupt flag register"}, - {"tc0.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc1.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"tc2.timsk", 0x39, 1, -1, -1, "T/C interrupt mask register"}, - {"exint.gifr", 0x3a, 1, -1, -1, "general interrupt flag register"}, - {"exint.gicr", 0x3b, 1, -1, -1, "general interrupt control register"}, - {"tc0.ocr0", 0x3c, 1, 0xff, -1, "T/C 0 output compare register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, -}; - -// AT90PWM1 -const Register_file rgftab_at90pwm1[92] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, 0x9f, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, - {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, - {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, - {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, - {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, - {"psc0.picr0", 0xbe, 2, -1, -1, "PSC 0 input capture register (16 bits)"}, - {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, - {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, - {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.picr1", 0xce, 2, 0x0fff, -1, "PSC 1 input capture register (16 bits)"}, - {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, - {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, - {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, - {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, -}; - -// AT90PWM2B -const Register_file rgftab_at90pwm2b[100] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, - {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, - {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, - {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, - {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, - {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, - {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, - {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, - {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, - {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, - {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, - {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, - {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, - {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, - {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, - {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, - {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, - {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, - {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, -}; - -// AT90PWM3 -const Register_file rgftab_at90pwm3[115] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, -1, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, -1, -1, "T/C 1 output compare register B (16 bits)"}, - {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, - {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, - {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, - {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, - {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, - {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, - {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, - {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, - {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, - {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, - {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, - {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, - {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, - {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, - {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, - {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, - {"psc0.picr0", 0xbe, 2, 0x0fff, -1, "PSC 0 input capture register (16 bits)"}, - {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, - {"psc1.ocr1sa", 0xc2, 2, 0x0fff, -1, "T/C 1 output compare SA register (16 bits)"}, - {"psc1.ocr1ra", 0xc4, 2, 0x0fff, -1, "T/C 1 output compare RA register (16 bits)"}, - {"psc1.ocr1sb", 0xc6, 2, 0x0fff, -1, "T/C 1 output compare SB register (16 bits)"}, - {"psc1.ocr1rb", 0xc8, 2, 0xffff, -1, "T/C 1 output compare RB register (16 bits)"}, - {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, - {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, - {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.picr1", 0xce, 2, 0x0fff, -1, "PSC 1 input capture register (16 bits)"}, - {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, - {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, - {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, - {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, -}; - -// AT90PWM3B -const Register_file rgftab_at90pwm3b[115] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, 0xff, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, -1, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, -1, -1, "T/C 1 output compare register B (16 bits)"}, - {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, - {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, - {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, - {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, - {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, - {"usart.ubrr", 0xa4, 2, -1, -1, "USART baud rate register (16 bits)"}, - {"usart.udr", 0xa6, 1, -1, -1, "USART I/O data register"}, - {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, - {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, - {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, - {"eusart.mubrr", 0xac, 2, -1, -1, "manchester receiver baud rate register (16 bits)"}, - {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, - {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc0.ocr0sa", 0xb2, 2, -1, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.ocr0ra", 0xb4, 2, -1, -1, "output compare 0 RA register (16 bits)"}, - {"psc0.ocr0sb", 0xb6, 2, -1, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0xb8, 2, -1, -1, "output compare 0 RB register (16 bits)"}, - {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, - {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, - {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, - {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, - {"psc1.ocr1sa", 0xc2, 2, -1, -1, "T/C 1 output compare SA register (16 bits)"}, - {"psc1.ocr1ra", 0xc4, 2, -1, -1, "T/C 1 output compare RA register (16 bits)"}, - {"psc1.ocr1sb", 0xc6, 2, -1, -1, "T/C 1 output compare SB register (16 bits)"}, - {"psc1.ocr1rb", 0xc8, 2, -1, -1, "T/C 1 output compare RB register (16 bits)"}, - {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, - {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, - {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.picr1", 0xce, 2, -1, -1, "PSC 1 input capture register (16 bits)"}, - {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.ocr2sa", 0xd2, 2, -1, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.ocr2ra", 0xd4, 2, -1, -1, "output compare 2 RA register (16 bits)"}, - {"psc2.ocr2sb", 0xd6, 2, -1, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0xd8, 2, -1, -1, "output compare 2 RB register (16 bits)"}, - {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, - {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.picr2", 0xde, 2, -1, -1, "PSC 2 input capture register (16 bits)"}, -}; - -// AT90PWM161 -const Register_file rgftab_at90pwm161[86] = { // I/O memory [0, 223] + 32 - {"ac.acsr", 0x00, 1, -1, -1, "analog comparator control and status register"}, - {"tc1.timsk1", 0x01, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc1.tifr1", 0x02, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"adc.adcsra", 0x06, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x07, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x08, 1, -1, -1, "ADC multiplexer selection register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"psc0.pim0", 0x0f, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc0.pifr0", 0x10, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pcnf0", 0x11, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0x12, 1, -1, -1, "PSC 0 control register"}, - {"psc2.pim2", 0x13, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"psc2.pifr2", 0x14, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pcnf2", 0x15, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0x16, 1, -1, -1, "PSC 2 control register"}, - {"spi.spcr", 0x17, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x18, 1, -1, -1, "SPI status register"}, - {"cpu.gpior0", 0x19, 1, -1, -1, "general purpose I/O register 0"}, - {"cpu.gpior1", 0x1a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1b, 1, -1, -1, "general purpose I/O register 2"}, - {"eeprom.eecr", 0x1c, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x1d, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x1e, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"exint.eifr", 0x20, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x21, 1, -1, -1, "external interrupt mask register"}, - {"psc0.ocr0sb", 0x22, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0x24, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, - {"psc2.ocr2sb", 0x26, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0x28, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, - {"psc0.ocr0ra", 0x2a, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, - {"adc.adc", 0x2c, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"psc2.ocr2ra", 0x2e, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"spi.spdr", 0x36, 1, 0xff, -1, "SPI data register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"dac.dacl", 0x38, 1, -1, -1, "DAC data register low byte"}, - {"dac.dach", 0x39, 1, -1, -1, "DAC data register high byte"}, - {"tc1.tcnt1", 0x3a, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"psc0.ocr0sa", 0x40, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.pfrc0a", 0x42, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0x43, 1, -1, -1, "PSC 0 input B control register"}, - {"psc2.ocr2sa", 0x44, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.pfrc2a", 0x46, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0x47, 1, -1, -1, "PSC 2 input B control register"}, - {"psc0.picr0", 0x48, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, - {"psc0.psoc0", 0x4a, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc2.picr2l", 0x4c, 1, 0xff, -1, "PSC 2 input capture register low byte"}, - {"psc2.picr2h", 0x4d, 1, -1, -1, "PSC 2 input capture register high byte"}, - {"psc2.psoc2", 0x4e, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0x4f, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.pcnfe2", 0x50, 1, -1, -1, "PSC 2 enhanced configuration register"}, - {"psc2.pasdly2", 0x51, 1, 0xff, -1, "analog synchronization delay register"}, - {"dac.dacon", 0x56, 1, -1, -1, "DAC control register"}, - {"adc.didr0", 0x57, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x58, 1, -1, -1, "digital input disable register 1"}, - {"adc.amp0csr", 0x59, 1, -1, -1, "amplifier 0 control and status register"}, - {"ac.ac1econ", 0x5a, 1, -1, -1, "analog comparator 1 extended control register"}, - {"ac.ac2econ", 0x5b, 1, -1, -1, "analog comparator 2 extended control register"}, - {"ac.ac3econ", 0x5c, 1, -1, -1, "analog comparator 3 extended control register"}, - {"ac.ac1con", 0x5d, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x5e, 1, -1, -1, "analog comparator 2 control register"}, - {"ac.ac3con", 0x5f, 1, -1, -1, "analog comparator 3 control register"}, - {"cpu.bgcrr", 0x60, 1, -1, -1, "bandgap resistor calibration register"}, - {"cpu.bgccr", 0x61, 1, -1, -1, "bandgap current calibration register"}, - {"wdt.wdtcsr", 0x62, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x63, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkcsr", 0x64, 1, -1, -1, "clock control and status register"}, - {"cpu.clkselr", 0x65, 1, -1, -1, "clock selection register"}, - {"cpu.prr", 0x66, 1, -1, -1, "power reduction register"}, - {"cpu.pllcsr", 0x67, 1, -1, -1, "PLL control and status register"}, - {"cpu.osccal", 0x68, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.eicra", 0x69, 1, -1, -1, "external interrupt control register A"}, - {"tc1.tccr1b", 0x6a, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.icr1", 0x6c, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, -}; - -// AT90PWM216 -const Register_file rgftab_at90pwm216[102] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, 0x8f, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, - {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, - {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, - {"usart.ubrrl", 0xa4, 1, -1, -1, "USART baud rate register low byte"}, - {"usart.ubrrh", 0xa5, 1, -1, -1, "USART baud rate register high byte"}, - {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, - {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, - {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, - {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, - {"eusart.mubrrl", 0xac, 1, -1, -1, "manchester receiver baud rate register low byte"}, - {"eusart.mubrrh", 0xad, 1, -1, -1, "manchester receiver baud rate register high byte"}, - {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, - {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, - {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, - {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, - {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, - {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, - {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, - {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, - {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, - {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.picr2", 0xde, 2, 0x8fff, -1, "PSC 2 input capture register (16 bits)"}, -}; - -// AT90PWM316 -const Register_file rgftab_at90pwm316[117] = { // I/O memory [0, 223] + 32 - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0x07, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0x07, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0x07, -1, "port E data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"cpu.gpior1", 0x19, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x1a, 1, -1, -1, "general purpose I/O register 2"}, - {"cpu.gpior3", 0x1b, 1, -1, -1, "general purpose I/O register 3"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, -1, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc1.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, -1, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, -1, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, -1, -1, "T/C 0 output compare register B"}, - {"cpu.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, -1, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0x7f, -1, "oscillator calibration register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"adc.amp0csr", 0x56, 1, -1, -1, "amplifier 0 control and status register"}, - {"adc.amp1csr", 0x57, 1, -1, -1, "amplifier 1 control and status register"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"adc.adcsrb", 0x5b, 1, 0x8f, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"adc.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"psc0.pifr0", 0x80, 1, -1, -1, "PSC 0 interrupt flag register"}, - {"psc0.pim0", 0x81, 1, -1, -1, "PSC 0 interrupt mask register"}, - {"psc1.pifr1", 0x82, 1, -1, -1, "PSC 1 interrupt flag register"}, - {"psc1.pim1", 0x83, 1, -1, -1, "PSC 1 interrupt mask register"}, - {"psc2.pifr2", 0x84, 1, -1, -1, "PSC 2 interrupt flag register"}, - {"psc2.pim2", 0x85, 1, -1, -1, "PSC 2 interrupt mask register"}, - {"dac.dacon", 0x8a, 1, -1, -1, "DAC control register"}, - {"dac.dac", 0x8b, 2, -1, -1, "DAC data register (16 bits)"}, - {"ac.ac0con", 0x8d, 1, -1, -1, "analog comparator 0 control register"}, - {"ac.ac1con", 0x8e, 1, -1, -1, "analog comparator 1 control register"}, - {"ac.ac2con", 0x8f, 1, -1, -1, "analog comparator 2 control register"}, - {"usart.ucsra", 0xa0, 1, -1, -1, "USART control and status register A"}, - {"usart.ucsrb", 0xa1, 1, -1, -1, "USART control and status register B"}, - {"usart.ucsrc", 0xa2, 1, -1, -1, "USART control and status register C"}, - {"usart.ubrrl", 0xa4, 1, -1, -1, "USART baud rate register low byte"}, - {"usart.ubrrh", 0xa5, 1, -1, -1, "USART baud rate register high byte"}, - {"usart.udr", 0xa6, 1, 0xff, -1, "USART I/O data register"}, - {"eusart.eucsra", 0xa8, 1, -1, -1, "EUSART control and status register A"}, - {"eusart.eucsrb", 0xa9, 1, -1, -1, "EUSART control register B"}, - {"eusart.eucsrc", 0xaa, 1, -1, -1, "EUSART status register C"}, - {"eusart.mubrrl", 0xac, 1, -1, -1, "manchester receiver baud rate register low byte"}, - {"eusart.mubrrh", 0xad, 1, -1, -1, "manchester receiver baud rate register high byte"}, - {"eusart.eudr", 0xae, 1, 0xff, -1, "EUSART I/O data register"}, - {"psc0.psoc0", 0xb0, 1, -1, -1, "PSC 0 synchro and output configuration register"}, - {"psc0.ocr0sa", 0xb2, 2, 0x0fff, -1, "output compare 0 SA register (16 bits)"}, - {"psc0.ocr0ra", 0xb4, 2, 0x0fff, -1, "output compare 0 RA register (16 bits)"}, - {"psc0.ocr0sb", 0xb6, 2, 0x0fff, -1, "output compare 0 SB register (16 bits)"}, - {"psc0.ocr0rb", 0xb8, 2, 0xffff, -1, "output compare 0 RB register (16 bits)"}, - {"psc0.pcnf0", 0xba, 1, -1, -1, "PSC 0 configuration register"}, - {"psc0.pctl0", 0xbb, 1, -1, -1, "PSC 0 control register"}, - {"psc0.pfrc0a", 0xbc, 1, -1, -1, "PSC 0 input A control register"}, - {"psc0.pfrc0b", 0xbd, 1, -1, -1, "PSC 0 input B control register"}, - {"psc0.picr0", 0xbe, 2, 0x8fff, -1, "PSC 0 input capture register (16 bits)"}, - {"psc1.psoc1", 0xc0, 1, -1, -1, "PSC 1 synchro and output configuration register"}, - {"psc1.ocr1sa", 0xc2, 2, 0x0fff, -1, "T/C 1 output compare SA register (16 bits)"}, - {"psc1.ocr1ra", 0xc4, 2, 0x0fff, -1, "T/C 1 output compare RA register (16 bits)"}, - {"psc1.ocr1sb", 0xc6, 2, 0x0fff, -1, "T/C 1 output compare SB register (16 bits)"}, - {"psc1.ocr1rb", 0xc8, 2, 0xffff, -1, "T/C 1 output compare RB register (16 bits)"}, - {"psc1.pcnf1", 0xca, 1, -1, -1, "PSC 1 configuration register"}, - {"psc1.pctl1", 0xcb, 1, -1, -1, "PSC 1 control register"}, - {"psc1.pfrc1a", 0xcc, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.pfrc1b", 0xcd, 1, -1, -1, "PSC 1 input B control register"}, - {"psc1.picr1", 0xce, 2, 0x8fff, -1, "PSC 1 input capture register (16 bits)"}, - {"psc2.psoc2", 0xd0, 1, -1, -1, "PSC 2 synchro and output configuration register"}, - {"psc2.pom2", 0xd1, 1, -1, -1, "PSC 2 output matrix register"}, - {"psc2.ocr2sa", 0xd2, 2, 0x0fff, -1, "output compare 2 SA register (16 bits)"}, - {"psc2.ocr2ra", 0xd4, 2, 0x0fff, -1, "output compare 2 RA register (16 bits)"}, - {"psc2.ocr2sb", 0xd6, 2, 0x0fff, -1, "output compare 2 SB register (16 bits)"}, - {"psc2.ocr2rb", 0xd8, 2, 0xffff, -1, "output compare 2 RB register (16 bits)"}, - {"psc2.pcnf2", 0xda, 1, -1, -1, "PSC 2 configuration register"}, - {"psc2.pctl2", 0xdb, 1, -1, -1, "PSC 2 control register"}, - {"psc2.pfrc2a", 0xdc, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.pfrc2b", 0xdd, 1, -1, -1, "PSC 2 input B control register"}, - {"psc2.picr2", 0xde, 2, 0x8fff, -1, "PSC 2 input capture register (16 bits)"}, -}; - -// AT90USB646 AT90USB647 AT90USB1287 -const Register_file rgftab_at90usb646[157] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, - {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"usb_host.uhcon", 0x7e, 1, -1, -1, "UHCON register"}, - {"usb_host.uhint", 0x7f, 1, -1, -1, "UHINT register"}, - {"usb_host.uhien", 0x80, 1, -1, -1, "UHIEN register"}, - {"usb_host.uhaddr", 0x81, 1, 0x7f, -1, "USB host address register"}, - {"usb_host.uhfnum", 0x82, 2, 0x07ff, -1, "UHFNUM register (16 bits)"}, - {"usb_host.uhflen", 0x84, 1, 0xff, -1, "UHFLEN register"}, - {"usb_host.upinrqx", 0x85, 1, 0xff, -1, "UPINRQX register"}, - {"usb_host.upintx", 0x86, 1, -1, -1, "UPINTX register"}, - {"usb_host.upnum", 0x87, 1, 0x07, -1, "UPNUM register"}, - {"usb_host.uprst", 0x88, 1, -1, -1, "UPRST register"}, - {"usb_host.upconx", 0x89, 1, -1, -1, "UPCONX register"}, - {"usb_host.upcfg0x", 0x8a, 1, -1, -1, "UPCFG0X register"}, - {"usb_host.upcfg1x", 0x8b, 1, -1, -1, "UPCFG1X register"}, - {"usb_host.upstax", 0x8c, 1, -1, -1, "UPSTAX register"}, - {"usb_host.upcfg2x", 0x8d, 1, 0xff, -1, "UPCFG2X register"}, - {"usb_host.upienx", 0x8e, 1, -1, -1, "UPIENX register"}, - {"usb_host.updatx", 0x8f, 1, 0xff, -1, "UPDATX register"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usb_global.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, - {"usb_global.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, - {"usb_global.usbsta", 0xb9, 1, -1, -1, "USB status register"}, - {"usb_global.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, - {"usb_global.otgcon", 0xbd, 1, -1, -1, "OTGCON register"}, - {"usb_global.otgien", 0xbe, 1, -1, -1, "OTGIEN register"}, - {"usb_global.otgint", 0xbf, 1, -1, -1, "OTGINT register"}, - {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, - {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, - {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, - {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, - {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, - {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, - {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, - {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, - {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, - {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, - {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, - {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, - {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, - {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, - {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, - {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, - {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, - {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, - {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, - {"usb_host.uperrx", 0xd5, 1, -1, -1, "UPERRX register"}, - {"usb_host.upbclx", 0xd6, 1, 0xff, -1, "UPBCLX register"}, - {"usb_host.upbchx", 0xd7, 1, 0x07, -1, "UPBCHX register"}, - {"usb_host.upint", 0xd8, 1, 0x7f, -1, "UPINT register"}, - {"usb_global.otgtcon", 0xd9, 1, -1, -1, "OTGTCON register"}, -}; - -// AT90USB1286 -const Register_file rgftab_at90usb1286[132] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, - {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, - {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, - {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, - {"porte.pine", 0x0c, 1, 0xff, -1, "port E input register"}, - {"porte.ddre", 0x0d, 1, 0xff, -1, "port E data direction register"}, - {"porte.porte", 0x0e, 1, 0xff, -1, "port E data register"}, - {"portf.pinf", 0x0f, 1, 0xff, -1, "port F input register"}, - {"portf.ddrf", 0x10, 1, 0xff, -1, "port F data direction register"}, - {"portf.portf", 0x11, 1, 0xff, -1, "port F data register"}, - {"tc0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"tc1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"tc2.tifr2", 0x17, 1, -1, -1, "T/C 2 interrupt flag register"}, - {"tc3.tifr3", 0x18, 1, -1, -1, "T/C 3 interrupt flag register"}, - {"exint.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"exint.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"exint.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, -1, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"tc0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc2.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"tc0.tccr0a", 0x24, 1, -1, -1, "T/C 0 control register A"}, - {"tc0.tccr0b", 0x25, 1, -1, -1, "T/C 0 control register B"}, - {"tc0.tcnt0", 0x26, 1, 0xff, -1, "timer/counter 0"}, - {"tc0.ocr0a", 0x27, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"tc0.ocr0b", 0x28, 1, 0xff, -1, "T/C 0 output compare register B"}, - {"pll.pllcsr", 0x29, 1, -1, -1, "PLL control and status register"}, - {"cpu.gpior1", 0x2a, 1, -1, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, -1, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"ac.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"jtag.ocdr", 0x31, 1, 0xff, -1, "on-chip debug register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"jtag.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"jtag.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.rampz", 0x3b, 1, 0x01, -1, "extended Z register"}, - {"cpu.eind", 0x3c, 1, 0x01, -1, "extended indirect jump register"}, - {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcsr", 0x40, 1, -1, -1, "watchdog timer control and status register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.prr0", 0x44, 1, -1, -1, "power reduction register 0"}, - {"cpu.prr1", 0x45, 1, -1, -1, "power reduction register 1"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"exint.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"exint.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"exint.eicrb", 0x4a, 1, -1, -1, "external interrupt control register B"}, - {"exint.pcmsk0", 0x4b, 1, 0xff, -1, "pin change interrupt mask register 0"}, - {"tc0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"tc1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"tc2.timsk2", 0x50, 1, -1, -1, "T/C 2 interrupt mask register"}, - {"tc3.timsk3", 0x51, 1, -1, -1, "T/C 3 interrupt mask register"}, - {"cpu.xmcra", 0x54, 1, -1, -1, "external memory control register A"}, - {"cpu.xmcrb", 0x55, 1, -1, -1, "external memory control register B"}, - {"adc.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"adc.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ac.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B"}, - {"adc.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"adc.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ac.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"tc1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"tc1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"tc1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"tc1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"tc1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"tc1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"tc1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"tc1.ocr1c", 0x6c, 2, 0xffff, -1, "T/C 1 output compare register C (16 bits)"}, - {"tc3.tccr3a", 0x70, 1, -1, -1, "T/C 3 control register A"}, - {"tc3.tccr3b", 0x71, 1, -1, -1, "T/C 3 control register B"}, - {"tc3.tccr3c", 0x72, 1, -1, -1, "T/C 3 control register C"}, - {"tc3.tcnt3", 0x74, 2, 0xffff, -1, "timer/counter 3 (16 bits)"}, - {"tc3.icr3", 0x76, 2, 0xffff, -1, "T/C 3 input capture register (16 bits)"}, - {"tc3.ocr3a", 0x78, 2, 0xffff, -1, "T/C 3 output compare register A (16 bits)"}, - {"tc3.ocr3b", 0x7a, 2, 0xffff, -1, "T/C 3 output compare register B (16 bits)"}, - {"tc3.ocr3c", 0x7c, 2, 0xffff, -1, "T/C 3 output compare register C (16 bits)"}, - {"tc2.tccr2a", 0x90, 1, -1, -1, "T/C 2 control register A"}, - {"tc2.tccr2b", 0x91, 1, -1, -1, "T/C 2 control register B"}, - {"tc2.tcnt2", 0x92, 1, 0xff, -1, "timer/counter 2"}, - {"tc2.ocr2a", 0x93, 1, 0xff, -1, "T/C 2 output compare register A"}, - {"tc2.ocr2b", 0x94, 1, 0xff, -1, "T/C 2 output compare register B"}, - {"tc2.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"twi.twbr", 0x98, 1, 0xff, -1, "TWI bit rate register"}, - {"twi.twsr", 0x99, 1, -1, -1, "TWI status register"}, - {"twi.twar", 0x9a, 1, -1, -1, "TWI peripheral address register"}, - {"twi.twdr", 0x9b, 1, 0xff, -1, "TWI data register"}, - {"twi.twcr", 0x9c, 1, -1, -1, "TWI control register"}, - {"twi.twamr", 0x9d, 1, -1, -1, "TWI peripheral address mask register"}, - {"usart1.ucsr1a", 0xa8, 1, -1, -1, "USART 1 control and status register A"}, - {"usart1.ucsr1b", 0xa9, 1, -1, -1, "USART 1 control and status register B"}, - {"usart1.ucsr1c", 0xaa, 1, -1, -1, "USART control and status register C"}, - {"usart1.ubrr1", 0xac, 2, 0x0fff, -1, "USART 1 baud rate register (16 bits)"}, - {"usart1.udr1", 0xae, 1, 0xff, -1, "USART 1 I/O data register"}, - {"usb_global.uhwcon", 0xb7, 1, -1, -1, "USB hardware configuration register"}, - {"usb_global.usbcon", 0xb8, 1, -1, -1, "USB general control register"}, - {"usb_global.usbsta", 0xb9, 1, -1, -1, "USB status register"}, - {"usb_global.usbint", 0xba, 1, -1, -1, "USB interrupt register"}, - {"usb_device.udcon", 0xc0, 1, -1, -1, "USB device control registers"}, - {"usb_device.udint", 0xc1, 1, -1, -1, "USB device interrupt register"}, - {"usb_device.udien", 0xc2, 1, -1, -1, "USB device interrupt enable register"}, - {"usb_device.udaddr", 0xc3, 1, -1, -1, "USB device address register"}, - {"usb_device.udfnum", 0xc4, 2, 0x07ff, -1, "USB device frame number high register (16 bits)"}, - {"usb_device.udmfn", 0xc6, 1, -1, -1, "USB device micro frame number register"}, - {"usb_device.ueintx", 0xc8, 1, -1, -1, "USB endpoint interrupt register"}, - {"usb_device.uenum", 0xc9, 1, 0x07, -1, "USB endpoint number register"}, - {"usb_device.uerst", 0xca, 1, -1, -1, "USB endpoint reset register"}, - {"usb_device.ueconx", 0xcb, 1, -1, -1, "USB endpoint control register"}, - {"usb_device.uecfg0x", 0xcc, 1, -1, -1, "USB endpoint configuration 0 register"}, - {"usb_device.uecfg1x", 0xcd, 1, -1, -1, "USB endpoint configuration 1 register"}, - {"usb_device.uesta0x", 0xce, 1, -1, -1, "USB endpoint status 0 register"}, - {"usb_device.uesta1x", 0xcf, 1, -1, -1, "USB endpoint status 1 register"}, - {"usb_device.ueienx", 0xd0, 1, -1, -1, "USB endpoint interrupt enable register"}, - {"usb_device.uedatx", 0xd1, 1, 0xff, -1, "USB data endpoint register"}, - {"usb_device.uebclx", 0xd2, 1, 0xff, -1, "USB endpoint byte count low byte"}, - {"usb_device.uebchx", 0xd3, 1, 0x07, -1, "USB endpoint byte count high byte"}, - {"usb_device.ueint", 0xd4, 1, 0x7f, -1, "USB endpoint number interrupt register"}, -}; - -// ATA5272 ATA5505 -const Register_file rgftab_ata5272[80] = { // I/O memory [0, 223] + 32 - {"porta.pina", 0x00, 1, 0xff, -1, "port A input register"}, - {"porta.ddra", 0x01, 1, 0xff, -1, "port A data direction register"}, - {"porta.porta", 0x02, 1, 0xff, -1, "port A data register"}, - {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, - {"cpu.portcr", 0x12, 1, -1, -1, "port control register"}, - {"timer_counter_0.tifr0", 0x15, 1, -1, -1, "T/C 0 interrupt flag register"}, - {"timer_counter_1.tifr1", 0x16, 1, -1, -1, "T/C 1 interrupt flag register"}, - {"external_interrupt.pcifr", 0x1b, 1, -1, -1, "pin change interrupt flag register"}, - {"external_interrupt.eifr", 0x1c, 1, -1, -1, "external interrupt flag register"}, - {"external_interrupt.eimsk", 0x1d, 1, -1, -1, "external interrupt mask register"}, - {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, - {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, - {"timer_counter_0.gtccr", 0x23, 1, -1, -1, "general T/C control register"}, - {"timer_counter_0.tccr0a", 0x25, 1, -1, -1, "T/C 0 control register A"}, - {"timer_counter_0.tccr0b", 0x26, 1, -1, -1, "T/C 0 control register B"}, - {"timer_counter_0.tcnt0", 0x27, 1, 0xff, -1, "timer/counter 0"}, - {"timer_counter_0.ocr0a", 0x28, 1, 0xff, -1, "T/C 0 output compare register A"}, - {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, - {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, - {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, - {"analog_comparator.acsr", 0x30, 1, -1, -1, "analog comparator control and status register"}, - {"cpu.dwdr", 0x31, 1, 0xff, -1, "debugWIRE data register"}, - {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, - {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, - {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, - {"boot_load.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, - {"cpu.sp", 0x3d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, - {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, - {"cpu.clkpr", 0x41, 1, -1, -1, "clock prescaler register"}, - {"cpu.clkcsr", 0x42, 1, -1, -1, "clock control and status register"}, - {"cpu.clkselr", 0x43, 1, -1, -1, "clock selection register"}, - {"cpu.prr", 0x44, 1, -1, -1, "power reduction register"}, - {"cpu.osccal", 0x46, 1, 0xff, -1, "oscillator calibration register"}, - {"external_interrupt.pcicr", 0x48, 1, -1, -1, "pin change interrupt control register"}, - {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, - {"external_interrupt.pcmsk0", 0x4b, 1, -1, -1, "pin change interrupt mask register 0"}, - {"external_interrupt.pcmsk1", 0x4c, 1, -1, -1, "pin change interrupt mask register 1"}, - {"timer_counter_0.timsk0", 0x4e, 1, -1, -1, "T/C 0 interrupt mask register"}, - {"timer_counter_1.timsk1", 0x4f, 1, -1, -1, "T/C 1 interrupt mask register"}, - {"ad_converter.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with CURRENT_SOURCE IO_MODULE)"}, - {"current_source.amiscr", 0x57, 1, -1, -1, "analog miscellaneous control register (shared with AD_CONVERTER IO_MODULE)"}, - {"ad_converter.adc", 0x58, 2, 0xffff, -1, "ADC data register (16 bits)"}, - {"ad_converter.adcsra", 0x5a, 1, -1, -1, "ADC control and status register A"}, - {"ad_converter.adcsrb", 0x5b, 1, -1, -1, "ADC control and status register B (shared with ANALOG_COMPARATOR IO_MODULE)"}, - {"analog_comparator.adcsrb", 0x5b, 1, -1, -1, "analog comparator & ADC control and status register B (shared with AD_CONVERTER IO_MODULE)"}, - {"ad_converter.admux", 0x5c, 1, -1, -1, "ADC multiplexer selection register"}, - {"ad_converter.didr0", 0x5e, 1, -1, -1, "digital input disable register 0"}, - {"ad_converter.didr1", 0x5f, 1, -1, -1, "digital input disable register 1"}, - {"timer_counter_1.tccr1a", 0x60, 1, -1, -1, "T/C 1 control register A"}, - {"timer_counter_1.tccr1b", 0x61, 1, -1, -1, "T/C 1 control register B"}, - {"timer_counter_1.tccr1c", 0x62, 1, -1, -1, "T/C 1 control register C"}, - {"timer_counter_1.tccr1d", 0x63, 1, -1, -1, "T/C 1 control register D"}, - {"timer_counter_1.tcnt1", 0x64, 2, 0xffff, -1, "timer/counter 1 (16 bits)"}, - {"timer_counter_1.icr1", 0x66, 2, 0xffff, -1, "T/C 1 input capture register (16 bits)"}, - {"timer_counter_1.ocr1a", 0x68, 2, 0xffff, -1, "T/C 1 output compare register A (16 bits)"}, - {"timer_counter_1.ocr1b", 0x6a, 2, 0xffff, -1, "T/C 1 output compare register B (16 bits)"}, - {"timer_counter_0.assr", 0x96, 1, -1, -1, "asynchronous status register"}, - {"usi.usicr", 0x98, 1, -1, -1, "USI control register"}, - {"usi.usisr", 0x99, 1, -1, -1, "USI status register"}, - {"usi.usidr", 0x9a, 1, 0xff, -1, "USI data register"}, - {"usi.usibr", 0x9b, 1, 0xff, -1, "USI buffer register"}, - {"usi.usipp", 0x9c, 1, 0x01, -1, "USI pin position register"}, - {"linuart.lincr", 0xa8, 1, -1, -1, "LIN control register"}, - {"linuart.linsir", 0xa9, 1, -1, -1, "LIN status and interrupt register"}, - {"linuart.linenir", 0xaa, 1, -1, -1, "LIN enable interrupt register"}, - {"linuart.linerr", 0xab, 1, -1, -1, "LIN error register"}, - {"linuart.linbtr", 0xac, 1, -1, -1, "LIN bit timing register"}, - {"linuart.linbrrl", 0xad, 1, -1, -1, "LIN baud rate low register low byte"}, - {"linuart.linbrrh", 0xae, 1, -1, -1, "LIN baud rate high register high byte"}, - {"linuart.lindlr", 0xaf, 1, -1, -1, "LIN data length register"}, - {"linuart.linidr", 0xb0, 1, -1, -1, "LIN identifier register"}, - {"linuart.linsel", 0xb1, 1, -1, -1, "LIN data buffer selection register"}, - {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, -}; - -// ATA5702M322 -const Register_file rgftab_ata5702m322[378] = { // I/O memory [0, 479] + 32 - {"gpioregs_dvcc.gpior0", 0x000, 1, 0xff, -1, "general purpose I/O register 0"}, - {"clk.prr1", 0x001, 1, -1, -1, "power reduction register 1"}, - {"clk.prr2", 0x002, 1, -1, -1, "power reduction register 2"}, - {"portb.pinb", 0x003, 1, 0xff, -1, "port B input register"}, - {"portb.ddrb", 0x004, 1, 0xff, -1, "port B data direction register"}, - {"portb.portb", 0x005, 1, 0xff, -1, "port B data register"}, - {"portc.pinc", 0x006, 1, 0x07, -1, "port C input register"}, - {"portc.ddrc", 0x007, 1, 0x07, -1, "port C data direction register"}, - {"portc.portc", 0x008, 1, 0x07, -1, "port C data register"}, - {"portd.pind", 0x009, 1, 0xff, -1, "port D input register"}, - {"portd.ddrd", 0x00a, 1, 0xff, -1, "port D data direction register"}, - {"portd.portd", 0x00b, 1, 0xff, -1, "port D data register"}, - {"lf_transponder.tpcr2", 0x00c, 1, -1, -1, "transponder control register 2"}, - {"lf_transponder.tpfr", 0x00d, 1, -1, -1, "transponder flag register"}, - {"cpu.mcucr", 0x00e, 1, -1, -1, "MCU control register"}, - {"txdsp.fscr", 0x00f, 1, -1, -1, "frequency synthesizer control register"}, - {"timer1.t1cr", 0x011, 1, -1, -1, "timer 1 control register"}, - {"timer2.t2cr", 0x012, 1, -1, -1, "timer 2 control register"}, - {"timer3.t3cr", 0x013, 1, -1, -1, "timer 3 control register"}, - {"timer4.t4cr", 0x014, 1, -1, -1, "timer 4 control register"}, - {"lf_timer.ltcmr", 0x015, 1, -1, -1, "LF timer control mode register"}, - {"eeprom.eecr2", 0x016, 1, -1, -1, "EEPROM control register 2"}, - {"lf_protocol_handler.phtcr", 0x017, 1, -1, -1, "PH telegram configuration register"}, - {"lf_fifo.ldffl", 0x018, 1, -1, -1, "LF data FIFO fill level register"}, - {"lf_fifo.ldfd", 0x019, 1, 0xff, -1, "LF data FIFO data register"}, - {"clk.prr0", 0x01a, 1, -1, -1, "power reduction register 0"}, - {"lf_protocol_handler.phfr", 0x01b, 1, -1, -1, "protocol handler flag register"}, - {"lf_receiver.lffr", 0x01c, 1, -1, -1, "LF flag register"}, - {"aes.aescr", 0x01d, 1, -1, -1, "AES control register"}, - {"aes.aessr", 0x01e, 1, -1, -1, "AES status register"}, - {"eeprom.eecr", 0x01f, 1, -1, -1, "EEPROM control register"}, - {"eeprom.eedr", 0x020, 1, 0xff, -1, "EEPROM data register"}, - {"eeprom.eear", 0x021, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, - {"eeprom.eepr", 0x023, 1, -1, -1, "EEPROM protection register"}, - {"gpioregs_dvcc.gpior1", 0x024, 1, 0xff, -1, "general purpose I/O register 1"}, - {"gpioregs_dvcc.gpior2", 0x025, 1, 0xff, -1, "general purpose I/O register 2"}, - {"int.pcicr", 0x026, 1, -1, -1, "pin change interrupt control register"}, - {"int.eimsk", 0x027, 1, -1, -1, "external interrupt mask register"}, - {"int.eifr", 0x028, 1, -1, -1, "external interrupt flag register"}, - {"lf_fifo.ldfcksw", 0x029, 1, -1, -1, "LF data FIFO clock switch register"}, - {"sup.vmscr", 0x02a, 1, -1, -1, "voltage monitor status and control register"}, - {"cpu.mcusr", 0x02b, 1, -1, -1, "MCU status register"}, - {"spi.spcr", 0x02c, 1, -1, -1, "SPI control register"}, - {"spi.spsr", 0x02d, 1, -1, -1, "SPI status register"}, - {"spi.spdr", 0x02e, 1, 0xff, -1, "SPI data register"}, - {"lf_receiver.lfcr0", 0x02f, 1, -1, -1, "LF receiver control register 0"}, - {"lf_receiver.lfcr1", 0x030, 1, -1, -1, "LF receiver control register 1"}, - {"cpu.dwdr", 0x031, 1, 0xff, -1, "debugWIRE data register"}, - {"timer0_wdt.t0ifr", 0x032, 1, -1, -1, "timer 0 interrupt flag register"}, - {"cpu.spmcsr", 0x037, 1, -1, -1, "store program memory control and status register"}, - {"cpu.smcr", 0x038, 1, -1, -1, "sleep mode control register"}, - {"lf_transponder.tpsr", 0x039, 1, -1, -1, "transponder status register"}, - {"lf_receiver.lfcr2", 0x03a, 1, -1, -1, "LF receiver control register 2"}, - {"lf_receiver.lfcr3", 0x03b, 1, -1, -1, "LF receiver control register 3"}, - {"cpu.sp", 0x03d, 2, 0x07ff, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"txdsp.fsen", 0x040, 1, -1, -1, "frequency synthesizer enable register"}, - {"txdsp.fsfcr", 0x041, 1, -1, -1, "frequency synthesizer filter control register"}, - {"txdsp.gacdiv", 0x042, 2, 0x1fff, -1, "Gauss clock divider register (16 bits)"}, - {"txdsp.ffreq1l", 0x044, 1, 0xff, -1, "fractional frequency 1 low byte"}, - {"txdsp.ffreq1m", 0x045, 1, 0xff, -1, "fractional frequency 1 middle byte"}, - {"txdsp.ffreq1h", 0x046, 1, 0x03, -1, "fractional frequency 1 high byte"}, - {"txdsp.ffreq2l", 0x047, 1, 0xff, -1, "fractional frequency 2 low byte"}, - {"txdsp.ffreq2m", 0x048, 1, 0xff, -1, "fractional frequency 2 middle byte"}, - {"txdsp.ffreq2h", 0x049, 1, 0x03, -1, "fractional frequency 2 high byte"}, - {"txdsp.bbte2", 0x04a, 1, -1, -1, "base band test enable 2 register"}, - {"int.eicra", 0x04b, 1, -1, -1, "external interrupt control register A"}, - {"int.pcmsk0", 0x04c, 1, -1, -1, "pin change interrupt mask register 0"}, - {"int.pcmsk1", 0x04d, 1, -1, -1, "pin change interrupt mask register 1"}, - {"timer0_wdt.wdtcr", 0x04e, 1, -1, -1, "watchdog timer control register"}, - {"timer1.t1cnt", 0x04f, 1, 0xff, -1, "timer 1 counter"}, - {"timer1.t1cor", 0x050, 1, 0xff, -1, "timer 1 compare register"}, - {"timer1.t1mr", 0x051, 1, -1, -1, "timer 1 mode register"}, - {"timer1.t1imr", 0x052, 1, -1, -1, "timer 1 interrupt mask register"}, - {"timer2.t2cnt", 0x053, 1, 0xff, -1, "timer 2 counter"}, - {"timer2.t2cor", 0x054, 1, 0xff, -1, "timer 2 compare register"}, - {"timer2.t2mr", 0x055, 1, -1, -1, "timer 2 mode register"}, - {"timer2.t2imr", 0x056, 1, -1, -1, "timer 2 interrupt mask register"}, - {"timer3.t3cnt", 0x057, 2, 0xffff, -1, "timer 3 counter (16 bits)"}, - {"timer3.t3cor", 0x059, 2, 0xffff, -1, "timer 3 compare register (16 bits)"}, - {"timer3.t3icr", 0x05b, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, - {"timer3.t3mra", 0x05d, 1, -1, -1, "timer 3 mode register A"}, - {"timer3.t3mrb", 0x05e, 1, -1, -1, "timer 3 mode register B"}, - {"timer3.t3imr", 0x05f, 1, -1, -1, "timer 3 interrupt mask register"}, - {"timer4.t4cnt", 0x060, 2, 0xffff, -1, "timer 4 counter (16 bits)"}, - {"timer4.t4cor", 0x062, 2, 0xffff, -1, "timer 4 compare register (16 bits)"}, - {"timer4.t4icr", 0x064, 2, 0xffff, -1, "timer 4 input capture register (16 bits)"}, - {"timer4.t4mra", 0x066, 1, -1, -1, "timer 4 mode register A"}, - {"timer4.t4mrb", 0x067, 1, -1, -1, "timer 4 mode register B"}, - {"timer4.t4imr", 0x068, 1, -1, -1, "timer 4 interrupt mask register"}, - {"timer5.t5temp", 0x069, 1, 0xff, -1, "timer 5 temp register"}, - {"timer5.t5ocr", 0x06a, 2, 0xffff, -1, "timer 5 output compare register (16 bits)"}, - {"timer5.t5ccr", 0x06c, 1, -1, -1, "timer 5 configuration and control register"}, - {"timer5.t5cnt", 0x06d, 2, 0xffff, -1, "timer 5 counter (16 bits)"}, - {"timer5.t5imr", 0x06f, 1, -1, -1, "timer 5 interrupt mask register"}, - {"tplf_cal.lfcalr1", 0x070, 1, -1, -1, "LF receiver calibration register 1"}, - {"tplf_cal.lfcalr2", 0x071, 1, -1, -1, "LF receiver calibration register 2"}, - {"tplf_cal.lfcalr3", 0x072, 1, -1, -1, "LF receiver calibration register 3"}, - {"tplf_cal.lfcalr4", 0x073, 1, -1, -1, "LF receiver calibration register 4"}, - {"tplf_cal.lfcalr5", 0x074, 1, -1, -1, "LF receiver calibration register 5"}, - {"tplf_cal.lfcalr6", 0x075, 1, -1, -1, "LF receiver calibration register 6"}, - {"tplf_cal.lfcalr7", 0x076, 1, 0xff, -1, "LF receiver calibration register 7"}, - {"tplf_cal.lfcalr8", 0x077, 1, 0x1f, -1, "LF receiver calibration register 8"}, - {"tplf_cal.lfcalr9", 0x078, 1, 0xff, -1, "LF receiver calibration register 9"}, - {"tplf_cal.lfcalr10", 0x079, 1, 0x7f, -1, "LF receiver calibration register 10"}, - {"tplf_cal.lfcalr11", 0x07a, 1, 0xff, -1, "LF receiver calibration register 11"}, - {"tplf_cal.lfcalr12", 0x07b, 1, 0xff, -1, "LF receiver calibration register 12"}, - {"tplf_cal.lfcalr13", 0x07c, 1, 0xff, -1, "LF receiver calibration register 13"}, - {"tplf_cal.lfcalr14", 0x07d, 1, 0x7f, -1, "LF receiver calibration register 14"}, - {"tplf_cal.lfcalr15", 0x07e, 1, 0xff, -1, "LF receiver calibration register 15"}, - {"tplf_cal.lfcalr16", 0x07f, 1, 0x1f, -1, "LF receiver calibration register 16"}, - {"tplf_cal.lfcalr17", 0x080, 1, 0x1f, -1, "LF receiver calibration register 17"}, - {"tplf_cal.lfcalr18", 0x081, 1, 0xff, -1, "LF receiver calibration register 18"}, - {"tplf_cal.lfcalr19", 0x082, 1, 0x7f, -1, "LF receiver calibration register 19"}, - {"tplf_cal.lfcalr20", 0x083, 1, 0xff, -1, "LF receiver calibration register 20"}, - {"tplf_cal.lfcalr21", 0x084, 1, 0xff, -1, "LF receiver calibration register 21"}, - {"tplf_cal.lfcalr22", 0x085, 1, 0xff, -1, "LF receiver calibration register 22"}, - {"tplf_cal.lfcalr23", 0x086, 1, 0x7f, -1, "LF receiver calibration register 23"}, - {"tplf_cal.lfcalr24", 0x087, 1, 0xff, -1, "LF receiver calibration register 24"}, - {"tplf_cal.lfcalr25", 0x088, 1, 0x1f, -1, "LF receiver calibration register 25"}, - {"tplf_cal.lfcalr26", 0x089, 1, 0x1f, -1, "LF receiver calibration register 26"}, - {"tplf_cal.lfcalr27", 0x08a, 1, 0xff, -1, "LF receiver calibration register 27"}, - {"tplf_cal.lfcalr28", 0x08b, 1, 0x7f, -1, "LF receiver calibration register 28"}, - {"tplf_cal.lfcalr29", 0x08c, 1, 0xff, -1, "LF receiver calibration register 29"}, - {"tplf_cal.lfcalr30", 0x08d, 1, 0xff, -1, "LF receiver calibration register 30"}, - {"tplf_cal.lfcalr31", 0x08e, 1, 0xff, -1, "LF receiver calibration register 31"}, - {"tplf_cal.lfcalr32", 0x08f, 1, 0x7f, -1, "LF receiver calibration register 32"}, - {"tplf_cal.lfcalr33", 0x090, 1, 0xff, -1, "LF receiver calibration register 33"}, - {"tplf_cal.lfcalr34", 0x091, 1, 0x1f, -1, "LF receiver calibration register 34"}, - {"tplf_cal.lfcalr35", 0x092, 1, 0xff, -1, "LF receiver calibration register 35"}, - {"tplf_cal.lfcalr36", 0x093, 1, 0x7f, -1, "LF receiver calibration register 36"}, - {"tplf_cal.lfcalr37", 0x094, 1, 0x3f, -1, "LF receiver calibration register 37"}, - {"tplf_cal.lfcalr38", 0x095, 1, 0x0f, -1, "LF receiver calibration register 38"}, - {"tplf_cal.lfcalr39", 0x096, 1, 0x0f, -1, "LF receiver calibration register 39"}, - {"tplf_cal.lfcalr40", 0x097, 1, 0x0f, -1, "LF receiver calibration register 40"}, - {"tplf_cal.lfcalr41", 0x098, 1, 0xff, -1, "LF receiver calibration register 41"}, - {"tplf_cal.lfcalr42", 0x099, 1, 0xff, -1, "LF receiver calibration register 42"}, - {"tplf_cal.lfcalr43", 0x09a, 1, 0xff, -1, "LF receiver calibration register 43"}, - {"tplf_cal.lfcalr44", 0x09b, 1, 0x3f, -1, "LF receiver calibration register 44"}, - {"tplf_cal.lfcalr45", 0x09c, 1, 0xff, -1, "LF receiver calibration register 45"}, - {"tplf_cal.lfcalr46", 0x09d, 1, 0xff, -1, "LF receiver calibration register 46"}, - {"tplf_cal.lfcalr47", 0x09e, 1, 0xff, -1, "LF receiver calibration register 47"}, - {"tplf_cal.lfcalr48", 0x09f, 1, 0x3f, -1, "LF receiver calibration register 48"}, - {"tplf_cal.lfcalr49", 0x0a0, 1, 0xff, -1, "LF receiver calibration register 49"}, - {"tplf_cal.lfcalr50", 0x0a1, 1, 0xff, -1, "LF receiver calibration register 50"}, - {"tplf_cal.lfcalr51", 0x0a2, 1, 0xff, -1, "LF receiver calibration register 51"}, - {"tplf_cal.lfcalr52", 0x0a3, 1, 0x3f, -1, "LF receiver calibration register 52"}, - {"tplf_cal.lfcalr53", 0x0a4, 1, 0xff, -1, "LF receiver calibration register 53"}, - {"clk.xfuse", 0x0a5, 1, -1, -1, "XFUSE register"}, - {"clk.mrccal", 0x0a6, 1, 0xfe, -1, "middle RC oscillator calibration register"}, - {"clk.frccal", 0x0a7, 1, 0x1f, -1, "fast RC oscillator calibration register"}, - {"sup.rctcal", 0x0a8, 1, -1, -1, "RC oscillator temperature compensation register"}, - {"clk.cmsr", 0x0a9, 1, -1, -1, "clock management status register"}, - {"clk.cmocr", 0x0aa, 1, -1, -1, "clock management override control register"}, - {"sup.supfr", 0x0ab, 1, -1, -1, "supply interrupt flag register"}, - {"sup.supcr", 0x0ac, 1, -1, -1, "supply control register"}, - {"sup.supca1", 0x0ad, 1, -1, -1, "supply calibration register 1"}, - {"sup.supca2", 0x0ae, 1, -1, -1, "supply calibration register 2"}, - {"sup.supca3", 0x0af, 1, -1, -1, "supply calibration register 3"}, - {"sup.supca4", 0x0b0, 1, -1, -1, "supply calibration register 4"}, - {"sup.calrdy", 0x0b1, 1, 0xff, -1, "calibration ready signature register"}, - {"dfifo.dfs", 0x0b2, 1, -1, -1, "data FIFO status register"}, - {"dfifo.dfl", 0x0b5, 1, -1, -1, "data FIFO fill level register"}, - {"dfifo.dfwp", 0x0b6, 1, 0x3f, -1, "data FIFO write pointer register"}, - {"dfifo.dfrp", 0x0b7, 1, 0x3f, -1, "data FIFO read pointer register"}, - {"dfifo.dfd", 0x0b8, 1, 0xff, -1, "data FIFO data register"}, - {"dfifo.dfi", 0x0b9, 1, -1, -1, "data FIFO interrupt mask register"}, - {"dfifo.dfc", 0x0ba, 1, -1, -1, "data FIFO configuration register"}, - {"sfifo.sfs", 0x0bb, 1, -1, -1, "support FIFO status register"}, - {"sfifo.sfl", 0x0bc, 1, -1, -1, "support FIFO fill level register"}, - {"sfifo.sfwp", 0x0bd, 1, 0x1f, -1, "support FIFO write pointer register"}, - {"sfifo.sfrp", 0x0be, 1, 0x1f, -1, "support FIFO read pointer register"}, - {"sfifo.sfd", 0x0bf, 1, 0xff, -1, "support FIFO data register"}, - {"sfifo.sfi", 0x0c0, 1, -1, -1, "support FIFO interrupt mask register"}, - {"sfifo.sfc", 0x0c1, 1, -1, -1, "support FIFO configuration register"}, - {"ssm.ssmcr", 0x0c2, 1, -1, -1, "sequencer state machine control register"}, - {"timer5.gtccr", 0x0c3, 1, -1, -1, "general T/C control register"}, - {"ssm.ssmfbr", 0x0c4, 1, -1, -1, "sequencer state machine filter bandwidth register"}, - {"ssm.ssmrr", 0x0c5, 1, -1, -1, "sequencer state machine run register"}, - {"ssm.ssmsr", 0x0c6, 1, -1, -1, "sequencer state machine status register"}, - {"ssm.ssmifr", 0x0c7, 1, -1, -1, "sequencer state machine interrupt flag register"}, - {"ssm.ssmimr", 0x0c8, 1, -1, -1, "sequencer state machine interrupt mask register"}, - {"ssm.msmstr", 0x0c9, 1, -1, -1, "master state machine state register"}, - {"ssm.ssmstr", 0x0ca, 1, -1, -1, "sequencer state machine state register"}, - {"vx_mode.vxmctrl", 0x0cb, 1, -1, -1, "VX mode control register"}, - {"ssm.msmcr1", 0x0cc, 1, -1, -1, "master state machine control register 1"}, - {"ssm.msmcr2", 0x0cd, 1, -1, -1, "master state machine control register 2"}, - {"ssm.msmcr3", 0x0ce, 1, -1, -1, "master state machine control register 3"}, - {"ssm.msmcr4", 0x0cf, 1, -1, -1, "master state machine control register 4"}, - {"spi2.sp2cr", 0x0d7, 1, -1, -1, "SPI 2 control register"}, - {"spi2.sp2dr", 0x0d8, 1, 0xff, -1, "SPI 2 data register"}, - {"spi2.sp2sr", 0x0d9, 1, -1, -1, "SPI 2 status register"}, - {"debug.trcid", 0x0dc, 2, 0xffff, -1, "trace ID register (16 bits)"}, - {"debug.trcdr", 0x0df, 1, 0xff, -1, "trace unit data register"}, - {"fe.fesr", 0x0e0, 1, -1, -1, "front-end status register"}, - {"fe.feen1", 0x0e1, 1, -1, -1, "front-end enable register 1"}, - {"fe.feen2", 0x0e2, 1, -1, -1, "front-end enable register 2"}, - {"fe.felna", 0x0e3, 1, 0xff, -1, "reserved register"}, - {"fe.feat", 0x0e4, 1, -1, -1, "front-end antenna tuning register"}, - {"fe.fepac", 0x0e5, 1, -1, -1, "front-end power amplifier control register"}, - {"fe.fevct", 0x0e6, 1, 0x0f, -1, "front-end VCO tuning register"}, - {"fe.febt", 0x0e7, 1, -1, -1, "front-end RC tuning register"}, - {"fe.fems", 0x0e8, 1, -1, -1, "front-end main and swallow control register"}, - {"fe.fetn4", 0x0e9, 1, -1, -1, "front-end RC tuning 4bit register"}, - {"fe.fecr", 0x0ea, 1, -1, -1, "front-end control register"}, - {"fe.fevco", 0x0eb, 1, -1, -1, "front-end VCO and PLL control register"}, - {"fe.fealr", 0x0ec, 1, -1, -1, "front-end antenna level detector range register"}, - {"fe.feant", 0x0ed, 1, -1, -1, "front-end antenna register"}, - {"fe.febia", 0x0ee, 1, 0xff, -1, "reserved register"}, - {"clk.clkod", 0x0f5, 1, 0xff, -1, "clock output divider register"}, - {"clk.clkocr", 0x0f6, 1, -1, -1, "clock output control register"}, - {"fe.fete1", 0x0fc, 1, -1, -1, "front-end test enable register 1"}, - {"fe.fete2", 0x0fd, 1, -1, -1, "front-end test enable register 2"}, - {"fe.fete3", 0x0fe, 1, -1, -1, "front-end test enable register 3"}, - {"fe.fetd", 0x0ff, 1, 0xff, -1, "front-end test data register"}, - {"txm.tmfsm", 0x100, 1, -1, -1, "tx modulator finite state machine register"}, - {"txm.tmcrc", 0x101, 2, 0xffff, -1, "tx modulator CRC result register (16 bits)"}, - {"txm.tmcsb", 0x103, 1, 0xff, -1, "tx modulator CRC skip bit number register"}, - {"txm.tmci", 0x104, 2, 0xffff, -1, "tx modulator CRC init value register (16 bits)"}, - {"txm.tmcp", 0x106, 2, 0xffff, -1, "tx modulator CRC polynomial register (16 bits)"}, - {"txm.tmshr", 0x108, 1, 0xff, -1, "tx modulator shift register"}, - {"txm.tmtll", 0x109, 2, 0x0fff, -1, "tx modulator telegram length register (16 bits)"}, - {"txm.tmssc", 0x10b, 1, -1, -1, "tx modulator stop sequence configuration register"}, - {"txm.tmsr", 0x10c, 1, -1, -1, "tx modulator status register"}, - {"txm.tmcr2", 0x10d, 1, -1, -1, "tx modulator control register 2"}, - {"txm.tmcr1", 0x10e, 1, -1, -1, "tx modulator control register 1"}, - {"lf_receiver.lfdsr1", 0x110, 1, -1, -1, "LF decoder setting register 1"}, - {"lf_receiver.lfdsr2", 0x111, 1, -1, -1, "LF decoder setting register 2"}, - {"lf_receiver.lfdsr3", 0x112, 1, -1, -1, "LF decoder setting register 3"}, - {"lf_receiver.lfdsr4", 0x113, 1, -1, -1, "LF decoder setting register 4"}, - {"lf_receiver.lfdsr5", 0x114, 1, -1, -1, "LF decoder setting register 5"}, - {"lf_receiver.lfdsr6", 0x115, 1, -1, -1, "LF decoder setting register 6"}, - {"lf_receiver.lfdsr7", 0x116, 1, -1, -1, "LF decoder setting register 7"}, - {"lf_receiver.lfdsr8", 0x117, 1, -1, -1, "LF decoder setting register 8"}, - {"lf_receiver.lfdsr9", 0x118, 1, -1, -1, "LF decoder setting register 9"}, - {"lf_receiver.lfdsr10", 0x119, 1, -1, -1, "LF decoder setting register 10"}, - {"lf_receiver.lfdsr11", 0x11a, 1, -1, -1, "LF decoder setting register 11"}, - {"eeprom.eepr1", 0x11b, 1, -1, -1, "EEPROM protection register 1"}, - {"eeprom.eepr2", 0x11c, 1, -1, -1, "EEPROM protection register 2"}, - {"eeprom.eepr3", 0x11d, 1, -1, -1, "EEPROM protection register 3"}, - {"crc.crccr", 0x125, 1, -1, -1, "CRC control register"}, - {"crc.crcdor", 0x126, 1, 0xff, -1, "CRC data output register"}, - {"lf_receiver.lfsrctm", 0x131, 1, -1, -1, "LF receiver SRC tuning MSB register"}, - {"debounce.dbcr", 0x132, 1, -1, -1, "debounce control register"}, - {"debounce.dbtc", 0x133, 1, 0xff, -1, "debounce timer compare register"}, - {"debounce.dbenb", 0x134, 1, 0xff, -1, "debounce enable port B register"}, - {"debounce.dbenc", 0x135, 1, 0x07, -1, "debounce enable port C register"}, - {"debug.dbgsw", 0x136, 1, -1, -1, "debugging support switch register"}, - {"spi.sffr", 0x137, 1, -1, -1, "SPI FIFO fill status register"}, - {"spi.sfir", 0x138, 1, -1, -1, "SPI FIFO interrupt register"}, - {"timer2.t2ifr", 0x139, 1, -1, -1, "timer 2 interrupt flag register"}, - {"mem.pgmst", 0x13a, 1, -1, -1, "program memory status register"}, - {"mem.eest", 0x13b, 1, -1, -1, "EEPROM status register"}, - {"lf_receiver.lfsrctl", 0x13c, 1, -1, -1, "LF receiver SRC tuning LSB register"}, - {"int.pcifr", 0x141, 1, -1, -1, "pin change interrupt flag register"}, - {"timer0_wdt.t0cr", 0x142, 1, -1, -1, "timer 0 control register"}, - {"debounce.dbend", 0x144, 1, 0xff, -1, "debounce enable port D register"}, - {"lf_transponder.tpcr1", 0x145, 1, -1, -1, "transponder control register 1"}, - {"lf_transponder.tpimr", 0x146, 1, -1, -1, "transponder interrupt mask register"}, - {"lf_transponder.tpdcr1", 0x147, 1, -1, -1, "transponder decoder comparator register 1"}, - {"lf_transponder.tpdcr2", 0x148, 1, -1, -1, "transponder decoder comparator register 2"}, - {"lf_transponder.tpdcr3", 0x149, 1, -1, -1, "transponder decoder comparator register 3"}, - {"lf_transponder.tpdcr4", 0x14a, 1, -1, -1, "transponder decoder comparator register 4"}, - {"lf_transponder.tpdcr5", 0x14b, 1, -1, -1, "transponder decoder comparator register 5"}, - {"lf_transponder.tpecr1", 0x14c, 1, -1, -1, "transponder encoder comparator register 1"}, - {"lf_transponder.tpecr2", 0x14d, 1, -1, -1, "transponder encoder comparator register 2"}, - {"lf_transponder.tpecr3", 0x14e, 1, -1, -1, "transponder encoder comparator register 3"}, - {"lf_transponder.tpecr4", 0x14f, 1, -1, -1, "transponder encoder comparator register 4"}, - {"lf_transponder.tpecmr", 0x150, 1, -1, -1, "transponder encoder mode register"}, - {"lf_transponder.tpcr3", 0x151, 1, -1, -1, "transponder control register 3"}, - {"lf_transponder.tpcr4", 0x152, 1, -1, -1, "transponder control register 4"}, - {"lf_transponder.tpcr5", 0x153, 1, -1, -1, "transponder control register 5"}, - {"tplf_cal.tpcalr1", 0x155, 1, -1, -1, "transponder calibration register 1"}, - {"tplf_cal.tpcalr2", 0x156, 1, -1, -1, "transponder calibration register 2"}, - {"tplf_cal.tpcalr3", 0x157, 1, -1, -1, "transponder calibration register 3"}, - {"tplf_cal.tpcalr4", 0x158, 1, -1, -1, "transponder calibration register 4"}, - {"tplf_cal.tpcalr5", 0x159, 1, 0x0f, -1, "transponder calibration register 5"}, - {"tplf_cal.tpcalr6", 0x15a, 1, 0x1f, -1, "transponder calibration register 6"}, - {"tplf_cal.tpcalr7", 0x15b, 1, 0x07, -1, "transponder calibration register 7"}, - {"tplf_cal.tpcalr8", 0x15c, 1, 0x7f, -1, "transponder calibration register 8"}, - {"tplf_cal.tpcalr9", 0x15d, 1, 0xff, -1, "transponder calibration register 9"}, - {"tplf_cal.tpcalr10", 0x15e, 1, 0x7f, -1, "transponder calibration register 10"}, - {"aes.aesdpr", 0x15f, 1, 0x0f, -1, "AES data pointer register"}, - {"aes.aeskr", 0x160, 1, 0xff, -1, "AES key register"}, - {"aes.aesdr", 0x161, 1, 0xff, -1, "AES data register"}, - {"gpioregs_lfvcc.gpior3", 0x162, 1, 0xff, -1, "general purpose I/O register 3"}, - {"gpioregs_lfvcc.gpior4", 0x163, 1, 0xff, -1, "general purpose I/O register 4"}, - {"gpioregs_lfvcc.gpior5", 0x164, 1, 0xff, -1, "general purpose I/O register 5"}, - {"gpioregs_lfvcc.gpior6", 0x165, 1, 0xff, -1, "general purpose I/O register 6"}, - {"gpioregs_lfvcc.gpior7", 0x166, 1, 0xff, -1, "general purpose I/O register 7"}, - {"gpioregs_lfvcc.gpior8", 0x167, 1, 0xff, -1, "general purpose I/O register 8"}, - {"lf_protocol_handler.phbcrr", 0x168, 1, 0xff, -1, "protocol handler bit counter read register"}, - {"tplf_cal.lfcpr", 0x16e, 1, -1, -1, "LF receiver calibration protect register"}, - {"lf_receiver.lfimr", 0x16f, 1, -1, -1, "LF interrupt mask register"}, - {"lf_protocol_handler.phid0", 0x170, 4, 0xffffffff, -1, "PH ID 0 register (32 bits)"}, - {"lf_protocol_handler.phid0l", 0x174, 1, 0x3f, -1, "PH identifier 0 length register"}, - {"lf_protocol_handler.phid1", 0x175, 4, 0xffffffff, -1, "PH ID 1 register (32 bits)"}, - {"lf_protocol_handler.phid1l", 0x179, 1, 0x3f, -1, "PH identifier 1 length register"}, - {"lf_protocol_handler.phidfr", 0x17a, 1, 0xff, -1, "protocol handler ID frame register"}, - {"lf_receiver.lfsysy", 0x17b, 4, 0xffffffff, -1, "LF receiver synchronization symbols register (32 bits)"}, - {"lf_receiver.lfsyle", 0x17f, 1, -1, -1, "LF receiver synchronization length register"}, - {"lf_receiver.lfstop", 0x180, 1, -1, -1, "LF receiver stop bit register"}, - {"lf_timer.ltcor", 0x181, 1, 0xff, -1, "LF timer compare register"}, - {"timer1.t1ifr", 0x182, 1, -1, -1, "timer 1 interrupt flag register"}, - {"lf_protocol_handler.phtblr", 0x184, 1, 0xff, -1, "protocol handler telegram bit length register"}, - {"lf_protocol_handler.phdfr", 0x185, 1, 0xff, -1, "protocol handler data frame end register"}, - {"lf_timer.ltemr", 0x186, 1, -1, -1, "LF timer event mask register"}, - {"lf_receiver.lfqc3", 0x187, 1, -1, -1, "LF receiver channel 3 quality factor register"}, - {"lf_receiver.lfqc2", 0x188, 1, -1, -1, "LF receiver channel 2 quality factor register"}, - {"lf_receiver.lfqc1", 0x189, 1, -1, -1, "LF receiver channel 1 quality factor register"}, - {"twi2.tw2br", 0x18a, 1, 0xff, -1, "TWI 2 bit rate register"}, - {"twi2.tw2cr", 0x18b, 1, -1, -1, "TWI 2 control register"}, - {"twi2.tw2sr", 0x18c, 1, -1, -1, "TWI 2 status register"}, - {"twi2.tw2dr", 0x18d, 1, 0xff, -1, "TWI 2 data register"}, - {"twi2.tw2ar", 0x18e, 1, -1, -1, "TWI 2 peripheral address register"}, - {"twi2.tw2amr", 0x18f, 1, -1, -1, "TWI 2 address mask register"}, - {"lf_rssi.rscr", 0x190, 1, -1, -1, "RSSI control register"}, - {"lf_rssi.rssr", 0x191, 1, -1, -1, "RSSI status register"}, - {"lf_rssi.rsms1r", 0x192, 1, -1, -1, "RSSI measurement setting 1 register"}, - {"lf_rssi.rsms2r", 0x193, 1, -1, -1, "RSSI measurement setting 2 register"}, - {"lf_rssi.rsfr", 0x194, 1, -1, -1, "RSSI flag register"}, - {"lf_rssi.rscalib", 0x196, 1, -1, -1, "RSSI calibration register"}, - {"lf_rssi.rsdlyr", 0x197, 1, -1, -1, "RSSI delay register"}, - {"lf_rssi.rsres1l", 0x198, 1, -1, -1, "RSSI result 1 low byte register"}, - {"lf_rssi.rsres1h", 0x199, 1, -1, -1, "RSSI result 1 high byte register"}, - {"lf_rssi.rsres2l", 0x19a, 1, -1, -1, "RSSI result 2 low byte register"}, - {"lf_rssi.rsres2h", 0x19b, 1, -1, -1, "RSSI result 2 high byte register"}, - {"lf_rssi.rsres3l", 0x19c, 1, -1, -1, "RSSI result 3 low byte register"}, - {"lf_rssi.rsres3h", 0x19d, 1, -1, -1, "RSSI result 3 high byte register"}, - {"lf_rssi.rsres4l", 0x19e, 1, -1, -1, "RSSI result 4 low byte register"}, - {"lf_rssi.rsres4h", 0x19f, 1, -1, -1, "RSSI result 4 high byte register"}, - {"lf_rssi.rssrcr", 0x1a0, 1, -1, -1, "RSSI SRC calibration register"}, - {"lf_rssi.sd12rr", 0x1a1, 1, -1, -1, "sign detection channel 1 vs 2 result register"}, - {"lf_rssi.sd13rr", 0x1a2, 1, -1, -1, "sign detection channel 1 vs 3 result register"}, - {"lf_rssi.sd23rr", 0x1a3, 1, -1, -1, "sign detection channel 2 vs 3 result register"}, - {"lf_rssi.sd360r", 0x1a4, 1, -1, -1, "sign detection 360 degree result register"}, - {"lf_rssi.rsdbgr", 0x1a5, 1, -1, -1, "RSSI debug register"}, - {"lf_fifo.ldfs", 0x1b1, 1, -1, -1, "LF data FIFO status register"}, - {"timer4.t4ifr", 0x1b2, 1, -1, -1, "timer 4 interrupt flag register"}, - {"lf_fifo.ldfwp", 0x1b3, 1, -1, -1, "LF data FIFO write pointer register"}, - {"lf_fifo.ldfrp", 0x1b4, 1, -1, -1, "LF data FIFO read pointer register"}, - {"timer5.t5ifr", 0x1b5, 1, -1, -1, "timer 5 interrupt flag register"}, - {"lf_fifo.ldfim", 0x1b6, 1, -1, -1, "LF data FIFO interrupt mask register"}, - {"lf_fifo.ldfc", 0x1b7, 1, -1, -1, "LF data FIFO configuration register"}, - {"lf_protocol_handler.phimr", 0x1b8, 1, -1, -1, "protocol handler interrupt mask register"}, - {"lf_protocol_handler.phcrcr", 0x1b9, 1, -1, -1, "protocol handler CRC control register"}, - {"lf_protocol_handler.phcst", 0x1ba, 2, 0xffff, -1, "PH CRC start value register (16 bits)"}, - {"lf_protocol_handler.phcrp", 0x1bc, 2, 0xffff, -1, "PH CRC polynomial register (16 bits)"}, - {"lf_protocol_handler.phcsr", 0x1be, 2, 0xffff, -1, "PH CRC checksum register (16 bits)"}, - {"crc.crcdir", 0x1c0, 1, 0xff, -1, "CRC data input register"}, - {"timer3.t3ifr", 0x1c1, 1, -1, -1, "timer 3 interrupt flag register"}, - {"cpu.cmcr", 0x1c3, 1, -1, -1, "clock management control register"}, - {"cpu.cmimr", 0x1c4, 1, -1, -1, "clock management interrupt mask register"}, - {"cpu.clpr", 0x1c5, 1, -1, -1, "clock prescaler register"}, - {"sup.vmcr", 0x1c6, 1, -1, -1, "voltage monitor control register"}, - {"debug.dbondr", 0x1c7, 1, -1, -1, "downbond test register"}, - {"sup.calrdylf", 0x1c8, 1, 0xff, -1, "calibration ready signature LFVCC register"}, - {"twi1.tw1br", 0x1c9, 1, 0xff, -1, "TWI 1 bit rate register"}, - {"twi1.tw1cr", 0x1ca, 1, -1, -1, "TWI 1 control register"}, - {"twi1.tw1sr", 0x1cb, 1, -1, -1, "TWI 1 status register"}, - {"twi1.tw1dr", 0x1cc, 1, 0xff, -1, "TWI 1 data register"}, - {"twi1.tw1ar", 0x1cd, 1, -1, -1, "TWI 1 peripheral address register"}, - {"twi1.tw1amr", 0x1ce, 1, -1, -1, "TWI 1 address mask register"}, - {"led.pdscr", 0x1cf, 1, -1, -1, "pad driver strength control register"}, - {"tmo.tmocr", 0x1d0, 1, -1, -1, "timer modulator output control register"}, - {"tplf_cal.srccal", 0x1d1, 1, -1, -1, "slow RC oscillator calibration register"}, - {"tplf_cal.srctcal", 0x1d2, 1, -1, -1, "slow RC oscillator temperature compensation register"}, - {"sup.supca5", 0x1d3, 1, -1, -1, "supply calibration register 5"}, - {"sup.supca6", 0x1d4, 1, -1, -1, "supply calibration register 6"}, - {"sup.supca7", 0x1d5, 1, -1, -1, "supply calibration register 7"}, - {"sup.supca8", 0x1d6, 1, -1, -1, "supply calibration register 8"}, - {"sup.supca9", 0x1d7, 1, -1, -1, "supply calibration register 9"}, - {"sup.supca10", 0x1d8, 1, 0x1f, -1, "supply calibration register 10"}, - {"tplf_cal.tpcalr11", 0x1d9, 1, -1, -1, "transponder calibration register 11"}, - {"tplf_cal.tpcalr12", 0x1da, 1, -1, -1, "transponder calibration register 12"}, - {"tplf_cal.tpcalr13", 0x1db, 1, 0xff, -1, "transponder calibration register 13"}, - {"sup.pmter", 0x1de, 1, 0xff, -1, "power management test enable register"}, - {"tplf_cal.srccall", 0x1df, 1, -1, -1, "slow RC oscillator calibration register low byte"}, -}; - // ATA5787 const Register_file rgftab_ata5787[292] = { // I/O memory [0, 479] + 32 {"clk.prr0", 0x001, 1, -1, -1, "power reduction register 0"}, @@ -29139,6 +25576,122 @@ const Register_file rgftab_ata5787[292] = { // I/O memory [0, 479] + 32 {"trace.trcid", 0x160, 2, 0xffff, -1, "trace ID register (16 bits)"}, }; +// ATA5790 +const Register_file rgftab_ata5790[112] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0xff, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0xff, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0xff, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"afe.tpcr", 0x0d, 1, -1, -1, "transponder control register"}, + {"afe.tpfr", 0x0e, 1, -1, -1, "transponder status and flag register"}, + {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, + {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, + {"timer_counter_2.t2cr", 0x11, 1, -1, -1, "timer 2 control register"}, + {"timer_counter_3.t3cr", 0x12, 1, -1, -1, "timer 3 control register"}, + {"aes.aescr", 0x13, 1, -1, -1, "AES control register"}, + {"aes.aessr", 0x14, 1, -1, -1, "AES status register"}, + {"mod.tmifr", 0x15, 1, -1, -1, "timer modulator interrupt flag register"}, + {"cpu.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"vmon.vmsr", 0x16, 1, -1, -1, "voltage monitor status register"}, + {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, + {"dddlfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, + {"timer_counter_0.t0ifr", 0x19, 1, -1, -1, "timer 0 interrupt flag register"}, + {"timer_counter_1.t1ifr", 0x1a, 1, -1, -1, "timer 1 interrupt flag register"}, + {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, + {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, + {"cpu.gpior", 0x1e, 1, 0xff, -1, "general purpose I/O register"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x0fff, -1, "EEPROM address register (16 bits)"}, + {"eeprom.eepr", 0x23, 1, -1, -1, "EEPROM protection register"}, + {"eeprom.eeccr", 0x24, 1, -1, -1, "EEPROM error correction code register"}, + {"external_interrupt.pcicr", 0x26, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eimsk", 0x27, 1, -1, -1, "external interrupt mask register"}, + {"mod.tmdr", 0x28, 1, 0xff, -1, "timer modulator data register"}, + {"aes.aesdr", 0x29, 1, 0xff, -1, "AES data register"}, + {"aes.aeskr", 0x2a, 1, -1, -1, "AES key register"}, + {"cpu.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"vmon.vmcr", 0x2b, 1, -1, -1, "voltage monitor control register"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"dddlfrx.lfcr0", 0x2f, 1, -1, -1, "LF receiver control register 0"}, + {"dddlfrx.lfcr1", 0x30, 1, -1, -1, "LF receiver control register 1"}, + {"dddlfrx.lfrdb", 0x32, 1, 0xff, -1, "LF receiver data buffer register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"dddlfrx.lfsr", 0x36, 1, -1, -1, "LF status register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, + {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, + {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"cpu.prr0", 0x43, 1, -1, -1, "power reduction register 0"}, + {"cpu.prr1", 0x44, 1, -1, -1, "power reduction register 1"}, + {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, + {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"irled.ldcr", 0x4d, 1, -1, -1, "LED driver control register"}, + {"timer_counter_2.t2cnt", 0x50, 1, 0xff, -1, "timer 2 counter"}, + {"timer_counter_2.t2cor", 0x51, 1, 0xff, -1, "timer 2 compare register"}, + {"timer_counter_2.t2mr", 0x53, 1, -1, -1, "timer 2 mode register"}, + {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer_counter_3.t3cnt", 0x56, 1, 0xff, -1, "timer 3 counter"}, + {"timer_counter_3.t3cor", 0x57, 1, 0xff, -1, "timer 3 compare register"}, + {"timer_counter_3.t3icr", 0x58, 1, 0xff, -1, "timer 3 input capture register"}, + {"timer_counter_3.t3mra", 0x59, 1, -1, -1, "timer 3 mode register A"}, + {"timer_counter_3.t3mrb", 0x5a, 1, -1, -1, "timer 3 mode register B"}, + {"timer_counter_3.t3imr", 0x5b, 1, -1, -1, "timer 3 interrupt mask register"}, + {"mod.tmcr", 0x5d, 1, -1, -1, "timer modulator control register"}, + {"mod.tmmr", 0x5e, 1, -1, -1, "timer modulator mode register"}, + {"mod.tmimr", 0x5f, 1, -1, -1, "timer modulator interrupt mask register"}, + {"dddlfrx.lfimr", 0x62, 1, -1, -1, "LF interrupt mask register"}, + {"dddlfrx.lfcad", 0x63, 1, 0xff, -1, "LF clock adjustment data register"}, + {"dddlfrx.lfid00", 0x64, 1, 0xff, -1, "LF ID 0 data register byte 0"}, + {"dddlfrx.lfid01", 0x65, 1, 0xff, -1, "LF ID 0 data register byte 1"}, + {"dddlfrx.lfid02", 0x66, 1, 0xff, -1, "LF ID 0 data register byte 2"}, + {"dddlfrx.lfid03", 0x67, 1, 0xff, -1, "LF ID 0 data register byte 3"}, + {"dddlfrx.lfid10", 0x68, 1, 0xff, -1, "LF ID 1 data register byte 0"}, + {"dddlfrx.lfid11", 0x69, 1, 0xff, -1, "LF ID 1 data register byte 1"}, + {"dddlfrx.lfid12", 0x6a, 1, 0xff, -1, "LF ID 1 data register byte 2"}, + {"dddlfrx.lfid13", 0x6b, 1, 0xff, -1, "LF ID 1 data register byte 3"}, + {"dddlfrx.lfrd0", 0x6c, 1, 0xff, -1, "LF receive data register byte 0"}, + {"dddlfrx.lfrd1", 0x6d, 1, 0xff, -1, "LF receive data register byte 1"}, + {"dddlfrx.lfrd2", 0x6e, 1, 0xff, -1, "LF receive data register byte 2"}, + {"dddlfrx.lfrd3", 0x6f, 1, 0xff, -1, "LF receive data register byte 3"}, + {"dddlfrx.lfid0m", 0x70, 1, -1, -1, "LF identifier 0 mask register"}, + {"dddlfrx.lfid1m", 0x71, 1, -1, -1, "LF identifier 1 mask register"}, + {"dddlfrx.lfrdf", 0x72, 1, -1, -1, "LF receive data frame register"}, + {"dddlfrx.lfrsd1", 0x73, 1, 0xff, -1, "LF RSSI data register 1"}, + {"dddlfrx.lfrsd2", 0x74, 1, 0xff, -1, "LF RSSI data register 2"}, + {"dddlfrx.lfrsd3", 0x75, 1, 0xff, -1, "LF RSSI data register 3"}, + {"dddlfrx.lfcc1", 0x76, 1, 0x0f, -1, "LF channel capacity select register 1"}, + {"dddlfrx.lfcc2", 0x77, 1, 0x0f, -1, "LF channel capacity select register 2"}, + {"dddlfrx.lfcc3", 0x78, 1, 0x0f, -1, "LF channel capacity select register 3"}, + {"afe.tpimr", 0x7c, 1, -1, -1, "transponder interrupt mask register"}, + {"rtc_timer.rtccr", 0x7e, 1, -1, -1, "real-time clock control register"}, + {"rtc_timer.rtcdr", 0x7f, 1, 0xff, -1, "real time clock data register"}, + {"mod.tmmdr", 0x88, 1, 0x0f, -1, "timer modulator manchester data register"}, + {"mod.tmbdr", 0x89, 1, 0x0f, -1, "timer modulator biphase data register"}, + {"mod.tmtdr", 0x8a, 1, 0xff, -1, "timer modulator transmit data register"}, + {"mod.tmsr", 0x8b, 1, 0xff, -1, "timer modulator shift register"}, + {"crc.crcdr", 0x8d, 1, 0xff, -1, "CRC data register"}, + {"crc.crccr", 0x8e, 1, -1, -1, "CRC control register"}, + {"crc.crcsr", 0x8f, 1, -1, -1, "CRC status register"}, +}; + // ATA5790N ATA5791 const Register_file rgftab_ata5790n[117] = { // I/O memory [0, 223] + 32 {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, @@ -29942,6 +26495,89 @@ const Register_file rgftab_ata5835[307] = { // I/O memory [0, 479] + 32 {"trace.trcid", 0x160, 2, 0xffff, -1, "trace ID register (16 bits)"}, }; +// ATA6285 ATA6286 +const Register_file rgftab_ata6285[79] = { // I/O memory [0, 223] + 32 + {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, + {"portb.ddrb", 0x04, 1, 0xff, -1, "port B data direction register"}, + {"portb.portb", 0x05, 1, 0xff, -1, "port B data register"}, + {"portc.pinc", 0x06, 1, 0x07, -1, "port C input register"}, + {"portc.ddrc", 0x07, 1, 0x07, -1, "port C data direction register"}, + {"portc.portc", 0x08, 1, 0x07, -1, "port C data register"}, + {"portd.pind", 0x09, 1, 0xff, -1, "port D input register"}, + {"portd.ddrd", 0x0a, 1, 0xff, -1, "port D data direction register"}, + {"portd.portd", 0x0b, 1, 0xff, -1, "port D data register"}, + {"cpu.cmcr", 0x0f, 1, -1, -1, "clock management control register"}, + {"cpu.cmsr", 0x10, 1, -1, -1, "clock management status register"}, + {"timer_counter_2.t2cra", 0x11, 1, -1, -1, "timer 2 control register A"}, + {"timer_counter_2.t2crb", 0x12, 1, -1, -1, "timer 2 control register B"}, + {"timer_counter_3.t3cra", 0x14, 1, -1, -1, "timer 3 control register A"}, + {"cpu.vmcsr", 0x16, 1, -1, -1, "voltage monitor control and status register"}, + {"external_interrupt.pcifr", 0x17, 1, -1, -1, "pin change interrupt flag register"}, + {"lfrx.lffr", 0x18, 1, -1, -1, "LF flag register"}, + {"sensor_interface.ssfr", 0x19, 1, -1, -1, "sensor status + flag register"}, + {"timer_counter_0.t10ifr", 0x1a, 1, -1, -1, "timer1/0 interrupt flag register"}, + {"timer_counter_1.t10ifr", 0x1a, 1, -1, -1, "timer1/0 interrupt flag register"}, + {"timer_counter_2.t2ifr", 0x1b, 1, -1, -1, "timer 2 interrupt flag register"}, + {"timer_counter_3.t3ifr", 0x1c, 1, -1, -1, "timer 3 interrupt flag register"}, + {"external_interrupt.eifr", 0x1d, 1, -1, -1, "external interrupt flag register"}, + {"cpu.gpior0", 0x1e, 1, 0xff, -1, "general purpose I/O register 0"}, + {"eeprom.eecr", 0x1f, 1, -1, -1, "EEPROM control register"}, + {"eeprom.eedr", 0x20, 1, 0xff, -1, "EEPROM data register"}, + {"eeprom.eear", 0x21, 2, 0x01ff, -1, "EEPROM address register (16 bits)"}, + {"external_interrupt.pcicr", 0x23, 1, -1, -1, "pin change interrupt control register"}, + {"external_interrupt.eimsk", 0x24, 1, -1, -1, "external interrupt mask register"}, + {"sensor_interface.svcr", 0x27, 1, 0x1f, -1, "sensor voltage control register"}, + {"sensor_interface.scr", 0x28, 1, -1, -1, "sensor control register"}, + {"sensor_interface.sccr", 0x29, 1, -1, -1, "sensor capacitor control register"}, + {"cpu.gpior1", 0x2a, 1, 0xff, -1, "general purpose I/O register 1"}, + {"cpu.gpior2", 0x2b, 1, 0xff, -1, "general purpose I/O register 2"}, + {"spi.spcr", 0x2c, 1, -1, -1, "SPI control register"}, + {"spi.spsr", 0x2d, 1, -1, -1, "SPI status register"}, + {"spi.spdr", 0x2e, 1, 0xff, -1, "SPI data register"}, + {"timer_counter_2.t2mdr", 0x2f, 1, 0xff, -1, "timer 2 modulator data register"}, + {"lfrx.lfrr", 0x30, 1, 0x7f, -1, "LF RSSI data register"}, + {"lfrx.lfcdr", 0x32, 1, -1, -1, "LF receiver control und data register"}, + {"cpu.smcr", 0x33, 1, -1, -1, "sleep mode control register"}, + {"cpu.mcusr", 0x34, 1, -1, -1, "MCU status register"}, + {"cpu.mcucr", 0x35, 1, -1, -1, "MCU control register"}, + {"lfrx.lfrb", 0x36, 1, 0xff, -1, "LF receiver data buffer register"}, + {"cpu.spmcsr", 0x37, 1, -1, -1, "store program memory control and status register"}, + {"timer_counter_1.t1cr", 0x38, 1, -1, -1, "timer 1 control register"}, + {"timer_counter_0.t0cr", 0x39, 1, -1, -1, "timer 0 control register"}, + {"cpu.cmimr", 0x3b, 1, -1, -1, "clock management interrupt mask register"}, + {"cpu.clkpr", 0x3c, 1, -1, -1, "clock prescaler register"}, + {"cpu.sp", 0x3d, 2, 0xffff, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x3f, 1, -1, -1, "status register"}, + {"wdt.wdtcr", 0x40, 1, -1, -1, "watchdog timer control register"}, + {"sensor_interface.simsk", 0x41, 1, -1, -1, "sensor interrupt mask register"}, + {"sensor_interface.tscr", 0x44, 1, -1, -1, "temperature sensor control register"}, + {"cpu.srccal", 0x45, 1, 0xff, -1, "slow RC oscillator calibration register"}, + {"cpu.frccal", 0x46, 1, 0x3f, -1, "fast RC oscillator calibration register"}, + {"sensor_interface.msvcal", 0x47, 1, 0xff, -1, "motion sensor voltage calibration register"}, + {"external_interrupt.eicra", 0x49, 1, -1, -1, "external interrupt control register A"}, + {"external_interrupt.pcmsk0", 0x4a, 1, -1, -1, "pin change interrupt mask register 0"}, + {"external_interrupt.pcmsk1", 0x4b, 1, -1, -1, "pin change interrupt mask register 1"}, + {"external_interrupt.pcmsk2", 0x4c, 1, -1, -1, "pin change interrupt mask register 2"}, + {"timer_counter_2.t2icrl", 0x4e, 1, 0xff, -1, "timer 2 input capture register low byte"}, + {"timer_counter_2.t2icr", 0x4f, 1, 0xff, -1, "timer 2 input capture register high byte"}, + {"timer_counter_2.t2cor", 0x50, 2, 0xffff, -1, "timer 2 compare register (16 bits)"}, + {"timer_counter_2.t2mra", 0x52, 1, -1, -1, "timer 2 mode register A"}, + {"timer_counter_2.t2mrb", 0x53, 1, -1, -1, "timer 2 mode register B"}, + {"timer_counter_2.t2imr", 0x54, 1, -1, -1, "timer 2 interrupt mask register"}, + {"timer_counter_3.t3icr", 0x56, 2, 0xffff, -1, "timer 3 input capture register (16 bits)"}, + {"timer_counter_3.t3cora", 0x58, 2, 0xffff, -1, "timer 3 compare register A (16 bits)"}, + {"timer_counter_3.t3corb", 0x5a, 2, 0xffff, -1, "timer 3 compare register B (16 bits)"}, + {"timer_counter_3.t3mra", 0x5c, 1, -1, -1, "timer 3 mode register A"}, + {"timer_counter_3.t3mrb", 0x5d, 1, -1, -1, "timer 3 mode register B"}, + {"timer_counter_3.t3crb", 0x5e, 1, -1, -1, "timer 3 control register B"}, + {"timer_counter_3.t3imr", 0x5f, 1, -1, -1, "timer 3 interrupt mask register"}, + {"lfrx.lfimr", 0x61, 1, -1, -1, "LF interrupt mask register"}, + {"lfrx.lfrcr", 0x62, 1, -1, -1, "LF receiver control register"}, + {"lfrx.lfhcr", 0x63, 1, 0x7f, -1, "LF header compare register"}, + {"lfrx.lfidc", 0x64, 2, 0xffff, -1, "LF ID compare register (16 bits)"}, + {"lfrx.lfcal", 0x66, 2, 0xffff, -1, "LF calibration register (16 bits)"}, +}; + // ATA6612C ATA6613C const Register_file rgftab_ata6612c[81] = { // I/O memory [0, 223] + 32 {"portb.pinb", 0x03, 1, 0xff, -1, "port B input register"}, @@ -30197,3291 +26833,6 @@ const Register_file rgftab_ata6616c[81] = { // I/O memory [0, 223] + 32 {"linuart.lindat", 0xb2, 1, -1, -1, "LIN data register"}, }; -// ATxmega16A4 ATxmega32A4 -const Register_file rgftab_atxmega16a4[553] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, -}; - -// ATxmega16A4U ATxmega32A4U -const Register_file rgftab_atxmega16a4u[630] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, - {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, - {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, - {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, - {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, - {"usb.status", 0x4c2, 1, -1, -1, "status register"}, - {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, - {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, - {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, - {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, - {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, - {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, - {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, - {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, - {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, - {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, - {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, - {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, -}; - -// ATxmega16C4 ATxmega32C4 -const Register_file rgftab_atxmega16c4[482] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, - {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, - {"usb.status", 0x4c2, 1, -1, -1, "status register"}, - {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, - {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, - {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, - {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, - {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, - {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, - {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, - {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, - {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, - {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, - {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, - {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, -}; - -// ATxmega16D4 ATxmega32D4 -const Register_file rgftab_atxmega16d4[460] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, - {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, - {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, -}; - -// ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 -const Register_file rgftab_atxmega32c3[569] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, - {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, - {"usb.status", 0x4c2, 1, -1, -1, "status register"}, - {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, - {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, - {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, - {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, - {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, - {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, - {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, - {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, - {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, - {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, - {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, - {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, - {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, - {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, - {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, - {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, - {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, - {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, - {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, - {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, - {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, - {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, - {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, - {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, - {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, - {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, - {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, - {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, - {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, - {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, - {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, - {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, - {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, - {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, - {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, - {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, - {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, - {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, - {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, - {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, - {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, - {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, - {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, - {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, - {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, - {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, - {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, - {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, - {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, - {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, - {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, - {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, -}; - -// ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 -const Register_file rgftab_atxmega32d3[567] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, - {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, - {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, - {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, - {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, - {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, - {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, - {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, - {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, - {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, - {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, - {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, - {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, - {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, - {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, - {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, - {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, - {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, - {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, - {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, - {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, - {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, - {"awexe.status", 0xa84, 1, -1, -1, "status register"}, - {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, - {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, - {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, - {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, - {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, - {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, - {"spie.status", 0xac2, 1, -1, -1, "status register"}, - {"spie.data", 0xac3, 1, -1, -1, "data register"}, - {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, - {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, - {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, - {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, - {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, - {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, - {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, - {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, - {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, - {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, - {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, - {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, - {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, - {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, - {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, - {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, - {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, - {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, - {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, - {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, - {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, -}; - // ATxmega64A1 ATxmega128A1 const Register_file rgftab_atxmega64a1[814] = { // I/O memory [0, 4095] {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, @@ -35247,6 +28598,4766 @@ const Register_file rgftab_atxmega64a1u[943] = { // I/O memory [0, 4095] {"spif.data", 0xbc3, 1, -1, -1, "data register"}, }; +// ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 +const Register_file rgftab_atxmega64a3[680] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, + {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, + {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, + {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, + {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, + {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, + {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, + {"usartf1.data", 0xbb0, 1, -1, -1, "data register"}, + {"usartf1.status", 0xbb1, 1, -1, -1, "status register"}, + {"usartf1.ctrla", 0xbb3, 1, -1, -1, "control register A"}, + {"usartf1.ctrlb", 0xbb4, 1, -1, -1, "control register B"}, + {"usartf1.ctrlc", 0xbb5, 1, -1, -1, "control register C"}, + {"usartf1.baudctrla", 0xbb6, 1, -1, -1, "baud rate control register A"}, + {"usartf1.baudctrlb", 0xbb7, 1, -1, -1, "baud rate control register B"}, + {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, + {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, + {"spif.status", 0xbc2, 1, -1, -1, "status register"}, + {"spif.data", 0xbc3, 1, -1, -1, "data register"}, +}; + +// ATxmega256A3B +const Register_file rgftab_atxmega256a3b[665] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"vbat.ctrl", 0x0f0, 1, -1, -1, "control register"}, + {"vbat.status", 0x0f1, 1, -1, -1, "status register"}, + {"vbat.backup0", 0x0f2, 1, -1, -1, "backup register 0"}, + {"vbat.backup1", 0x0f3, 1, -1, -1, "backup register 1"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc32.ctrl", 0x420, 1, -1, -1, "control register"}, + {"rtc32.syncctrl", 0x421, 1, -1, -1, "synchronization control/status register"}, + {"rtc32.intctrl", 0x422, 1, -1, -1, "interrupt control register"}, + {"rtc32.intflags", 0x423, 1, -1, -1, "interrupt flags register"}, + {"rtc32.cnt", 0x424, 4, -1, -1, "counter (32 bits)"}, + {"rtc32.per", 0x428, 4, -1, -1, "period register (32 bits)"}, + {"rtc32.comp", 0x42c, 4, -1, -1, "compare register (32 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, + {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, + {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, + {"spif.status", 0xbc2, 1, -1, -1, "status register"}, + {"spif.data", 0xbc3, 1, -1, -1, "data register"}, +}; + +// ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3U +const Register_file rgftab_atxmega64a3u[792] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"acb.currctrl", 0x398, 1, -1, -1, "current source control register"}, + {"acb.currcalib", 0x399, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"usarte1.data", 0xab0, 1, -1, -1, "data register"}, + {"usarte1.status", 0xab1, 1, -1, -1, "status register"}, + {"usarte1.ctrla", 0xab3, 1, -1, -1, "control register A"}, + {"usarte1.ctrlb", 0xab4, 1, -1, -1, "control register B"}, + {"usarte1.ctrlc", 0xab5, 1, -1, -1, "control register C"}, + {"usarte1.baudctrla", 0xab6, 1, -1, -1, "baud rate control register A"}, + {"usarte1.baudctrlb", 0xab7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega256A3BU +const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"vbat.ctrl", 0x0f0, 1, -1, -1, "control register"}, + {"vbat.status", 0x0f1, 1, -1, -1, "status register"}, + {"vbat.backup0", 0x0f2, 1, -1, -1, "backup register 0"}, + {"vbat.backup1", 0x0f3, 1, -1, -1, "backup register 1"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, + {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, + {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, + {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, + {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, + {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, + {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, + {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, + {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, + {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, + {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, + {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, + {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, + {"acb.status", 0x397, 1, -1, -1, "status register"}, + {"rtc32.ctrl", 0x420, 1, -1, -1, "control register"}, + {"rtc32.syncctrl", 0x421, 1, -1, -1, "synchronization control/status register"}, + {"rtc32.intctrl", 0x422, 1, -1, -1, "interrupt control register"}, + {"rtc32.intflags", 0x423, 1, -1, -1, "interrupt flags register"}, + {"rtc32.cnt", 0x424, 4, -1, -1, "counter (32 bits)"}, + {"rtc32.per", 0x428, 4, -1, -1, "period register (32 bits)"}, + {"rtc32.comp", 0x42c, 4, -1, -1, "compare register (32 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, + {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, + {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, + {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, + {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, + {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, + {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, + {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, + {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, + {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, + {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, + {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, + {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, + {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, + {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, + {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, + {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, + {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, + {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, + {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, + {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, + {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega16A4 ATxmega32A4 +const Register_file rgftab_atxmega16a4[553] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega16A4U ATxmega32A4U +const Register_file rgftab_atxmega16a4u[630] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, +}; + +// ATxmega64A4U ATxmega128A4U +const Register_file rgftab_atxmega64a4u[632] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, + {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, + {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, + {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, + {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, + {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, + {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, + {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, + {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, + {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, + {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, + {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, + {"aes.status", 0x0c1, 1, -1, -1, "status register"}, + {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, + {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, + {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"dma.status", 0x104, 1, -1, -1, "status register"}, + {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, + {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, + {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, + {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, + {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, + {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, + {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, + {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, + {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, + {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, + {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, + {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, + {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, + {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, + {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, + {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, + {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, + {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, + {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, + {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, + {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, + {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, + {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, + {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, + {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, + {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, + {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, + {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, + {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, + {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, + {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, + {"dacb.status", 0x325, 1, -1, -1, "status register"}, + {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, + {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, + {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, + {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, + {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, + {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, + {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, + {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, + {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, + {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, + {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, + {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, + {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, + {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, + {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, +}; + // ATxmega64B1 ATxmega128B1 const Register_file rgftab_atxmega64b1[574] = { // I/O memory [0, 4095] {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, @@ -36287,24 +34398,12 @@ const Register_file rgftab_atxmega64b3[458] = { // I/O memory [0, 4095] {"lcd.data19", 0xd23, 1, -1, -1, "LCD data register 19"}, }; -// ATxmega64A4U ATxmega128A4U -const Register_file rgftab_atxmega64a4u[632] = { // I/O memory [0, 4095] +// ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 +const Register_file rgftab_atxmega32c3[569] = { // I/O memory [0, 4095] {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, @@ -36359,629 +34458,6 @@ const Register_file rgftab_atxmega64a4u[632] = { // I/O memory [0, 4095] {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, - {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, - {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, - {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, - {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, - {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, - {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, - {"rtc.status", 0x401, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, - {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, - {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, - {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, - {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, - {"usb.status", 0x4c2, 1, -1, -1, "status register"}, - {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, - {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, - {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, - {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, - {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, - {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, - {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, - {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, - {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, - {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, - {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, - {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, -}; - -// ATxmega64D4 ATxmega128D4 -const Register_file rgftab_atxmega64d4[460] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, @@ -37083,1275 +34559,6 @@ const Register_file rgftab_atxmega64d4[460] = { // I/O memory [0, 4095] {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, - {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, - {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, - {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, - {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, - {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, - {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, - {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, - {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, - {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, - {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, - {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, - {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, -}; - -// ATxmega256A3B -const Register_file rgftab_atxmega256a3b[665] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"vbat.ctrl", 0x0f0, 1, -1, -1, "control register"}, - {"vbat.status", 0x0f1, 1, -1, -1, "status register"}, - {"vbat.backup0", 0x0f2, 1, -1, -1, "backup register 0"}, - {"vbat.backup1", 0x0f3, 1, -1, -1, "backup register 1"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, - {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, - {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, - {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, - {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, - {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, - {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, - {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, - {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.timctrl", 0x324, 1, -1, -1, "timing control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, - {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, - {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, - {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, - {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, - {"acb.status", 0x397, 1, -1, -1, "status register"}, - {"rtc32.ctrl", 0x420, 1, -1, -1, "control register"}, - {"rtc32.syncctrl", 0x421, 1, -1, -1, "synchronization control/status register"}, - {"rtc32.intctrl", 0x422, 1, -1, -1, "interrupt control register"}, - {"rtc32.intflags", 0x423, 1, -1, -1, "interrupt flags register"}, - {"rtc32.cnt", 0x424, 4, -1, -1, "counter (32 bits)"}, - {"rtc32.per", 0x428, 4, -1, -1, "period register (32 bits)"}, - {"rtc32.comp", 0x42c, 4, -1, -1, "compare register (32 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, - {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, - {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, - {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, - {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, - {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, - {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, - {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, - {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, - {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, - {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, - {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, - {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, - {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, - {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, - {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, - {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, - {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, - {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, - {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, - {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, - {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, - {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, - {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, - {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, - {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, - {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, - {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, - {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, - {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, - {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, - {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, - {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, - {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, - {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, - {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, - {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, - {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, - {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, - {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, - {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, - {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, - {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, - {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, - {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, - {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, - {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, - {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, - {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, - {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, - {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, - {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, - {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, - {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, - {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, - {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, - {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, - {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, - {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, - {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, - {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, - {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, - {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, - {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, - {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, - {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, - {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, - {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, - {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, - {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, - {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, - {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, - {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, - {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, - {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, - {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, - {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, - {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, - {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, - {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, - {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, - {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, - {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, - {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, - {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, - {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, - {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, - {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, - {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, - {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, - {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, - {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, - {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, - {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, - {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, - {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, - {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, - {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, - {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, - {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, - {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, - {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, - {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, - {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, - {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, - {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, - {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, - {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, - {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, - {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, - {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, - {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, - {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, - {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, - {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, - {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, - {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, - {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, - {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, - {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, - {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, - {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, - {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, - {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, - {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, - {"awexc.status", 0x884, 1, -1, -1, "status register"}, - {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, - {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, - {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, - {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, - {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, - {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, - {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, - {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, - {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, - {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, - {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, - {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, - {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, - {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, - {"spic.status", 0x8c2, 1, -1, -1, "status register"}, - {"spic.data", 0x8c3, 1, -1, -1, "data register"}, - {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, - {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, - {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, - {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, - {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, - {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, - {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, - {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, - {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, - {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, - {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, - {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, - {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, - {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, - {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, - {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, - {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, - {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, - {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, - {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, - {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, - {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, - {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, - {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, - {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, - {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, - {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, - {"spid.status", 0x9c2, 1, -1, -1, "status register"}, - {"spid.data", 0x9c3, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, - {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, - {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, - {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, - {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, - {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, - {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, - {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, - {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, - {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, - {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, - {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, - {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, - {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, - {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, - {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, - {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, - {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, - {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, - {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, - {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, - {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, - {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, - {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, - {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, - {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, - {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, - {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, - {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, - {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, - {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, - {"awexe.status", 0xa84, 1, -1, -1, "status register"}, - {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, - {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, - {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, - {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, - {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, - {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, - {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, - {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, - {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, - {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, - {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, - {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, - {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, - {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, - {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, - {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, - {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, - {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, - {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, - {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, - {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, - {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, - {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, - {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, - {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, - {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, - {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, - {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, - {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, - {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, - {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, - {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, - {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, - {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, - {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, - {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, - {"spif.ctrl", 0xbc0, 1, -1, -1, "control register"}, - {"spif.intctrl", 0xbc1, 1, -1, -1, "interrupt control register"}, - {"spif.status", 0xbc2, 1, -1, -1, "status register"}, - {"spif.data", 0xbc3, 1, -1, -1, "data register"}, -}; - -// ATxmega256A3BU -const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] - {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, - {"gpio.gpior4", 0x004, 1, -1, -1, "general purpose I/O register 4"}, - {"gpio.gpior5", 0x005, 1, -1, -1, "general purpose I/O register 5"}, - {"gpio.gpior6", 0x006, 1, -1, -1, "general purpose I/O register 6"}, - {"gpio.gpior7", 0x007, 1, -1, -1, "general purpose I/O register 7"}, - {"gpio.gpior8", 0x008, 1, -1, -1, "general purpose I/O register 8"}, - {"gpio.gpior9", 0x009, 1, -1, -1, "general purpose I/O register 9"}, - {"gpio.gpiora", 0x00a, 1, -1, -1, "general purpose I/O register 10"}, - {"gpio.gpiorb", 0x00b, 1, -1, -1, "general purpose I/O register 11"}, - {"gpio.gpiorc", 0x00c, 1, -1, -1, "general purpose I/O register 12"}, - {"gpio.gpiord", 0x00d, 1, -1, -1, "general purpose I/O register 13"}, - {"gpio.gpiore", 0x00e, 1, -1, -1, "general purpose I/O register 14"}, - {"gpio.gpiorf", 0x00f, 1, -1, -1, "general purpose I/O register 15"}, - {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, - {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, - {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, - {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, - {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, - {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, - {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, - {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, - {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, - {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, - {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, - {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, - {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, - {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, - {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, - {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, - {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, - {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, - {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, - {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, - {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, - {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, - {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, - {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, - {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, - {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, - {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, - {"clk.lock", 0x042, 1, -1, -1, "lock register"}, - {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, - {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, - {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, - {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, - {"osc.status", 0x051, 1, -1, -1, "status register"}, - {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, - {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, - {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, - {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, - {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, - {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, - {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, - {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, - {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, - {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, - {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, - {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, - {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, - {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, - {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, - {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, - {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, - {"pr.prpb", 0x072, 1, -1, -1, "power reduction port B register"}, - {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, - {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, - {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, - {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, - {"rst.status", 0x078, 1, -1, -1, "status register"}, - {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, - {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, - {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, - {"wdt.status", 0x082, 1, -1, -1, "status register"}, - {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, - {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, - {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, - {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, - {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, - {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, - {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, - {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, - {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, - {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, - {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, - {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, - {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, - {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, - {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, - {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, - {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, - {"aes.ctrl", 0x0c0, 1, -1, -1, "control register"}, - {"aes.status", 0x0c1, 1, -1, -1, "status register"}, - {"aes.state", 0x0c2, 1, -1, -1, "AES state register"}, - {"aes.key", 0x0c3, 1, -1, -1, "AES key register"}, - {"aes.intctrl", 0x0c4, 1, -1, -1, "interrupt control register"}, - {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, - {"crc.status", 0x0d1, 1, -1, -1, "status register"}, - {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, - {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, - {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, - {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, - {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, - {"vbat.ctrl", 0x0f0, 1, -1, -1, "control register"}, - {"vbat.status", 0x0f1, 1, -1, -1, "status register"}, - {"vbat.backup0", 0x0f2, 1, -1, -1, "backup register 0"}, - {"vbat.backup1", 0x0f3, 1, -1, -1, "backup register 1"}, - {"dma.ctrl", 0x100, 1, -1, -1, "control register"}, - {"dma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, - {"dma.status", 0x104, 1, -1, -1, "status register"}, - {"dma.temp", 0x106, 2, -1, -1, "temporary register for 16-bit access (16 bits)"}, - {"dma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, - {"dma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, - {"dma.ch0.addrctrl", 0x112, 1, -1, -1, "address control register"}, - {"dma.ch0.trigsrc", 0x113, 1, -1, -1, "channel trigger source register"}, - {"dma.ch0.trfcnt", 0x114, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch0.repcnt", 0x116, 1, -1, -1, "channel repeat counter"}, - {"dma.ch0.srcaddr0", 0x118, 1, -1, -1, "channel source address register 0"}, - {"dma.ch0.srcaddr1", 0x119, 1, -1, -1, "channel source address register 1"}, - {"dma.ch0.srcaddr2", 0x11a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch0.destaddr0", 0x11c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch0.destaddr1", 0x11d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch0.destaddr2", 0x11e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, - {"dma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, - {"dma.ch1.addrctrl", 0x122, 1, -1, -1, "address control register"}, - {"dma.ch1.trigsrc", 0x123, 1, -1, -1, "channel trigger source register"}, - {"dma.ch1.trfcnt", 0x124, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch1.repcnt", 0x126, 1, -1, -1, "channel repeat counter"}, - {"dma.ch1.srcaddr0", 0x128, 1, -1, -1, "channel source address register 0"}, - {"dma.ch1.srcaddr1", 0x129, 1, -1, -1, "channel source address register 1"}, - {"dma.ch1.srcaddr2", 0x12a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch1.destaddr0", 0x12c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch1.destaddr1", 0x12d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch1.destaddr2", 0x12e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, - {"dma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, - {"dma.ch2.addrctrl", 0x132, 1, -1, -1, "address control register"}, - {"dma.ch2.trigsrc", 0x133, 1, -1, -1, "channel trigger source register"}, - {"dma.ch2.trfcnt", 0x134, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch2.repcnt", 0x136, 1, -1, -1, "channel repeat counter"}, - {"dma.ch2.srcaddr0", 0x138, 1, -1, -1, "channel source address register 0"}, - {"dma.ch2.srcaddr1", 0x139, 1, -1, -1, "channel source address register 1"}, - {"dma.ch2.srcaddr2", 0x13a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch2.destaddr0", 0x13c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch2.destaddr1", 0x13d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch2.destaddr2", 0x13e, 1, -1, -1, "channel destination address register 2"}, - {"dma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, - {"dma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, - {"dma.ch3.addrctrl", 0x142, 1, -1, -1, "address control register"}, - {"dma.ch3.trigsrc", 0x143, 1, -1, -1, "channel trigger source register"}, - {"dma.ch3.trfcnt", 0x144, 2, -1, -1, "channel block transfer counter (16 bits)"}, - {"dma.ch3.repcnt", 0x146, 1, -1, -1, "channel repeat counter"}, - {"dma.ch3.srcaddr0", 0x148, 1, -1, -1, "channel source address register 0"}, - {"dma.ch3.srcaddr1", 0x149, 1, -1, -1, "channel source address register 1"}, - {"dma.ch3.srcaddr2", 0x14a, 1, -1, -1, "channel source address register 2"}, - {"dma.ch3.destaddr0", 0x14c, 1, -1, -1, "channel destination address register 0"}, - {"dma.ch3.destaddr1", 0x14d, 1, -1, -1, "channel destination address register 1"}, - {"dma.ch3.destaddr2", 0x14e, 1, -1, -1, "channel destination address register 2"}, - {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, - {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, - {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, - {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, - {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, - {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, - {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, - {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, - {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, - {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, - {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, - {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, - {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, - {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, - {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, - {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, - {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, - {"evsys.data", 0x191, 1, -1, -1, "data register"}, - {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, - {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, - {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, - {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, - {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, - {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, - {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, - {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, - {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, - {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, - {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, - {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, - {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, - {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, - {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, - {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, - {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, - {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, - {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, - {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, - {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, - {"adcb.ctrla", 0x240, 1, -1, -1, "control register A"}, - {"adcb.ctrlb", 0x241, 1, -1, -1, "control register B"}, - {"adcb.refctrl", 0x242, 1, -1, -1, "reference control register"}, - {"adcb.evctrl", 0x243, 1, -1, -1, "event control register"}, - {"adcb.prescaler", 0x244, 1, -1, -1, "clock prescaler register"}, - {"adcb.intflags", 0x246, 1, -1, -1, "interrupt flags register"}, - {"adcb.temp", 0x247, 1, -1, -1, "temporary register"}, - {"adcb.cal", 0x24c, 2, -1, -1, "calibration register (16 bits)"}, - {"adcb.ch0res", 0x250, 2, -1, -1, "channel 0 result register (16 bits)"}, - {"adcb.ch1res", 0x252, 2, -1, -1, "channel 1 result register (16 bits)"}, - {"adcb.ch2res", 0x254, 2, -1, -1, "channel 2 result register (16 bits)"}, - {"adcb.ch3res", 0x256, 2, -1, -1, "channel 3 result register (16 bits)"}, - {"adcb.cmp", 0x258, 2, -1, -1, "compare register (16 bits)"}, - {"adc.ch0.ctrl", 0x260, 1, -1, -1, "control register"}, - {"adc.ch0.muxctrl", 0x261, 1, -1, -1, "MUX control register"}, - {"adc.ch0.intctrl", 0x262, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch0.intflags", 0x263, 1, -1, -1, "interrupt flags register"}, - {"adc.ch0.res", 0x264, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch0.scan", 0x266, 1, -1, -1, "input channel scan register"}, - {"adc.ch1.ctrl", 0x268, 1, -1, -1, "control register"}, - {"adc.ch1.muxctrl", 0x269, 1, -1, -1, "MUX control register"}, - {"adc.ch1.intctrl", 0x26a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch1.intflags", 0x26b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch1.res", 0x26c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch1.scan", 0x26e, 1, -1, -1, "input channel scan register"}, - {"adc.ch2.ctrl", 0x270, 1, -1, -1, "control register"}, - {"adc.ch2.muxctrl", 0x271, 1, -1, -1, "MUX control register"}, - {"adc.ch2.intctrl", 0x272, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch2.intflags", 0x273, 1, -1, -1, "interrupt flags register"}, - {"adc.ch2.res", 0x274, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch2.scan", 0x276, 1, -1, -1, "input channel scan register"}, - {"adc.ch3.ctrl", 0x278, 1, -1, -1, "control register"}, - {"adc.ch3.muxctrl", 0x279, 1, -1, -1, "MUX control register"}, - {"adc.ch3.intctrl", 0x27a, 1, -1, -1, "channel interrupt control register"}, - {"adc.ch3.intflags", 0x27b, 1, -1, -1, "interrupt flags register"}, - {"adc.ch3.res", 0x27c, 2, -1, -1, "channel result register (16 bits)"}, - {"adc.ch3.scan", 0x27e, 1, -1, -1, "input channel scan register"}, - {"dacb.ctrla", 0x320, 1, -1, -1, "control register A"}, - {"dacb.ctrlb", 0x321, 1, -1, -1, "control register B"}, - {"dacb.ctrlc", 0x322, 1, -1, -1, "control register C"}, - {"dacb.evctrl", 0x323, 1, -1, -1, "event control register"}, - {"dacb.status", 0x325, 1, -1, -1, "status register"}, - {"dacb.ch0gaincal", 0x328, 1, -1, -1, "gain calibration register"}, - {"dacb.ch0offsetcal", 0x329, 1, -1, -1, "offset calibration register"}, - {"dacb.ch1gaincal", 0x32a, 1, -1, -1, "gain calibration register"}, - {"dacb.ch1offsetcal", 0x32b, 1, -1, -1, "offset calibration register"}, - {"dacb.ch0data", 0x338, 2, -1, -1, "channel 0 data register (16 bits)"}, - {"dacb.ch1data", 0x33a, 2, -1, -1, "channel 1 data register (16 bits)"}, - {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, - {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, - {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, - {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, - {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, - {"aca.status", 0x387, 1, -1, -1, "status register"}, - {"acb.ac0ctrl", 0x390, 1, -1, -1, "analog comparator 0 control register"}, - {"acb.ac1ctrl", 0x391, 1, -1, -1, "analog comparator 1 control register"}, - {"acb.ac0muxctrl", 0x392, 1, -1, -1, "analog comparator 0 MUX control register"}, - {"acb.ac1muxctrl", 0x393, 1, -1, -1, "analog comparator 1 MUX control register"}, - {"acb.ctrla", 0x394, 1, -1, -1, "control register A"}, - {"acb.ctrlb", 0x395, 1, -1, -1, "control register B"}, - {"acb.winctrl", 0x396, 1, -1, -1, "window mode control register"}, - {"acb.status", 0x397, 1, -1, -1, "status register"}, - {"rtc32.ctrl", 0x420, 1, -1, -1, "control register"}, - {"rtc32.syncctrl", 0x421, 1, -1, -1, "synchronization control/status register"}, - {"rtc32.intctrl", 0x422, 1, -1, -1, "interrupt control register"}, - {"rtc32.intflags", 0x423, 1, -1, -1, "interrupt flags register"}, - {"rtc32.cnt", 0x424, 4, -1, -1, "counter (32 bits)"}, - {"rtc32.per", 0x428, 4, -1, -1, "period register (32 bits)"}, - {"rtc32.comp", 0x42c, 4, -1, -1, "compare register (32 bits)"}, - {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, - {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, - {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, - {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, - {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, - {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, - {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, - {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, - {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, - {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, - {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, - {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, - {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, - {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, - {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, {"usb.status", 0x4c2, 1, -1, -1, "status register"}, @@ -38605,13 +34812,6 @@ const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, - {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, - {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, - {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, - {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, - {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, - {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, - {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, {"spic.status", 0x8c2, 1, -1, -1, "status register"}, @@ -38663,27 +34863,6 @@ const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tcd1.ctrla", 0x940, 1, -1, -1, "control register A"}, - {"tcd1.ctrlb", 0x941, 1, -1, -1, "control register B"}, - {"tcd1.ctrlc", 0x942, 1, -1, -1, "control register C"}, - {"tcd1.ctrld", 0x943, 1, -1, -1, "control register D"}, - {"tcd1.ctrle", 0x944, 1, -1, -1, "control register E"}, - {"tcd1.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, - {"tcd1.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, - {"tcd1.ctrlfclr", 0x948, 1, -1, -1, "control register F clear"}, - {"tcd1.ctrlfset", 0x949, 1, -1, -1, "control register F set"}, - {"tcd1.ctrlgclr", 0x94a, 1, -1, -1, "control register G clear"}, - {"tcd1.ctrlgset", 0x94b, 1, -1, -1, "control register G set"}, - {"tcd1.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, - {"tcd1.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcd1.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, - {"tcd1.per", 0x966, 2, -1, -1, "period register (16 bits)"}, - {"tcd1.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tcd1.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tcd1.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, - {"tcd1.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tcd1.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"hiresd.ctrla", 0x990, 1, -1, -1, "control register A"}, {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, @@ -38691,13 +34870,6 @@ const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, - {"usartd1.data", 0x9b0, 1, -1, -1, "data register"}, - {"usartd1.status", 0x9b1, 1, -1, -1, "status register"}, - {"usartd1.ctrla", 0x9b3, 1, -1, -1, "control register A"}, - {"usartd1.ctrlb", 0x9b4, 1, -1, -1, "control register B"}, - {"usartd1.ctrlc", 0x9b5, 1, -1, -1, "control register C"}, - {"usartd1.baudctrla", 0x9b6, 1, -1, -1, "baud rate control register A"}, - {"usartd1.baudctrlb", 0x9b7, 1, -1, -1, "baud rate control register B"}, {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, {"spid.status", 0x9c2, 1, -1, -1, "status register"}, @@ -38746,39 +34918,6 @@ const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"tce1.ctrla", 0xa40, 1, -1, -1, "control register A"}, - {"tce1.ctrlb", 0xa41, 1, -1, -1, "control register B"}, - {"tce1.ctrlc", 0xa42, 1, -1, -1, "control register C"}, - {"tce1.ctrld", 0xa43, 1, -1, -1, "control register D"}, - {"tce1.ctrle", 0xa44, 1, -1, -1, "control register E"}, - {"tce1.intctrla", 0xa46, 1, -1, -1, "interrupt control register A"}, - {"tce1.intctrlb", 0xa47, 1, -1, -1, "interrupt control register B"}, - {"tce1.ctrlfclr", 0xa48, 1, -1, -1, "control register F clear"}, - {"tce1.ctrlfset", 0xa49, 1, -1, -1, "control register F set"}, - {"tce1.ctrlgclr", 0xa4a, 1, -1, -1, "control register G clear"}, - {"tce1.ctrlgset", 0xa4b, 1, -1, -1, "control register G set"}, - {"tce1.intflags", 0xa4c, 1, -1, -1, "interrupt flags register"}, - {"tce1.temp", 0xa4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tce1.cnt", 0xa60, 2, -1, -1, "counter (16 bits)"}, - {"tce1.per", 0xa66, 2, -1, -1, "period register (16 bits)"}, - {"tce1.cca", 0xa68, 2, -1, -1, "compare or capture A register (16 bits)"}, - {"tce1.ccb", 0xa6a, 2, -1, -1, "compare or capture B register (16 bits)"}, - {"tce1.perbuf", 0xa76, 2, -1, -1, "period buffer register (16 bits)"}, - {"tce1.ccabuf", 0xa78, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, - {"tce1.ccbbuf", 0xa7a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, - {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, - {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, - {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, - {"awexe.status", 0xa84, 1, -1, -1, "status register"}, - {"awexe.statusset", 0xa85, 1, -1, -1, "status set register"}, - {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, - {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, - {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, - {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, - {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, - {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, - {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, - {"hirese.ctrla", 0xa90, 1, -1, -1, "control register A"}, {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, @@ -38830,14 +34969,6 @@ const Register_file rgftab_atxmega256a3bu[780] = { // I/O memory [0, 4095] {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, - {"hiresf.ctrla", 0xb90, 1, -1, -1, "control register A"}, - {"usartf0.data", 0xba0, 1, -1, -1, "data register"}, - {"usartf0.status", 0xba1, 1, -1, -1, "status register"}, - {"usartf0.ctrla", 0xba3, 1, -1, -1, "control register A"}, - {"usartf0.ctrlb", 0xba4, 1, -1, -1, "control register B"}, - {"usartf0.ctrlc", 0xba5, 1, -1, -1, "control register C"}, - {"usartf0.baudctrla", 0xba6, 1, -1, -1, "baud rate control register A"}, - {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, }; // ATxmega384C3 @@ -39447,6 +35578,1063 @@ const Register_file rgftab_atxmega384c3[603] = { // I/O memory [0, 4095] {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, }; +// ATxmega16C4 ATxmega32C4 +const Register_file rgftab_atxmega16c4[482] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"clk.usbctrl", 0x044, 1, -1, -1, "USB control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"usb.ctrla", 0x4c0, 1, -1, -1, "control register A"}, + {"usb.ctrlb", 0x4c1, 1, -1, -1, "control register B"}, + {"usb.status", 0x4c2, 1, -1, -1, "status register"}, + {"usb.addr", 0x4c3, 1, -1, -1, "address register"}, + {"usb.fifowp", 0x4c4, 1, -1, -1, "FIFO write pointer register"}, + {"usb.fiforp", 0x4c5, 1, -1, -1, "FIFO read pointer register"}, + {"usb.epptr", 0x4c6, 2, -1, -1, "endpoint configuration table pointer register (16 bits)"}, + {"usb.intctrla", 0x4c8, 1, -1, -1, "interrupt control register A"}, + {"usb.intctrlb", 0x4c9, 1, -1, -1, "interrupt control register B"}, + {"usb.intflagsaclr", 0x4ca, 1, -1, -1, "clear interrupt flag register A"}, + {"usb.intflagsaset", 0x4cb, 1, -1, -1, "set interrupt flag register A"}, + {"usb.intflagsbclr", 0x4cc, 1, -1, -1, "clear interrupt flag register B"}, + {"usb.intflagsbset", 0x4cd, 1, -1, -1, "set interrupt flag register B"}, + {"usb.cal0", 0x4fa, 1, -1, -1, "calibration byte 0"}, + {"usb.cal1", 0x4fb, 1, -1, -1, "calibration byte 1"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"usartc1.data", 0x8b0, 1, -1, -1, "data register"}, + {"usartc1.status", 0x8b1, 1, -1, -1, "status register"}, + {"usartc1.ctrla", 0x8b3, 1, -1, -1, "control register A"}, + {"usartc1.ctrlb", 0x8b4, 1, -1, -1, "control register B"}, + {"usartc1.ctrlc", 0x8b5, 1, -1, -1, "control register C"}, + {"usartc1.baudctrla", 0x8b6, 1, -1, -1, "baud rate control register A"}, + {"usartc1.baudctrlb", 0x8b7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 +const Register_file rgftab_atxmega32d3[567] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portf.dir", 0x6a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x6a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x6a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x6a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x6a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x6a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x6a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x6a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x6a8, 1, -1, -1, "I/O port input register"}, + {"portf.intctrl", 0x6a9, 1, -1, -1, "interrupt control register"}, + {"portf.int0mask", 0x6aa, 1, -1, -1, "port interrupt 0 mask register"}, + {"portf.int1mask", 0x6ab, 1, -1, -1, "port interrupt 1 mask register"}, + {"portf.intflags", 0x6ac, 1, -1, -1, "interrupt flags register"}, + {"portf.remap", 0x6ae, 1, -1, -1, "I/O port pins remap register"}, + {"portf.pin0ctrl", 0x6b0, 1, -1, -1, "pin 0 control register"}, + {"portf.pin1ctrl", 0x6b1, 1, -1, -1, "pin 1 control register"}, + {"portf.pin2ctrl", 0x6b2, 1, -1, -1, "pin 2 control register"}, + {"portf.pin3ctrl", 0x6b3, 1, -1, -1, "pin 3 control register"}, + {"portf.pin4ctrl", 0x6b4, 1, -1, -1, "pin 4 control register"}, + {"portf.pin5ctrl", 0x6b5, 1, -1, -1, "pin 5 control register"}, + {"portf.pin6ctrl", 0x6b6, 1, -1, -1, "pin 6 control register"}, + {"portf.pin7ctrl", 0x6b7, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce2.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce2.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce2.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce2.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce2.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce2.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce2.ctrlf", 0xa09, 1, -1, -1, "control register F"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce2.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce2.lcnt", 0xa20, 1, -1, -1, "low byte counter"}, + {"tce2.hcnt", 0xa21, 1, -1, -1, "high byte counter"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce2.lper", 0xa26, 1, -1, -1, "low byte period register"}, + {"tce2.hper", 0xa27, 1, -1, -1, "high byte period register"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce2.lcmpa", 0xa28, 1, -1, -1, "low byte compare A"}, + {"tce2.hcmpa", 0xa29, 1, -1, -1, "high byte compare A"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce2.lcmpb", 0xa2a, 1, -1, -1, "low byte compare B"}, + {"tce2.hcmpb", 0xa2b, 1, -1, -1, "high byte compare B"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce2.lcmpc", 0xa2c, 1, -1, -1, "low byte compare C"}, + {"tce2.hcmpc", 0xa2d, 1, -1, -1, "high byte compare C"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce2.lcmpd", 0xa2e, 1, -1, -1, "low byte compare D"}, + {"tce2.hcmpd", 0xa2f, 1, -1, -1, "high byte compare D"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"awexe.ctrl", 0xa80, 1, -1, -1, "control register"}, + {"awexe.fdemask", 0xa82, 1, -1, -1, "fault detection event mask register"}, + {"awexe.fdctrl", 0xa83, 1, -1, -1, "fault detection control register"}, + {"awexe.status", 0xa84, 1, -1, -1, "status register"}, + {"awexe.dtboth", 0xa86, 1, -1, -1, "dead-time both sides register"}, + {"awexe.dtbothbuf", 0xa87, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexe.dtls", 0xa88, 1, -1, -1, "dead-time low side register"}, + {"awexe.dths", 0xa89, 1, -1, -1, "dead-time high side register"}, + {"awexe.dtlsbuf", 0xa8a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexe.dthsbuf", 0xa8b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexe.outoven", 0xa8c, 1, -1, -1, "output override enable register"}, + {"usarte0.data", 0xaa0, 1, -1, -1, "data register"}, + {"usarte0.status", 0xaa1, 1, -1, -1, "status register"}, + {"usarte0.ctrla", 0xaa3, 1, -1, -1, "control register A"}, + {"usarte0.ctrlb", 0xaa4, 1, -1, -1, "control register B"}, + {"usarte0.ctrlc", 0xaa5, 1, -1, -1, "control register C"}, + {"usarte0.baudctrla", 0xaa6, 1, -1, -1, "baud rate control register A"}, + {"usarte0.baudctrlb", 0xaa7, 1, -1, -1, "baud rate control register B"}, + {"spie.ctrl", 0xac0, 1, -1, -1, "control register"}, + {"spie.intctrl", 0xac1, 1, -1, -1, "interrupt control register"}, + {"spie.status", 0xac2, 1, -1, -1, "status register"}, + {"spie.data", 0xac3, 1, -1, -1, "data register"}, + {"tcf0.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf2.ctrla", 0xb00, 1, -1, -1, "control register A"}, + {"tcf0.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf2.ctrlb", 0xb01, 1, -1, -1, "control register B"}, + {"tcf0.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf2.ctrlc", 0xb02, 1, -1, -1, "control register C"}, + {"tcf0.ctrld", 0xb03, 1, -1, -1, "control register D"}, + {"tcf0.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf2.ctrle", 0xb04, 1, -1, -1, "control register E"}, + {"tcf0.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf2.intctrla", 0xb06, 1, -1, -1, "interrupt control register A"}, + {"tcf0.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf2.intctrlb", 0xb07, 1, -1, -1, "interrupt control register B"}, + {"tcf0.ctrlfclr", 0xb08, 1, -1, -1, "control register F clear"}, + {"tcf0.ctrlfset", 0xb09, 1, -1, -1, "control register F set"}, + {"tcf2.ctrlf", 0xb09, 1, -1, -1, "control register F"}, + {"tcf0.ctrlgclr", 0xb0a, 1, -1, -1, "control register G clear"}, + {"tcf0.ctrlgset", 0xb0b, 1, -1, -1, "control register G set"}, + {"tcf0.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf2.intflags", 0xb0c, 1, -1, -1, "interrupt flags register"}, + {"tcf0.temp", 0xb0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcf0.cnt", 0xb20, 2, -1, -1, "counter (16 bits)"}, + {"tcf2.lcnt", 0xb20, 1, -1, -1, "low byte counter"}, + {"tcf2.hcnt", 0xb21, 1, -1, -1, "high byte counter"}, + {"tcf0.per", 0xb26, 2, -1, -1, "period register (16 bits)"}, + {"tcf2.lper", 0xb26, 1, -1, -1, "low byte period register"}, + {"tcf2.hper", 0xb27, 1, -1, -1, "high byte period register"}, + {"tcf0.cca", 0xb28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcf2.lcmpa", 0xb28, 1, -1, -1, "low byte compare A"}, + {"tcf2.hcmpa", 0xb29, 1, -1, -1, "high byte compare A"}, + {"tcf0.ccb", 0xb2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcf2.lcmpb", 0xb2a, 1, -1, -1, "low byte compare B"}, + {"tcf2.hcmpb", 0xb2b, 1, -1, -1, "high byte compare B"}, + {"tcf0.ccc", 0xb2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcf2.lcmpc", 0xb2c, 1, -1, -1, "low byte compare C"}, + {"tcf2.hcmpc", 0xb2d, 1, -1, -1, "high byte compare C"}, + {"tcf0.ccd", 0xb2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcf2.lcmpd", 0xb2e, 1, -1, -1, "low byte compare D"}, + {"tcf2.hcmpd", 0xb2f, 1, -1, -1, "high byte compare D"}, + {"tcf0.perbuf", 0xb36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcf0.ccabuf", 0xb38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcf0.ccbbuf", 0xb3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcf0.cccbuf", 0xb3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcf0.ccdbuf", 0xb3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + // ATxmega384D3 const Register_file rgftab_atxmega384d3[560] = { // I/O memory [0, 4095] {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, @@ -40011,6 +37199,1376 @@ const Register_file rgftab_atxmega384d3[560] = { // I/O memory [0, 4095] {"usartf0.baudctrlb", 0xba7, 1, -1, -1, "baud rate control register B"}, }; +// ATxmega16D4 ATxmega32D4 +const Register_file rgftab_atxmega16d4[460] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.jtaguid", 0x094, 1, -1, -1, "JTAG user ID register"}, + {"mcu.mcucr", 0x096, 1, -1, -1, "MCU control register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.ch1res", 0x212, 2, -1, -1, "channel 1 result register (16 bits)"}, + {"adca.ch2res", 0x214, 2, -1, -1, "channel 2 result register (16 bits)"}, + {"adca.ch3res", 0x216, 2, -1, -1, "channel 3 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch1.ctrl", 0x228, 1, -1, -1, "control register"}, + {"adc.ch1.muxctrl", 0x229, 1, -1, -1, "MUX control register"}, + {"adc.ch1.intctrl", 0x22a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch1.intflags", 0x22b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch1.res", 0x22c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch1.scan", 0x22e, 1, -1, -1, "input channel scan register"}, + {"adc.ch2.ctrl", 0x230, 1, -1, -1, "control register"}, + {"adc.ch2.muxctrl", 0x231, 1, -1, -1, "MUX control register"}, + {"adc.ch2.intctrl", 0x232, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch2.intflags", 0x233, 1, -1, -1, "interrupt flags register"}, + {"adc.ch2.res", 0x234, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch2.scan", 0x236, 1, -1, -1, "input channel scan register"}, + {"adc.ch3.ctrl", 0x238, 1, -1, -1, "control register"}, + {"adc.ch3.muxctrl", 0x239, 1, -1, -1, "MUX control register"}, + {"adc.ch3.intctrl", 0x23a, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch3.intflags", 0x23b, 1, -1, -1, "interrupt flags register"}, + {"adc.ch3.res", 0x23c, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch3.scan", 0x23e, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega64D4 ATxmega128D4 +const Register_file rgftab_atxmega64d4[460] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"dfllrc2m.ctrl", 0x068, 1, -1, -1, "control register"}, + {"dfllrc2m.cala", 0x06a, 1, -1, -1, "calibration register A"}, + {"dfllrc2m.calb", 0x06b, 1, -1, -1, "calibration register B"}, + {"dfllrc2m.comp0", 0x06c, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc2m.comp1", 0x06d, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc2m.comp2", 0x06e, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"pr.prpe", 0x075, 1, -1, -1, "power reduction port E register"}, + {"pr.prpf", 0x076, 1, -1, -1, "power reduction port F register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.awexlock", 0x099, 1, -1, -1, "AWEX lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.vpctrla", 0x0b2, 1, -1, -1, "virtual port control register A"}, + {"portcfg.vpctrlb", 0x0b3, 1, -1, -1, "virtual port control register B"}, + {"portcfg.clkevout", 0x0b4, 1, -1, -1, "clock and event out register"}, + {"portcfg.evoutsel", 0x0b6, 1, -1, -1, "event output select register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 2, -1, -1, "calibration register (16 bits)"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twie.ctrl", 0x4a0, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x4a1, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x4a2, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x4a3, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x4a4, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x4a5, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x4a6, 1, -1, -1, "address register"}, + {"twi.host.data", 0x4a7, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x4a8, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x4a9, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x4aa, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x4ab, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x4ac, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x4ad, 1, -1, -1, "address mask register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.int0mask", 0x60a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porta.int1mask", 0x60b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portb.dir", 0x620, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x621, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x622, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x623, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x624, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x625, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x626, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x627, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x628, 1, -1, -1, "I/O port input register"}, + {"portb.intctrl", 0x629, 1, -1, -1, "interrupt control register"}, + {"portb.int0mask", 0x62a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portb.int1mask", 0x62b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portb.intflags", 0x62c, 1, -1, -1, "interrupt flags register"}, + {"portb.remap", 0x62e, 1, -1, -1, "I/O port pins remap register"}, + {"portb.pin0ctrl", 0x630, 1, -1, -1, "pin 0 control register"}, + {"portb.pin1ctrl", 0x631, 1, -1, -1, "pin 1 control register"}, + {"portb.pin2ctrl", 0x632, 1, -1, -1, "pin 2 control register"}, + {"portb.pin3ctrl", 0x633, 1, -1, -1, "pin 3 control register"}, + {"portb.pin4ctrl", 0x634, 1, -1, -1, "pin 4 control register"}, + {"portb.pin5ctrl", 0x635, 1, -1, -1, "pin 5 control register"}, + {"portb.pin6ctrl", 0x636, 1, -1, -1, "pin 6 control register"}, + {"portb.pin7ctrl", 0x637, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.int0mask", 0x64a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portc.int1mask", 0x64b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.int0mask", 0x66a, 1, -1, -1, "port interrupt 0 mask register"}, + {"portd.int1mask", 0x66b, 1, -1, -1, "port interrupt 1 mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"porte.dir", 0x680, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x681, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x682, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x683, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x684, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x685, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x686, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x687, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x688, 1, -1, -1, "I/O port input register"}, + {"porte.intctrl", 0x689, 1, -1, -1, "interrupt control register"}, + {"porte.int0mask", 0x68a, 1, -1, -1, "port interrupt 0 mask register"}, + {"porte.int1mask", 0x68b, 1, -1, -1, "port interrupt 1 mask register"}, + {"porte.intflags", 0x68c, 1, -1, -1, "interrupt flags register"}, + {"porte.remap", 0x68e, 1, -1, -1, "I/O port pins remap register"}, + {"porte.pin0ctrl", 0x690, 1, -1, -1, "pin 0 control register"}, + {"porte.pin1ctrl", 0x691, 1, -1, -1, "pin 1 control register"}, + {"porte.pin2ctrl", 0x692, 1, -1, -1, "pin 2 control register"}, + {"porte.pin3ctrl", 0x693, 1, -1, -1, "pin 3 control register"}, + {"porte.pin4ctrl", 0x694, 1, -1, -1, "pin 4 control register"}, + {"porte.pin5ctrl", 0x695, 1, -1, -1, "pin 5 control register"}, + {"porte.pin6ctrl", 0x696, 1, -1, -1, "pin 6 control register"}, + {"porte.pin7ctrl", 0x697, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.int0mask", 0x7ea, 1, -1, -1, "port interrupt 0 mask register"}, + {"portr.int1mask", 0x7eb, 1, -1, -1, "port interrupt 1 mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc0.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc2.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc0.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc2.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc0.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc2.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc0.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc0.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc2.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc0.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc2.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc0.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc2.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc0.ctrlfclr", 0x808, 1, -1, -1, "control register F clear"}, + {"tcc0.ctrlfset", 0x809, 1, -1, -1, "control register F set"}, + {"tcc2.ctrlf", 0x809, 1, -1, -1, "control register F"}, + {"tcc0.ctrlgclr", 0x80a, 1, -1, -1, "control register G clear"}, + {"tcc0.ctrlgset", 0x80b, 1, -1, -1, "control register G set"}, + {"tcc0.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc2.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc0.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc0.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc2.lcnt", 0x820, 1, -1, -1, "low byte counter"}, + {"tcc2.hcnt", 0x821, 1, -1, -1, "high byte counter"}, + {"tcc0.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc2.lper", 0x826, 1, -1, -1, "low byte period register"}, + {"tcc2.hper", 0x827, 1, -1, -1, "high byte period register"}, + {"tcc0.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc2.lcmpa", 0x828, 1, -1, -1, "low byte compare A"}, + {"tcc2.hcmpa", 0x829, 1, -1, -1, "high byte compare A"}, + {"tcc0.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc2.lcmpb", 0x82a, 1, -1, -1, "low byte compare B"}, + {"tcc2.hcmpb", 0x82b, 1, -1, -1, "high byte compare B"}, + {"tcc0.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc2.lcmpc", 0x82c, 1, -1, -1, "low byte compare C"}, + {"tcc2.hcmpc", 0x82d, 1, -1, -1, "high byte compare C"}, + {"tcc0.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc2.lcmpd", 0x82e, 1, -1, -1, "low byte compare D"}, + {"tcc2.hcmpd", 0x82f, 1, -1, -1, "high byte compare D"}, + {"tcc0.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc0.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc0.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc0.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc0.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc1.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc1.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc1.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc1.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc1.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc1.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc1.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc1.ctrlfclr", 0x848, 1, -1, -1, "control register F clear"}, + {"tcc1.ctrlfset", 0x849, 1, -1, -1, "control register F set"}, + {"tcc1.ctrlgclr", 0x84a, 1, -1, -1, "control register G clear"}, + {"tcc1.ctrlgset", 0x84b, 1, -1, -1, "control register G set"}, + {"tcc1.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc1.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc1.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc1.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc1.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc1.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc1.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc1.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc1.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"awexc.ctrl", 0x880, 1, -1, -1, "control register"}, + {"awexc.fdemask", 0x882, 1, -1, -1, "fault detection event mask register"}, + {"awexc.fdctrl", 0x883, 1, -1, -1, "fault detection control register"}, + {"awexc.status", 0x884, 1, -1, -1, "status register"}, + {"awexc.statusset", 0x885, 1, -1, -1, "status set register"}, + {"awexc.dtboth", 0x886, 1, -1, -1, "dead-time both sides register"}, + {"awexc.dtbothbuf", 0x887, 1, -1, -1, "dead-time both sides buffer register"}, + {"awexc.dtls", 0x888, 1, -1, -1, "dead-time low side register"}, + {"awexc.dths", 0x889, 1, -1, -1, "dead-time high side register"}, + {"awexc.dtlsbuf", 0x88a, 1, -1, -1, "dead-time low side buffer register"}, + {"awexc.dthsbuf", 0x88b, 1, -1, -1, "dead-time high side buffer register"}, + {"awexc.outoven", 0x88c, 1, -1, -1, "output override enable register"}, + {"hiresc.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8a0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8a1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8a3, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8a4, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8a5, 1, -1, -1, "control register C"}, + {"usartc0.baudctrla", 0x8a6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8a7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8c0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8c1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8c2, 1, -1, -1, "status register"}, + {"spic.data", 0x8c3, 1, -1, -1, "data register"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd0.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd2.ctrla", 0x900, 1, -1, -1, "control register A"}, + {"tcd0.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd2.ctrlb", 0x901, 1, -1, -1, "control register B"}, + {"tcd0.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd2.ctrlc", 0x902, 1, -1, -1, "control register C"}, + {"tcd0.ctrld", 0x903, 1, -1, -1, "control register D"}, + {"tcd0.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd2.ctrle", 0x904, 1, -1, -1, "control register E"}, + {"tcd0.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd2.intctrla", 0x906, 1, -1, -1, "interrupt control register A"}, + {"tcd0.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd2.intctrlb", 0x907, 1, -1, -1, "interrupt control register B"}, + {"tcd0.ctrlfclr", 0x908, 1, -1, -1, "control register F clear"}, + {"tcd0.ctrlfset", 0x909, 1, -1, -1, "control register F set"}, + {"tcd2.ctrlf", 0x909, 1, -1, -1, "control register F"}, + {"tcd0.ctrlgclr", 0x90a, 1, -1, -1, "control register G clear"}, + {"tcd0.ctrlgset", 0x90b, 1, -1, -1, "control register G set"}, + {"tcd0.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd2.intflags", 0x90c, 1, -1, -1, "interrupt flags register"}, + {"tcd0.temp", 0x90f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd0.cnt", 0x920, 2, -1, -1, "counter (16 bits)"}, + {"tcd2.lcnt", 0x920, 1, -1, -1, "low byte counter"}, + {"tcd2.hcnt", 0x921, 1, -1, -1, "high byte counter"}, + {"tcd0.per", 0x926, 2, -1, -1, "period register (16 bits)"}, + {"tcd2.lper", 0x926, 1, -1, -1, "low byte period register"}, + {"tcd2.hper", 0x927, 1, -1, -1, "high byte period register"}, + {"tcd0.cca", 0x928, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd2.lcmpa", 0x928, 1, -1, -1, "low byte compare A"}, + {"tcd2.hcmpa", 0x929, 1, -1, -1, "high byte compare A"}, + {"tcd0.ccb", 0x92a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd2.lcmpb", 0x92a, 1, -1, -1, "low byte compare B"}, + {"tcd2.hcmpb", 0x92b, 1, -1, -1, "high byte compare B"}, + {"tcd0.ccc", 0x92c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcd2.lcmpc", 0x92c, 1, -1, -1, "low byte compare C"}, + {"tcd2.hcmpc", 0x92d, 1, -1, -1, "high byte compare C"}, + {"tcd0.ccd", 0x92e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcd2.lcmpd", 0x92e, 1, -1, -1, "low byte compare D"}, + {"tcd2.hcmpd", 0x92f, 1, -1, -1, "high byte compare D"}, + {"tcd0.perbuf", 0x936, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd0.ccabuf", 0x938, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd0.ccbbuf", 0x93a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcd0.cccbuf", 0x93c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcd0.ccdbuf", 0x93e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"usartd0.data", 0x9a0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9a1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9a3, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9a4, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9a5, 1, -1, -1, "control register C"}, + {"usartd0.baudctrla", 0x9a6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9a7, 1, -1, -1, "baud rate control register B"}, + {"spid.ctrl", 0x9c0, 1, -1, -1, "control register"}, + {"spid.intctrl", 0x9c1, 1, -1, -1, "interrupt control register"}, + {"spid.status", 0x9c2, 1, -1, -1, "status register"}, + {"spid.data", 0x9c3, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0xa00, 1, -1, -1, "control register A"}, + {"tce0.ctrlb", 0xa01, 1, -1, -1, "control register B"}, + {"tce0.ctrlc", 0xa02, 1, -1, -1, "control register C"}, + {"tce0.ctrld", 0xa03, 1, -1, -1, "control register D"}, + {"tce0.ctrle", 0xa04, 1, -1, -1, "control register E"}, + {"tce0.intctrla", 0xa06, 1, -1, -1, "interrupt control register A"}, + {"tce0.intctrlb", 0xa07, 1, -1, -1, "interrupt control register B"}, + {"tce0.ctrlfclr", 0xa08, 1, -1, -1, "control register F clear"}, + {"tce0.ctrlfset", 0xa09, 1, -1, -1, "control register F set"}, + {"tce0.ctrlgclr", 0xa0a, 1, -1, -1, "control register G clear"}, + {"tce0.ctrlgset", 0xa0b, 1, -1, -1, "control register G set"}, + {"tce0.intflags", 0xa0c, 1, -1, -1, "interrupt flags register"}, + {"tce0.temp", 0xa0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tce0.cnt", 0xa20, 2, -1, -1, "counter (16 bits)"}, + {"tce0.per", 0xa26, 2, -1, -1, "period register (16 bits)"}, + {"tce0.cca", 0xa28, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tce0.ccb", 0xa2a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tce0.ccc", 0xa2c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tce0.ccd", 0xa2e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tce0.perbuf", 0xa36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tce0.ccabuf", 0xa38, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tce0.ccbbuf", 0xa3a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tce0.cccbuf", 0xa3c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tce0.ccdbuf", 0xa3e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, +}; + +// ATxmega8E5 ATxmega16E5 ATxmega32E5 +const Register_file rgftab_atxmega8e5[438] = { // I/O memory [0, 4095] + {"gpio.gpior0", 0x000, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x002, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x003, 1, -1, -1, "general purpose I/O register 3"}, + {"vport0.dir", 0x010, 1, -1, -1, "data direction register"}, + {"vport0.out", 0x011, 1, -1, -1, "I/O port output register"}, + {"vport0.in", 0x012, 1, -1, -1, "I/O port input register"}, + {"vport0.intflags", 0x013, 1, -1, -1, "interrupt flags register"}, + {"vport1.dir", 0x014, 1, -1, -1, "data direction register"}, + {"vport1.out", 0x015, 1, -1, -1, "I/O port output register"}, + {"vport1.in", 0x016, 1, -1, -1, "I/O port input register"}, + {"vport1.intflags", 0x017, 1, -1, -1, "interrupt flags register"}, + {"vport2.dir", 0x018, 1, -1, -1, "data direction register"}, + {"vport2.out", 0x019, 1, -1, -1, "I/O port output register"}, + {"vport2.in", 0x01a, 1, -1, -1, "I/O port input register"}, + {"vport2.intflags", 0x01b, 1, -1, -1, "interrupt flags register"}, + {"vport3.dir", 0x01c, 1, -1, -1, "data direction register"}, + {"vport3.out", 0x01d, 1, -1, -1, "I/O port output register"}, + {"vport3.in", 0x01e, 1, -1, -1, "I/O port input register"}, + {"vport3.intflags", 0x01f, 1, -1, -1, "interrupt flags register"}, + {"ocd.ocdr0", 0x02e, 1, -1, -1, "OCD register 0"}, + {"ocd.ocdr1", 0x02f, 1, -1, -1, "OCD register 1"}, + {"cpu.ccp", 0x034, 1, -1, -1, "configuration change protection register"}, + {"cpu.rampd", 0x038, 1, -1, -1, "extended Z register for data space"}, + {"cpu.rampx", 0x039, 1, -1, -1, "extended X register"}, + {"cpu.rampy", 0x03a, 1, -1, -1, "extended Y register"}, + {"cpu.rampz", 0x03b, 1, -1, -1, "extended Z register"}, + {"cpu.eind", 0x03c, 1, -1, -1, "extended indirect jump register"}, + {"cpu.spl", 0x03d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x03e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x03f, 1, -1, -1, "status register"}, + {"clk.ctrl", 0x040, 1, -1, -1, "control register"}, + {"clk.psctrl", 0x041, 1, -1, -1, "prescaler control register"}, + {"clk.lock", 0x042, 1, -1, -1, "lock register"}, + {"clk.rtcctrl", 0x043, 1, -1, -1, "RTC control register"}, + {"sleep.ctrl", 0x048, 1, -1, -1, "control register"}, + {"osc.ctrl", 0x050, 1, -1, -1, "control register"}, + {"osc.status", 0x051, 1, -1, -1, "status register"}, + {"osc.xoscctrl", 0x052, 1, -1, -1, "external oscillator control register"}, + {"osc.xoscfail", 0x053, 1, -1, -1, "external oscillator failure detection register"}, + {"osc.rc32kcal", 0x054, 1, -1, -1, "32.768 kHz internal oscillator calibration register"}, + {"osc.pllctrl", 0x055, 1, -1, -1, "PLL control register"}, + {"osc.dfllctrl", 0x056, 1, -1, -1, "DFLL control register"}, + {"osc.rc8mcal", 0x057, 1, -1, -1, "internal 8 MHz RC oscillator calibration register"}, + {"dfllrc32m.ctrl", 0x060, 1, -1, -1, "control register"}, + {"dfllrc32m.cala", 0x062, 1, -1, -1, "calibration register A"}, + {"dfllrc32m.calb", 0x063, 1, -1, -1, "calibration register B"}, + {"dfllrc32m.comp0", 0x064, 1, -1, -1, "oscillator compare register 0"}, + {"dfllrc32m.comp1", 0x065, 1, -1, -1, "oscillator compare register 1"}, + {"dfllrc32m.comp2", 0x066, 1, -1, -1, "oscillator compare register 2"}, + {"pr.prgen", 0x070, 1, -1, -1, "general power reduction register"}, + {"pr.prpa", 0x071, 1, -1, -1, "power reduction port A register"}, + {"pr.prpc", 0x073, 1, -1, -1, "power reduction port C register"}, + {"pr.prpd", 0x074, 1, -1, -1, "power reduction port D register"}, + {"rst.status", 0x078, 1, -1, -1, "status register"}, + {"rst.ctrl", 0x079, 1, -1, -1, "control register"}, + {"wdt.ctrl", 0x080, 1, -1, -1, "control register"}, + {"wdt.winctrl", 0x081, 1, -1, -1, "window mode control register"}, + {"wdt.status", 0x082, 1, -1, -1, "status register"}, + {"mcu.devid0", 0x090, 1, -1, -1, "device ID byte 0"}, + {"mcu.devid1", 0x091, 1, -1, -1, "device ID byte 1"}, + {"mcu.devid2", 0x092, 1, -1, -1, "device ID byte 2"}, + {"mcu.revid", 0x093, 1, -1, -1, "revision ID register"}, + {"mcu.anainit", 0x097, 1, -1, -1, "analog startup delay register"}, + {"mcu.evsyslock", 0x098, 1, -1, -1, "event system lock register"}, + {"mcu.wexlock", 0x099, 1, -1, -1, "WEX lock register"}, + {"mcu.faultlock", 0x09a, 1, -1, -1, "FAULT lock register"}, + {"pmic.status", 0x0a0, 1, -1, -1, "status register"}, + {"pmic.intpri", 0x0a1, 1, -1, -1, "interrupt priority register"}, + {"pmic.ctrl", 0x0a2, 1, -1, -1, "control register"}, + {"portcfg.mpcmask", 0x0b0, 1, -1, -1, "multi-pin configuration mask register"}, + {"portcfg.clkout", 0x0b4, 1, -1, -1, "clock out register"}, + {"portcfg.acevout", 0x0b6, 1, -1, -1, "analog comparator and event out register"}, + {"portcfg.srlctrl", 0x0b7, 1, -1, -1, "slew rate limit control register"}, + {"crc.ctrl", 0x0d0, 1, -1, -1, "control register"}, + {"crc.status", 0x0d1, 1, -1, -1, "status register"}, + {"crc.datain", 0x0d3, 1, -1, -1, "data input register"}, + {"crc.checksum0", 0x0d4, 1, -1, -1, "checksum byte 0"}, + {"crc.checksum1", 0x0d5, 1, -1, -1, "checksum byte 1"}, + {"crc.checksum2", 0x0d6, 1, -1, -1, "checksum byte 2"}, + {"crc.checksum3", 0x0d7, 1, -1, -1, "checksum byte 3"}, + {"edma.ctrl", 0x100, 1, -1, -1, "control register"}, + {"edma.intflags", 0x103, 1, -1, -1, "interrupt flags register"}, + {"edma.status", 0x104, 1, -1, -1, "status register"}, + {"edma.temp", 0x106, 1, -1, -1, "temporary register for 16-bit access"}, + {"edma.ch0.ctrla", 0x110, 1, -1, -1, "channel control register A"}, + {"edma.ch0.ctrlb", 0x111, 1, -1, -1, "channel control register B"}, + {"edma.ch0.addrctrl", 0x112, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch0.destaddrctrl", 0x113, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch0.trigsrc", 0x114, 1, -1, -1, "channel trigger source register"}, + {"edma.ch0.trfcnt", 0x116, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch0.addr", 0x118, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch0.destaddr", 0x11c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, + {"edma.ch1.ctrla", 0x120, 1, -1, -1, "channel control register A"}, + {"edma.ch1.ctrlb", 0x121, 1, -1, -1, "channel control register B"}, + {"edma.ch1.addrctrl", 0x122, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch1.destaddrctrl", 0x123, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch1.trigsrc", 0x124, 1, -1, -1, "channel trigger source register"}, + {"edma.ch1.trfcnt", 0x126, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch1.addr", 0x128, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch1.destaddr", 0x12c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, + {"edma.ch2.ctrla", 0x130, 1, -1, -1, "channel control register A"}, + {"edma.ch2.ctrlb", 0x131, 1, -1, -1, "channel control register B"}, + {"edma.ch2.addrctrl", 0x132, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch2.destaddrctrl", 0x133, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch2.trigsrc", 0x134, 1, -1, -1, "channel trigger source register"}, + {"edma.ch2.trfcnt", 0x136, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch2.addr", 0x138, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch2.destaddr", 0x13c, 2, -1, -1, "channel destination address for standard channels only register (16 bits)"}, + {"edma.ch3.ctrla", 0x140, 1, -1, -1, "channel control register A"}, + {"edma.ch3.ctrlb", 0x141, 1, -1, -1, "channel control register B"}, + {"edma.ch3.addrctrl", 0x142, 1, -1, -1, "memory address control register for peripheral channel or source address control register for standard channel"}, + {"edma.ch3.destaddrctrl", 0x143, 1, -1, -1, "destination address control register for standard channels only"}, + {"edma.ch3.trigsrc", 0x144, 1, -1, -1, "channel trigger source register"}, + {"edma.ch3.trfcnt", 0x146, 2, -1, -1, "channel block transfer counter for peripheral channel or low byte for standard channel (16 bits)"}, + {"edma.ch3.addr", 0x148, 2, -1, -1, "channel memory address for peripheral ch/channel source address low for standard ch (16 bits)"}, + {"edma.ch3.destaddr", 0x14c, 2, -1, -1, "channel destination address register for standard channels only (16 bits)"}, + {"evsys.ch0mux", 0x180, 1, -1, -1, "event channel 0 multiplexer register"}, + {"evsys.ch1mux", 0x181, 1, -1, -1, "event channel 1 multiplexer register"}, + {"evsys.ch2mux", 0x182, 1, -1, -1, "event channel 2 multiplexer register"}, + {"evsys.ch3mux", 0x183, 1, -1, -1, "event channel 3 multiplexer register"}, + {"evsys.ch4mux", 0x184, 1, -1, -1, "event channel 4 multiplexer register"}, + {"evsys.ch5mux", 0x185, 1, -1, -1, "event channel 5 multiplexer register"}, + {"evsys.ch6mux", 0x186, 1, -1, -1, "event channel 6 multiplexer register"}, + {"evsys.ch7mux", 0x187, 1, -1, -1, "event channel 7 multiplexer register"}, + {"evsys.ch0ctrl", 0x188, 1, -1, -1, "channel 0 control register"}, + {"evsys.ch1ctrl", 0x189, 1, -1, -1, "channel 1 control register"}, + {"evsys.ch2ctrl", 0x18a, 1, -1, -1, "channel 2 control register"}, + {"evsys.ch3ctrl", 0x18b, 1, -1, -1, "channel 3 control register"}, + {"evsys.ch4ctrl", 0x18c, 1, -1, -1, "channel 4 control register"}, + {"evsys.ch5ctrl", 0x18d, 1, -1, -1, "channel 5 control register"}, + {"evsys.ch6ctrl", 0x18e, 1, -1, -1, "channel 6 control register"}, + {"evsys.ch7ctrl", 0x18f, 1, -1, -1, "channel 7 control register"}, + {"evsys.strobe", 0x190, 1, -1, -1, "event strobe register"}, + {"evsys.data", 0x191, 1, -1, -1, "data register"}, + {"evsys.dfctrl", 0x192, 1, -1, -1, "digital filter control register"}, + {"nvm.addr0", 0x1c0, 1, -1, -1, "address register 0"}, + {"nvm.addr1", 0x1c1, 1, -1, -1, "address register 1"}, + {"nvm.addr2", 0x1c2, 1, -1, -1, "address register 2"}, + {"nvm.data0", 0x1c4, 1, -1, -1, "data register 0"}, + {"nvm.data1", 0x1c5, 1, -1, -1, "data register 1"}, + {"nvm.data2", 0x1c6, 1, -1, -1, "data register 2"}, + {"nvm.cmd", 0x1ca, 1, -1, -1, "command register"}, + {"nvm.ctrla", 0x1cb, 1, -1, -1, "control register A"}, + {"nvm.ctrlb", 0x1cc, 1, -1, -1, "control register B"}, + {"nvm.intctrl", 0x1cd, 1, -1, -1, "interrupt control register"}, + {"nvm.status", 0x1cf, 1, -1, -1, "status register"}, + {"nvm.lockbits", 0x1d0, 1, -1, -1, "lock bits register"}, + {"adca.ctrla", 0x200, 1, -1, -1, "control register A"}, + {"adca.ctrlb", 0x201, 1, -1, -1, "control register B"}, + {"adca.refctrl", 0x202, 1, -1, -1, "reference control register"}, + {"adca.evctrl", 0x203, 1, -1, -1, "event control register"}, + {"adca.prescaler", 0x204, 1, -1, -1, "clock prescaler register"}, + {"adca.intflags", 0x206, 1, -1, -1, "interrupt flags register"}, + {"adca.temp", 0x207, 1, -1, -1, "temporary register"}, + {"adca.sampctrl", 0x208, 1, -1, -1, "ADC sampling time control register"}, + {"adca.cal", 0x20c, 1, -1, -1, "calibration register"}, + {"adca.ch0res", 0x210, 2, -1, -1, "channel 0 result register (16 bits)"}, + {"adca.cmp", 0x218, 2, -1, -1, "compare register (16 bits)"}, + {"adc.ch0.ctrl", 0x220, 1, -1, -1, "control register"}, + {"adc.ch0.muxctrl", 0x221, 1, -1, -1, "MUX control register"}, + {"adc.ch0.intctrl", 0x222, 1, -1, -1, "channel interrupt control register"}, + {"adc.ch0.intflags", 0x223, 1, -1, -1, "interrupt flags register"}, + {"adc.ch0.res", 0x224, 2, -1, -1, "channel result register (16 bits)"}, + {"adc.ch0.scan", 0x226, 1, -1, -1, "input channel scan register"}, + {"adc.ch0.corrctrl", 0x227, 1, -1, -1, "correction control register"}, + {"adc.ch0.offsetcorr0", 0x228, 1, -1, -1, "offset correction register 0"}, + {"adc.ch0.offsetcorr1", 0x229, 1, -1, -1, "offset correction register 1"}, + {"adc.ch0.gaincorr0", 0x22a, 1, -1, -1, "gain correction register 0"}, + {"adc.ch0.gaincorr1", 0x22b, 1, -1, -1, "gain correction register 1"}, + {"adc.ch0.avgctrl", 0x22c, 1, -1, -1, "average control register"}, + {"daca.ctrla", 0x300, 1, -1, -1, "control register A"}, + {"daca.ctrlb", 0x301, 1, -1, -1, "control register B"}, + {"daca.ctrlc", 0x302, 1, -1, -1, "control register C"}, + {"daca.evctrl", 0x303, 1, -1, -1, "event control register"}, + {"daca.status", 0x305, 1, -1, -1, "status register"}, + {"daca.ch0gaincal", 0x308, 1, -1, -1, "gain calibration register"}, + {"daca.ch0offsetcal", 0x309, 1, -1, -1, "offset calibration register"}, + {"daca.ch1gaincal", 0x30a, 1, -1, -1, "gain calibration register"}, + {"daca.ch1offsetcal", 0x30b, 1, -1, -1, "offset calibration register"}, + {"daca.ch0data", 0x318, 2, -1, -1, "channel 0 data register (16 bits)"}, + {"daca.ch1data", 0x31a, 2, -1, -1, "channel 1 data register (16 bits)"}, + {"aca.ac0ctrl", 0x380, 1, -1, -1, "analog comparator 0 control register"}, + {"aca.ac1ctrl", 0x381, 1, -1, -1, "analog comparator 1 control register"}, + {"aca.ac0muxctrl", 0x382, 1, -1, -1, "analog comparator 0 MUX control register"}, + {"aca.ac1muxctrl", 0x383, 1, -1, -1, "analog comparator 1 MUX control register"}, + {"aca.ctrla", 0x384, 1, -1, -1, "control register A"}, + {"aca.ctrlb", 0x385, 1, -1, -1, "control register B"}, + {"aca.winctrl", 0x386, 1, -1, -1, "window mode control register"}, + {"aca.status", 0x387, 1, -1, -1, "status register"}, + {"aca.currctrl", 0x388, 1, -1, -1, "current source control register"}, + {"aca.currcalib", 0x389, 1, -1, -1, "current source calibration register"}, + {"rtc.ctrl", 0x400, 1, -1, -1, "control register"}, + {"rtc.status", 0x401, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x402, 1, -1, -1, "interrupt control register"}, + {"rtc.intflags", 0x403, 1, -1, -1, "interrupt flags register"}, + {"rtc.temp", 0x404, 1, -1, -1, "temporary register"}, + {"rtc.calib", 0x406, 1, -1, -1, "calibration register"}, + {"rtc.cnt", 0x408, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x40a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.comp", 0x40c, 2, -1, -1, "compare register (16 bits)"}, + {"xcl.ctrla", 0x460, 1, -1, -1, "control register A"}, + {"xcl.ctrlb", 0x461, 1, -1, -1, "control register B"}, + {"xcl.ctrlc", 0x462, 1, -1, -1, "control register C"}, + {"xcl.ctrld", 0x463, 1, -1, -1, "control register D"}, + {"xcl.ctrle", 0x464, 1, -1, -1, "control register E"}, + {"xcl.ctrlf", 0x465, 1, -1, -1, "control register F"}, + {"xcl.ctrlg", 0x466, 1, -1, -1, "control register G"}, + {"xcl.intctrl", 0x467, 1, -1, -1, "interrupt control register"}, + {"xcl.intflags", 0x468, 1, -1, -1, "interrupt flags register"}, + {"xcl.plc", 0x469, 1, -1, -1, "peripheral length control register"}, + {"xcl.cntl", 0x46a, 1, -1, -1, "counter low byte"}, + {"xcl.cnth", 0x46b, 1, -1, -1, "counter high byte"}, + {"xcl.cmpl", 0x46c, 1, -1, -1, "compare register low byte"}, + {"xcl.cmph", 0x46d, 1, -1, -1, "compare register high byte"}, + {"xcl.percaptl", 0x46e, 1, -1, -1, "period or capture register low byte"}, + {"xcl.percapth", 0x46f, 1, -1, -1, "period or capture register high byte"}, + {"twic.ctrl", 0x480, 1, -1, -1, "control register"}, + {"twi.host.ctrla", 0x481, 1, -1, -1, "control register A"}, + {"twi.host.ctrlb", 0x482, 1, -1, -1, "control register B"}, + {"twi.host.ctrlc", 0x483, 1, -1, -1, "control register C"}, + {"twi.host.status", 0x484, 1, -1, -1, "status register"}, + {"twi.host.baud", 0x485, 1, -1, -1, "baud rate control register"}, + {"twi.host.addr", 0x486, 1, -1, -1, "address register"}, + {"twi.host.data", 0x487, 1, -1, -1, "data register"}, + {"twi.peripheral.ctrla", 0x488, 1, -1, -1, "control register A"}, + {"twi.peripheral.ctrlb", 0x489, 1, -1, -1, "control register B"}, + {"twi.peripheral.status", 0x48a, 1, -1, -1, "status register"}, + {"twi.peripheral.addr", 0x48b, 1, -1, -1, "address register"}, + {"twi.peripheral.data", 0x48c, 1, -1, -1, "data register"}, + {"twi.peripheral.addrmask", 0x48d, 1, -1, -1, "address mask register"}, + {"twi.timeout.tos", 0x48e, 1, -1, -1, "timeout status register"}, + {"twi.timeout.toconf", 0x48f, 1, -1, -1, "timeout configuration register"}, + {"porta.dir", 0x600, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x601, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x602, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x603, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x604, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x605, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x606, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x607, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x608, 1, -1, -1, "I/O port input register"}, + {"porta.intctrl", 0x609, 1, -1, -1, "interrupt control register"}, + {"porta.intmask", 0x60a, 1, -1, -1, "port interrupt mask register"}, + {"porta.intflags", 0x60c, 1, -1, -1, "interrupt flags register"}, + {"porta.remap", 0x60e, 1, -1, -1, "I/O port pins remap register"}, + {"porta.pin0ctrl", 0x610, 1, -1, -1, "pin 0 control register"}, + {"porta.pin1ctrl", 0x611, 1, -1, -1, "pin 1 control register"}, + {"porta.pin2ctrl", 0x612, 1, -1, -1, "pin 2 control register"}, + {"porta.pin3ctrl", 0x613, 1, -1, -1, "pin 3 control register"}, + {"porta.pin4ctrl", 0x614, 1, -1, -1, "pin 4 control register"}, + {"porta.pin5ctrl", 0x615, 1, -1, -1, "pin 5 control register"}, + {"porta.pin6ctrl", 0x616, 1, -1, -1, "pin 6 control register"}, + {"porta.pin7ctrl", 0x617, 1, -1, -1, "pin 7 control register"}, + {"portc.dir", 0x640, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x641, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x642, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x643, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x644, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x645, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x646, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x647, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x648, 1, -1, -1, "I/O port input register"}, + {"portc.intctrl", 0x649, 1, -1, -1, "interrupt control register"}, + {"portc.intmask", 0x64a, 1, -1, -1, "port interrupt mask register"}, + {"portc.intflags", 0x64c, 1, -1, -1, "interrupt flags register"}, + {"portc.remap", 0x64e, 1, -1, -1, "I/O port pins remap register"}, + {"portc.pin0ctrl", 0x650, 1, -1, -1, "pin 0 control register"}, + {"portc.pin1ctrl", 0x651, 1, -1, -1, "pin 1 control register"}, + {"portc.pin2ctrl", 0x652, 1, -1, -1, "pin 2 control register"}, + {"portc.pin3ctrl", 0x653, 1, -1, -1, "pin 3 control register"}, + {"portc.pin4ctrl", 0x654, 1, -1, -1, "pin 4 control register"}, + {"portc.pin5ctrl", 0x655, 1, -1, -1, "pin 5 control register"}, + {"portc.pin6ctrl", 0x656, 1, -1, -1, "pin 6 control register"}, + {"portc.pin7ctrl", 0x657, 1, -1, -1, "pin 7 control register"}, + {"portd.dir", 0x660, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x661, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x662, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x663, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x664, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x665, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x666, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x667, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x668, 1, -1, -1, "I/O port input register"}, + {"portd.intctrl", 0x669, 1, -1, -1, "interrupt control register"}, + {"portd.intmask", 0x66a, 1, -1, -1, "port interrupt mask register"}, + {"portd.intflags", 0x66c, 1, -1, -1, "interrupt flags register"}, + {"portd.remap", 0x66e, 1, -1, -1, "I/O port pins remap register"}, + {"portd.pin0ctrl", 0x670, 1, -1, -1, "pin 0 control register"}, + {"portd.pin1ctrl", 0x671, 1, -1, -1, "pin 1 control register"}, + {"portd.pin2ctrl", 0x672, 1, -1, -1, "pin 2 control register"}, + {"portd.pin3ctrl", 0x673, 1, -1, -1, "pin 3 control register"}, + {"portd.pin4ctrl", 0x674, 1, -1, -1, "pin 4 control register"}, + {"portd.pin5ctrl", 0x675, 1, -1, -1, "pin 5 control register"}, + {"portd.pin6ctrl", 0x676, 1, -1, -1, "pin 6 control register"}, + {"portd.pin7ctrl", 0x677, 1, -1, -1, "pin 7 control register"}, + {"portr.dir", 0x7e0, 1, -1, -1, "data direction register"}, + {"portr.dirset", 0x7e1, 1, -1, -1, "data direction set register"}, + {"portr.dirclr", 0x7e2, 1, -1, -1, "data direction clear register"}, + {"portr.dirtgl", 0x7e3, 1, -1, -1, "data direction toggle register"}, + {"portr.out", 0x7e4, 1, -1, -1, "I/O port output register"}, + {"portr.outset", 0x7e5, 1, -1, -1, "I/O port output set register"}, + {"portr.outclr", 0x7e6, 1, -1, -1, "I/O port output clear register"}, + {"portr.outtgl", 0x7e7, 1, -1, -1, "I/O port output toggle register"}, + {"portr.in", 0x7e8, 1, -1, -1, "I/O port input register"}, + {"portr.intctrl", 0x7e9, 1, -1, -1, "interrupt control register"}, + {"portr.intmask", 0x7ea, 1, -1, -1, "port interrupt mask register"}, + {"portr.intflags", 0x7ec, 1, -1, -1, "interrupt flags register"}, + {"portr.remap", 0x7ee, 1, -1, -1, "I/O port pins remap register"}, + {"portr.pin0ctrl", 0x7f0, 1, -1, -1, "pin 0 control register"}, + {"portr.pin1ctrl", 0x7f1, 1, -1, -1, "pin 1 control register"}, + {"portr.pin2ctrl", 0x7f2, 1, -1, -1, "pin 2 control register"}, + {"portr.pin3ctrl", 0x7f3, 1, -1, -1, "pin 3 control register"}, + {"portr.pin4ctrl", 0x7f4, 1, -1, -1, "pin 4 control register"}, + {"portr.pin5ctrl", 0x7f5, 1, -1, -1, "pin 5 control register"}, + {"portr.pin6ctrl", 0x7f6, 1, -1, -1, "pin 6 control register"}, + {"portr.pin7ctrl", 0x7f7, 1, -1, -1, "pin 7 control register"}, + {"tcc4.ctrla", 0x800, 1, -1, -1, "control register A"}, + {"tcc4.ctrlb", 0x801, 1, -1, -1, "control register B"}, + {"tcc4.ctrlc", 0x802, 1, -1, -1, "control register C"}, + {"tcc4.ctrld", 0x803, 1, -1, -1, "control register D"}, + {"tcc4.ctrle", 0x804, 1, -1, -1, "control register E"}, + {"tcc4.ctrlf", 0x805, 1, -1, -1, "control register F"}, + {"tcc4.intctrla", 0x806, 1, -1, -1, "interrupt control register A"}, + {"tcc4.intctrlb", 0x807, 1, -1, -1, "interrupt control register B"}, + {"tcc4.ctrlgclr", 0x808, 1, -1, -1, "control register G clear"}, + {"tcc4.ctrlgset", 0x809, 1, -1, -1, "control register G set"}, + {"tcc4.ctrlhclr", 0x80a, 1, -1, -1, "control register H clear"}, + {"tcc4.ctrlhset", 0x80b, 1, -1, -1, "control register H set"}, + {"tcc4.intflags", 0x80c, 1, -1, -1, "interrupt flags register"}, + {"tcc4.temp", 0x80f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc4.cnt", 0x820, 2, -1, -1, "counter (16 bits)"}, + {"tcc4.per", 0x826, 2, -1, -1, "period register (16 bits)"}, + {"tcc4.cca", 0x828, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc4.ccb", 0x82a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc4.ccc", 0x82c, 2, -1, -1, "compare or capture C register (16 bits)"}, + {"tcc4.ccd", 0x82e, 2, -1, -1, "compare or capture D register (16 bits)"}, + {"tcc4.perbuf", 0x836, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc4.ccabuf", 0x838, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc4.ccbbuf", 0x83a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"tcc4.cccbuf", 0x83c, 2, -1, -1, "compare or capture C buffer register (16 bits)"}, + {"tcc4.ccdbuf", 0x83e, 2, -1, -1, "compare or capture D buffer register (16 bits)"}, + {"tcc5.ctrla", 0x840, 1, -1, -1, "control register A"}, + {"tcc5.ctrlb", 0x841, 1, -1, -1, "control register B"}, + {"tcc5.ctrlc", 0x842, 1, -1, -1, "control register C"}, + {"tcc5.ctrld", 0x843, 1, -1, -1, "control register D"}, + {"tcc5.ctrle", 0x844, 1, -1, -1, "control register E"}, + {"tcc5.ctrlf", 0x845, 1, -1, -1, "control register F"}, + {"tcc5.intctrla", 0x846, 1, -1, -1, "interrupt control register A"}, + {"tcc5.intctrlb", 0x847, 1, -1, -1, "interrupt control register B"}, + {"tcc5.ctrlgclr", 0x848, 1, -1, -1, "control register G clear"}, + {"tcc5.ctrlgset", 0x849, 1, -1, -1, "control register G set"}, + {"tcc5.ctrlhclr", 0x84a, 1, -1, -1, "control register H clear"}, + {"tcc5.ctrlhset", 0x84b, 1, -1, -1, "control register H set"}, + {"tcc5.intflags", 0x84c, 1, -1, -1, "interrupt flags register"}, + {"tcc5.temp", 0x84f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcc5.cnt", 0x860, 2, -1, -1, "counter (16 bits)"}, + {"tcc5.per", 0x866, 2, -1, -1, "period register (16 bits)"}, + {"tcc5.cca", 0x868, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcc5.ccb", 0x86a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcc5.perbuf", 0x876, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcc5.ccabuf", 0x878, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcc5.ccbbuf", 0x87a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"faultc4.ctrla", 0x880, 1, -1, -1, "control register A"}, + {"faultc4.ctrlb", 0x881, 1, -1, -1, "control register B"}, + {"faultc4.ctrlc", 0x882, 1, -1, -1, "control register C"}, + {"faultc4.ctrld", 0x883, 1, -1, -1, "control register D"}, + {"faultc4.ctrle", 0x884, 1, -1, -1, "control register E"}, + {"faultc4.status", 0x885, 1, -1, -1, "status register"}, + {"faultc4.ctrlgclr", 0x886, 1, -1, -1, "control register G clear"}, + {"faultc4.ctrlgset", 0x887, 1, -1, -1, "control register G set"}, + {"faultc5.ctrla", 0x890, 1, -1, -1, "control register A"}, + {"faultc5.ctrlb", 0x891, 1, -1, -1, "control register B"}, + {"faultc5.ctrlc", 0x892, 1, -1, -1, "control register C"}, + {"faultc5.ctrld", 0x893, 1, -1, -1, "control register D"}, + {"faultc5.ctrle", 0x894, 1, -1, -1, "control register E"}, + {"faultc5.status", 0x895, 1, -1, -1, "status register"}, + {"faultc5.ctrlgclr", 0x896, 1, -1, -1, "control register G clear"}, + {"faultc5.ctrlgset", 0x897, 1, -1, -1, "control register G set"}, + {"wexc.ctrl", 0x8a0, 1, -1, -1, "control register"}, + {"wexc.dtboth", 0x8a1, 1, -1, -1, "dead-time both sides register"}, + {"wexc.dtls", 0x8a2, 1, -1, -1, "dead-time low side register"}, + {"wexc.dths", 0x8a3, 1, -1, -1, "dead-time high side register"}, + {"wexc.statusclr", 0x8a4, 1, -1, -1, "status clear register"}, + {"wexc.statusset", 0x8a5, 1, -1, -1, "status set register"}, + {"wexc.swap", 0x8a6, 1, -1, -1, "swap register"}, + {"wexc.pgo", 0x8a7, 1, -1, -1, "pattern generation override register"}, + {"wexc.pgv", 0x8a8, 1, -1, -1, "pattern generation value register"}, + {"wexc.swapbuf", 0x8aa, 1, -1, -1, "dead time low side buffer register"}, + {"wexc.pgobuf", 0x8ab, 1, -1, -1, "pattern generation overwrite buffer register"}, + {"wexc.pgvbuf", 0x8ac, 1, -1, -1, "pattern generation value buffer register"}, + {"wexc.outovdis", 0x8af, 1, -1, -1, "output override disable register"}, + {"hiresc.ctrla", 0x8b0, 1, -1, -1, "control register A"}, + {"usartc0.data", 0x8c0, 1, -1, -1, "data register"}, + {"usartc0.status", 0x8c1, 1, -1, -1, "status register"}, + {"usartc0.ctrla", 0x8c2, 1, -1, -1, "control register A"}, + {"usartc0.ctrlb", 0x8c3, 1, -1, -1, "control register B"}, + {"usartc0.ctrlc", 0x8c4, 1, -1, -1, "control register C"}, + {"usartc0.ctrld", 0x8c5, 1, -1, -1, "control register D"}, + {"usartc0.baudctrla", 0x8c6, 1, -1, -1, "baud rate control register A"}, + {"usartc0.baudctrlb", 0x8c7, 1, -1, -1, "baud rate control register B"}, + {"spic.ctrl", 0x8e0, 1, -1, -1, "control register"}, + {"spic.intctrl", 0x8e1, 1, -1, -1, "interrupt control register"}, + {"spic.status", 0x8e2, 1, -1, -1, "status register"}, + {"spic.data", 0x8e3, 1, -1, -1, "data register"}, + {"spic.ctrlb", 0x8e4, 1, -1, -1, "control register B"}, + {"ircom.ctrl", 0x8f8, 1, -1, -1, "control register"}, + {"ircom.txplctrl", 0x8f9, 1, -1, -1, "IrDA transmitter pulse length control register"}, + {"ircom.rxplctrl", 0x8fa, 1, -1, -1, "IrDA receiver pulse length control register"}, + {"tcd5.ctrla", 0x940, 1, -1, -1, "control register A"}, + {"tcd5.ctrlb", 0x941, 1, -1, -1, "control register B"}, + {"tcd5.ctrlc", 0x942, 1, -1, -1, "control register C"}, + {"tcd5.ctrld", 0x943, 1, -1, -1, "control register D"}, + {"tcd5.ctrle", 0x944, 1, -1, -1, "control register E"}, + {"tcd5.ctrlf", 0x945, 1, -1, -1, "control register F"}, + {"tcd5.intctrla", 0x946, 1, -1, -1, "interrupt control register A"}, + {"tcd5.intctrlb", 0x947, 1, -1, -1, "interrupt control register B"}, + {"tcd5.ctrlgclr", 0x948, 1, -1, -1, "control register G clear"}, + {"tcd5.ctrlgset", 0x949, 1, -1, -1, "control register G set"}, + {"tcd5.ctrlhclr", 0x94a, 1, -1, -1, "control register H clear"}, + {"tcd5.ctrlhset", 0x94b, 1, -1, -1, "control register H set"}, + {"tcd5.intflags", 0x94c, 1, -1, -1, "interrupt flags register"}, + {"tcd5.temp", 0x94f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcd5.cnt", 0x960, 2, -1, -1, "counter (16 bits)"}, + {"tcd5.per", 0x966, 2, -1, -1, "period register (16 bits)"}, + {"tcd5.cca", 0x968, 2, -1, -1, "compare or capture A register (16 bits)"}, + {"tcd5.ccb", 0x96a, 2, -1, -1, "compare or capture B register (16 bits)"}, + {"tcd5.perbuf", 0x976, 2, -1, -1, "period buffer register (16 bits)"}, + {"tcd5.ccabuf", 0x978, 2, -1, -1, "compare or capture A buffer register (16 bits)"}, + {"tcd5.ccbbuf", 0x97a, 2, -1, -1, "compare or capture B buffer register (16 bits)"}, + {"usartd0.data", 0x9c0, 1, -1, -1, "data register"}, + {"usartd0.status", 0x9c1, 1, -1, -1, "status register"}, + {"usartd0.ctrla", 0x9c2, 1, -1, -1, "control register A"}, + {"usartd0.ctrlb", 0x9c3, 1, -1, -1, "control register B"}, + {"usartd0.ctrlc", 0x9c4, 1, -1, -1, "control register C"}, + {"usartd0.ctrld", 0x9c5, 1, -1, -1, "control register D"}, + {"usartd0.baudctrla", 0x9c6, 1, -1, -1, "baud rate control register A"}, + {"usartd0.baudctrlb", 0x9c7, 1, -1, -1, "baud rate control register B"}, +}; + // ATtiny202 ATtiny402 const Register_file rgftab_attiny202[217] = { // I/O memory [0, 4351] {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, @@ -40232,6 +38790,761 @@ const Register_file rgftab_attiny202[217] = { // I/O memory [0, 4351] {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, }; +// ATtiny204 ATtiny404 +const Register_file rgftab_attiny204[235] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, -1, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny406 +const Register_file rgftab_attiny406[253] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, -1, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny804 ATtiny806 ATtiny807 ATtiny1604 ATtiny1606 ATtiny1607 +const Register_file rgftab_attiny804[255] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, + {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, + {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, + {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, + {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, + {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, + {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, + {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, + {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, + {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, + {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, + {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, + {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, + {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, + {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, + {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, + {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, + {"evsys.asyncuser11", 0x019d, 1, -1, 0x00, "asynchronous user ch 11 input selection - TCB 1 register"}, + {"evsys.asyncuser12", 0x019e, 1, -1, 0x00, "asynchronous user ch 12 input selection - ADC 1 register"}, + {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, + {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, + {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, + {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, + {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, + {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, + {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, + {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0824, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + // ATtiny212 ATtiny412 const Register_file rgftab_attiny212[247] = { // I/O memory [0, 4351] {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, @@ -40752,263 +40065,6 @@ const Register_file rgftab_attiny214[265] = { // I/O memory [0, 4351] {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, }; -// ATtiny406 -const Register_file rgftab_attiny406[253] = { // I/O memory [0, 4351] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, - {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, - {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, - {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, - {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, - {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, - {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x00, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, -1, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, - {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, - {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, - {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, - {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, - {"evsys.syncch1", 0x018b, 1, -1, 0x00, "synchronous channel 1 generator selection register"}, - {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, - {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, - {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, - {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, - {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, - {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, - {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, - {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, - {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, - {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, - {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, - {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, - {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, - {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, - {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, - {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, - {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, - {"ac0.ctrla", 0x0670, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrla", 0x0672, 1, -1, 0x00, "mux control A register"}, - {"ac0.intctrl", 0x0676, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0677, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, - {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, - {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, - {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, - {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, - {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, - {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, - {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0824, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, -}; - // ATtiny416 const Register_file rgftab_attiny416[283] = { // I/O memory [0, 4351] {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, @@ -41870,577 +40926,6 @@ const Register_file rgftab_attiny417[283] = { // I/O memory [0, 4351] {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, }; -// ATtiny426 ATtiny427 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 ATtiny3226 ATtiny3227 -const Register_file rgftab_attiny426[308] = { // I/O memory [0, 4351] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, -1, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, - {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, - {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, - {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, - {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, - {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, - {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, - {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"evsys.sweventa", 0x0180, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x01a8, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, - {"evsys.userevsysevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userusart0irda", 0x01ac, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x01ad, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x01ae, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x01af, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x01b0, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x01b1, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x01b2, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x01b3, 1, -1, 0x00, "user TCB 1 event register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e3, 1, -1, 0x00, "SPI route A register"}, - {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, - {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, - {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, - {"adc0.result", 0x0610, 4, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x0614, 2, -1, -1, "sample register (16 bits)"}, - {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, - {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, - {"adc0.temp2", 0x061a, 1, -1, -1, "temporary data register 2"}, - {"adc0.winlt", 0x061c, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x061e, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, - {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, - {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, - {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, - {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, - {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, - {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x08c2, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, -}; - -// ATtiny804 ATtiny806 ATtiny807 ATtiny1604 ATtiny1606 ATtiny1607 -const Register_file rgftab_attiny804[255] = { // I/O memory [0, 4351] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, - {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, - {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, - {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.spl", 0x003d, 1, -1, -1, "stack pointer low byte"}, - {"cpu.sph", 0x003e, 1, -1, -1, "stack pointer high byte"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, - {"clkctrl.mclkstatus", 0x0063, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, - {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, - {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, - {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, - {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, - {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, -1, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"evsys.asyncstrobe", 0x0180, 1, -1, 0x00, "asynchronous channel strobe register"}, - {"evsys.syncstrobe", 0x0181, 1, -1, 0x00, "synchronous channel strobe register"}, - {"evsys.asyncch0", 0x0182, 1, -1, 0x00, "asynchronous channel 0 generator selection register"}, - {"evsys.asyncch1", 0x0183, 1, -1, 0x00, "asynchronous channel 1 generator selection register"}, - {"evsys.syncch0", 0x018a, 1, -1, 0x00, "synchronous channel 0 generator selection register"}, - {"evsys.asyncuser0", 0x0192, 1, -1, 0x00, "asynchronous user ch 0 input selection - TCB 0 register"}, - {"evsys.asyncuser1", 0x0193, 1, -1, 0x00, "asynchronous user ch 1 input selection - ADC 0 register"}, - {"evsys.asyncuser2", 0x0194, 1, -1, 0x00, "asynchronous user ch 2 input selection - CCL LUT 0 event 0 register"}, - {"evsys.asyncuser3", 0x0195, 1, -1, 0x00, "asynchronous user ch 3 input selection - CCL LUT 1 event 0 register"}, - {"evsys.asyncuser4", 0x0196, 1, -1, 0x00, "asynchronous user ch 4 input selection - CCL LUT 0 event 1 register"}, - {"evsys.asyncuser5", 0x0197, 1, -1, 0x00, "asynchronous user ch 5 input selection - CCL LUT 1 event 1 register"}, - {"evsys.asyncuser6", 0x0198, 1, -1, 0x00, "asynchronous user ch 6 input selection - TCD 0 event 0 register"}, - {"evsys.asyncuser7", 0x0199, 1, -1, 0x00, "asynchronous user ch 7 input selection - TCD 0 event 1 register"}, - {"evsys.asyncuser8", 0x019a, 1, -1, 0x00, "asynchronous user ch 8 input selection - event out 0 register"}, - {"evsys.asyncuser9", 0x019b, 1, -1, 0x00, "asynchronous user ch 9 input selection - event out 1 register"}, - {"evsys.asyncuser10", 0x019c, 1, -1, 0x00, "asynchronous user ch 10 input selection - event out 2 register"}, - {"evsys.asyncuser11", 0x019d, 1, -1, 0x00, "asynchronous user ch 11 input selection - TCB 1 register"}, - {"evsys.asyncuser12", 0x019e, 1, -1, 0x00, "asynchronous user ch 12 input selection - ADC 1 register"}, - {"evsys.syncuser0", 0x01a2, 1, -1, 0x00, "synchronous user ch 0 - TCA 0 register"}, - {"evsys.syncuser1", 0x01a3, 1, -1, 0x00, "synchronous user ch 1 - USART 0 register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.lut0ctrla", 0x01c5, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c6, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01c7, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01c8, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01c9, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01ca, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01cb, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cc, 1, -1, 0x00, "truth register 1"}, - {"portmux.ctrla", 0x0200, 1, -1, 0x00, "control register A"}, - {"portmux.ctrlb", 0x0201, 1, -1, 0x00, "control register B"}, - {"portmux.ctrlc", 0x0202, 1, -1, 0x00, "control register C"}, - {"portmux.ctrld", 0x0203, 1, -1, 0x00, "control register D"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0606, 1, -1, 0x00, "positive mux input register"}, - {"adc0.command", 0x0608, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x0609, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060a, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060b, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060c, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060d, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.calib", 0x0616, 1, -1, 0x00, "calibration register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0810, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x0812, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0813, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0814, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0815, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0816, 1, -1, -1, "host baud rate register"}, - {"twi0.haddr", 0x0817, 1, -1, -1, "host address register"}, - {"twi0.hdata", 0x0818, 1, -1, -1, "host data register"}, - {"twi0.sctrla", 0x0819, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x081a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x081b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x081c, 1, -1, -1, "client address register"}, - {"twi0.sdata", 0x081d, 1, -1, -1, "client data register"}, - {"twi0.saddrmask", 0x081e, 1, -1, -1, "client address mask register"}, - {"spi0.ctrla", 0x0820, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0821, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0822, 1, -1, -1, "interrupt control register"}, - {"spi0.intflags", 0x0823, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0824, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0a44, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0a45, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0a46, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0a47, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0a48, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0a49, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0a4a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0a4c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.extbrk", 0x0f02, 1, -1, 0x00, "external break register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, -}; - // ATtiny814 const Register_file rgftab_attiny814[265] = { // I/O memory [0, 4351] {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, @@ -43682,6 +42167,629 @@ const Register_file rgftab_attiny3216[326] = { // I/O memory [0, 4351] {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, }; +// ATtiny424 ATtiny824 ATtiny1624 ATtiny3224 +const Register_file rgftab_attiny424[307] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.sweventa", 0x0180, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x01a8, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userusart0irda", 0x01ac, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x01ad, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x01ae, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x01af, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x01b0, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x01b1, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x01b2, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x01b3, 1, -1, 0x00, "user TCB 1 event register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e3, 1, -1, 0x00, "SPI route A register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, -1, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, -1, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + +// ATtiny426 ATtiny427 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 ATtiny3226 ATtiny3227 +const Register_file rgftab_attiny426[308] = { // I/O memory [0, 4351] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"gpio.gpior0", 0x001c, 1, -1, -1, "general purpose I/O register 0"}, + {"gpio.gpior1", 0x001d, 1, -1, -1, "general purpose I/O register 1"}, + {"gpio.gpior2", 0x001e, 1, -1, -1, "general purpose I/O register 2"}, + {"gpio.gpior3", 0x001f, 1, -1, -1, "general purpose I/O register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, -1, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclklock", 0x0062, 1, -1, -1, "MCLK lock register"}, + {"clkctrl.mclkstatus", 0x0063, 1, -1, -1, "MCLK status register"}, + {"clkctrl.osc20mctrla", 0x0070, 1, -1, -1, "OSC20M control A register"}, + {"clkctrl.osc20mcaliba", 0x0071, 1, -1, 0x00, "OSC20M calibration A register"}, + {"clkctrl.osc20mcalibb", 0x0072, 1, -1, 0x00, "OSC20M calibration B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x0080, 1, -1, 0x05, "control register A"}, + {"bod.ctrlb", 0x0081, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0088, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0089, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x008a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x008b, 1, -1, 0x00, "status register"}, + {"vref.ctrla", 0x00a0, 1, -1, 0x00, "control register A"}, + {"vref.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"evsys.sweventa", 0x0180, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0190, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0191, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0192, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0193, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0194, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0195, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x01a0, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x01a1, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x01a2, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x01a3, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x01a4, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x01a5, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x01a6, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x01a7, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x01a8, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x01a9, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x01aa, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x01ab, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userusart0irda", 0x01ac, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x01ad, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x01ae, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x01af, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x01b0, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x01b1, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x01b2, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x01b3, 1, -1, 0x00, "user TCB 1 event register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e3, 1, -1, 0x00, "SPI route A register"}, + {"portmux.tcaroutea", 0x05e4, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e5, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, -1, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, -1, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrla", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0684, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x00, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x08a0, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x08a2, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x08a3, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x08a4, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x08a5, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x08a6, 1, -1, -1, "host baud rate register"}, + {"twi0.haddr", 0x08a7, 1, -1, -1, "host address register"}, + {"twi0.hdata", 0x08a8, 1, -1, -1, "host data register"}, + {"twi0.sctrla", 0x08a9, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x08aa, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x08ab, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x08ac, 1, -1, -1, "client address register"}, + {"twi0.sdata", 0x08ad, 1, -1, -1, "client data register"}, + {"twi0.saddrmask", 0x08ae, 1, -1, -1, "client address mask register"}, + {"spi0.ctrla", 0x08c0, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x08c1, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x08c2, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x08c3, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x08c4, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, -1, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, -1, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, -1, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, -1, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0a80, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0a81, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0a84, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0a85, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0a86, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0a87, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0a88, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0a89, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0a8a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0a8c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0a90, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0a91, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0a94, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0a95, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0a96, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0a97, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0a98, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0a99, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0a9a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0a9c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x00, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, +}; + // ATmega808 ATmega1608 const Register_file rgftab_atmega808[406] = { // I/O memory [0, 4351] {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, @@ -45374,4024 +44482,6 @@ const Register_file rgftab_atmega3209[432] = { // I/O memory [0, 4351] {"nvmctrl.addr", 0x1008, 2, -1, -1, "address register (16 bits)"}, }; -// AVR16DU14 AVR32DU14 -const Register_file rgftab_avr16du14[370] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.oschfstatus", 0x006a, 1, -1, -1, "OSCHF status register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"clkctrl.usbpllstatus", 0x0085, 1, -1, 0x00, "PLL status register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.acref", 0x00b0, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutd", 0x022a, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022b, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022c, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x022d, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x022e, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x022f, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"usb0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, - {"usb0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, - {"usb0.busstate", 0x0c02, 1, -1, 0x00, "bus state register"}, - {"usb0.addr", 0x0c03, 1, -1, 0x00, "address register"}, - {"usb0.fifowp", 0x0c04, 1, -1, 0xff, "FIFO write pointer register"}, - {"usb0.fiforp", 0x0c05, 1, -1, 0xff, "FIFO read pointer register"}, - {"usb0.epptr", 0x0c06, 2, -1, 0x0000, "endpoint configuration table pointer register (16 bits)"}, - {"usb0.intctrla", 0x0c08, 1, -1, 0x00, "interrupt control register A"}, - {"usb0.intctrlb", 0x0c09, 1, -1, 0x00, "interrupt control register B"}, - {"usb0.intflagsa", 0x0c0a, 1, -1, 0x00, "interrupt flags A register"}, - {"usb0.intflagsb", 0x0c0b, 1, -1, 0x00, "interrupt flags B register"}, - {"usb.status.outclr", 0x0c40, 1, -1, 0x00, "endpoint n OUT status clear register"}, - {"usb.status.outset", 0x0c41, 1, -1, 0x00, "endpoint n OUT status set register"}, - {"usb.status.inclr", 0x0c42, 1, -1, 0x00, "endpoint n IN status clear register"}, - {"usb.status.inset", 0x0c43, 1, -1, 0x00, "endpoint n IN status set register"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.vusbctrl", 0x0f06, 1, -1, 0x00, "USB voltage system control register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR16EB14 AVR32EB14 -const Register_file rgftab_avr16eb14[390] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, 0x00, "PLL control A register"}, - {"clkctrl.pllctrlb", 0x0071, 1, -1, 0x00, "PLL control B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.usertce0cnta", 0x022e, 1, -1, 0x00, "user TCE 0 event A register"}, - {"evsys.usertce0cntb", 0x022f, 1, -1, 0x00, "user TCE 0 event B register"}, - {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcf0cnt", 0x0234, 1, -1, 0x00, "user TCF 0 clock event register"}, - {"evsys.usertcf0act", 0x0235, 1, -1, 0x00, "user TCF 0 action event register"}, - {"evsys.userwexa", 0x0236, 1, -1, 0x00, "user WEX event A register"}, - {"evsys.userwexb", 0x0237, 1, -1, 0x00, "user WEX event B register"}, - {"evsys.userwexc", 0x0238, 1, -1, 0x00, "user WEX event C register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, - {"portmux.tcfroutea", 0x05ec, 1, -1, 0x00, "TCF route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, - {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, - {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, - {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, - {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, - {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, - {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, - {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tce0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, - {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, - {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, - {"tce0.amp", 0x0a22, 2, -1, 0x0000, "amplitude register (16 bits)"}, - {"tce0.offset", 0x0a24, 2, -1, 0x0000, "offset register (16 bits)"}, - {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, - {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, - {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, - {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, - {"tce0.cmp3", 0x0a2e, 2, -1, 0x0000, "compare 3 register (16 bits)"}, - {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, - {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, - {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, - {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, - {"tce0.cmp3buf", 0x0a3e, 2, -1, 0x0000, "compare 3 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcf0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, - {"tcf0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, - {"tcf0.ctrlc", 0x0c02, 1, -1, 0x00, "control register C"}, - {"tcf0.ctrld", 0x0c03, 1, -1, 0x00, "control register D"}, - {"tcf0.evctrl", 0x0c04, 1, -1, 0x00, "event control register"}, - {"tcf0.intctrl", 0x0c05, 1, -1, 0x00, "interrupt control register"}, - {"tcf0.intflags", 0x0c06, 1, -1, 0x00, "interrupt flags register"}, - {"tcf0.status", 0x0c07, 1, -1, 0x00, "status register"}, - {"tcf0.dbgctrl", 0x0c0d, 1, -1, 0x00, "debug control register"}, - {"tcf0.cnt", 0x0c10, 4, -1, 0x00000000, "counter (32 bits)"}, - {"tcf0.cmp", 0x0c14, 4, -1, 0x00000000, "compare register (32 bits)"}, - {"wex0.ctrla", 0x0c80, 1, -1, 0x00, "control register A"}, - {"wex0.ctrlb", 0x0c81, 1, -1, 0x00, "control register B"}, - {"wex0.ctrlc", 0x0c82, 1, -1, 0x00, "control register C"}, - {"wex0.evctrla", 0x0c84, 1, -1, 0x00, "event control register A"}, - {"wex0.evctrlb", 0x0c85, 1, -1, 0x00, "event control register B"}, - {"wex0.evctrlc", 0x0c86, 1, -1, 0x00, "event control register C"}, - {"wex0.bufctrl", 0x0c87, 1, -1, 0x00, "buffer valid control register"}, - {"wex0.blankctrl", 0x0c88, 1, -1, 0x00, "blanking control register"}, - {"wex0.blanktime", 0x0c89, 1, -1, 0x00, "blanking time register"}, - {"wex0.faultctrl", 0x0c8a, 1, -1, 0x00, "fault control register"}, - {"wex0.faultdrv", 0x0c8b, 1, -1, 0x00, "fault drive register"}, - {"wex0.faultout", 0x0c8c, 1, -1, 0x00, "fault output register"}, - {"wex0.intctrl", 0x0c8d, 1, -1, 0x00, "interrupt control register"}, - {"wex0.intflags", 0x0c8e, 1, -1, 0x00, "interrupt flags register"}, - {"wex0.status", 0x0c8f, 1, -1, 0x00, "status register"}, - {"wex0.dtls", 0x0c90, 1, -1, 0x00, "dead-time low side register"}, - {"wex0.dths", 0x0c91, 1, -1, 0x00, "dead-time high side register"}, - {"wex0.dtboth", 0x0c92, 1, -1, 0x00, "dead-time both sides register"}, - {"wex0.swap", 0x0c93, 1, -1, 0x00, "DTI swap register"}, - {"wex0.pgmovr", 0x0c94, 1, -1, 0x00, "pattern generation override register"}, - {"wex0.pgmout", 0x0c95, 1, -1, 0x00, "pattern generation output register"}, - {"wex0.outoven", 0x0c97, 1, -1, 0x00, "output override enable register"}, - {"wex0.dtlsbuf", 0x0c98, 1, -1, 0x00, "dead-time low side buffer register"}, - {"wex0.dthsbuf", 0x0c99, 1, -1, 0x00, "dead-time high side buffer register"}, - {"wex0.dtbothbuf", 0x0c9a, 1, -1, 0x00, "dead-time both sides buffer register"}, - {"wex0.swapbuf", 0x0c9b, 1, -1, 0x00, "DTI swap buffer register"}, - {"wex0.pgmovrbuf", 0x0c9c, 1, -1, 0x00, "pattern generation override buffer register"}, - {"wex0.pgmoutbuf", 0x0c9d, 1, -1, 0x00, "pattern generation output buffer register"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, -}; - -// AVR16LA14 AVR32LA14 -const Register_file rgftab_avr16la14[339] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, - {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x00, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.intctrl", 0x0122, 1, -1, 0x00, "interrupt control register"}, - {"crcscan.intflags", 0x0123, 1, -1, 0x00, "interrupt flags register"}, - {"crcscan.statusa", 0x0124, 1, -1, 0x04, "status A register"}, - {"crcscan.scanadr", 0x0125, 1, -1, 0x00, "scan address register"}, - {"crcscan.data", 0x0126, 1, -1, 0x00, "data register"}, - {"crcscan.crc", 0x0128, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userac0sample", 0x0224, 1, -1, 0x00, "user 4 - AC0 register"}, - {"evsys.useradc0start", 0x0225, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0226, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x0227, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0228, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0229, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0rxd", 0x022a, 1, -1, 0x00, "user 10 - USART0 RxD event input register"}, - {"evsys.usertce0cnta", 0x022b, 1, -1, 0x00, "user TCE 0 event A register"}, - {"evsys.usertce0cntb", 0x022c, 1, -1, 0x00, "user TCE 0 event B register"}, - {"evsys.usertcb0capt", 0x022d, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x022e, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x022f, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0230, 1, -1, 0x00, "user TCB 1 event register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, 0x0000, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.refscale", 0x0683, 1, -1, 0xff, "reference scaling register"}, - {"ac0.intctrl", 0x0684, 1, -1, 0x00, "interrupt control register"}, - {"ac0.intflags", 0x0685, 1, -1, -1, "interrupt flags register"}, - {"ac0.status", 0x0686, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0800, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0801, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0802, 1, -1, 0x00, "control register C"}, - {"usart0.ctrld", 0x0803, 1, -1, 0x00, "control register D"}, - {"usart0.ctrle", 0x0804, 1, -1, 0x00, "control register E"}, - {"usart0.ctrlf", 0x0805, 1, -1, 0x00, "control register F"}, - {"usart0.ctrlg", 0x0806, 1, -1, 0x00, "control register G"}, - {"usart0.command", 0x0807, 1, -1, 0x00, "command register"}, - {"usart0.evctrl", 0x0809, 1, -1, 0x00, "event control register"}, - {"usart0.baud", 0x080a, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.intctrl", 0x080c, 1, -1, 0x00, "interrupt control register"}, - {"usart0.intflags", 0x080d, 1, -1, 0x01, "interrupt flags register"}, - {"usart0.status", 0x080e, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0810, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0811, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0812, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0813, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.auxdata0", 0x0818, 1, -1, 0x00, "auxiliary data 0 register"}, - {"usart0.auxdata1", 0x0819, 1, -1, 0x00, "auxiliary data 1 register"}, - {"usart0.auxdata2", 0x081a, 1, -1, 0x00, "auxiliary data 2 register"}, - {"usart0.dbgctrl", 0x081f, 1, -1, 0x00, "debug control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, - {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, - {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, - {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, - {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, - {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, - {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, - {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, - {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, - {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, - {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.vddctrl", 0x0f07, 1, -1, 0x01, "VDD range control register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, -}; - -// AVR16DD20 AVR32DD20 AVR64DD20 -const Register_file rgftab_avr16dd20[391] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, - {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, - {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 -const Register_file rgftab_avr16du20[371] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.oschfstatus", 0x006a, 1, -1, -1, "OSCHF status register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"clkctrl.usbpllstatus", 0x0085, 1, -1, 0x00, "PLL status register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.acref", 0x00b0, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutd", 0x022a, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022b, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022c, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x022d, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x022e, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x022f, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"usb0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, - {"usb0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, - {"usb0.busstate", 0x0c02, 1, -1, 0x00, "bus state register"}, - {"usb0.addr", 0x0c03, 1, -1, 0x00, "address register"}, - {"usb0.fifowp", 0x0c04, 1, -1, 0xff, "FIFO write pointer register"}, - {"usb0.fiforp", 0x0c05, 1, -1, 0xff, "FIFO read pointer register"}, - {"usb0.epptr", 0x0c06, 2, -1, 0x0000, "endpoint configuration table pointer register (16 bits)"}, - {"usb0.intctrla", 0x0c08, 1, -1, 0x00, "interrupt control register A"}, - {"usb0.intctrlb", 0x0c09, 1, -1, 0x00, "interrupt control register B"}, - {"usb0.intflagsa", 0x0c0a, 1, -1, 0x00, "interrupt flags A register"}, - {"usb0.intflagsb", 0x0c0b, 1, -1, 0x00, "interrupt flags B register"}, - {"usb.status.outclr", 0x0c40, 1, -1, 0x00, "endpoint n OUT status clear register"}, - {"usb.status.outset", 0x0c41, 1, -1, 0x00, "endpoint n OUT status set register"}, - {"usb.status.inclr", 0x0c42, 1, -1, 0x00, "endpoint n IN status clear register"}, - {"usb.status.inset", 0x0c43, 1, -1, 0x00, "endpoint n IN status set register"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.vusbctrl", 0x0f06, 1, -1, 0x00, "USB voltage system control register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB20 AVR32EB28 AVR32EB32 -const Register_file rgftab_avr16eb20[391] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, 0x00, "PLL control A register"}, - {"clkctrl.pllctrlb", 0x0071, 1, -1, 0x00, "PLL control B register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.usertce0cnta", 0x022e, 1, -1, 0x00, "user TCE 0 event A register"}, - {"evsys.usertce0cntb", 0x022f, 1, -1, 0x00, "user TCE 0 event B register"}, - {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcf0cnt", 0x0234, 1, -1, 0x00, "user TCF 0 clock event register"}, - {"evsys.usertcf0act", 0x0235, 1, -1, 0x00, "user TCF 0 action event register"}, - {"evsys.userwexa", 0x0236, 1, -1, 0x00, "user WEX event A register"}, - {"evsys.userwexb", 0x0237, 1, -1, 0x00, "user WEX event B register"}, - {"evsys.userwexc", 0x0238, 1, -1, 0x00, "user WEX event C register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcfroutea", 0x05ec, 1, -1, 0x00, "TCF route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, - {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, - {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, - {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, - {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, - {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, - {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, - {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tce0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, - {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, - {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, - {"tce0.amp", 0x0a22, 2, -1, 0x0000, "amplitude register (16 bits)"}, - {"tce0.offset", 0x0a24, 2, -1, 0x0000, "offset register (16 bits)"}, - {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, - {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, - {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, - {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, - {"tce0.cmp3", 0x0a2e, 2, -1, 0x0000, "compare 3 register (16 bits)"}, - {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, - {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, - {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, - {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, - {"tce0.cmp3buf", 0x0a3e, 2, -1, 0x0000, "compare 3 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcf0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, - {"tcf0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, - {"tcf0.ctrlc", 0x0c02, 1, -1, 0x00, "control register C"}, - {"tcf0.ctrld", 0x0c03, 1, -1, 0x00, "control register D"}, - {"tcf0.evctrl", 0x0c04, 1, -1, 0x00, "event control register"}, - {"tcf0.intctrl", 0x0c05, 1, -1, 0x00, "interrupt control register"}, - {"tcf0.intflags", 0x0c06, 1, -1, 0x00, "interrupt flags register"}, - {"tcf0.status", 0x0c07, 1, -1, 0x00, "status register"}, - {"tcf0.dbgctrl", 0x0c0d, 1, -1, 0x00, "debug control register"}, - {"tcf0.cnt", 0x0c10, 4, -1, 0x00000000, "counter (32 bits)"}, - {"tcf0.cmp", 0x0c14, 4, -1, 0x00000000, "compare register (32 bits)"}, - {"wex0.ctrla", 0x0c80, 1, -1, 0x00, "control register A"}, - {"wex0.ctrlb", 0x0c81, 1, -1, 0x00, "control register B"}, - {"wex0.ctrlc", 0x0c82, 1, -1, 0x00, "control register C"}, - {"wex0.evctrla", 0x0c84, 1, -1, 0x00, "event control register A"}, - {"wex0.evctrlb", 0x0c85, 1, -1, 0x00, "event control register B"}, - {"wex0.evctrlc", 0x0c86, 1, -1, 0x00, "event control register C"}, - {"wex0.bufctrl", 0x0c87, 1, -1, 0x00, "buffer valid control register"}, - {"wex0.blankctrl", 0x0c88, 1, -1, 0x00, "blanking control register"}, - {"wex0.blanktime", 0x0c89, 1, -1, 0x00, "blanking time register"}, - {"wex0.faultctrl", 0x0c8a, 1, -1, 0x00, "fault control register"}, - {"wex0.faultdrv", 0x0c8b, 1, -1, 0x00, "fault drive register"}, - {"wex0.faultout", 0x0c8c, 1, -1, 0x00, "fault output register"}, - {"wex0.intctrl", 0x0c8d, 1, -1, 0x00, "interrupt control register"}, - {"wex0.intflags", 0x0c8e, 1, -1, 0x00, "interrupt flags register"}, - {"wex0.status", 0x0c8f, 1, -1, 0x00, "status register"}, - {"wex0.dtls", 0x0c90, 1, -1, 0x00, "dead-time low side register"}, - {"wex0.dths", 0x0c91, 1, -1, 0x00, "dead-time high side register"}, - {"wex0.dtboth", 0x0c92, 1, -1, 0x00, "dead-time both sides register"}, - {"wex0.swap", 0x0c93, 1, -1, 0x00, "DTI swap register"}, - {"wex0.pgmovr", 0x0c94, 1, -1, 0x00, "pattern generation override register"}, - {"wex0.pgmout", 0x0c95, 1, -1, 0x00, "pattern generation output register"}, - {"wex0.outoven", 0x0c97, 1, -1, 0x00, "output override enable register"}, - {"wex0.dtlsbuf", 0x0c98, 1, -1, 0x00, "dead-time low side buffer register"}, - {"wex0.dthsbuf", 0x0c99, 1, -1, 0x00, "dead-time high side buffer register"}, - {"wex0.dtbothbuf", 0x0c9a, 1, -1, 0x00, "dead-time both sides buffer register"}, - {"wex0.swapbuf", 0x0c9b, 1, -1, 0x00, "DTI swap buffer register"}, - {"wex0.pgmovrbuf", 0x0c9c, 1, -1, 0x00, "pattern generation override buffer register"}, - {"wex0.pgmoutbuf", 0x0c9d, 1, -1, 0x00, "pattern generation output buffer register"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, -}; - -// AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA20 AVR32LA28 AVR32LA32 -const Register_file rgftab_avr16la20[341] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, - {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x00, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.intctrl", 0x0122, 1, -1, 0x00, "interrupt control register"}, - {"crcscan.intflags", 0x0123, 1, -1, 0x00, "interrupt flags register"}, - {"crcscan.statusa", 0x0124, 1, -1, 0x04, "status A register"}, - {"crcscan.scanadr", 0x0125, 1, -1, 0x00, "scan address register"}, - {"crcscan.data", 0x0126, 1, -1, 0x00, "data register"}, - {"crcscan.crc", 0x0128, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userac0sample", 0x0224, 1, -1, 0x00, "user 4 - AC0 register"}, - {"evsys.useradc0start", 0x0225, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0226, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x0227, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0228, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0229, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0rxd", 0x022a, 1, -1, 0x00, "user 10 - USART0 RxD event input register"}, - {"evsys.usertce0cnta", 0x022b, 1, -1, 0x00, "user TCE 0 event A register"}, - {"evsys.usertce0cntb", 0x022c, 1, -1, 0x00, "user TCE 0 event B register"}, - {"evsys.usertcb0capt", 0x022d, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x022e, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x022f, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0230, 1, -1, 0x00, "user TCB 1 event register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, 0x0000, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.refscale", 0x0683, 1, -1, 0xff, "reference scaling register"}, - {"ac0.intctrl", 0x0684, 1, -1, 0x00, "interrupt control register"}, - {"ac0.intflags", 0x0685, 1, -1, -1, "interrupt flags register"}, - {"ac0.status", 0x0686, 1, -1, 0x00, "status register"}, - {"usart0.ctrla", 0x0800, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0801, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0802, 1, -1, 0x00, "control register C"}, - {"usart0.ctrld", 0x0803, 1, -1, 0x00, "control register D"}, - {"usart0.ctrle", 0x0804, 1, -1, 0x00, "control register E"}, - {"usart0.ctrlf", 0x0805, 1, -1, 0x00, "control register F"}, - {"usart0.ctrlg", 0x0806, 1, -1, 0x00, "control register G"}, - {"usart0.command", 0x0807, 1, -1, 0x00, "command register"}, - {"usart0.evctrl", 0x0809, 1, -1, 0x00, "event control register"}, - {"usart0.baud", 0x080a, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.intctrl", 0x080c, 1, -1, 0x00, "interrupt control register"}, - {"usart0.intflags", 0x080d, 1, -1, 0x01, "interrupt flags register"}, - {"usart0.status", 0x080e, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0810, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0811, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0812, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0813, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.auxdata0", 0x0818, 1, -1, 0x00, "auxiliary data 0 register"}, - {"usart0.auxdata1", 0x0819, 1, -1, 0x00, "auxiliary data 1 register"}, - {"usart0.auxdata2", 0x081a, 1, -1, 0x00, "auxiliary data 2 register"}, - {"usart0.dbgctrl", 0x081f, 1, -1, 0x00, "debug control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, - {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, - {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, - {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, - {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, - {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, - {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, - {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, - {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, - {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, - {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.vddctrl", 0x0f07, 1, -1, 0x01, "VDD range control register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, -}; - -// AVR16DD28 AVR16DD32 AVR32DD28 AVR32DD32 AVR64DD28 AVR64DD32 -const Register_file rgftab_avr16dd28[401] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, - {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, - {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR16EA28 AVR16EA32 AVR32EA28 AVR32EA32 AVR64EA28 AVR64EA32 -const Register_file rgftab_avr16ea28[444] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022b, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x022c, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x022e, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x022f, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0230, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0231, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x0232, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0233, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertca1cnta", 0x0234, 1, -1, 0x00, "user TCA 1 event A register"}, - {"evsys.usertca1cntb", 0x0235, 1, -1, 0x00, "user TCA 1 event B register"}, - {"evsys.usertcb0capt", 0x0236, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0237, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0238, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0239, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x023a, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x023b, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x023c, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x023d, 1, -1, 0x00, "user TCB 3 event register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, - {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, - {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, - {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, - {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, - {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, - {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, - {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, - {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, - {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, - {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, - {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, - {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, - {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, - {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, - {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, - {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, - {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, - {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, - {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, - {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, - {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, - {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, - {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, - {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, - {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, -}; - -// AVR32SD20 -const Register_file rgftab_avr32sd20[540] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, - {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, -1, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"rstctrl.mcflagsa", 0x0042, 1, -1, -1, "machine check flags A register"}, - {"rstctrl.mcflagsb", 0x0043, 1, -1, -1, "machine check flags B register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.ctrlb", 0x0051, 1, -1, 0x00, "control register B"}, - {"slpctrl.vregctrl", 0x0052, 1, -1, 0x40, "control B register"}, - {"slpctrl.intctrl", 0x0053, 1, -1, 0x00, "interrupt control register"}, - {"slpctrl.intflags", 0x0054, 1, -1, 0x00, "interrupt flags register"}, - {"bod.ctrla", 0x0060, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x0061, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0068, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0069, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x006a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x006b, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x0072, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x0074, 1, -1, 0x00, "AC reference register"}, - {"clkctrl.mclkctrla", 0x0080, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0081, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0082, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0083, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0084, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0085, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0086, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.mclkcfd0ctrla", 0x0088, 1, -1, 0x00, "MCLK clock failure detect 0 control A register"}, - {"clkctrl.mclkcfd1ctrla", 0x0089, 1, -1, 0x00, "MCLK clock failure detect 1 control A register"}, - {"clkctrl.mclkcfm0value", 0x0090, 2, -1, 0x0000, "MCLK clock failure measurement 0 value register (16 bits)"}, - {"clkctrl.mclkcfm0winlt", 0x0092, 2, -1, 0x0000, "MCLK clock failure measurement 0 window low threshold register (16 bits)"}, - {"clkctrl.mclkcfm0winht", 0x0094, 2, -1, 0x0000, "MCLK clock failure measurement 0 window high threshold register (16 bits)"}, - {"clkctrl.mclkcfm0refnum", 0x0096, 2, -1, 0x0000, "MCLK clock failure measurement 0 reference clock cycles register (16 bits)"}, - {"clkctrl.mclkcfm0ctrla", 0x0098, 1, -1, 0x00, "MCLK clock failure measurement 0 control A register"}, - {"clkctrl.mclkcfm0ctrlb", 0x0099, 1, -1, 0x00, "MCLK clock failure measurement 0 control B register"}, - {"clkctrl.mclkcfm1value", 0x00a0, 2, -1, 0x0000, "MCLK clock failure measurement 1 value register (16 bits)"}, - {"clkctrl.mclkcfm1winlt", 0x00a2, 2, -1, 0x0000, "MCLK clock failure measurement 1 window low threshold register (16 bits)"}, - {"clkctrl.mclkcfm1winht", 0x00a4, 2, -1, 0x0000, "MCLK clock failure measurement 1 window high threshold register (16 bits)"}, - {"clkctrl.mclkcfm1refnum", 0x00a6, 2, -1, 0x0000, "MCLK clock failure measurement 1 reference clock cycles register (16 bits)"}, - {"clkctrl.mclkcfm1ctrla", 0x00a8, 1, -1, 0x00, "MCLK clock failure measurement 1 control A register"}, - {"clkctrl.mclkcfm1ctrlb", 0x00a9, 1, -1, 0x00, "MCLK clock failure measurement 1 control B register"}, - {"clkctrl.oschfctrla", 0x00c0, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x00c1, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x00c8, 1, -1, 0x00, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x00d0, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x00d4, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x00d8, 1, -1, 0x00, "XOSC HF control A register"}, - {"mvio.intctrl", 0x0100, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x0101, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x0102, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0110, 1, -1, -1, "control register A"}, - {"wdt.ctrlb", 0x0111, 1, -1, 0x40, "control register B"}, - {"wdt.status", 0x0112, 1, -1, 0x00, "status register"}, - {"wdt.cnt", 0x0114, 2, -1, 0x0000, "counter (16 bits)"}, - {"cpuint.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0121, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0122, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0123, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0130, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0131, 1, -1, 0x00, "control register B"}, - {"crcscan.intctrl", 0x0132, 1, -1, 0x00, "interrupt control register"}, - {"crcscan.intflags", 0x0133, 1, -1, 0x00, "interrupt flags register"}, - {"crcscan.statusa", 0x0134, 1, -1, 0x04, "status A register"}, - {"crcscan.scanadr", 0x0135, 1, -1, 0x00, "scan address register"}, - {"crcscan.data", 0x0136, 1, -1, 0x00, "data register"}, - {"crcscan.crc", 0x0138, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, - {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, - {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, - {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, - {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, - {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, - {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, - {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, - {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, - {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, - {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.useradc1start", 0x022d, 1, -1, 0x00, "user 13 - ADC1 register"}, - {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userusart0irda", 0x0232, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0233, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.usertca0cnta", 0x0235, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0236, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0237, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0238, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0239, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x023a, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x023b, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x023c, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x023d, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x023e, 1, -1, 0x00, "user TCB 3 event register"}, - {"evsys.usertcd0inputa", 0x023f, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0240, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.usererrctrlevent0", 0x0241, 1, -1, 0x00, "user 33 - ERRCTRL event 0 register"}, - {"evsys.usererrctrlevent1", 0x0242, 1, -1, 0x00, "user 34 - ERRCTRL event 1 register"}, - {"evsys.userclkctrlcfd", 0x0243, 1, -1, 0x00, "user 35 - CLKCTRL CFD register"}, - {"evsys.userclkctrlcfm", 0x0244, 1, -1, 0x00, "user 36 - CLKCTRL CFM register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05eb, 1, -1, 0x00, "ZCD route A register"}, - {"portmux.errctrlroutea", 0x05ed, 1, -1, 0x00, "error controller route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, - {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, - {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, - {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, - {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, - {"adc1.ctrlf", 0x0645, 1, -1, 0x00, "control register F"}, - {"adc1.intctrl", 0x0646, 1, -1, 0x00, "interrupt control register"}, - {"adc1.intflags", 0x0647, 1, -1, 0x00, "interrupt flags register"}, - {"adc1.status", 0x0648, 1, -1, 0x00, "status register"}, - {"adc1.dbgctrl", 0x0649, 1, -1, 0x00, "debug control register"}, - {"adc1.command", 0x064a, 1, -1, 0x00, "command register"}, - {"adc1.muxpos", 0x064b, 1, -1, 0x00, "positive mux input register"}, - {"adc1.result", 0x064c, 2, -1, -1, "result register (32 bits)"}, - {"adc1.sample", 0x064e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc1.winlt", 0x0650, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc1.winht", 0x0652, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc1.temp", 0x0654, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, - {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, - {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"swdt.ctrla", 0x0e20, 1, -1, 0x00, "control register A"}, - {"swdt.ctrlb", 0x0e21, 1, -1, 0x00, "control register B"}, - {"swdt.intctrl", 0x0e22, 1, -1, 0x00, "interrupt control register"}, - {"swdt.intflags", 0x0e23, 1, -1, 0x00, "interrupt flags register"}, - {"swdt.cnt", 0x0e24, 4, -1, 0x00000000, "counter (32 bits)"}, - {"swdt.reset", 0x0e28, 4, -1, 0x00000000, "counter reset register (32 bits)"}, - {"swdt.window", 0x0e2c, 2, -1, 0x0000, "counter window register (16 bits)"}, - {"swdt.command", 0x0e2e, 1, -1, 0x00, "command register"}, - {"ramctrl.ctrla", 0x0e30, 1, -1, 0x00, "control register A"}, - {"ramctrl.intflags", 0x0e31, 1, -1, 0x00, "interrupt flags register"}, - {"ramctrl.addr", 0x0e32, 2, -1, 0x0000, "address register (16 bits)"}, - {"ramctrl.syndrome", 0x0e34, 1, -1, 0x00, "ECC syndrome register"}, - {"errctrl.ctrla", 0x0e40, 1, -1, 0x01, "control register A"}, - {"errctrl.statusa", 0x0e41, 1, -1, -1, "status A register"}, - {"errctrl.timeout", 0x0e42, 1, -1, 0xff, "timeout value register"}, - {"errctrl.timecnt", 0x0e43, 1, -1, 0xff, "timeout counter register"}, - {"errctrl.cause", 0x0e44, 1, -1, -1, "reset cause register"}, - {"errctrl.escvregfail", 0x0e50, 1, -1, 0x82, "error source control VREGFAIL register"}, - {"errctrl.escbuserr", 0x0e51, 1, -1, 0x82, "error source control BUSERR register"}, - {"errctrl.escram2", 0x0e52, 1, -1, 0x82, "error source control RAM2 register"}, - {"errctrl.escflash2", 0x0e53, 1, -1, 0x82, "error source control FLASH2 register"}, - {"errctrl.escopc", 0x0e54, 1, -1, 0x82, "error source control OPC register"}, - {"errctrl.escsplim", 0x0e55, 1, -1, 0x82, "error source control SPLIM register"}, - {"errctrl.escram1", 0x0e56, 1, -1, 0x82, "error source control RAM1 register"}, - {"errctrl.escflash1", 0x0e57, 1, -1, 0x82, "error source control FLASH1 register"}, - {"errctrl.escvregwarn", 0x0e58, 1, -1, 0x82, "error source control VREGWARN register"}, - {"errctrl.esccfd0", 0x0e59, 1, -1, 0x82, "error source control CFD0 register"}, - {"errctrl.esccfd1", 0x0e5a, 1, -1, 0x82, "error source control CFD1 register"}, - {"errctrl.esccfm0", 0x0e5b, 1, -1, 0x82, "error source control CFM0 register"}, - {"errctrl.esccfm1", 0x0e5c, 1, -1, 0x82, "error source control CFM1 register"}, - {"errctrl.escswdt", 0x0e5d, 1, -1, 0x82, "error source control SWDT register"}, - {"errctrl.esceeprom", 0x0e5e, 1, -1, 0x82, "error source control EEPROM register"}, - {"errctrl.escevsys0", 0x0e5f, 1, -1, 0x82, "error source control EVSYS0 register"}, - {"errctrl.escevsys1", 0x0e60, 1, -1, 0x82, "error source control EVSYS1 register"}, - {"errctrl.esf", 0x0e70, 4, -1, -1, "error status flags register (32 bits)"}, - {"errctrl.esftest", 0x0e74, 4, -1, 0x00000000, "error status flag test injection register (32 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.ctrld", 0x1003, 1, -1, 0x00, "control register D"}, - {"nvmctrl.intctrla", 0x1004, 1, -1, 0x00, "interrupt control register A"}, - {"nvmctrl.intflagsa", 0x1005, 1, -1, 0x00, "interrupt flags A register"}, - {"nvmctrl.intflagsb", 0x1006, 1, -1, -1, "interrupt flags B register"}, - {"nvmctrl.status", 0x1007, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, - {"nvmctrl.parity", 0x1010, 1, -1, -1, "ECC parity register"}, - {"nvmctrl.syndrome", 0x1011, 1, -1, -1, "ECC syndrome register"}, -}; - // AVR32DA28 AVR32DA28S AVR64DA28 AVR64DA28S const Register_file rgftab_avr32da28[432] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -49828,1034 +44918,6 @@ const Register_file rgftab_avr32da28[432] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR32DB28 AVR64DB28 -const Register_file rgftab_avr32db28[461] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR32SD28 -const Register_file rgftab_avr32sd28[559] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, - {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, -1, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"rstctrl.mcflagsa", 0x0042, 1, -1, -1, "machine check flags A register"}, - {"rstctrl.mcflagsb", 0x0043, 1, -1, -1, "machine check flags B register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.ctrlb", 0x0051, 1, -1, 0x00, "control register B"}, - {"slpctrl.vregctrl", 0x0052, 1, -1, 0x40, "control B register"}, - {"slpctrl.intctrl", 0x0053, 1, -1, 0x00, "interrupt control register"}, - {"slpctrl.intflags", 0x0054, 1, -1, 0x00, "interrupt flags register"}, - {"bod.ctrla", 0x0060, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x0061, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0068, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0069, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x006a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x006b, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x0072, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x0074, 1, -1, 0x00, "AC reference register"}, - {"clkctrl.mclkctrla", 0x0080, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0081, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0082, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0083, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0084, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0085, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0086, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.mclkcfd0ctrla", 0x0088, 1, -1, 0x00, "MCLK clock failure detect 0 control A register"}, - {"clkctrl.mclkcfd1ctrla", 0x0089, 1, -1, 0x00, "MCLK clock failure detect 1 control A register"}, - {"clkctrl.mclkcfm0value", 0x0090, 2, -1, 0x0000, "MCLK clock failure measurement 0 value register (16 bits)"}, - {"clkctrl.mclkcfm0winlt", 0x0092, 2, -1, 0x0000, "MCLK clock failure measurement 0 window low threshold register (16 bits)"}, - {"clkctrl.mclkcfm0winht", 0x0094, 2, -1, 0x0000, "MCLK clock failure measurement 0 window high threshold register (16 bits)"}, - {"clkctrl.mclkcfm0refnum", 0x0096, 2, -1, 0x0000, "MCLK clock failure measurement 0 reference clock cycles register (16 bits)"}, - {"clkctrl.mclkcfm0ctrla", 0x0098, 1, -1, 0x00, "MCLK clock failure measurement 0 control A register"}, - {"clkctrl.mclkcfm0ctrlb", 0x0099, 1, -1, 0x00, "MCLK clock failure measurement 0 control B register"}, - {"clkctrl.mclkcfm1value", 0x00a0, 2, -1, 0x0000, "MCLK clock failure measurement 1 value register (16 bits)"}, - {"clkctrl.mclkcfm1winlt", 0x00a2, 2, -1, 0x0000, "MCLK clock failure measurement 1 window low threshold register (16 bits)"}, - {"clkctrl.mclkcfm1winht", 0x00a4, 2, -1, 0x0000, "MCLK clock failure measurement 1 window high threshold register (16 bits)"}, - {"clkctrl.mclkcfm1refnum", 0x00a6, 2, -1, 0x0000, "MCLK clock failure measurement 1 reference clock cycles register (16 bits)"}, - {"clkctrl.mclkcfm1ctrla", 0x00a8, 1, -1, 0x00, "MCLK clock failure measurement 1 control A register"}, - {"clkctrl.mclkcfm1ctrlb", 0x00a9, 1, -1, 0x00, "MCLK clock failure measurement 1 control B register"}, - {"clkctrl.oschfctrla", 0x00c0, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x00c1, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x00c8, 1, -1, 0x00, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x00d0, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x00d4, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x00d8, 1, -1, 0x00, "XOSC HF control A register"}, - {"mvio.intctrl", 0x0100, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x0101, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x0102, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0110, 1, -1, -1, "control register A"}, - {"wdt.ctrlb", 0x0111, 1, -1, 0x40, "control register B"}, - {"wdt.status", 0x0112, 1, -1, 0x00, "status register"}, - {"wdt.cnt", 0x0114, 2, -1, 0x0000, "counter (16 bits)"}, - {"cpuint.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0121, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0122, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0123, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0130, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0131, 1, -1, 0x00, "control register B"}, - {"crcscan.intctrl", 0x0132, 1, -1, 0x00, "interrupt control register"}, - {"crcscan.intflags", 0x0133, 1, -1, 0x00, "interrupt flags register"}, - {"crcscan.statusa", 0x0134, 1, -1, 0x04, "status A register"}, - {"crcscan.scanadr", 0x0135, 1, -1, 0x00, "scan address register"}, - {"crcscan.data", 0x0136, 1, -1, 0x00, "data register"}, - {"crcscan.crc", 0x0138, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, - {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, - {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, - {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, - {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, - {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, - {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, - {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, - {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, - {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, - {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.useradc1start", 0x022d, 1, -1, 0x00, "user 13 - ADC1 register"}, - {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userusart0irda", 0x0232, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0233, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0234, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x0235, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0236, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0237, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0238, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0239, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x023a, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x023b, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x023c, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x023d, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x023e, 1, -1, 0x00, "user TCB 3 event register"}, - {"evsys.usertcd0inputa", 0x023f, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0240, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.usererrctrlevent0", 0x0241, 1, -1, 0x00, "user 33 - ERRCTRL event 0 register"}, - {"evsys.usererrctrlevent1", 0x0242, 1, -1, 0x00, "user 34 - ERRCTRL event 1 register"}, - {"evsys.userclkctrlcfd", 0x0243, 1, -1, 0x00, "user 35 - CLKCTRL CFD register"}, - {"evsys.userclkctrlcfm", 0x0244, 1, -1, 0x00, "user 36 - CLKCTRL CFM register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05eb, 1, -1, 0x00, "ZCD route A register"}, - {"portmux.errctrlroutea", 0x05ed, 1, -1, 0x00, "error controller route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, - {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, - {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, - {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, - {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, - {"adc1.ctrlf", 0x0645, 1, -1, 0x00, "control register F"}, - {"adc1.intctrl", 0x0646, 1, -1, 0x00, "interrupt control register"}, - {"adc1.intflags", 0x0647, 1, -1, 0x00, "interrupt flags register"}, - {"adc1.status", 0x0648, 1, -1, 0x00, "status register"}, - {"adc1.dbgctrl", 0x0649, 1, -1, 0x00, "debug control register"}, - {"adc1.command", 0x064a, 1, -1, 0x00, "command register"}, - {"adc1.muxpos", 0x064b, 1, -1, 0x00, "positive mux input register"}, - {"adc1.result", 0x064c, 2, -1, -1, "result register (32 bits)"}, - {"adc1.sample", 0x064e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc1.winlt", 0x0650, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc1.winht", 0x0652, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc1.temp", 0x0654, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, - {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, - {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"swdt.ctrla", 0x0e20, 1, -1, 0x00, "control register A"}, - {"swdt.ctrlb", 0x0e21, 1, -1, 0x00, "control register B"}, - {"swdt.intctrl", 0x0e22, 1, -1, 0x00, "interrupt control register"}, - {"swdt.intflags", 0x0e23, 1, -1, 0x00, "interrupt flags register"}, - {"swdt.cnt", 0x0e24, 4, -1, 0x00000000, "counter (32 bits)"}, - {"swdt.reset", 0x0e28, 4, -1, 0x00000000, "counter reset register (32 bits)"}, - {"swdt.window", 0x0e2c, 2, -1, 0x0000, "counter window register (16 bits)"}, - {"swdt.command", 0x0e2e, 1, -1, 0x00, "command register"}, - {"ramctrl.ctrla", 0x0e30, 1, -1, 0x00, "control register A"}, - {"ramctrl.intflags", 0x0e31, 1, -1, 0x00, "interrupt flags register"}, - {"ramctrl.addr", 0x0e32, 2, -1, 0x0000, "address register (16 bits)"}, - {"ramctrl.syndrome", 0x0e34, 1, -1, 0x00, "ECC syndrome register"}, - {"errctrl.ctrla", 0x0e40, 1, -1, 0x01, "control register A"}, - {"errctrl.statusa", 0x0e41, 1, -1, -1, "status A register"}, - {"errctrl.timeout", 0x0e42, 1, -1, 0xff, "timeout value register"}, - {"errctrl.timecnt", 0x0e43, 1, -1, 0xff, "timeout counter register"}, - {"errctrl.cause", 0x0e44, 1, -1, -1, "reset cause register"}, - {"errctrl.escvregfail", 0x0e50, 1, -1, 0x82, "error source control VREGFAIL register"}, - {"errctrl.escbuserr", 0x0e51, 1, -1, 0x82, "error source control BUSERR register"}, - {"errctrl.escram2", 0x0e52, 1, -1, 0x82, "error source control RAM2 register"}, - {"errctrl.escflash2", 0x0e53, 1, -1, 0x82, "error source control FLASH2 register"}, - {"errctrl.escopc", 0x0e54, 1, -1, 0x82, "error source control OPC register"}, - {"errctrl.escsplim", 0x0e55, 1, -1, 0x82, "error source control SPLIM register"}, - {"errctrl.escram1", 0x0e56, 1, -1, 0x82, "error source control RAM1 register"}, - {"errctrl.escflash1", 0x0e57, 1, -1, 0x82, "error source control FLASH1 register"}, - {"errctrl.escvregwarn", 0x0e58, 1, -1, 0x82, "error source control VREGWARN register"}, - {"errctrl.esccfd0", 0x0e59, 1, -1, 0x82, "error source control CFD0 register"}, - {"errctrl.esccfd1", 0x0e5a, 1, -1, 0x82, "error source control CFD1 register"}, - {"errctrl.esccfm0", 0x0e5b, 1, -1, 0x82, "error source control CFM0 register"}, - {"errctrl.esccfm1", 0x0e5c, 1, -1, 0x82, "error source control CFM1 register"}, - {"errctrl.escswdt", 0x0e5d, 1, -1, 0x82, "error source control SWDT register"}, - {"errctrl.esceeprom", 0x0e5e, 1, -1, 0x82, "error source control EEPROM register"}, - {"errctrl.escevsys0", 0x0e5f, 1, -1, 0x82, "error source control EVSYS0 register"}, - {"errctrl.escevsys1", 0x0e60, 1, -1, 0x82, "error source control EVSYS1 register"}, - {"errctrl.esf", 0x0e70, 4, -1, -1, "error status flags register (32 bits)"}, - {"errctrl.esftest", 0x0e74, 4, -1, 0x00000000, "error status flag test injection register (32 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.ctrld", 0x1003, 1, -1, 0x00, "control register D"}, - {"nvmctrl.intctrla", 0x1004, 1, -1, 0x00, "interrupt control register A"}, - {"nvmctrl.intflagsa", 0x1005, 1, -1, 0x00, "interrupt flags A register"}, - {"nvmctrl.intflagsb", 0x1006, 1, -1, -1, "interrupt flags B register"}, - {"nvmctrl.status", 0x1007, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, - {"nvmctrl.parity", 0x1010, 1, -1, -1, "ECC parity register"}, - {"nvmctrl.syndrome", 0x1011, 1, -1, -1, "ECC syndrome register"}, -}; - // AVR32DA32 AVR32DA32S AVR64DA32 AVR64DA32S const Register_file rgftab_avr32da32[447] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -51307,1065 +45369,6 @@ const Register_file rgftab_avr32da32[447] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR32DB32 AVR64DB32 -const Register_file rgftab_avr32db32[476] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, - {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, - {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, - {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, - {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, - {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, - {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, - {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, - {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, - {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, - {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, - {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, - {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, - {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, - {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - -// AVR32SD32 -const Register_file rgftab_avr32sd32[575] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, - {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, -1, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"rstctrl.mcflagsa", 0x0042, 1, -1, -1, "machine check flags A register"}, - {"rstctrl.mcflagsb", 0x0043, 1, -1, -1, "machine check flags B register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.ctrlb", 0x0051, 1, -1, 0x00, "control register B"}, - {"slpctrl.vregctrl", 0x0052, 1, -1, 0x40, "control B register"}, - {"slpctrl.intctrl", 0x0053, 1, -1, 0x00, "interrupt control register"}, - {"slpctrl.intflags", 0x0054, 1, -1, 0x00, "interrupt flags register"}, - {"bod.ctrla", 0x0060, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x0061, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x0068, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x0069, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x006a, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x006b, 1, -1, 0x00, "status register"}, - {"vref.dac0ref", 0x0072, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x0074, 1, -1, 0x00, "AC reference register"}, - {"clkctrl.mclkctrla", 0x0080, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0081, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0082, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0083, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0084, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0085, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.mclktimebase", 0x0086, 1, -1, 0x00, "MCLK timebase register"}, - {"clkctrl.mclkcfd0ctrla", 0x0088, 1, -1, 0x00, "MCLK clock failure detect 0 control A register"}, - {"clkctrl.mclkcfd1ctrla", 0x0089, 1, -1, 0x00, "MCLK clock failure detect 1 control A register"}, - {"clkctrl.mclkcfm0value", 0x0090, 2, -1, 0x0000, "MCLK clock failure measurement 0 value register (16 bits)"}, - {"clkctrl.mclkcfm0winlt", 0x0092, 2, -1, 0x0000, "MCLK clock failure measurement 0 window low threshold register (16 bits)"}, - {"clkctrl.mclkcfm0winht", 0x0094, 2, -1, 0x0000, "MCLK clock failure measurement 0 window high threshold register (16 bits)"}, - {"clkctrl.mclkcfm0refnum", 0x0096, 2, -1, 0x0000, "MCLK clock failure measurement 0 reference clock cycles register (16 bits)"}, - {"clkctrl.mclkcfm0ctrla", 0x0098, 1, -1, 0x00, "MCLK clock failure measurement 0 control A register"}, - {"clkctrl.mclkcfm0ctrlb", 0x0099, 1, -1, 0x00, "MCLK clock failure measurement 0 control B register"}, - {"clkctrl.mclkcfm1value", 0x00a0, 2, -1, 0x0000, "MCLK clock failure measurement 1 value register (16 bits)"}, - {"clkctrl.mclkcfm1winlt", 0x00a2, 2, -1, 0x0000, "MCLK clock failure measurement 1 window low threshold register (16 bits)"}, - {"clkctrl.mclkcfm1winht", 0x00a4, 2, -1, 0x0000, "MCLK clock failure measurement 1 window high threshold register (16 bits)"}, - {"clkctrl.mclkcfm1refnum", 0x00a6, 2, -1, 0x0000, "MCLK clock failure measurement 1 reference clock cycles register (16 bits)"}, - {"clkctrl.mclkcfm1ctrla", 0x00a8, 1, -1, 0x00, "MCLK clock failure measurement 1 control A register"}, - {"clkctrl.mclkcfm1ctrlb", 0x00a9, 1, -1, 0x00, "MCLK clock failure measurement 1 control B register"}, - {"clkctrl.oschfctrla", 0x00c0, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x00c1, 1, -1, 0x00, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x00c8, 1, -1, 0x00, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x00d0, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x00d4, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x00d8, 1, -1, 0x00, "XOSC HF control A register"}, - {"mvio.intctrl", 0x0100, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x0101, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x0102, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0110, 1, -1, -1, "control register A"}, - {"wdt.ctrlb", 0x0111, 1, -1, 0x40, "control register B"}, - {"wdt.status", 0x0112, 1, -1, 0x00, "status register"}, - {"wdt.cnt", 0x0114, 2, -1, 0x0000, "counter (16 bits)"}, - {"cpuint.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0121, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0122, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0123, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0130, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0131, 1, -1, 0x00, "control register B"}, - {"crcscan.intctrl", 0x0132, 1, -1, 0x00, "interrupt control register"}, - {"crcscan.intflags", 0x0133, 1, -1, 0x00, "interrupt flags register"}, - {"crcscan.statusa", 0x0134, 1, -1, 0x04, "status A register"}, - {"crcscan.scanadr", 0x0135, 1, -1, 0x00, "scan address register"}, - {"crcscan.data", 0x0136, 1, -1, 0x00, "data register"}, - {"crcscan.crc", 0x0138, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, - {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, - {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, - {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, - {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, - {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, - {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, - {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, - {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, - {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, - {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.useradc1start", 0x022d, 1, -1, 0x00, "user 13 - ADC1 register"}, - {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0231, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0232, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0233, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0234, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x0235, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x0236, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x0237, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x0238, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0239, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x023a, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x023b, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x023c, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x023d, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x023e, 1, -1, 0x00, "user TCB 3 event register"}, - {"evsys.usertcd0inputa", 0x023f, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0240, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.usererrctrlevent0", 0x0241, 1, -1, 0x00, "user 33 - ERRCTRL event 0 register"}, - {"evsys.usererrctrlevent1", 0x0242, 1, -1, 0x00, "user 34 - ERRCTRL event 1 register"}, - {"evsys.userclkctrlcfd", 0x0243, 1, -1, 0x00, "user 35 - CLKCTRL CFD register"}, - {"evsys.userclkctrlcfm", 0x0244, 1, -1, 0x00, "user 36 - CLKCTRL CFM register"}, - {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, - {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, - {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, - {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05eb, 1, -1, 0x00, "ZCD route A register"}, - {"portmux.errctrlroutea", 0x05ed, 1, -1, 0x00, "error controller route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, - {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, - {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, - {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, - {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, - {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, - {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, - {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, - {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, - {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, - {"adc1.ctrlf", 0x0645, 1, -1, 0x00, "control register F"}, - {"adc1.intctrl", 0x0646, 1, -1, 0x00, "interrupt control register"}, - {"adc1.intflags", 0x0647, 1, -1, 0x00, "interrupt flags register"}, - {"adc1.status", 0x0648, 1, -1, 0x00, "status register"}, - {"adc1.dbgctrl", 0x0649, 1, -1, 0x00, "debug control register"}, - {"adc1.command", 0x064a, 1, -1, 0x00, "command register"}, - {"adc1.muxpos", 0x064b, 1, -1, 0x00, "positive mux input register"}, - {"adc1.result", 0x064c, 2, -1, -1, "result register (32 bits)"}, - {"adc1.sample", 0x064e, 2, -1, 0x0000, "sample register (16 bits)"}, - {"adc1.winlt", 0x0650, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc1.winht", 0x0652, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"adc1.temp", 0x0654, 1, -1, 0x00, "temporary data register"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, - {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, - {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, - {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, - {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, - {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, - {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, - {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, - {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, - {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, - {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, - {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, - {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, - {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, - {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, - {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, - {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"swdt.ctrla", 0x0e20, 1, -1, 0x00, "control register A"}, - {"swdt.ctrlb", 0x0e21, 1, -1, 0x00, "control register B"}, - {"swdt.intctrl", 0x0e22, 1, -1, 0x00, "interrupt control register"}, - {"swdt.intflags", 0x0e23, 1, -1, 0x00, "interrupt flags register"}, - {"swdt.cnt", 0x0e24, 4, -1, 0x00000000, "counter (32 bits)"}, - {"swdt.reset", 0x0e28, 4, -1, 0x00000000, "counter reset register (32 bits)"}, - {"swdt.window", 0x0e2c, 2, -1, 0x0000, "counter window register (16 bits)"}, - {"swdt.command", 0x0e2e, 1, -1, 0x00, "command register"}, - {"ramctrl.ctrla", 0x0e30, 1, -1, 0x00, "control register A"}, - {"ramctrl.intflags", 0x0e31, 1, -1, 0x00, "interrupt flags register"}, - {"ramctrl.addr", 0x0e32, 2, -1, 0x0000, "address register (16 bits)"}, - {"ramctrl.syndrome", 0x0e34, 1, -1, 0x00, "ECC syndrome register"}, - {"errctrl.ctrla", 0x0e40, 1, -1, 0x01, "control register A"}, - {"errctrl.statusa", 0x0e41, 1, -1, -1, "status A register"}, - {"errctrl.timeout", 0x0e42, 1, -1, 0xff, "timeout value register"}, - {"errctrl.timecnt", 0x0e43, 1, -1, 0xff, "timeout counter register"}, - {"errctrl.cause", 0x0e44, 1, -1, -1, "reset cause register"}, - {"errctrl.escvregfail", 0x0e50, 1, -1, 0x82, "error source control VREGFAIL register"}, - {"errctrl.escbuserr", 0x0e51, 1, -1, 0x82, "error source control BUSERR register"}, - {"errctrl.escram2", 0x0e52, 1, -1, 0x82, "error source control RAM2 register"}, - {"errctrl.escflash2", 0x0e53, 1, -1, 0x82, "error source control FLASH2 register"}, - {"errctrl.escopc", 0x0e54, 1, -1, 0x82, "error source control OPC register"}, - {"errctrl.escsplim", 0x0e55, 1, -1, 0x82, "error source control SPLIM register"}, - {"errctrl.escram1", 0x0e56, 1, -1, 0x82, "error source control RAM1 register"}, - {"errctrl.escflash1", 0x0e57, 1, -1, 0x82, "error source control FLASH1 register"}, - {"errctrl.escvregwarn", 0x0e58, 1, -1, 0x82, "error source control VREGWARN register"}, - {"errctrl.esccfd0", 0x0e59, 1, -1, 0x82, "error source control CFD0 register"}, - {"errctrl.esccfd1", 0x0e5a, 1, -1, 0x82, "error source control CFD1 register"}, - {"errctrl.esccfm0", 0x0e5b, 1, -1, 0x82, "error source control CFM0 register"}, - {"errctrl.esccfm1", 0x0e5c, 1, -1, 0x82, "error source control CFM1 register"}, - {"errctrl.escswdt", 0x0e5d, 1, -1, 0x82, "error source control SWDT register"}, - {"errctrl.esceeprom", 0x0e5e, 1, -1, 0x82, "error source control EEPROM register"}, - {"errctrl.escevsys0", 0x0e5f, 1, -1, 0x82, "error source control EVSYS0 register"}, - {"errctrl.escevsys1", 0x0e60, 1, -1, 0x82, "error source control EVSYS1 register"}, - {"errctrl.esf", 0x0e70, 4, -1, -1, "error status flags register (32 bits)"}, - {"errctrl.esftest", 0x0e74, 4, -1, 0x00000000, "error status flag test injection register (32 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, - {"nvmctrl.ctrld", 0x1003, 1, -1, 0x00, "control register D"}, - {"nvmctrl.intctrla", 0x1004, 1, -1, 0x00, "interrupt control register A"}, - {"nvmctrl.intflagsa", 0x1005, 1, -1, 0x00, "interrupt flags A register"}, - {"nvmctrl.intflagsb", 0x1006, 1, -1, -1, "interrupt flags B register"}, - {"nvmctrl.status", 0x1007, 1, -1, 0x00, "status register"}, - {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, - {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, - {"nvmctrl.parity", 0x1010, 1, -1, -1, "ECC parity register"}, - {"nvmctrl.syndrome", 0x1011, 1, -1, -1, "ECC syndrome register"}, -}; - // AVR32DA48 AVR32DA48S const Register_file rgftab_avr32da48[610] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -52980,652 +45983,6 @@ const Register_file rgftab_avr32da48[610] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR32DB48 AVR64DB48 -const Register_file rgftab_avr32db48[642] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, - {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, - {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, - {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, - {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, - {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, - {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, - {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, - {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, - {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, - {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, - {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, - {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, - {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, - {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, - {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, - {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, - {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, - {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, - {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, - {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, - {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, - {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, - {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, - {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, - {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, - {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, - {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, - {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, - {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, - {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, - {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, - {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, - {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, - {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, - {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, - {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, - {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, - {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, - {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, - {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, - {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, - {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, - {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, - {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, - {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, - {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, - {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, - {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, - {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, - {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, - {"usart3.status", 0x0864, 1, -1, 0x20, "status register"}, - {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, - {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, - {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, - {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, - {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, - {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, - {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, - {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, - {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, - {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, - {"usart4.status", 0x0884, 1, -1, 0x20, "status register"}, - {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, - {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, - {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, - {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, - {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, - {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, - {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, - {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, - {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, - {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, - {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, - {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, - {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, - {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, - {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, - {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, - {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, - {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, - {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, - {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, - {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, - {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, - {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, - {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, - {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, - {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, - {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, - {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, - {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, - {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, - {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, - {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, - {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, - {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, - {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, - {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, - {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, - {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, - {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - // AVR64DA48 AVR64DA48S const Register_file rgftab_avr64da48[600] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -54892,707 +47249,6 @@ const Register_file rgftab_avr64da64[658] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR64DB64 -const Register_file rgftab_avr64db64[697] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, - {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, - {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, - {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"vportg.dir", 0x0018, 1, -1, -1, "data direction register"}, - {"vportg.out", 0x0019, 1, -1, -1, "I/O port output register"}, - {"vportg.in", 0x001a, 1, -1, -1, "I/O port input register"}, - {"vportg.intflags", 0x001b, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, - {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, - {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, - {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, - {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, - {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, - {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, - {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, - {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, - {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, - {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, - {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userevsysevoutg", 0x0233, 1, -1, 0x00, "user EVOUT port G register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, - {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, - {"evsys.userusart5irda", 0x0239, 1, -1, 0x00, "user USART 5 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, - {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, - {"evsys.usertcb4capt", 0x0246, 1, -1, 0x00, "user TCB 4 capture register"}, - {"evsys.usertcb4count", 0x0247, 1, -1, 0x00, "user TCB 4 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, - {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, - {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, - {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, - {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, - {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, - {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, - {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, - {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, - {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, - {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, - {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, - {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, - {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, - {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, - {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, - {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, - {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, - {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, - {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, - {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, - {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portg.dir", 0x04c0, 1, -1, -1, "data direction register"}, - {"portg.dirset", 0x04c1, 1, -1, -1, "data direction set register"}, - {"portg.dirclr", 0x04c2, 1, -1, -1, "data direction clear register"}, - {"portg.dirtgl", 0x04c3, 1, -1, -1, "data direction toggle register"}, - {"portg.out", 0x04c4, 1, -1, -1, "I/O port output register"}, - {"portg.outset", 0x04c5, 1, -1, -1, "I/O port output set register"}, - {"portg.outclr", 0x04c6, 1, -1, -1, "I/O port output clear register"}, - {"portg.outtgl", 0x04c7, 1, -1, -1, "I/O port output toggle register"}, - {"portg.in", 0x04c8, 1, -1, -1, "I/O port input register"}, - {"portg.intflags", 0x04c9, 1, -1, 0x00, "interrupt flags register"}, - {"portg.portctrl", 0x04ca, 1, -1, 0x00, "port control register"}, - {"portg.pinconfig", 0x04cb, 1, -1, 0x00, "pin control config register"}, - {"portg.pinctrlupd", 0x04cc, 1, -1, 0x00, "pin control update register"}, - {"portg.pinctrlset", 0x04cd, 1, -1, 0x00, "pin control set register"}, - {"portg.pinctrlclr", 0x04ce, 1, -1, 0x00, "pin control clear register"}, - {"portg.pin0ctrl", 0x04d0, 1, -1, 0x00, "pin 0 control register"}, - {"portg.pin1ctrl", 0x04d1, 1, -1, 0x00, "pin 1 control register"}, - {"portg.pin2ctrl", 0x04d2, 1, -1, 0x00, "pin 2 control register"}, - {"portg.pin3ctrl", 0x04d3, 1, -1, 0x00, "pin 3 control register"}, - {"portg.pin4ctrl", 0x04d4, 1, -1, 0x00, "pin 4 control register"}, - {"portg.pin5ctrl", 0x04d5, 1, -1, 0x00, "pin 5 control register"}, - {"portg.pin6ctrl", 0x04d6, 1, -1, 0x00, "pin 6 control register"}, - {"portg.pin7ctrl", 0x04d7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, - {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, - {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, - {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, - {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, - {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, - {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, - {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, - {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, - {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, - {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, - {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, - {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, - {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, - {"usart3.status", 0x0864, 1, -1, 0x20, "status register"}, - {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, - {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, - {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, - {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, - {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, - {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, - {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, - {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, - {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, - {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, - {"usart4.status", 0x0884, 1, -1, 0x20, "status register"}, - {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, - {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, - {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, - {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, - {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, - {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, - {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart5.rxdatal", 0x08a0, 1, -1, 0x00, "receive data low byte"}, - {"usart5.rxdatah", 0x08a1, 1, -1, 0x00, "receive data high byte"}, - {"usart5.txdatal", 0x08a2, 1, -1, 0x00, "transmit data low byte"}, - {"usart5.txdatah", 0x08a3, 1, -1, 0x00, "transmit data high byte"}, - {"usart5.status", 0x08a4, 1, -1, 0x20, "status register"}, - {"usart5.ctrla", 0x08a5, 1, -1, 0x00, "control register A"}, - {"usart5.ctrlb", 0x08a6, 1, -1, 0x00, "control register B"}, - {"usart5.ctrlc", 0x08a7, 1, -1, 0x03, "control register C"}, - {"usart5.baud", 0x08a8, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart5.ctrld", 0x08aa, 1, -1, 0x00, "control register D"}, - {"usart5.dbgctrl", 0x08ab, 1, -1, 0x00, "debug control register"}, - {"usart5.evctrl", 0x08ac, 1, -1, 0x00, "event control register"}, - {"usart5.txplctrl", 0x08ad, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart5.rxplctrl", 0x08ae, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, - {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, - {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, - {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, - {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, - {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, - {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, - {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, - {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, - {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, - {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, - {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, - {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, - {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, - {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, - {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, - {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, - {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, - {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, - {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, - {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, - {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, - {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, - {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, - {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, - {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, - {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, - {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, - {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, - {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, - {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, - {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, - {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb4.ctrla", 0x0b40, 1, -1, 0x00, "control register A"}, - {"tcb4.ctrlb", 0x0b41, 1, -1, 0x00, "control register B"}, - {"tcb4.evctrl", 0x0b44, 1, -1, 0x00, "event control register"}, - {"tcb4.intctrl", 0x0b45, 1, -1, 0x00, "interrupt control register"}, - {"tcb4.intflags", 0x0b46, 1, -1, 0x00, "interrupt flags register"}, - {"tcb4.status", 0x0b47, 1, -1, 0x00, "status register"}, - {"tcb4.dbgctrl", 0x0b48, 1, -1, 0x00, "debug control register"}, - {"tcb4.temp", 0x0b49, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb4.cnt", 0x0b4a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb4.ccmp", 0x0b4c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - // AVR128DA28 AVR128DA28S const Register_file rgftab_avr128da28[433] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -56030,472 +47686,6 @@ const Register_file rgftab_avr128da28[433] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR128DB28 -const Register_file rgftab_avr128db28[462] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - // AVR128DA32 AVR128DA32S const Register_file rgftab_avr128da32[448] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -56948,487 +48138,6 @@ const Register_file rgftab_avr128da32[448] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR128DB32 -const Register_file rgftab_avr128db32[477] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, - {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, - {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, - {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, - {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, - {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, - {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, - {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, - {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, - {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, - {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, - {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, - {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, - {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, - {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - // AVR128DA48 AVR128DA48S const Register_file rgftab_avr128da48[601] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -58034,653 +48743,6 @@ const Register_file rgftab_avr128da48[601] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; -// AVR128DB48 -const Register_file rgftab_avr128db48[643] = { // I/O memory [0, 4159] - {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, - {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, - {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, - {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, - {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, - {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, - {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, - {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, - {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, - {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, - {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, - {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, - {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, - {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, - {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, - {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, - {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, - {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, - {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, - {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, - {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, - {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, - {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, - {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, - {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, - {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, - {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, - {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, - {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, - {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, - {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, - {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, - {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, - {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, - {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, - {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, - {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, - {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, - {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, - {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, - {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, - {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, - {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, - {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, - {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, - {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, - {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, - {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, - {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, - {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, - {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, - {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, - {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, - {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, - {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, - {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, - {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, - {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, - {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, - {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, - {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, - {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, - {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, - {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, - {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, - {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, - {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, - {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, - {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, - {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, - {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, - {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, - {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, - {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, - {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, - {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, - {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, - {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, - {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, - {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, - {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, - {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, - {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, - {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, - {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, - {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, - {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, - {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, - {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, - {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, - {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, - {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, - {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, - {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, - {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, - {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, - {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, - {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, - {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, - {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, - {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, - {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, - {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, - {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, - {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, - {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, - {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, - {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, - {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, - {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, - {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, - {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, - {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, - {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, - {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, - {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, - {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, - {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, - {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, - {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, - {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, - {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, - {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, - {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, - {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, - {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, - {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, - {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, - {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, - {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, - {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, - {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, - {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, - {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, - {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, - {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, - {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, - {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, - {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, - {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, - {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, - {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, - {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, - {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, - {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, - {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, - {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, - {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, - {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, - {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, - {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, - {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, - {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, - {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, - {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, - {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, - {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, - {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, - {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, - {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, - {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, - {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, - {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, - {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, - {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, - {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, - {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, - {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, - {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, - {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, - {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, - {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, - {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, - {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, - {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, - {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, - {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, - {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, - {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, - {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, - {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, - {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, - {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, - {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, - {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, - {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, - {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, - {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, - {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, - {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, - {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, - {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, - {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, - {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, - {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, - {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, - {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, - {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, - {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, - {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, - {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, - {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, - {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, - {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, - {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, - {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, - {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, - {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, - {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, - {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, - {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, - {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, - {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, - {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, - {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, - {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, - {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, - {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, - {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, - {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, - {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, - {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, - {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, - {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, - {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, - {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, - {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, - {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, - {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, - {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, - {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, - {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, - {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, - {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, - {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, - {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, - {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, - {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, - {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, - {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, - {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, - {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, - {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, - {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, - {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, - {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, - {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, - {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, - {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, - {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, - {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, - {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, - {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, - {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, - {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, - {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, - {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, - {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, - {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, - {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, - {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, - {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, - {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, - {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, - {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, - {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, - {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, - {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, - {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, - {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, - {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, - {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, - {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, - {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, - {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, - {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, - {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, - {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, - {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, - {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, - {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, - {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, - {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, - {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, - {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, - {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, - {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, - {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, - {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, - {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, - {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, - {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, - {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, - {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, - {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, - {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, - {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, - {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, - {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, - {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, - {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, - {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, - {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, - {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, - {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, - {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, - {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, - {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, - {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, - {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, - {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, - {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, - {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, - {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, - {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, - {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, - {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, - {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, - {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, - {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, - {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, - {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, - {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, - {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, - {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, - {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, - {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, - {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, - {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, - {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, - {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, - {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, - {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, - {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, - {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, - {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, - {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, - {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, - {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, - {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, - {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, - {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, - {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, - {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, - {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, - {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, - {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, - {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, - {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, - {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, - {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, - {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, - {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, - {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, - {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, - {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, - {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, - {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, - {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, - {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, - {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, - {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, - {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, - {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, - {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, - {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, - {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, - {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, - {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, - {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, - {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, - {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, - {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, - {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, - {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, - {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, - {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, - {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, - {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, - {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, - {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, - {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, - {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, - {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, - {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, - {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, - {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, - {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, - {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, - {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, - {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, - {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, - {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, - {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, - {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, - {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, - {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, - {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, - {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, - {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, - {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, - {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, - {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, - {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, - {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, - {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, - {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, - {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, - {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, - {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, - {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, - {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, - {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, - {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, - {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, - {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, - {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, - {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, - {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, - {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, - {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, - {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, - {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, - {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, - {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, - {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, - {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, - {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, - {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, - {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, - {"usart3.status", 0x0864, 1, -1, 0x20, "status register"}, - {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, - {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, - {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, - {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, - {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, - {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, - {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, - {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, - {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, - {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, - {"usart4.status", 0x0884, 1, -1, 0x20, "status register"}, - {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, - {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, - {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, - {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, - {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, - {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, - {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, - {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, - {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, - {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, - {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, - {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, - {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, - {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, - {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, - {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, - {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, - {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, - {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, - {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, - {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, - {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, - {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, - {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, - {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, - {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, - {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, - {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, - {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, - {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, - {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, - {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, - {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, - {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, - {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, - {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, - {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, - {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, - {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, - {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, - {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, - {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, - {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, - {"spi0.data", 0x0944, 1, -1, -1, "data register"}, - {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, - {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, - {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, - {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, - {"spi1.data", 0x0964, 1, -1, -1, "data register"}, - {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, - {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, - {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, - {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, - {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, - {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, - {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, - {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, - {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, - {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, - {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, - {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, - {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, - {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, - {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, - {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, - {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, - {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, - {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, - {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, - {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, - {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, - {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, - {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, - {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, - {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, - {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, - {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, - {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, - {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, - {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, - {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, - {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, - {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, - {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, - {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, - {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, - {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, - {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, - {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, - {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, - {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, - {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, - {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, - {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, - {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, - {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, - {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, - {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, - {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, - {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, - {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, - {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, - {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, - {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, - {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, - {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, - {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, - {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, - {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, - {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, - {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, - {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, - {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, - {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, - {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, - {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, - {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, - {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, - {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, - {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, - {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, - {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, - {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, - {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, - {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, - {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, - {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, - {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, - {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, - {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, - {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, - {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, - {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, - {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, - {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, - {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, - {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, - {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, - {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, - {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, - {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, - {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, - {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, - {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, - {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, - {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, - {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, - {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, - {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, - {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, - {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, - {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, - {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, - {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, - {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, - {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, - {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, - {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, - {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, - {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, - {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, - {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, - {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, - {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, - {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, -}; - // AVR128DA64 AVR128DA64S const Register_file rgftab_avr128da64[659] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, @@ -59344,6 +49406,3892 @@ const Register_file rgftab_avr128da64[659] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; +// AVR32DB28 AVR64DB28 +const Register_file rgftab_avr32db28[461] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DB32 AVR64DB32 +const Register_file rgftab_avr32db32[476] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR32DB48 AVR64DB48 +const Register_file rgftab_avr32db48[642] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, + {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, + {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, + {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, + {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, + {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, + {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, + {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, + {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, + {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, + {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x20, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x20, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR64DB64 +const Register_file rgftab_avr64db64[697] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"vportg.dir", 0x0018, 1, -1, -1, "data direction register"}, + {"vportg.out", 0x0019, 1, -1, -1, "I/O port output register"}, + {"vportg.in", 0x001a, 1, -1, -1, "I/O port input register"}, + {"vportg.intflags", 0x001b, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userevsysevoutg", 0x0233, 1, -1, 0x00, "user EVOUT port G register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.userusart5irda", 0x0239, 1, -1, 0x00, "user USART 5 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcb4capt", 0x0246, 1, -1, 0x00, "user TCB 4 capture register"}, + {"evsys.usertcb4count", 0x0247, 1, -1, 0x00, "user TCB 4 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, + {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, + {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, + {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portg.dir", 0x04c0, 1, -1, -1, "data direction register"}, + {"portg.dirset", 0x04c1, 1, -1, -1, "data direction set register"}, + {"portg.dirclr", 0x04c2, 1, -1, -1, "data direction clear register"}, + {"portg.dirtgl", 0x04c3, 1, -1, -1, "data direction toggle register"}, + {"portg.out", 0x04c4, 1, -1, -1, "I/O port output register"}, + {"portg.outset", 0x04c5, 1, -1, -1, "I/O port output set register"}, + {"portg.outclr", 0x04c6, 1, -1, -1, "I/O port output clear register"}, + {"portg.outtgl", 0x04c7, 1, -1, -1, "I/O port output toggle register"}, + {"portg.in", 0x04c8, 1, -1, -1, "I/O port input register"}, + {"portg.intflags", 0x04c9, 1, -1, 0x00, "interrupt flags register"}, + {"portg.portctrl", 0x04ca, 1, -1, 0x00, "port control register"}, + {"portg.pinconfig", 0x04cb, 1, -1, 0x00, "pin control config register"}, + {"portg.pinctrlupd", 0x04cc, 1, -1, 0x00, "pin control update register"}, + {"portg.pinctrlset", 0x04cd, 1, -1, 0x00, "pin control set register"}, + {"portg.pinctrlclr", 0x04ce, 1, -1, 0x00, "pin control clear register"}, + {"portg.pin0ctrl", 0x04d0, 1, -1, 0x00, "pin 0 control register"}, + {"portg.pin1ctrl", 0x04d1, 1, -1, 0x00, "pin 1 control register"}, + {"portg.pin2ctrl", 0x04d2, 1, -1, 0x00, "pin 2 control register"}, + {"portg.pin3ctrl", 0x04d3, 1, -1, 0x00, "pin 3 control register"}, + {"portg.pin4ctrl", 0x04d4, 1, -1, 0x00, "pin 4 control register"}, + {"portg.pin5ctrl", 0x04d5, 1, -1, 0x00, "pin 5 control register"}, + {"portg.pin6ctrl", 0x04d6, 1, -1, 0x00, "pin 6 control register"}, + {"portg.pin7ctrl", 0x04d7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, + {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, + {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, + {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, + {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, + {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, + {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, + {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x20, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x20, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart5.rxdatal", 0x08a0, 1, -1, 0x00, "receive data low byte"}, + {"usart5.rxdatah", 0x08a1, 1, -1, 0x00, "receive data high byte"}, + {"usart5.txdatal", 0x08a2, 1, -1, 0x00, "transmit data low byte"}, + {"usart5.txdatah", 0x08a3, 1, -1, 0x00, "transmit data high byte"}, + {"usart5.status", 0x08a4, 1, -1, 0x20, "status register"}, + {"usart5.ctrla", 0x08a5, 1, -1, 0x00, "control register A"}, + {"usart5.ctrlb", 0x08a6, 1, -1, 0x00, "control register B"}, + {"usart5.ctrlc", 0x08a7, 1, -1, 0x03, "control register C"}, + {"usart5.baud", 0x08a8, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart5.ctrld", 0x08aa, 1, -1, 0x00, "control register D"}, + {"usart5.dbgctrl", 0x08ab, 1, -1, 0x00, "debug control register"}, + {"usart5.evctrl", 0x08ac, 1, -1, 0x00, "event control register"}, + {"usart5.txplctrl", 0x08ad, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart5.rxplctrl", 0x08ae, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb4.ctrla", 0x0b40, 1, -1, 0x00, "control register A"}, + {"tcb4.ctrlb", 0x0b41, 1, -1, 0x00, "control register B"}, + {"tcb4.evctrl", 0x0b44, 1, -1, 0x00, "event control register"}, + {"tcb4.intctrl", 0x0b45, 1, -1, 0x00, "interrupt control register"}, + {"tcb4.intflags", 0x0b46, 1, -1, 0x00, "interrupt flags register"}, + {"tcb4.status", 0x0b47, 1, -1, 0x00, "status register"}, + {"tcb4.dbgctrl", 0x0b48, 1, -1, 0x00, "debug control register"}, + {"tcb4.temp", 0x0b49, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb4.cnt", 0x0b4a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb4.ccmp", 0x0b4c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR128DB28 +const Register_file rgftab_avr128db28[462] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR128DB32 +const Register_file rgftab_avr128db32[477] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR128DB48 +const Register_file rgftab_avr128db48[643] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, -1, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, -1, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, -1, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, -1, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, -1, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, -1, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.rampz", 0x003b, 1, -1, 0x00, "extended Z register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.channel6", 0x0216, 1, -1, 0x00, "multiplexer channel 6 register"}, + {"evsys.channel7", 0x0217, 1, -1, 0x00, "multiplexer channel 7 register"}, + {"evsys.channel8", 0x0218, 1, -1, 0x00, "multiplexer channel 8 register"}, + {"evsys.channel9", 0x0219, 1, -1, 0x00, "multiplexer channel 9 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x022d, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022e, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x0231, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x0232, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0234, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0235, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0236, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.userusart3irda", 0x0237, 1, -1, 0x00, "user USART 3 IrDA event register"}, + {"evsys.userusart4irda", 0x0238, 1, -1, 0x00, "user USART 4 IrDA event register"}, + {"evsys.usertca0cnta", 0x023a, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x023b, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x023c, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x023d, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x023e, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x023f, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0240, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0241, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0242, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0243, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x0244, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x0245, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x0248, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0249, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.useropamp0enable", 0x024a, 1, -1, 0x00, "user OPAMP 0 enable register"}, + {"evsys.useropamp0disable", 0x024b, 1, -1, 0x00, "user OPAMP 0 disable register"}, + {"evsys.useropamp0dump", 0x024c, 1, -1, 0x00, "user OPAMP 0 dump register"}, + {"evsys.useropamp0drive", 0x024d, 1, -1, 0x00, "user OPAMP 0 drive register"}, + {"evsys.useropamp1enable", 0x024e, 1, -1, 0x00, "user OPAMP 1 enable register"}, + {"evsys.useropamp1disable", 0x024f, 1, -1, 0x00, "user OPAMP 1 disable register"}, + {"evsys.useropamp1dump", 0x0250, 1, -1, 0x00, "user OPAMP 1 dump register"}, + {"evsys.useropamp1drive", 0x0251, 1, -1, 0x00, "user OPAMP 1 drive register"}, + {"evsys.useropamp2enable", 0x0252, 1, -1, 0x00, "user OPAMP 2 enable register"}, + {"evsys.useropamp2disable", 0x0253, 1, -1, 0x00, "user OPAMP 2 disable register"}, + {"evsys.useropamp2dump", 0x0254, 1, -1, 0x00, "user OPAMP 2 dump register"}, + {"evsys.useropamp2drive", 0x0255, 1, -1, 0x00, "user OPAMP 2 drive register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portb.dir", 0x0420, 1, -1, -1, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, -1, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, -1, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, -1, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, -1, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, -1, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, -1, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, -1, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, -1, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"porte.dir", 0x0480, 1, -1, -1, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, -1, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, -1, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, -1, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, -1, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, -1, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, -1, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, -1, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, -1, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e4, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e5, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e6, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e7, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e8, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05e9, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05ea, 1, -1, 0x00, "ZCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd1.ctrla", 0x06c8, 1, -1, 0x00, "control register A"}, + {"zcd1.intctrl", 0x06ca, 1, -1, 0x00, "interrupt control register"}, + {"zcd1.status", 0x06cb, 1, -1, 0x00, "status register"}, + {"zcd2.ctrla", 0x06d0, 1, -1, 0x00, "control register A"}, + {"zcd2.intctrl", 0x06d2, 1, -1, 0x00, "interrupt control register"}, + {"zcd2.status", 0x06d3, 1, -1, 0x00, "status register"}, + {"opamp.ctrla", 0x0700, 1, -1, 0x00, "control register A"}, + {"opamp.dbgctrl", 0x0701, 1, -1, 0x00, "debug control register"}, + {"opamp.timebase", 0x0702, 1, -1, 0x01, "timebase register"}, + {"opamp.pwrctrl", 0x070f, 1, -1, 0x00, "power control register"}, + {"opamp.op0ctrla", 0x0710, 1, -1, 0x00, "op amp 0 control A register"}, + {"opamp.op0status", 0x0711, 1, -1, 0x00, "op amp 0 status register"}, + {"opamp.op0resmux", 0x0712, 1, -1, 0x00, "op amp 0 resistor ladder multiplexer register"}, + {"opamp.op0inmux", 0x0713, 1, -1, 0x00, "op amp 0 input multiplexer register"}, + {"opamp.op0settle", 0x0714, 1, -1, 0x00, "op amp 0 settle register"}, + {"opamp.op0cal", 0x0715, 1, -1, -1, "op amp 0 calibration register"}, + {"opamp.op1ctrla", 0x0718, 1, -1, 0x00, "op amp 1 control A register"}, + {"opamp.op1status", 0x0719, 1, -1, 0x00, "op amp 1 status register"}, + {"opamp.op1resmux", 0x071a, 1, -1, 0x00, "op amp 1 resistor ladder multiplexer register"}, + {"opamp.op1inmux", 0x071b, 1, -1, 0x00, "op amp 1 input multiplexer register"}, + {"opamp.op1settle", 0x071c, 1, -1, 0x00, "op amp 1 settle register"}, + {"opamp.op1cal", 0x071d, 1, -1, -1, "op amp 1 calibration register"}, + {"opamp.op2ctrla", 0x0720, 1, -1, 0x00, "op amp 2 control A register"}, + {"opamp.op2status", 0x0721, 1, -1, 0x00, "op amp 2 status register"}, + {"opamp.op2resmux", 0x0722, 1, -1, 0x00, "op amp 2 resistor ladder multiplexer register"}, + {"opamp.op2inmux", 0x0723, 1, -1, 0x00, "op amp 2 input multiplexer register"}, + {"opamp.op2settle", 0x0724, 1, -1, 0x00, "op amp 2 settle register"}, + {"opamp.op2cal", 0x0725, 1, -1, -1, "op amp 2 calibration register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart3.rxdatal", 0x0860, 1, -1, 0x00, "receive data low byte"}, + {"usart3.rxdatah", 0x0861, 1, -1, 0x00, "receive data high byte"}, + {"usart3.txdatal", 0x0862, 1, -1, 0x00, "transmit data low byte"}, + {"usart3.txdatah", 0x0863, 1, -1, 0x00, "transmit data high byte"}, + {"usart3.status", 0x0864, 1, -1, 0x20, "status register"}, + {"usart3.ctrla", 0x0865, 1, -1, 0x00, "control register A"}, + {"usart3.ctrlb", 0x0866, 1, -1, 0x00, "control register B"}, + {"usart3.ctrlc", 0x0867, 1, -1, 0x03, "control register C"}, + {"usart3.baud", 0x0868, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart3.ctrld", 0x086a, 1, -1, 0x00, "control register D"}, + {"usart3.dbgctrl", 0x086b, 1, -1, 0x00, "debug control register"}, + {"usart3.evctrl", 0x086c, 1, -1, 0x00, "event control register"}, + {"usart3.txplctrl", 0x086d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart3.rxplctrl", 0x086e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart4.rxdatal", 0x0880, 1, -1, 0x00, "receive data low byte"}, + {"usart4.rxdatah", 0x0881, 1, -1, 0x00, "receive data high byte"}, + {"usart4.txdatal", 0x0882, 1, -1, 0x00, "transmit data low byte"}, + {"usart4.txdatah", 0x0883, 1, -1, 0x00, "transmit data high byte"}, + {"usart4.status", 0x0884, 1, -1, 0x20, "status register"}, + {"usart4.ctrla", 0x0885, 1, -1, 0x00, "control register A"}, + {"usart4.ctrlb", 0x0886, 1, -1, 0x00, "control register B"}, + {"usart4.ctrlc", 0x0887, 1, -1, 0x03, "control register C"}, + {"usart4.baud", 0x0888, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart4.ctrld", 0x088a, 1, -1, 0x00, "control register D"}, + {"usart4.dbgctrl", 0x088b, 1, -1, 0x00, "debug control register"}, + {"usart4.evctrl", 0x088c, 1, -1, 0x00, "event control register"}, + {"usart4.txplctrl", 0x088d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart4.rxplctrl", 0x088e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f18, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f19, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + // AVR128DB64 const Register_file rgftab_avr128db64[698] = { // I/O memory [0, 4159] {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, @@ -60046,181 +53994,6069 @@ const Register_file rgftab_avr128db64[698] = { // I/O memory [0, 4159] {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, }; +// AVR16DD14 AVR32DD14 AVR64DD14 +const Register_file rgftab_avr16dd14[390] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR16DD20 AVR32DD20 AVR64DD20 +const Register_file rgftab_avr16dd20[391] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR16DD28 AVR16DD32 AVR32DD28 AVR32DD32 AVR64DD28 AVR64DD32 +const Register_file rgftab_avr16dd28[401] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, -1, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, -1, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, -1, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, -1, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, -1, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, -1, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, -1, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, -1, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, -1, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, -1, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, -1, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, -1, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, -1, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.adc0ref", 0x00b0, 1, -1, 0x00, "ADC 0 reference register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"mvio.intctrl", 0x00c0, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x00c1, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x00c2, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.sweventb", 0x0201, 1, -1, 0x00, "software event B register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x022e, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x022f, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0230, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0231, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0232, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0233, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0234, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x0235, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x0236, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcd0inputa", 0x0237, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0238, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"porta.dir", 0x0400, 1, -1, -1, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, -1, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, -1, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, -1, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, -1, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, -1, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, -1, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, -1, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, -1, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"portc.dir", 0x0440, 1, -1, -1, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, -1, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, -1, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, -1, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, -1, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, -1, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, -1, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, -1, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, -1, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portd.dir", 0x0460, 1, -1, -1, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, -1, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, -1, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, -1, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, -1, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, -1, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, -1, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, -1, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, -1, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portf.dir", 0x04a0, 1, -1, -1, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, -1, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, -1, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, -1, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, -1, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, -1, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, -1, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, -1, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, -1, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.sampctrl", 0x0605, 1, -1, 0x00, "sample control register"}, + {"adc0.muxpos", 0x0608, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x0609, 1, -1, 0x00, "negative mux input register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.evctrl", 0x060b, 1, -1, 0x00, "event control register"}, + {"adc0.intctrl", 0x060c, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x060d, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.dbgctrl", 0x060e, 1, -1, 0x00, "debug control register"}, + {"adc0.temp", 0x060f, 1, -1, 0x00, "temporary data register"}, + {"adc0.res", 0x0610, 2, -1, -1, "ADC accumulator result register (16 bits)"}, + {"adc0.winlt", 0x0612, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0614, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.status", 0x1002, 1, -1, 0x00, "status register"}, + {"nvmctrl.intctrl", 0x1003, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1004, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.data", 0x1006, 2, -1, -1, "data register (16 bits)"}, + {"nvmctrl.addr", 0x1008, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR16DU14 AVR32DU14 +const Register_file rgftab_avr16du14[370] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.oschfstatus", 0x006a, 1, -1, -1, "OSCHF status register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"clkctrl.usbpllstatus", 0x0085, 1, -1, 0x00, "PLL status register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.acref", 0x00b0, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutd", 0x022a, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022b, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022c, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x022d, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x022e, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x022f, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"usb0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, + {"usb0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, + {"usb0.busstate", 0x0c02, 1, -1, 0x00, "bus state register"}, + {"usb0.addr", 0x0c03, 1, -1, 0x00, "address register"}, + {"usb0.fifowp", 0x0c04, 1, -1, 0xff, "FIFO write pointer register"}, + {"usb0.fiforp", 0x0c05, 1, -1, 0xff, "FIFO read pointer register"}, + {"usb0.epptr", 0x0c06, 2, -1, 0x0000, "endpoint configuration table pointer register (16 bits)"}, + {"usb0.intctrla", 0x0c08, 1, -1, 0x00, "interrupt control register A"}, + {"usb0.intctrlb", 0x0c09, 1, -1, 0x00, "interrupt control register B"}, + {"usb0.intflagsa", 0x0c0a, 1, -1, 0x00, "interrupt flags A register"}, + {"usb0.intflagsb", 0x0c0b, 1, -1, 0x00, "interrupt flags B register"}, + {"usb.status.outclr", 0x0c40, 1, -1, 0x00, "endpoint n OUT status clear register"}, + {"usb.status.outset", 0x0c41, 1, -1, 0x00, "endpoint n OUT status set register"}, + {"usb.status.inclr", 0x0c42, 1, -1, 0x00, "endpoint n IN status clear register"}, + {"usb.status.inset", 0x0c43, 1, -1, 0x00, "endpoint n IN status set register"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.vusbctrl", 0x0f06, 1, -1, 0x00, "USB voltage system control register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 +const Register_file rgftab_avr16du20[371] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.vregctrl", 0x0051, 1, -1, 0x00, "control B register"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, -1, "OSCHF tune register"}, + {"clkctrl.oschfstatus", 0x006a, 1, -1, -1, "OSCHF status register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"clkctrl.usbpllstatus", 0x0085, 1, -1, 0x00, "PLL status register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.acref", 0x00b0, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutd", 0x022a, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022b, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022c, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x022d, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x022e, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x022f, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"usb0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, + {"usb0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, + {"usb0.busstate", 0x0c02, 1, -1, 0x00, "bus state register"}, + {"usb0.addr", 0x0c03, 1, -1, 0x00, "address register"}, + {"usb0.fifowp", 0x0c04, 1, -1, 0xff, "FIFO write pointer register"}, + {"usb0.fiforp", 0x0c05, 1, -1, 0xff, "FIFO read pointer register"}, + {"usb0.epptr", 0x0c06, 2, -1, 0x0000, "endpoint configuration table pointer register (16 bits)"}, + {"usb0.intctrla", 0x0c08, 1, -1, 0x00, "interrupt control register A"}, + {"usb0.intctrlb", 0x0c09, 1, -1, 0x00, "interrupt control register B"}, + {"usb0.intflagsa", 0x0c0a, 1, -1, 0x00, "interrupt flags A register"}, + {"usb0.intflagsb", 0x0c0b, 1, -1, 0x00, "interrupt flags B register"}, + {"usb.status.outclr", 0x0c40, 1, -1, 0x00, "endpoint n OUT status clear register"}, + {"usb.status.outset", 0x0c41, 1, -1, 0x00, "endpoint n OUT status set register"}, + {"usb.status.inclr", 0x0c42, 1, -1, 0x00, "endpoint n IN status clear register"}, + {"usb.status.inset", 0x0c43, 1, -1, 0x00, "endpoint n IN status set register"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.vusbctrl", 0x0f06, 1, -1, 0x00, "USB voltage system control register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, +}; + +// AVR16EA28 AVR16EA32 AVR32EA28 AVR32EA32 AVR64EA28 AVR64EA32 +const Register_file rgftab_avr16ea28[444] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022b, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022c, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022e, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022f, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0230, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0231, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x0232, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0233, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x0234, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x0235, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x0236, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0237, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0238, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0239, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023a, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023b, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023c, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023d, 1, -1, 0x00, "user TCB 3 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16EA48 AVR32EA48 AVR64EA48 +const Register_file rgftab_avr16ea48[502] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportb.dir", 0x0004, 1, -1, 0x00, "data direction register"}, + {"vportb.out", 0x0005, 1, -1, 0x00, "I/O port output register"}, + {"vportb.in", 0x0006, 1, -1, 0x00, "I/O port input register"}, + {"vportb.intflags", 0x0007, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vporte.dir", 0x0010, 1, -1, 0x00, "data direction register"}, + {"vporte.out", 0x0011, 1, -1, 0x00, "I/O port output register"}, + {"vporte.in", 0x0012, 1, -1, 0x00, "I/O port input register"}, + {"vporte.intflags", 0x0013, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0062, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0063, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0064, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x0080, 1, -1, 0x00, "XOSC HF control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutb", 0x022a, 1, -1, 0x00, "user EVOUT port B register"}, + {"evsys.userevsysevoutc", 0x022b, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022c, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoute", 0x022d, 1, -1, 0x00, "user EVOUT port E register"}, + {"evsys.userevsysevoutf", 0x022e, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022f, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0230, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0231, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x0232, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0233, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertca1cnta", 0x0234, 1, -1, 0x00, "user TCA 1 event A register"}, + {"evsys.usertca1cntb", 0x0235, 1, -1, 0x00, "user TCA 1 event B register"}, + {"evsys.usertcb0capt", 0x0236, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0237, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0238, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0239, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023a, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023b, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023c, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023d, 1, -1, 0x00, "user TCB 3 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portb.dir", 0x0420, 1, -1, 0x00, "data direction register"}, + {"portb.dirset", 0x0421, 1, -1, 0x00, "data direction set register"}, + {"portb.dirclr", 0x0422, 1, -1, 0x00, "data direction clear register"}, + {"portb.dirtgl", 0x0423, 1, -1, 0x00, "data direction toggle register"}, + {"portb.out", 0x0424, 1, -1, 0x00, "I/O port output register"}, + {"portb.outset", 0x0425, 1, -1, 0x00, "I/O port output set register"}, + {"portb.outclr", 0x0426, 1, -1, 0x00, "I/O port output clear register"}, + {"portb.outtgl", 0x0427, 1, -1, 0x00, "I/O port output toggle register"}, + {"portb.in", 0x0428, 1, -1, 0x00, "I/O port input register"}, + {"portb.intflags", 0x0429, 1, -1, 0x00, "interrupt flags register"}, + {"portb.portctrl", 0x042a, 1, -1, 0x00, "port control register"}, + {"portb.pinconfig", 0x042b, 1, -1, 0x00, "pin control config register"}, + {"portb.pinctrlupd", 0x042c, 1, -1, 0x00, "pin control update register"}, + {"portb.pinctrlset", 0x042d, 1, -1, 0x00, "pin control set register"}, + {"portb.pinctrlclr", 0x042e, 1, -1, 0x00, "pin control clear register"}, + {"portb.pin0ctrl", 0x0430, 1, -1, 0x00, "pin 0 control register"}, + {"portb.pin1ctrl", 0x0431, 1, -1, 0x00, "pin 1 control register"}, + {"portb.pin2ctrl", 0x0432, 1, -1, 0x00, "pin 2 control register"}, + {"portb.pin3ctrl", 0x0433, 1, -1, 0x00, "pin 3 control register"}, + {"portb.pin4ctrl", 0x0434, 1, -1, 0x00, "pin 4 control register"}, + {"portb.pin5ctrl", 0x0435, 1, -1, 0x00, "pin 5 control register"}, + {"portb.pin6ctrl", 0x0436, 1, -1, 0x00, "pin 6 control register"}, + {"portb.pin7ctrl", 0x0437, 1, -1, 0x00, "pin 7 control register"}, + {"portb.evgenctrla", 0x0438, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"porte.dir", 0x0480, 1, -1, 0x00, "data direction register"}, + {"porte.dirset", 0x0481, 1, -1, 0x00, "data direction set register"}, + {"porte.dirclr", 0x0482, 1, -1, 0x00, "data direction clear register"}, + {"porte.dirtgl", 0x0483, 1, -1, 0x00, "data direction toggle register"}, + {"porte.out", 0x0484, 1, -1, 0x00, "I/O port output register"}, + {"porte.outset", 0x0485, 1, -1, 0x00, "I/O port output set register"}, + {"porte.outclr", 0x0486, 1, -1, 0x00, "I/O port output clear register"}, + {"porte.outtgl", 0x0487, 1, -1, 0x00, "I/O port output toggle register"}, + {"porte.in", 0x0488, 1, -1, 0x00, "I/O port input register"}, + {"porte.intflags", 0x0489, 1, -1, 0x00, "interrupt flags register"}, + {"porte.portctrl", 0x048a, 1, -1, 0x00, "port control register"}, + {"porte.pinconfig", 0x048b, 1, -1, 0x00, "pin control config register"}, + {"porte.pinctrlupd", 0x048c, 1, -1, 0x00, "pin control update register"}, + {"porte.pinctrlset", 0x048d, 1, -1, 0x00, "pin control set register"}, + {"porte.pinctrlclr", 0x048e, 1, -1, 0x00, "pin control clear register"}, + {"porte.pin0ctrl", 0x0490, 1, -1, 0x00, "pin 0 control register"}, + {"porte.pin1ctrl", 0x0491, 1, -1, 0x00, "pin 1 control register"}, + {"porte.pin2ctrl", 0x0492, 1, -1, 0x00, "pin 2 control register"}, + {"porte.pin3ctrl", 0x0493, 1, -1, 0x00, "pin 3 control register"}, + {"porte.pin4ctrl", 0x0494, 1, -1, 0x00, "pin 4 control register"}, + {"porte.pin5ctrl", 0x0495, 1, -1, 0x00, "pin 5 control register"}, + {"porte.pin6ctrl", 0x0496, 1, -1, 0x00, "pin 6 control register"}, + {"porte.pin7ctrl", 0x0497, 1, -1, 0x00, "pin 7 control register"}, + {"porte.evgenctrla", 0x0498, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tca1.ctrla", 0x0a40, 1, -1, 0x00, "control register A"}, + {"tca1.ctrlb", 0x0a41, 1, -1, 0x00, "control register B"}, + {"tca1.ctrlc", 0x0a42, 1, -1, 0x00, "control register C"}, + {"tca1.ctrld", 0x0a43, 1, -1, 0x00, "control register D"}, + {"tca1.ctrleclr", 0x0a44, 1, -1, 0x00, "control register E clear"}, + {"tca1.ctrleset", 0x0a45, 1, -1, 0x00, "control register E set"}, + {"tca1.ctrlfclr", 0x0a46, 1, -1, 0x00, "control register F clear"}, + {"tca1.ctrlfset", 0x0a47, 1, -1, 0x00, "control register F set"}, + {"tca1.evctrl", 0x0a49, 1, -1, 0x00, "event control register"}, + {"tca1.intctrl", 0x0a4a, 1, -1, 0x00, "interrupt control register"}, + {"tca1.intflags", 0x0a4b, 1, -1, 0x00, "interrupt flags register"}, + {"tca1.dbgctrl", 0x0a4e, 1, -1, 0x00, "debug control register"}, + {"tca1.temp", 0x0a4f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca1.cnt", 0x0a60, 2, -1, -1, "counter (16 bits)"}, + {"tca1.lcnt", 0x0a60, 1, -1, -1, "low byte counter"}, + {"tca1.hcnt", 0x0a61, 1, -1, -1, "high byte counter"}, + {"tca1.per", 0x0a66, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca1.lper", 0x0a66, 1, -1, 0xff, "low byte period register"}, + {"tca1.hper", 0x0a67, 1, -1, 0xff, "high byte period register"}, + {"tca1.cmp0", 0x0a68, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca1.lcmp0", 0x0a68, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp0", 0x0a69, 1, -1, -1, "high byte compare register 0"}, + {"tca1.cmp1", 0x0a6a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca1.lcmp1", 0x0a6a, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp1", 0x0a6b, 1, -1, -1, "high byte compare register 1"}, + {"tca1.cmp2", 0x0a6c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca1.lcmp2", 0x0a6c, 1, -1, -1, "low byte compare register"}, + {"tca1.hcmp2", 0x0a6d, 1, -1, -1, "high byte compare register 2"}, + {"tca1.perbuf", 0x0a76, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca1.cmp0buf", 0x0a78, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca1.cmp1buf", 0x0a7a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca1.cmp2buf", 0x0a7c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.ocdmctrl", 0x0f04, 1, -1, -1, "OCD message control register"}, + {"syscfg.ocdmstatus", 0x0f05, 1, -1, 0x00, "OCD message status register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16EB14 AVR32EB14 +const Register_file rgftab_avr16eb14[390] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.pllctrlb", 0x0071, 1, -1, 0x00, "PLL control B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.usertce0cnta", 0x022e, 1, -1, 0x00, "user TCE 0 event A register"}, + {"evsys.usertce0cntb", 0x022f, 1, -1, 0x00, "user TCE 0 event B register"}, + {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcf0cnt", 0x0234, 1, -1, 0x00, "user TCF 0 clock event register"}, + {"evsys.usertcf0act", 0x0235, 1, -1, 0x00, "user TCF 0 action event register"}, + {"evsys.userwexa", 0x0236, 1, -1, 0x00, "user WEX event A register"}, + {"evsys.userwexb", 0x0237, 1, -1, 0x00, "user WEX event B register"}, + {"evsys.userwexc", 0x0238, 1, -1, 0x00, "user WEX event C register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, + {"portmux.tcfroutea", 0x05ec, 1, -1, 0x00, "TCF route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tce0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, + {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, + {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, + {"tce0.amp", 0x0a22, 2, -1, 0x0000, "amplitude register (16 bits)"}, + {"tce0.offset", 0x0a24, 2, -1, 0x0000, "offset register (16 bits)"}, + {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, + {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, + {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tce0.cmp3", 0x0a2e, 2, -1, 0x0000, "compare 3 register (16 bits)"}, + {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, + {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, + {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tce0.cmp3buf", 0x0a3e, 2, -1, 0x0000, "compare 3 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcf0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, + {"tcf0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, + {"tcf0.ctrlc", 0x0c02, 1, -1, 0x00, "control register C"}, + {"tcf0.ctrld", 0x0c03, 1, -1, 0x00, "control register D"}, + {"tcf0.evctrl", 0x0c04, 1, -1, 0x00, "event control register"}, + {"tcf0.intctrl", 0x0c05, 1, -1, 0x00, "interrupt control register"}, + {"tcf0.intflags", 0x0c06, 1, -1, 0x00, "interrupt flags register"}, + {"tcf0.status", 0x0c07, 1, -1, 0x00, "status register"}, + {"tcf0.dbgctrl", 0x0c0d, 1, -1, 0x00, "debug control register"}, + {"tcf0.cnt", 0x0c10, 4, -1, 0x00000000, "counter (32 bits)"}, + {"tcf0.cmp", 0x0c14, 4, -1, 0x00000000, "compare register (32 bits)"}, + {"wex0.ctrla", 0x0c80, 1, -1, 0x00, "control register A"}, + {"wex0.ctrlb", 0x0c81, 1, -1, 0x00, "control register B"}, + {"wex0.ctrlc", 0x0c82, 1, -1, 0x00, "control register C"}, + {"wex0.evctrla", 0x0c84, 1, -1, 0x00, "event control register A"}, + {"wex0.evctrlb", 0x0c85, 1, -1, 0x00, "event control register B"}, + {"wex0.evctrlc", 0x0c86, 1, -1, 0x00, "event control register C"}, + {"wex0.bufctrl", 0x0c87, 1, -1, 0x00, "buffer valid control register"}, + {"wex0.blankctrl", 0x0c88, 1, -1, 0x00, "blanking control register"}, + {"wex0.blanktime", 0x0c89, 1, -1, 0x00, "blanking time register"}, + {"wex0.faultctrl", 0x0c8a, 1, -1, 0x00, "fault control register"}, + {"wex0.faultdrv", 0x0c8b, 1, -1, 0x00, "fault drive register"}, + {"wex0.faultout", 0x0c8c, 1, -1, 0x00, "fault output register"}, + {"wex0.intctrl", 0x0c8d, 1, -1, 0x00, "interrupt control register"}, + {"wex0.intflags", 0x0c8e, 1, -1, 0x00, "interrupt flags register"}, + {"wex0.status", 0x0c8f, 1, -1, 0x00, "status register"}, + {"wex0.dtls", 0x0c90, 1, -1, 0x00, "dead-time low side register"}, + {"wex0.dths", 0x0c91, 1, -1, 0x00, "dead-time high side register"}, + {"wex0.dtboth", 0x0c92, 1, -1, 0x00, "dead-time both sides register"}, + {"wex0.swap", 0x0c93, 1, -1, 0x00, "DTI swap register"}, + {"wex0.pgmovr", 0x0c94, 1, -1, 0x00, "pattern generation override register"}, + {"wex0.pgmout", 0x0c95, 1, -1, 0x00, "pattern generation output register"}, + {"wex0.outoven", 0x0c97, 1, -1, 0x00, "output override enable register"}, + {"wex0.dtlsbuf", 0x0c98, 1, -1, 0x00, "dead-time low side buffer register"}, + {"wex0.dthsbuf", 0x0c99, 1, -1, 0x00, "dead-time high side buffer register"}, + {"wex0.dtbothbuf", 0x0c9a, 1, -1, 0x00, "dead-time both sides buffer register"}, + {"wex0.swapbuf", 0x0c9b, 1, -1, 0x00, "DTI swap buffer register"}, + {"wex0.pgmovrbuf", 0x0c9c, 1, -1, 0x00, "pattern generation override buffer register"}, + {"wex0.pgmoutbuf", 0x0c9d, 1, -1, 0x00, "pattern generation output buffer register"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB20 AVR32EB28 AVR32EB32 +const Register_file rgftab_avr16eb20[391] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x0070, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.pllctrlb", 0x0071, 1, -1, 0x00, "PLL control B register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x00b2, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.status", 0x0122, 1, -1, 0x02, "status register"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.useradc0start", 0x0228, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0229, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022a, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x022b, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x022c, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x022d, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.usertce0cnta", 0x022e, 1, -1, 0x00, "user TCE 0 event A register"}, + {"evsys.usertce0cntb", 0x022f, 1, -1, 0x00, "user TCE 0 event B register"}, + {"evsys.usertcb0capt", 0x0230, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0231, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0232, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0233, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcf0cnt", 0x0234, 1, -1, 0x00, "user TCF 0 clock event register"}, + {"evsys.usertcf0act", 0x0235, 1, -1, 0x00, "user TCF 0 action event register"}, + {"evsys.userwexa", 0x0236, 1, -1, 0x00, "user WEX event A register"}, + {"evsys.userwexb", 0x0237, 1, -1, 0x00, "user WEX event B register"}, + {"evsys.userwexc", 0x0238, 1, -1, 0x00, "user WEX event C register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcfroutea", 0x05ec, 1, -1, 0x00, "TCF route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.intctrl", 0x0604, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0605, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0606, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0607, 1, -1, 0x00, "debug control register"}, + {"adc0.ctrle", 0x0608, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0609, 1, -1, 0x00, "control register F"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.pgactrl", 0x060b, 1, -1, 0x00, "PGA control register"}, + {"adc0.muxpos", 0x060c, 1, -1, 0x00, "positive mux input register"}, + {"adc0.muxneg", 0x060d, 1, -1, 0x00, "negative mux input register"}, + {"adc0.result", 0x0610, 4, -1, 0x00000000, "result register (32 bits)"}, + {"adc0.sample", 0x0614, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.temp0", 0x0618, 1, -1, 0x00, "temporary data register 0"}, + {"adc0.temp1", 0x0619, 1, -1, 0x00, "temporary data register 1"}, + {"adc0.temp2", 0x061a, 1, -1, 0x00, "temporary data register 2"}, + {"adc0.winlt", 0x061c, 2, -1, 0x0000, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x061e, 2, -1, 0x0000, "window comparator high threshold register (16 bits)"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tce0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, + {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, + {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, + {"tce0.amp", 0x0a22, 2, -1, 0x0000, "amplitude register (16 bits)"}, + {"tce0.offset", 0x0a24, 2, -1, 0x0000, "offset register (16 bits)"}, + {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, + {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, + {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tce0.cmp3", 0x0a2e, 2, -1, 0x0000, "compare 3 register (16 bits)"}, + {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, + {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, + {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tce0.cmp3buf", 0x0a3e, 2, -1, 0x0000, "compare 3 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcf0.ctrla", 0x0c00, 1, -1, 0x00, "control register A"}, + {"tcf0.ctrlb", 0x0c01, 1, -1, 0x00, "control register B"}, + {"tcf0.ctrlc", 0x0c02, 1, -1, 0x00, "control register C"}, + {"tcf0.ctrld", 0x0c03, 1, -1, 0x00, "control register D"}, + {"tcf0.evctrl", 0x0c04, 1, -1, 0x00, "event control register"}, + {"tcf0.intctrl", 0x0c05, 1, -1, 0x00, "interrupt control register"}, + {"tcf0.intflags", 0x0c06, 1, -1, 0x00, "interrupt flags register"}, + {"tcf0.status", 0x0c07, 1, -1, 0x00, "status register"}, + {"tcf0.dbgctrl", 0x0c0d, 1, -1, 0x00, "debug control register"}, + {"tcf0.cnt", 0x0c10, 4, -1, 0x00000000, "counter (32 bits)"}, + {"tcf0.cmp", 0x0c14, 4, -1, 0x00000000, "compare register (32 bits)"}, + {"wex0.ctrla", 0x0c80, 1, -1, 0x00, "control register A"}, + {"wex0.ctrlb", 0x0c81, 1, -1, 0x00, "control register B"}, + {"wex0.ctrlc", 0x0c82, 1, -1, 0x00, "control register C"}, + {"wex0.evctrla", 0x0c84, 1, -1, 0x00, "event control register A"}, + {"wex0.evctrlb", 0x0c85, 1, -1, 0x00, "event control register B"}, + {"wex0.evctrlc", 0x0c86, 1, -1, 0x00, "event control register C"}, + {"wex0.bufctrl", 0x0c87, 1, -1, 0x00, "buffer valid control register"}, + {"wex0.blankctrl", 0x0c88, 1, -1, 0x00, "blanking control register"}, + {"wex0.blanktime", 0x0c89, 1, -1, 0x00, "blanking time register"}, + {"wex0.faultctrl", 0x0c8a, 1, -1, 0x00, "fault control register"}, + {"wex0.faultdrv", 0x0c8b, 1, -1, 0x00, "fault drive register"}, + {"wex0.faultout", 0x0c8c, 1, -1, 0x00, "fault output register"}, + {"wex0.intctrl", 0x0c8d, 1, -1, 0x00, "interrupt control register"}, + {"wex0.intflags", 0x0c8e, 1, -1, 0x00, "interrupt flags register"}, + {"wex0.status", 0x0c8f, 1, -1, 0x00, "status register"}, + {"wex0.dtls", 0x0c90, 1, -1, 0x00, "dead-time low side register"}, + {"wex0.dths", 0x0c91, 1, -1, 0x00, "dead-time high side register"}, + {"wex0.dtboth", 0x0c92, 1, -1, 0x00, "dead-time both sides register"}, + {"wex0.swap", 0x0c93, 1, -1, 0x00, "DTI swap register"}, + {"wex0.pgmovr", 0x0c94, 1, -1, 0x00, "pattern generation override register"}, + {"wex0.pgmout", 0x0c95, 1, -1, 0x00, "pattern generation output register"}, + {"wex0.outoven", 0x0c97, 1, -1, 0x00, "output override enable register"}, + {"wex0.dtlsbuf", 0x0c98, 1, -1, 0x00, "dead-time low side buffer register"}, + {"wex0.dthsbuf", 0x0c99, 1, -1, 0x00, "dead-time high side buffer register"}, + {"wex0.dtbothbuf", 0x0c9a, 1, -1, 0x00, "dead-time both sides buffer register"}, + {"wex0.swapbuf", 0x0c9b, 1, -1, 0x00, "DTI swap buffer register"}, + {"wex0.pgmovrbuf", 0x0c9c, 1, -1, 0x00, "pattern generation override buffer register"}, + {"wex0.pgmoutbuf", 0x0c9d, 1, -1, 0x00, "pattern generation output buffer register"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16LA14 AVR32LA14 +const Register_file rgftab_avr16la14[339] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, + {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x00, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.intctrl", 0x0122, 1, -1, 0x00, "interrupt control register"}, + {"crcscan.intflags", 0x0123, 1, -1, 0x00, "interrupt flags register"}, + {"crcscan.statusa", 0x0124, 1, -1, 0x04, "status A register"}, + {"crcscan.scanadr", 0x0125, 1, -1, 0x00, "scan address register"}, + {"crcscan.data", 0x0126, 1, -1, 0x00, "data register"}, + {"crcscan.crc", 0x0128, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userac0sample", 0x0224, 1, -1, 0x00, "user 4 - AC0 register"}, + {"evsys.useradc0start", 0x0225, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0226, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x0227, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0228, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0229, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0rxd", 0x022a, 1, -1, 0x00, "user 10 - USART0 RxD event input register"}, + {"evsys.usertce0cnta", 0x022b, 1, -1, 0x00, "user TCE 0 event A register"}, + {"evsys.usertce0cntb", 0x022c, 1, -1, 0x00, "user TCE 0 event B register"}, + {"evsys.usertcb0capt", 0x022d, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x022e, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x022f, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0230, 1, -1, 0x00, "user TCB 1 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, 0x0000, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.refscale", 0x0683, 1, -1, 0xff, "reference scaling register"}, + {"ac0.intctrl", 0x0684, 1, -1, 0x00, "interrupt control register"}, + {"ac0.intflags", 0x0685, 1, -1, -1, "interrupt flags register"}, + {"ac0.status", 0x0686, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0800, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0801, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0802, 1, -1, 0x00, "control register C"}, + {"usart0.ctrld", 0x0803, 1, -1, 0x00, "control register D"}, + {"usart0.ctrle", 0x0804, 1, -1, 0x00, "control register E"}, + {"usart0.ctrlf", 0x0805, 1, -1, 0x00, "control register F"}, + {"usart0.ctrlg", 0x0806, 1, -1, 0x00, "control register G"}, + {"usart0.command", 0x0807, 1, -1, 0x00, "command register"}, + {"usart0.evctrl", 0x0809, 1, -1, 0x00, "event control register"}, + {"usart0.baud", 0x080a, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.intctrl", 0x080c, 1, -1, 0x00, "interrupt control register"}, + {"usart0.intflags", 0x080d, 1, -1, 0x01, "interrupt flags register"}, + {"usart0.status", 0x080e, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0810, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0811, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0812, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0813, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.auxdata0", 0x0818, 1, -1, 0x00, "auxiliary data 0 register"}, + {"usart0.auxdata1", 0x0819, 1, -1, 0x00, "auxiliary data 1 register"}, + {"usart0.auxdata2", 0x081a, 1, -1, 0x00, "auxiliary data 2 register"}, + {"usart0.dbgctrl", 0x081f, 1, -1, 0x00, "debug control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, + {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, + {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, + {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, + {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, + {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, + {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, + {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.vddctrl", 0x0f07, 1, -1, 0x01, "VDD range control register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA20 AVR32LA28 AVR32LA32 +const Register_file rgftab_avr16la20[341] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, + {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, 0x00, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"clkctrl.mclkctrla", 0x0060, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0061, 1, -1, 0x11, "MCLK control B register"}, + {"clkctrl.mclkstatus", 0x0065, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0066, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.oschfctrla", 0x0068, 1, -1, 0x00, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x0069, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.osc32kctrla", 0x0078, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x007c, 1, -1, 0x00, "XOSC32K control A register"}, + {"bod.ctrla", 0x00a0, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x00a1, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x00a8, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x00a9, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x00aa, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x00ab, 1, -1, 0x00, "status register"}, + {"vref.acref", 0x00b4, 1, -1, 0x00, "AC reference register"}, + {"wdt.ctrla", 0x0100, 1, -1, 0x00, "control register A"}, + {"wdt.status", 0x0101, 1, -1, 0x00, "status register"}, + {"cpuint.ctrla", 0x0110, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0111, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0112, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0113, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0121, 1, -1, 0x00, "control register B"}, + {"crcscan.intctrl", 0x0122, 1, -1, 0x00, "interrupt control register"}, + {"crcscan.intflags", 0x0123, 1, -1, 0x00, "interrupt flags register"}, + {"crcscan.statusa", 0x0124, 1, -1, 0x04, "status A register"}, + {"crcscan.scanadr", 0x0125, 1, -1, 0x00, "scan address register"}, + {"crcscan.data", 0x0126, 1, -1, 0x00, "data register"}, + {"crcscan.crc", 0x0128, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.calib", 0x0146, 1, -1, 0x00, "calibration register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userac0sample", 0x0224, 1, -1, 0x00, "user 4 - AC0 register"}, + {"evsys.useradc0start", 0x0225, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.userevsysevouta", 0x0226, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x0227, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0228, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0229, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0rxd", 0x022a, 1, -1, 0x00, "user 10 - USART0 RxD event input register"}, + {"evsys.usertce0cnta", 0x022b, 1, -1, 0x00, "user TCE 0 event A register"}, + {"evsys.usertce0cntb", 0x022c, 1, -1, 0x00, "user TCE 0 event B register"}, + {"evsys.usertcb0capt", 0x022d, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x022e, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x022f, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x0230, 1, -1, 0x00, "user TCB 1 event register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tceroutea", 0x05e7, 1, -1, 0x00, "TCE route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, 0x0000, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.refscale", 0x0683, 1, -1, 0xff, "reference scaling register"}, + {"ac0.intctrl", 0x0684, 1, -1, 0x00, "interrupt control register"}, + {"ac0.intflags", 0x0685, 1, -1, -1, "interrupt flags register"}, + {"ac0.status", 0x0686, 1, -1, 0x00, "status register"}, + {"usart0.ctrla", 0x0800, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0801, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0802, 1, -1, 0x00, "control register C"}, + {"usart0.ctrld", 0x0803, 1, -1, 0x00, "control register D"}, + {"usart0.ctrle", 0x0804, 1, -1, 0x00, "control register E"}, + {"usart0.ctrlf", 0x0805, 1, -1, 0x00, "control register F"}, + {"usart0.ctrlg", 0x0806, 1, -1, 0x00, "control register G"}, + {"usart0.command", 0x0807, 1, -1, 0x00, "command register"}, + {"usart0.evctrl", 0x0809, 1, -1, 0x00, "event control register"}, + {"usart0.baud", 0x080a, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.intctrl", 0x080c, 1, -1, 0x00, "interrupt control register"}, + {"usart0.intflags", 0x080d, 1, -1, 0x01, "interrupt flags register"}, + {"usart0.status", 0x080e, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0810, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0811, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0812, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0813, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.auxdata0", 0x0818, 1, -1, 0x00, "auxiliary data 0 register"}, + {"usart0.auxdata1", 0x0819, 1, -1, 0x00, "auxiliary data 1 register"}, + {"usart0.auxdata2", 0x081a, 1, -1, 0x00, "auxiliary data 2 register"}, + {"usart0.dbgctrl", 0x081f, 1, -1, 0x00, "debug control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"tce0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tce0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tce0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tce0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tce0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tce0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tce0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tce0.evgenctrl", 0x0a08, 1, -1, 0x00, "event generation control register"}, + {"tce0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tce0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tce0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tce0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tce0.temp", 0x0a0f, 1, -1, 0x00, "temporary register for 16-bit access"}, + {"tce0.cnt", 0x0a20, 2, -1, 0x0000, "counter (16 bits)"}, + {"tce0.per", 0x0a26, 2, -1, 0x0000, "period register (16 bits)"}, + {"tce0.cmp0", 0x0a28, 2, -1, 0x0000, "compare 0 register (16 bits)"}, + {"tce0.cmp1", 0x0a2a, 2, -1, 0x0000, "compare 1 register (16 bits)"}, + {"tce0.cmp2", 0x0a2c, 2, -1, 0x0000, "compare 2 register (16 bits)"}, + {"tce0.perbuf", 0x0a36, 2, -1, 0x0000, "period buffer register (16 bits)"}, + {"tce0.cmp0buf", 0x0a38, 2, -1, 0x0000, "compare 0 buffer register (16 bits)"}, + {"tce0.cmp1buf", 0x0a3a, 2, -1, 0x0000, "compare 1 buffer register (16 bits)"}, + {"tce0.cmp2buf", 0x0a3c, 2, -1, 0x0000, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.ctrlc", 0x0b02, 1, -1, 0x00, "control register C"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.ctrlc", 0x0b12, 1, -1, 0x00, "control register C"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"syscfg.vddctrl", 0x0f07, 1, -1, 0x01, "VDD range control register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.intctrl", 0x1004, 1, -1, 0x00, "interrupt control register"}, + {"nvmctrl.intflags", 0x1005, 1, -1, 0x00, "interrupt flags register"}, + {"nvmctrl.status", 0x1006, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 2, -1, 0x0000, "data register (16 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, 0x00000000, "address register (32 bits)"}, +}; + +// AVR32SD20 +const Register_file rgftab_avr32sd20[540] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, + {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, -1, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"rstctrl.mcflagsa", 0x0042, 1, -1, -1, "machine check flags A register"}, + {"rstctrl.mcflagsb", 0x0043, 1, -1, -1, "machine check flags B register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.ctrlb", 0x0051, 1, -1, 0x00, "control register B"}, + {"slpctrl.vregctrl", 0x0052, 1, -1, 0x40, "control B register"}, + {"slpctrl.intctrl", 0x0053, 1, -1, 0x00, "interrupt control register"}, + {"slpctrl.intflags", 0x0054, 1, -1, 0x00, "interrupt flags register"}, + {"bod.ctrla", 0x0060, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0061, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0068, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0069, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x006a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x006b, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x0072, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x0074, 1, -1, 0x00, "AC reference register"}, + {"clkctrl.mclkctrla", 0x0080, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0081, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0082, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0083, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0084, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0085, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0086, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.mclkcfd0ctrla", 0x0088, 1, -1, 0x00, "MCLK clock failure detect 0 control A register"}, + {"clkctrl.mclkcfd1ctrla", 0x0089, 1, -1, 0x00, "MCLK clock failure detect 1 control A register"}, + {"clkctrl.mclkcfm0value", 0x0090, 2, -1, 0x0000, "MCLK clock failure measurement 0 value register (16 bits)"}, + {"clkctrl.mclkcfm0winlt", 0x0092, 2, -1, 0x0000, "MCLK clock failure measurement 0 window low threshold register (16 bits)"}, + {"clkctrl.mclkcfm0winht", 0x0094, 2, -1, 0x0000, "MCLK clock failure measurement 0 window high threshold register (16 bits)"}, + {"clkctrl.mclkcfm0refnum", 0x0096, 2, -1, 0x0000, "MCLK clock failure measurement 0 reference clock cycles register (16 bits)"}, + {"clkctrl.mclkcfm0ctrla", 0x0098, 1, -1, 0x00, "MCLK clock failure measurement 0 control A register"}, + {"clkctrl.mclkcfm0ctrlb", 0x0099, 1, -1, 0x00, "MCLK clock failure measurement 0 control B register"}, + {"clkctrl.mclkcfm1value", 0x00a0, 2, -1, 0x0000, "MCLK clock failure measurement 1 value register (16 bits)"}, + {"clkctrl.mclkcfm1winlt", 0x00a2, 2, -1, 0x0000, "MCLK clock failure measurement 1 window low threshold register (16 bits)"}, + {"clkctrl.mclkcfm1winht", 0x00a4, 2, -1, 0x0000, "MCLK clock failure measurement 1 window high threshold register (16 bits)"}, + {"clkctrl.mclkcfm1refnum", 0x00a6, 2, -1, 0x0000, "MCLK clock failure measurement 1 reference clock cycles register (16 bits)"}, + {"clkctrl.mclkcfm1ctrla", 0x00a8, 1, -1, 0x00, "MCLK clock failure measurement 1 control A register"}, + {"clkctrl.mclkcfm1ctrlb", 0x00a9, 1, -1, 0x00, "MCLK clock failure measurement 1 control B register"}, + {"clkctrl.oschfctrla", 0x00c0, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x00c1, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x00c8, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x00d0, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x00d4, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x00d8, 1, -1, 0x00, "XOSC HF control A register"}, + {"mvio.intctrl", 0x0100, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x0101, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x0102, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0110, 1, -1, -1, "control register A"}, + {"wdt.ctrlb", 0x0111, 1, -1, 0x40, "control register B"}, + {"wdt.status", 0x0112, 1, -1, 0x00, "status register"}, + {"wdt.cnt", 0x0114, 2, -1, 0x0000, "counter (16 bits)"}, + {"cpuint.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0121, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0122, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0123, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0130, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0131, 1, -1, 0x00, "control register B"}, + {"crcscan.intctrl", 0x0132, 1, -1, 0x00, "interrupt control register"}, + {"crcscan.intflags", 0x0133, 1, -1, 0x00, "interrupt flags register"}, + {"crcscan.statusa", 0x0134, 1, -1, 0x04, "status A register"}, + {"crcscan.scanadr", 0x0135, 1, -1, 0x00, "scan address register"}, + {"crcscan.data", 0x0136, 1, -1, 0x00, "data register"}, + {"crcscan.crc", 0x0138, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.useradc1start", 0x022d, 1, -1, 0x00, "user 13 - ADC1 register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userusart0irda", 0x0232, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0233, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.usertca0cnta", 0x0235, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0236, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0237, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0238, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0239, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x023a, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023b, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023c, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023d, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023e, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x023f, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0240, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.usererrctrlevent0", 0x0241, 1, -1, 0x00, "user 33 - ERRCTRL event 0 register"}, + {"evsys.usererrctrlevent1", 0x0242, 1, -1, 0x00, "user 34 - ERRCTRL event 1 register"}, + {"evsys.userclkctrlcfd", 0x0243, 1, -1, 0x00, "user 35 - CLKCTRL CFD register"}, + {"evsys.userclkctrlcfm", 0x0244, 1, -1, 0x00, "user 36 - CLKCTRL CFM register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05eb, 1, -1, 0x00, "ZCD route A register"}, + {"portmux.errctrlroutea", 0x05ed, 1, -1, 0x00, "error controller route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, + {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, + {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, + {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, + {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, + {"adc1.ctrlf", 0x0645, 1, -1, 0x00, "control register F"}, + {"adc1.intctrl", 0x0646, 1, -1, 0x00, "interrupt control register"}, + {"adc1.intflags", 0x0647, 1, -1, 0x00, "interrupt flags register"}, + {"adc1.status", 0x0648, 1, -1, 0x00, "status register"}, + {"adc1.dbgctrl", 0x0649, 1, -1, 0x00, "debug control register"}, + {"adc1.command", 0x064a, 1, -1, 0x00, "command register"}, + {"adc1.muxpos", 0x064b, 1, -1, 0x00, "positive mux input register"}, + {"adc1.result", 0x064c, 2, -1, -1, "result register (32 bits)"}, + {"adc1.sample", 0x064e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc1.winlt", 0x0650, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc1.winht", 0x0652, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc1.temp", 0x0654, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"swdt.ctrla", 0x0e20, 1, -1, 0x00, "control register A"}, + {"swdt.ctrlb", 0x0e21, 1, -1, 0x00, "control register B"}, + {"swdt.intctrl", 0x0e22, 1, -1, 0x00, "interrupt control register"}, + {"swdt.intflags", 0x0e23, 1, -1, 0x00, "interrupt flags register"}, + {"swdt.cnt", 0x0e24, 4, -1, 0x00000000, "counter (32 bits)"}, + {"swdt.reset", 0x0e28, 4, -1, 0x00000000, "counter reset register (32 bits)"}, + {"swdt.window", 0x0e2c, 2, -1, 0x0000, "counter window register (16 bits)"}, + {"swdt.command", 0x0e2e, 1, -1, 0x00, "command register"}, + {"ramctrl.ctrla", 0x0e30, 1, -1, 0x00, "control register A"}, + {"ramctrl.intflags", 0x0e31, 1, -1, 0x00, "interrupt flags register"}, + {"ramctrl.addr", 0x0e32, 2, -1, 0x0000, "address register (16 bits)"}, + {"ramctrl.syndrome", 0x0e34, 1, -1, 0x00, "ECC syndrome register"}, + {"errctrl.ctrla", 0x0e40, 1, -1, 0x01, "control register A"}, + {"errctrl.statusa", 0x0e41, 1, -1, -1, "status A register"}, + {"errctrl.timeout", 0x0e42, 1, -1, 0xff, "timeout value register"}, + {"errctrl.timecnt", 0x0e43, 1, -1, 0xff, "timeout counter register"}, + {"errctrl.cause", 0x0e44, 1, -1, -1, "reset cause register"}, + {"errctrl.escvregfail", 0x0e50, 1, -1, 0x82, "error source control VREGFAIL register"}, + {"errctrl.escbuserr", 0x0e51, 1, -1, 0x82, "error source control BUSERR register"}, + {"errctrl.escram2", 0x0e52, 1, -1, 0x82, "error source control RAM2 register"}, + {"errctrl.escflash2", 0x0e53, 1, -1, 0x82, "error source control FLASH2 register"}, + {"errctrl.escopc", 0x0e54, 1, -1, 0x82, "error source control OPC register"}, + {"errctrl.escsplim", 0x0e55, 1, -1, 0x82, "error source control SPLIM register"}, + {"errctrl.escram1", 0x0e56, 1, -1, 0x82, "error source control RAM1 register"}, + {"errctrl.escflash1", 0x0e57, 1, -1, 0x82, "error source control FLASH1 register"}, + {"errctrl.escvregwarn", 0x0e58, 1, -1, 0x82, "error source control VREGWARN register"}, + {"errctrl.esccfd0", 0x0e59, 1, -1, 0x82, "error source control CFD0 register"}, + {"errctrl.esccfd1", 0x0e5a, 1, -1, 0x82, "error source control CFD1 register"}, + {"errctrl.esccfm0", 0x0e5b, 1, -1, 0x82, "error source control CFM0 register"}, + {"errctrl.esccfm1", 0x0e5c, 1, -1, 0x82, "error source control CFM1 register"}, + {"errctrl.escswdt", 0x0e5d, 1, -1, 0x82, "error source control SWDT register"}, + {"errctrl.esceeprom", 0x0e5e, 1, -1, 0x82, "error source control EEPROM register"}, + {"errctrl.escevsys0", 0x0e5f, 1, -1, 0x82, "error source control EVSYS0 register"}, + {"errctrl.escevsys1", 0x0e60, 1, -1, 0x82, "error source control EVSYS1 register"}, + {"errctrl.esf", 0x0e70, 4, -1, -1, "error status flags register (32 bits)"}, + {"errctrl.esftest", 0x0e74, 4, -1, 0x00000000, "error status flag test injection register (32 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.ctrld", 0x1003, 1, -1, 0x00, "control register D"}, + {"nvmctrl.intctrla", 0x1004, 1, -1, 0x00, "interrupt control register A"}, + {"nvmctrl.intflagsa", 0x1005, 1, -1, 0x00, "interrupt flags A register"}, + {"nvmctrl.intflagsb", 0x1006, 1, -1, -1, "interrupt flags B register"}, + {"nvmctrl.status", 0x1007, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, + {"nvmctrl.parity", 0x1010, 1, -1, -1, "ECC parity register"}, + {"nvmctrl.syndrome", 0x1011, 1, -1, -1, "ECC syndrome register"}, +}; + +// AVR32SD28 +const Register_file rgftab_avr32sd28[559] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, + {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, -1, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"rstctrl.mcflagsa", 0x0042, 1, -1, -1, "machine check flags A register"}, + {"rstctrl.mcflagsb", 0x0043, 1, -1, -1, "machine check flags B register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.ctrlb", 0x0051, 1, -1, 0x00, "control register B"}, + {"slpctrl.vregctrl", 0x0052, 1, -1, 0x40, "control B register"}, + {"slpctrl.intctrl", 0x0053, 1, -1, 0x00, "interrupt control register"}, + {"slpctrl.intflags", 0x0054, 1, -1, 0x00, "interrupt flags register"}, + {"bod.ctrla", 0x0060, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0061, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0068, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0069, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x006a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x006b, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x0072, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x0074, 1, -1, 0x00, "AC reference register"}, + {"clkctrl.mclkctrla", 0x0080, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0081, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0082, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0083, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0084, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0085, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0086, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.mclkcfd0ctrla", 0x0088, 1, -1, 0x00, "MCLK clock failure detect 0 control A register"}, + {"clkctrl.mclkcfd1ctrla", 0x0089, 1, -1, 0x00, "MCLK clock failure detect 1 control A register"}, + {"clkctrl.mclkcfm0value", 0x0090, 2, -1, 0x0000, "MCLK clock failure measurement 0 value register (16 bits)"}, + {"clkctrl.mclkcfm0winlt", 0x0092, 2, -1, 0x0000, "MCLK clock failure measurement 0 window low threshold register (16 bits)"}, + {"clkctrl.mclkcfm0winht", 0x0094, 2, -1, 0x0000, "MCLK clock failure measurement 0 window high threshold register (16 bits)"}, + {"clkctrl.mclkcfm0refnum", 0x0096, 2, -1, 0x0000, "MCLK clock failure measurement 0 reference clock cycles register (16 bits)"}, + {"clkctrl.mclkcfm0ctrla", 0x0098, 1, -1, 0x00, "MCLK clock failure measurement 0 control A register"}, + {"clkctrl.mclkcfm0ctrlb", 0x0099, 1, -1, 0x00, "MCLK clock failure measurement 0 control B register"}, + {"clkctrl.mclkcfm1value", 0x00a0, 2, -1, 0x0000, "MCLK clock failure measurement 1 value register (16 bits)"}, + {"clkctrl.mclkcfm1winlt", 0x00a2, 2, -1, 0x0000, "MCLK clock failure measurement 1 window low threshold register (16 bits)"}, + {"clkctrl.mclkcfm1winht", 0x00a4, 2, -1, 0x0000, "MCLK clock failure measurement 1 window high threshold register (16 bits)"}, + {"clkctrl.mclkcfm1refnum", 0x00a6, 2, -1, 0x0000, "MCLK clock failure measurement 1 reference clock cycles register (16 bits)"}, + {"clkctrl.mclkcfm1ctrla", 0x00a8, 1, -1, 0x00, "MCLK clock failure measurement 1 control A register"}, + {"clkctrl.mclkcfm1ctrlb", 0x00a9, 1, -1, 0x00, "MCLK clock failure measurement 1 control B register"}, + {"clkctrl.oschfctrla", 0x00c0, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x00c1, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x00c8, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x00d0, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x00d4, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x00d8, 1, -1, 0x00, "XOSC HF control A register"}, + {"mvio.intctrl", 0x0100, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x0101, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x0102, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0110, 1, -1, -1, "control register A"}, + {"wdt.ctrlb", 0x0111, 1, -1, 0x40, "control register B"}, + {"wdt.status", 0x0112, 1, -1, 0x00, "status register"}, + {"wdt.cnt", 0x0114, 2, -1, 0x0000, "counter (16 bits)"}, + {"cpuint.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0121, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0122, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0123, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0130, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0131, 1, -1, 0x00, "control register B"}, + {"crcscan.intctrl", 0x0132, 1, -1, 0x00, "interrupt control register"}, + {"crcscan.intflags", 0x0133, 1, -1, 0x00, "interrupt flags register"}, + {"crcscan.statusa", 0x0134, 1, -1, 0x04, "status A register"}, + {"crcscan.scanadr", 0x0135, 1, -1, 0x00, "scan address register"}, + {"crcscan.data", 0x0136, 1, -1, 0x00, "data register"}, + {"crcscan.crc", 0x0138, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.useradc1start", 0x022d, 1, -1, 0x00, "user 13 - ADC1 register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userusart0irda", 0x0232, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0233, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0234, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x0235, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0236, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0237, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0238, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0239, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x023a, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023b, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023c, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023d, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023e, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x023f, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0240, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.usererrctrlevent0", 0x0241, 1, -1, 0x00, "user 33 - ERRCTRL event 0 register"}, + {"evsys.usererrctrlevent1", 0x0242, 1, -1, 0x00, "user 34 - ERRCTRL event 1 register"}, + {"evsys.userclkctrlcfd", 0x0243, 1, -1, 0x00, "user 35 - CLKCTRL CFD register"}, + {"evsys.userclkctrlcfm", 0x0244, 1, -1, 0x00, "user 36 - CLKCTRL CFM register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05eb, 1, -1, 0x00, "ZCD route A register"}, + {"portmux.errctrlroutea", 0x05ed, 1, -1, 0x00, "error controller route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, + {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, + {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, + {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, + {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, + {"adc1.ctrlf", 0x0645, 1, -1, 0x00, "control register F"}, + {"adc1.intctrl", 0x0646, 1, -1, 0x00, "interrupt control register"}, + {"adc1.intflags", 0x0647, 1, -1, 0x00, "interrupt flags register"}, + {"adc1.status", 0x0648, 1, -1, 0x00, "status register"}, + {"adc1.dbgctrl", 0x0649, 1, -1, 0x00, "debug control register"}, + {"adc1.command", 0x064a, 1, -1, 0x00, "command register"}, + {"adc1.muxpos", 0x064b, 1, -1, 0x00, "positive mux input register"}, + {"adc1.result", 0x064c, 2, -1, -1, "result register (32 bits)"}, + {"adc1.sample", 0x064e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc1.winlt", 0x0650, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc1.winht", 0x0652, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc1.temp", 0x0654, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"swdt.ctrla", 0x0e20, 1, -1, 0x00, "control register A"}, + {"swdt.ctrlb", 0x0e21, 1, -1, 0x00, "control register B"}, + {"swdt.intctrl", 0x0e22, 1, -1, 0x00, "interrupt control register"}, + {"swdt.intflags", 0x0e23, 1, -1, 0x00, "interrupt flags register"}, + {"swdt.cnt", 0x0e24, 4, -1, 0x00000000, "counter (32 bits)"}, + {"swdt.reset", 0x0e28, 4, -1, 0x00000000, "counter reset register (32 bits)"}, + {"swdt.window", 0x0e2c, 2, -1, 0x0000, "counter window register (16 bits)"}, + {"swdt.command", 0x0e2e, 1, -1, 0x00, "command register"}, + {"ramctrl.ctrla", 0x0e30, 1, -1, 0x00, "control register A"}, + {"ramctrl.intflags", 0x0e31, 1, -1, 0x00, "interrupt flags register"}, + {"ramctrl.addr", 0x0e32, 2, -1, 0x0000, "address register (16 bits)"}, + {"ramctrl.syndrome", 0x0e34, 1, -1, 0x00, "ECC syndrome register"}, + {"errctrl.ctrla", 0x0e40, 1, -1, 0x01, "control register A"}, + {"errctrl.statusa", 0x0e41, 1, -1, -1, "status A register"}, + {"errctrl.timeout", 0x0e42, 1, -1, 0xff, "timeout value register"}, + {"errctrl.timecnt", 0x0e43, 1, -1, 0xff, "timeout counter register"}, + {"errctrl.cause", 0x0e44, 1, -1, -1, "reset cause register"}, + {"errctrl.escvregfail", 0x0e50, 1, -1, 0x82, "error source control VREGFAIL register"}, + {"errctrl.escbuserr", 0x0e51, 1, -1, 0x82, "error source control BUSERR register"}, + {"errctrl.escram2", 0x0e52, 1, -1, 0x82, "error source control RAM2 register"}, + {"errctrl.escflash2", 0x0e53, 1, -1, 0x82, "error source control FLASH2 register"}, + {"errctrl.escopc", 0x0e54, 1, -1, 0x82, "error source control OPC register"}, + {"errctrl.escsplim", 0x0e55, 1, -1, 0x82, "error source control SPLIM register"}, + {"errctrl.escram1", 0x0e56, 1, -1, 0x82, "error source control RAM1 register"}, + {"errctrl.escflash1", 0x0e57, 1, -1, 0x82, "error source control FLASH1 register"}, + {"errctrl.escvregwarn", 0x0e58, 1, -1, 0x82, "error source control VREGWARN register"}, + {"errctrl.esccfd0", 0x0e59, 1, -1, 0x82, "error source control CFD0 register"}, + {"errctrl.esccfd1", 0x0e5a, 1, -1, 0x82, "error source control CFD1 register"}, + {"errctrl.esccfm0", 0x0e5b, 1, -1, 0x82, "error source control CFM0 register"}, + {"errctrl.esccfm1", 0x0e5c, 1, -1, 0x82, "error source control CFM1 register"}, + {"errctrl.escswdt", 0x0e5d, 1, -1, 0x82, "error source control SWDT register"}, + {"errctrl.esceeprom", 0x0e5e, 1, -1, 0x82, "error source control EEPROM register"}, + {"errctrl.escevsys0", 0x0e5f, 1, -1, 0x82, "error source control EVSYS0 register"}, + {"errctrl.escevsys1", 0x0e60, 1, -1, 0x82, "error source control EVSYS1 register"}, + {"errctrl.esf", 0x0e70, 4, -1, -1, "error status flags register (32 bits)"}, + {"errctrl.esftest", 0x0e74, 4, -1, 0x00000000, "error status flag test injection register (32 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.ctrld", 0x1003, 1, -1, 0x00, "control register D"}, + {"nvmctrl.intctrla", 0x1004, 1, -1, 0x00, "interrupt control register A"}, + {"nvmctrl.intflagsa", 0x1005, 1, -1, 0x00, "interrupt flags A register"}, + {"nvmctrl.intflagsb", 0x1006, 1, -1, -1, "interrupt flags B register"}, + {"nvmctrl.status", 0x1007, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, + {"nvmctrl.parity", 0x1010, 1, -1, -1, "ECC parity register"}, + {"nvmctrl.syndrome", 0x1011, 1, -1, -1, "ECC syndrome register"}, +}; + +// AVR32SD32 +const Register_file rgftab_avr32sd32[575] = { // I/O memory [0, 4159] + {"vporta.dir", 0x0000, 1, -1, 0x00, "data direction register"}, + {"vporta.out", 0x0001, 1, -1, 0x00, "I/O port output register"}, + {"vporta.in", 0x0002, 1, -1, 0x00, "I/O port input register"}, + {"vporta.intflags", 0x0003, 1, -1, 0x00, "interrupt flags register"}, + {"vportc.dir", 0x0008, 1, -1, 0x00, "data direction register"}, + {"vportc.out", 0x0009, 1, -1, 0x00, "I/O port output register"}, + {"vportc.in", 0x000a, 1, -1, 0x00, "I/O port input register"}, + {"vportc.intflags", 0x000b, 1, -1, 0x00, "interrupt flags register"}, + {"vportd.dir", 0x000c, 1, -1, 0x00, "data direction register"}, + {"vportd.out", 0x000d, 1, -1, 0x00, "I/O port output register"}, + {"vportd.in", 0x000e, 1, -1, 0x00, "I/O port input register"}, + {"vportd.intflags", 0x000f, 1, -1, 0x00, "interrupt flags register"}, + {"vportf.dir", 0x0014, 1, -1, 0x00, "data direction register"}, + {"vportf.out", 0x0015, 1, -1, 0x00, "I/O port output register"}, + {"vportf.in", 0x0016, 1, -1, 0x00, "I/O port input register"}, + {"vportf.intflags", 0x0017, 1, -1, 0x00, "interrupt flags register"}, + {"gpr.gpr0", 0x001c, 1, -1, -1, "general purpose register 0"}, + {"gpr.gpr1", 0x001d, 1, -1, -1, "general purpose register 1"}, + {"gpr.gpr2", 0x001e, 1, -1, -1, "general purpose register 2"}, + {"gpr.gpr3", 0x001f, 1, -1, -1, "general purpose register 3"}, + {"cpu.splim", 0x0030, 2, -1, 0x0000, "stack pointer limit register (16 bits)"}, + {"cpu.ccp", 0x0034, 1, -1, 0x00, "configuration change protection register"}, + {"cpu.ctrla", 0x0035, 1, -1, 0x00, "control register A"}, + {"cpu.intflags", 0x0036, 1, -1, -1, "interrupt flags register"}, + {"cpu.sp", 0x003d, 2, -1, 0x7fff, "stack pointer (16 bits)"}, + {"cpu.sreg", 0x003f, 1, -1, 0x00, "status register"}, + {"rstctrl.rstfr", 0x0040, 1, -1, -1, "reset flags register"}, + {"rstctrl.swrr", 0x0041, 1, -1, 0x00, "software reset register"}, + {"rstctrl.mcflagsa", 0x0042, 1, -1, -1, "machine check flags A register"}, + {"rstctrl.mcflagsb", 0x0043, 1, -1, -1, "machine check flags B register"}, + {"slpctrl.ctrla", 0x0050, 1, -1, 0x00, "control register A"}, + {"slpctrl.ctrlb", 0x0051, 1, -1, 0x00, "control register B"}, + {"slpctrl.vregctrl", 0x0052, 1, -1, 0x40, "control B register"}, + {"slpctrl.intctrl", 0x0053, 1, -1, 0x00, "interrupt control register"}, + {"slpctrl.intflags", 0x0054, 1, -1, 0x00, "interrupt flags register"}, + {"bod.ctrla", 0x0060, 1, -1, 0x01, "control register A"}, + {"bod.ctrlb", 0x0061, 1, -1, 0x00, "control register B"}, + {"bod.vlmctrla", 0x0068, 1, -1, 0x00, "voltage level monitor control register"}, + {"bod.intctrl", 0x0069, 1, -1, 0x00, "interrupt control register"}, + {"bod.intflags", 0x006a, 1, -1, 0x00, "interrupt flags register"}, + {"bod.status", 0x006b, 1, -1, 0x00, "status register"}, + {"vref.dac0ref", 0x0072, 1, -1, 0x00, "DAC 0 reference register"}, + {"vref.acref", 0x0074, 1, -1, 0x00, "AC reference register"}, + {"clkctrl.mclkctrla", 0x0080, 1, -1, 0x00, "MCLK control A register"}, + {"clkctrl.mclkctrlb", 0x0081, 1, -1, 0x00, "MCLK control B register"}, + {"clkctrl.mclkctrlc", 0x0082, 1, -1, 0x00, "MCLK control C register"}, + {"clkctrl.mclkintctrl", 0x0083, 1, -1, 0x00, "MCLK interrupt control register"}, + {"clkctrl.mclkintflags", 0x0084, 1, -1, 0x00, "MCLK interrupt flags register"}, + {"clkctrl.mclkstatus", 0x0085, 1, -1, 0x00, "MCLK status register"}, + {"clkctrl.mclktimebase", 0x0086, 1, -1, 0x00, "MCLK timebase register"}, + {"clkctrl.mclkcfd0ctrla", 0x0088, 1, -1, 0x00, "MCLK clock failure detect 0 control A register"}, + {"clkctrl.mclkcfd1ctrla", 0x0089, 1, -1, 0x00, "MCLK clock failure detect 1 control A register"}, + {"clkctrl.mclkcfm0value", 0x0090, 2, -1, 0x0000, "MCLK clock failure measurement 0 value register (16 bits)"}, + {"clkctrl.mclkcfm0winlt", 0x0092, 2, -1, 0x0000, "MCLK clock failure measurement 0 window low threshold register (16 bits)"}, + {"clkctrl.mclkcfm0winht", 0x0094, 2, -1, 0x0000, "MCLK clock failure measurement 0 window high threshold register (16 bits)"}, + {"clkctrl.mclkcfm0refnum", 0x0096, 2, -1, 0x0000, "MCLK clock failure measurement 0 reference clock cycles register (16 bits)"}, + {"clkctrl.mclkcfm0ctrla", 0x0098, 1, -1, 0x00, "MCLK clock failure measurement 0 control A register"}, + {"clkctrl.mclkcfm0ctrlb", 0x0099, 1, -1, 0x00, "MCLK clock failure measurement 0 control B register"}, + {"clkctrl.mclkcfm1value", 0x00a0, 2, -1, 0x0000, "MCLK clock failure measurement 1 value register (16 bits)"}, + {"clkctrl.mclkcfm1winlt", 0x00a2, 2, -1, 0x0000, "MCLK clock failure measurement 1 window low threshold register (16 bits)"}, + {"clkctrl.mclkcfm1winht", 0x00a4, 2, -1, 0x0000, "MCLK clock failure measurement 1 window high threshold register (16 bits)"}, + {"clkctrl.mclkcfm1refnum", 0x00a6, 2, -1, 0x0000, "MCLK clock failure measurement 1 reference clock cycles register (16 bits)"}, + {"clkctrl.mclkcfm1ctrla", 0x00a8, 1, -1, 0x00, "MCLK clock failure measurement 1 control A register"}, + {"clkctrl.mclkcfm1ctrlb", 0x00a9, 1, -1, 0x00, "MCLK clock failure measurement 1 control B register"}, + {"clkctrl.oschfctrla", 0x00c0, 1, -1, 0x0c, "OSCHF control A register"}, + {"clkctrl.oschftune", 0x00c1, 1, -1, 0x00, "OSCHF tune register"}, + {"clkctrl.pllctrla", 0x00c8, 1, -1, 0x00, "PLL control A register"}, + {"clkctrl.osc32kctrla", 0x00d0, 1, -1, 0x00, "OSC32K control A register"}, + {"clkctrl.xosc32kctrla", 0x00d4, 1, -1, 0x00, "XOSC32K control A register"}, + {"clkctrl.xoschfctrla", 0x00d8, 1, -1, 0x00, "XOSC HF control A register"}, + {"mvio.intctrl", 0x0100, 1, -1, 0x00, "interrupt control register"}, + {"mvio.intflags", 0x0101, 1, -1, 0x00, "interrupt flags register"}, + {"mvio.status", 0x0102, 1, -1, 0x00, "status register"}, + {"wdt.ctrla", 0x0110, 1, -1, -1, "control register A"}, + {"wdt.ctrlb", 0x0111, 1, -1, 0x40, "control register B"}, + {"wdt.status", 0x0112, 1, -1, 0x00, "status register"}, + {"wdt.cnt", 0x0114, 2, -1, 0x0000, "counter (16 bits)"}, + {"cpuint.ctrla", 0x0120, 1, -1, 0x00, "control register A"}, + {"cpuint.status", 0x0121, 1, -1, 0x00, "status register"}, + {"cpuint.lvl0pri", 0x0122, 1, -1, 0x00, "interrupt level 0 priority register"}, + {"cpuint.lvl1vec", 0x0123, 1, -1, 0x00, "interrupt level 1 priority vector register"}, + {"crcscan.ctrla", 0x0130, 1, -1, 0x00, "control register A"}, + {"crcscan.ctrlb", 0x0131, 1, -1, 0x00, "control register B"}, + {"crcscan.intctrl", 0x0132, 1, -1, 0x00, "interrupt control register"}, + {"crcscan.intflags", 0x0133, 1, -1, 0x00, "interrupt flags register"}, + {"crcscan.statusa", 0x0134, 1, -1, 0x04, "status A register"}, + {"crcscan.scanadr", 0x0135, 1, -1, 0x00, "scan address register"}, + {"crcscan.data", 0x0136, 1, -1, 0x00, "data register"}, + {"crcscan.crc", 0x0138, 4, -1, 0xffffffff, "CRC result register (32 bits)"}, + {"rtc.ctrla", 0x0140, 1, -1, 0x00, "control register A"}, + {"rtc.status", 0x0141, 1, -1, 0x00, "status register"}, + {"rtc.intctrl", 0x0142, 1, -1, 0x00, "interrupt control register"}, + {"rtc.intflags", 0x0143, 1, -1, 0x00, "interrupt flags register"}, + {"rtc.temp", 0x0144, 1, -1, -1, "temporary register"}, + {"rtc.dbgctrl", 0x0145, 1, -1, 0x00, "debug control register"}, + {"rtc.clksel", 0x0147, 1, -1, 0x00, "clock select register"}, + {"rtc.cnt", 0x0148, 2, -1, -1, "counter (16 bits)"}, + {"rtc.per", 0x014a, 2, -1, 0xffff, "period register (16 bits)"}, + {"rtc.cmp", 0x014c, 2, -1, -1, "compare register (16 bits)"}, + {"rtc.pitctrla", 0x0150, 1, -1, 0x00, "PIT control A register"}, + {"rtc.pitstatus", 0x0151, 1, -1, 0x00, "PIT status register"}, + {"rtc.pitintctrl", 0x0152, 1, -1, 0x00, "PIT interrupt control register"}, + {"rtc.pitintflags", 0x0153, 1, -1, 0x00, "PIT interrupt flags register"}, + {"rtc.pitdbgctrl", 0x0155, 1, -1, 0x00, "PIT debug control register"}, + {"rtc.pitevgenctrla", 0x0156, 1, -1, 0x00, "PIT event generation control A register"}, + {"ccl.ctrla", 0x01c0, 1, -1, 0x00, "control register A"}, + {"ccl.seqctrl0", 0x01c1, 1, -1, 0x00, "sequential control register 0"}, + {"ccl.seqctrl1", 0x01c2, 1, -1, 0x00, "sequential control register 1"}, + {"ccl.seqctrl2", 0x01c3, 1, -1, 0x00, "sequential control register 2"}, + {"ccl.intctrl0", 0x01c5, 1, -1, 0x00, "interrupt control register 0"}, + {"ccl.intctrl1", 0x01c6, 1, -1, 0x00, "interrupt control register 1"}, + {"ccl.intflags", 0x01c7, 1, -1, 0x00, "interrupt flags register"}, + {"ccl.lut0ctrla", 0x01c8, 1, -1, 0x00, "LUT 0 control A register"}, + {"ccl.lut0ctrlb", 0x01c9, 1, -1, 0x00, "LUT 0 control B register"}, + {"ccl.lut0ctrlc", 0x01ca, 1, -1, 0x00, "LUT 0 control C register"}, + {"ccl.truth0", 0x01cb, 1, -1, 0x00, "truth register 0"}, + {"ccl.lut1ctrla", 0x01cc, 1, -1, 0x00, "LUT 1 control A register"}, + {"ccl.lut1ctrlb", 0x01cd, 1, -1, 0x00, "LUT 1 control B register"}, + {"ccl.lut1ctrlc", 0x01ce, 1, -1, 0x00, "LUT 1 control C register"}, + {"ccl.truth1", 0x01cf, 1, -1, 0x00, "truth register 1"}, + {"ccl.lut2ctrla", 0x01d0, 1, -1, 0x00, "LUT 2 control A register"}, + {"ccl.lut2ctrlb", 0x01d1, 1, -1, 0x00, "LUT 2 control B register"}, + {"ccl.lut2ctrlc", 0x01d2, 1, -1, 0x00, "LUT 2 control C register"}, + {"ccl.truth2", 0x01d3, 1, -1, 0x00, "truth register 2"}, + {"ccl.lut3ctrla", 0x01d4, 1, -1, 0x00, "LUT 3 control A register"}, + {"ccl.lut3ctrlb", 0x01d5, 1, -1, 0x00, "LUT 3 control B register"}, + {"ccl.lut3ctrlc", 0x01d6, 1, -1, 0x00, "LUT 3 control C register"}, + {"ccl.truth3", 0x01d7, 1, -1, 0x00, "truth register 3"}, + {"ccl.lut4ctrla", 0x01d8, 1, -1, 0x00, "LUT 4 control A register"}, + {"ccl.lut4ctrlb", 0x01d9, 1, -1, 0x00, "LUT 4 control B register"}, + {"ccl.lut4ctrlc", 0x01da, 1, -1, 0x00, "LUT 4 control C register"}, + {"ccl.truth4", 0x01db, 1, -1, 0x00, "truth register 4"}, + {"ccl.lut5ctrla", 0x01dc, 1, -1, 0x00, "LUT 5 control A register"}, + {"ccl.lut5ctrlb", 0x01dd, 1, -1, 0x00, "LUT 5 control B register"}, + {"ccl.lut5ctrlc", 0x01de, 1, -1, 0x00, "LUT 5 control C register"}, + {"ccl.truth5", 0x01df, 1, -1, 0x00, "truth register 5"}, + {"evsys.sweventa", 0x0200, 1, -1, 0x00, "software event A register"}, + {"evsys.channel0", 0x0210, 1, -1, 0x00, "multiplexer channel 0 register"}, + {"evsys.channel1", 0x0211, 1, -1, 0x00, "multiplexer channel 1 register"}, + {"evsys.channel2", 0x0212, 1, -1, 0x00, "multiplexer channel 2 register"}, + {"evsys.channel3", 0x0213, 1, -1, 0x00, "multiplexer channel 3 register"}, + {"evsys.channel4", 0x0214, 1, -1, 0x00, "multiplexer channel 4 register"}, + {"evsys.channel5", 0x0215, 1, -1, 0x00, "multiplexer channel 5 register"}, + {"evsys.userccllut0a", 0x0220, 1, -1, 0x00, "user CCL LUT 0 event A register"}, + {"evsys.userccllut0b", 0x0221, 1, -1, 0x00, "user CCL LUT 0 event B register"}, + {"evsys.userccllut1a", 0x0222, 1, -1, 0x00, "user CCL LUT 1 event A register"}, + {"evsys.userccllut1b", 0x0223, 1, -1, 0x00, "user CCL LUT 1 event B register"}, + {"evsys.userccllut2a", 0x0224, 1, -1, 0x00, "user CCL LUT 2 event A register"}, + {"evsys.userccllut2b", 0x0225, 1, -1, 0x00, "user CCL LUT 2 event B register"}, + {"evsys.userccllut3a", 0x0226, 1, -1, 0x00, "user CCL LUT 3 event A register"}, + {"evsys.userccllut3b", 0x0227, 1, -1, 0x00, "user CCL LUT 3 event B register"}, + {"evsys.userccllut4a", 0x0228, 1, -1, 0x00, "user CCL LUT 4 event A register"}, + {"evsys.userccllut4b", 0x0229, 1, -1, 0x00, "user CCL LUT 4 event B register"}, + {"evsys.userccllut5a", 0x022a, 1, -1, 0x00, "user CCL LUT 5 event A register"}, + {"evsys.userccllut5b", 0x022b, 1, -1, 0x00, "user CCL LUT 5 event B register"}, + {"evsys.useradc0start", 0x022c, 1, -1, 0x00, "user ADC 0 start register"}, + {"evsys.useradc1start", 0x022d, 1, -1, 0x00, "user 13 - ADC1 register"}, + {"evsys.userevsysevouta", 0x022e, 1, -1, 0x00, "user EVOUT port A register"}, + {"evsys.userevsysevoutc", 0x022f, 1, -1, 0x00, "user EVOUT port C register"}, + {"evsys.userevsysevoutd", 0x0230, 1, -1, 0x00, "user EVOUT port D register"}, + {"evsys.userevsysevoutf", 0x0231, 1, -1, 0x00, "user EVOUT port F register"}, + {"evsys.userusart0irda", 0x0232, 1, -1, 0x00, "user USART 0 IrDA event register"}, + {"evsys.userusart1irda", 0x0233, 1, -1, 0x00, "user USART 1 IrDA event register"}, + {"evsys.userusart2irda", 0x0234, 1, -1, 0x00, "user USART 2 IrDA event register"}, + {"evsys.usertca0cnta", 0x0235, 1, -1, 0x00, "user TCA 0 event A register"}, + {"evsys.usertca0cntb", 0x0236, 1, -1, 0x00, "user TCA 0 event B register"}, + {"evsys.usertcb0capt", 0x0237, 1, -1, 0x00, "user TCB 0 capture register"}, + {"evsys.usertcb0count", 0x0238, 1, -1, 0x00, "user TCB 0 event register"}, + {"evsys.usertcb1capt", 0x0239, 1, -1, 0x00, "user TCB 1 capture register"}, + {"evsys.usertcb1count", 0x023a, 1, -1, 0x00, "user TCB 1 event register"}, + {"evsys.usertcb2capt", 0x023b, 1, -1, 0x00, "user TCB 2 capture register"}, + {"evsys.usertcb2count", 0x023c, 1, -1, 0x00, "user TCB 2 event register"}, + {"evsys.usertcb3capt", 0x023d, 1, -1, 0x00, "user TCB 3 capture register"}, + {"evsys.usertcb3count", 0x023e, 1, -1, 0x00, "user TCB 3 event register"}, + {"evsys.usertcd0inputa", 0x023f, 1, -1, 0x00, "user TCD 0 input event A register"}, + {"evsys.usertcd0inputb", 0x0240, 1, -1, 0x00, "user TCD 0 input event B register"}, + {"evsys.usererrctrlevent0", 0x0241, 1, -1, 0x00, "user 33 - ERRCTRL event 0 register"}, + {"evsys.usererrctrlevent1", 0x0242, 1, -1, 0x00, "user 34 - ERRCTRL event 1 register"}, + {"evsys.userclkctrlcfd", 0x0243, 1, -1, 0x00, "user 35 - CLKCTRL CFD register"}, + {"evsys.userclkctrlcfm", 0x0244, 1, -1, 0x00, "user 36 - CLKCTRL CFM register"}, + {"porta.dir", 0x0400, 1, -1, 0x00, "data direction register"}, + {"porta.dirset", 0x0401, 1, -1, 0x00, "data direction set register"}, + {"porta.dirclr", 0x0402, 1, -1, 0x00, "data direction clear register"}, + {"porta.dirtgl", 0x0403, 1, -1, 0x00, "data direction toggle register"}, + {"porta.out", 0x0404, 1, -1, 0x00, "I/O port output register"}, + {"porta.outset", 0x0405, 1, -1, 0x00, "I/O port output set register"}, + {"porta.outclr", 0x0406, 1, -1, 0x00, "I/O port output clear register"}, + {"porta.outtgl", 0x0407, 1, -1, 0x00, "I/O port output toggle register"}, + {"porta.in", 0x0408, 1, -1, 0x00, "I/O port input register"}, + {"porta.intflags", 0x0409, 1, -1, 0x00, "interrupt flags register"}, + {"porta.portctrl", 0x040a, 1, -1, 0x00, "port control register"}, + {"porta.pinconfig", 0x040b, 1, -1, 0x00, "pin control config register"}, + {"porta.pinctrlupd", 0x040c, 1, -1, 0x00, "pin control update register"}, + {"porta.pinctrlset", 0x040d, 1, -1, 0x00, "pin control set register"}, + {"porta.pinctrlclr", 0x040e, 1, -1, 0x00, "pin control clear register"}, + {"porta.pin0ctrl", 0x0410, 1, -1, 0x00, "pin 0 control register"}, + {"porta.pin1ctrl", 0x0411, 1, -1, 0x00, "pin 1 control register"}, + {"porta.pin2ctrl", 0x0412, 1, -1, 0x00, "pin 2 control register"}, + {"porta.pin3ctrl", 0x0413, 1, -1, 0x00, "pin 3 control register"}, + {"porta.pin4ctrl", 0x0414, 1, -1, 0x00, "pin 4 control register"}, + {"porta.pin5ctrl", 0x0415, 1, -1, 0x00, "pin 5 control register"}, + {"porta.pin6ctrl", 0x0416, 1, -1, 0x00, "pin 6 control register"}, + {"porta.pin7ctrl", 0x0417, 1, -1, 0x00, "pin 7 control register"}, + {"porta.evgenctrla", 0x0418, 1, -1, 0x00, "event generation control A register"}, + {"portc.dir", 0x0440, 1, -1, 0x00, "data direction register"}, + {"portc.dirset", 0x0441, 1, -1, 0x00, "data direction set register"}, + {"portc.dirclr", 0x0442, 1, -1, 0x00, "data direction clear register"}, + {"portc.dirtgl", 0x0443, 1, -1, 0x00, "data direction toggle register"}, + {"portc.out", 0x0444, 1, -1, 0x00, "I/O port output register"}, + {"portc.outset", 0x0445, 1, -1, 0x00, "I/O port output set register"}, + {"portc.outclr", 0x0446, 1, -1, 0x00, "I/O port output clear register"}, + {"portc.outtgl", 0x0447, 1, -1, 0x00, "I/O port output toggle register"}, + {"portc.in", 0x0448, 1, -1, 0x00, "I/O port input register"}, + {"portc.intflags", 0x0449, 1, -1, 0x00, "interrupt flags register"}, + {"portc.portctrl", 0x044a, 1, -1, 0x00, "port control register"}, + {"portc.pinconfig", 0x044b, 1, -1, 0x00, "pin control config register"}, + {"portc.pinctrlupd", 0x044c, 1, -1, 0x00, "pin control update register"}, + {"portc.pinctrlset", 0x044d, 1, -1, 0x00, "pin control set register"}, + {"portc.pinctrlclr", 0x044e, 1, -1, 0x00, "pin control clear register"}, + {"portc.pin0ctrl", 0x0450, 1, -1, 0x00, "pin 0 control register"}, + {"portc.pin1ctrl", 0x0451, 1, -1, 0x00, "pin 1 control register"}, + {"portc.pin2ctrl", 0x0452, 1, -1, 0x00, "pin 2 control register"}, + {"portc.pin3ctrl", 0x0453, 1, -1, 0x00, "pin 3 control register"}, + {"portc.pin4ctrl", 0x0454, 1, -1, 0x00, "pin 4 control register"}, + {"portc.pin5ctrl", 0x0455, 1, -1, 0x00, "pin 5 control register"}, + {"portc.pin6ctrl", 0x0456, 1, -1, 0x00, "pin 6 control register"}, + {"portc.pin7ctrl", 0x0457, 1, -1, 0x00, "pin 7 control register"}, + {"portc.evgenctrla", 0x0458, 1, -1, 0x00, "event generation control A register"}, + {"portd.dir", 0x0460, 1, -1, 0x00, "data direction register"}, + {"portd.dirset", 0x0461, 1, -1, 0x00, "data direction set register"}, + {"portd.dirclr", 0x0462, 1, -1, 0x00, "data direction clear register"}, + {"portd.dirtgl", 0x0463, 1, -1, 0x00, "data direction toggle register"}, + {"portd.out", 0x0464, 1, -1, 0x00, "I/O port output register"}, + {"portd.outset", 0x0465, 1, -1, 0x00, "I/O port output set register"}, + {"portd.outclr", 0x0466, 1, -1, 0x00, "I/O port output clear register"}, + {"portd.outtgl", 0x0467, 1, -1, 0x00, "I/O port output toggle register"}, + {"portd.in", 0x0468, 1, -1, 0x00, "I/O port input register"}, + {"portd.intflags", 0x0469, 1, -1, 0x00, "interrupt flags register"}, + {"portd.portctrl", 0x046a, 1, -1, 0x00, "port control register"}, + {"portd.pinconfig", 0x046b, 1, -1, 0x00, "pin control config register"}, + {"portd.pinctrlupd", 0x046c, 1, -1, 0x00, "pin control update register"}, + {"portd.pinctrlset", 0x046d, 1, -1, 0x00, "pin control set register"}, + {"portd.pinctrlclr", 0x046e, 1, -1, 0x00, "pin control clear register"}, + {"portd.pin0ctrl", 0x0470, 1, -1, 0x00, "pin 0 control register"}, + {"portd.pin1ctrl", 0x0471, 1, -1, 0x00, "pin 1 control register"}, + {"portd.pin2ctrl", 0x0472, 1, -1, 0x00, "pin 2 control register"}, + {"portd.pin3ctrl", 0x0473, 1, -1, 0x00, "pin 3 control register"}, + {"portd.pin4ctrl", 0x0474, 1, -1, 0x00, "pin 4 control register"}, + {"portd.pin5ctrl", 0x0475, 1, -1, 0x00, "pin 5 control register"}, + {"portd.pin6ctrl", 0x0476, 1, -1, 0x00, "pin 6 control register"}, + {"portd.pin7ctrl", 0x0477, 1, -1, 0x00, "pin 7 control register"}, + {"portd.evgenctrla", 0x0478, 1, -1, 0x00, "event generation control A register"}, + {"portf.dir", 0x04a0, 1, -1, 0x00, "data direction register"}, + {"portf.dirset", 0x04a1, 1, -1, 0x00, "data direction set register"}, + {"portf.dirclr", 0x04a2, 1, -1, 0x00, "data direction clear register"}, + {"portf.dirtgl", 0x04a3, 1, -1, 0x00, "data direction toggle register"}, + {"portf.out", 0x04a4, 1, -1, 0x00, "I/O port output register"}, + {"portf.outset", 0x04a5, 1, -1, 0x00, "I/O port output set register"}, + {"portf.outclr", 0x04a6, 1, -1, 0x00, "I/O port output clear register"}, + {"portf.outtgl", 0x04a7, 1, -1, 0x00, "I/O port output toggle register"}, + {"portf.in", 0x04a8, 1, -1, 0x00, "I/O port input register"}, + {"portf.intflags", 0x04a9, 1, -1, 0x00, "interrupt flags register"}, + {"portf.portctrl", 0x04aa, 1, -1, 0x00, "port control register"}, + {"portf.pinconfig", 0x04ab, 1, -1, 0x00, "pin control config register"}, + {"portf.pinctrlupd", 0x04ac, 1, -1, 0x00, "pin control update register"}, + {"portf.pinctrlset", 0x04ad, 1, -1, 0x00, "pin control set register"}, + {"portf.pinctrlclr", 0x04ae, 1, -1, 0x00, "pin control clear register"}, + {"portf.pin0ctrl", 0x04b0, 1, -1, 0x00, "pin 0 control register"}, + {"portf.pin1ctrl", 0x04b1, 1, -1, 0x00, "pin 1 control register"}, + {"portf.pin2ctrl", 0x04b2, 1, -1, 0x00, "pin 2 control register"}, + {"portf.pin3ctrl", 0x04b3, 1, -1, 0x00, "pin 3 control register"}, + {"portf.pin4ctrl", 0x04b4, 1, -1, 0x00, "pin 4 control register"}, + {"portf.pin5ctrl", 0x04b5, 1, -1, 0x00, "pin 5 control register"}, + {"portf.pin6ctrl", 0x04b6, 1, -1, 0x00, "pin 6 control register"}, + {"portf.pin7ctrl", 0x04b7, 1, -1, 0x00, "pin 7 control register"}, + {"portf.evgenctrla", 0x04b8, 1, -1, 0x00, "event generation control A register"}, + {"portmux.evsysroutea", 0x05e0, 1, -1, 0x00, "port multiplexer EVSYS register"}, + {"portmux.cclroutea", 0x05e1, 1, -1, 0x00, "CCL route A register"}, + {"portmux.usartroutea", 0x05e2, 1, -1, 0x00, "USART route A register"}, + {"portmux.usartrouteb", 0x05e3, 1, -1, 0x00, "USART route B register"}, + {"portmux.spiroutea", 0x05e5, 1, -1, 0x00, "SPI route A register"}, + {"portmux.twiroutea", 0x05e6, 1, -1, 0x00, "TWI route A register"}, + {"portmux.tcaroutea", 0x05e7, 1, -1, 0x00, "TCA route A register"}, + {"portmux.tcbroutea", 0x05e8, 1, -1, 0x00, "TCB route A register"}, + {"portmux.tcdroutea", 0x05e9, 1, -1, 0x00, "TCD route A register"}, + {"portmux.acroutea", 0x05ea, 1, -1, 0x00, "AC route A register"}, + {"portmux.zcdroutea", 0x05eb, 1, -1, 0x00, "ZCD route A register"}, + {"portmux.errctrlroutea", 0x05ed, 1, -1, 0x00, "error controller route A register"}, + {"adc0.ctrla", 0x0600, 1, -1, 0x00, "control register A"}, + {"adc0.ctrlb", 0x0601, 1, -1, 0x00, "control register B"}, + {"adc0.ctrlc", 0x0602, 1, -1, 0x00, "control register C"}, + {"adc0.ctrld", 0x0603, 1, -1, 0x00, "control register D"}, + {"adc0.ctrle", 0x0604, 1, -1, 0x00, "control register E"}, + {"adc0.ctrlf", 0x0605, 1, -1, 0x00, "control register F"}, + {"adc0.intctrl", 0x0606, 1, -1, 0x00, "interrupt control register"}, + {"adc0.intflags", 0x0607, 1, -1, 0x00, "interrupt flags register"}, + {"adc0.status", 0x0608, 1, -1, 0x00, "status register"}, + {"adc0.dbgctrl", 0x0609, 1, -1, 0x00, "debug control register"}, + {"adc0.command", 0x060a, 1, -1, 0x00, "command register"}, + {"adc0.muxpos", 0x060b, 1, -1, 0x00, "positive mux input register"}, + {"adc0.result", 0x060c, 2, -1, -1, "result register (32 bits)"}, + {"adc0.sample", 0x060e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc0.winlt", 0x0610, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc0.winht", 0x0612, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc0.temp", 0x0614, 1, -1, 0x00, "temporary data register"}, + {"adc1.ctrla", 0x0640, 1, -1, 0x00, "control register A"}, + {"adc1.ctrlb", 0x0641, 1, -1, 0x00, "control register B"}, + {"adc1.ctrlc", 0x0642, 1, -1, 0x00, "control register C"}, + {"adc1.ctrld", 0x0643, 1, -1, 0x00, "control register D"}, + {"adc1.ctrle", 0x0644, 1, -1, 0x00, "control register E"}, + {"adc1.ctrlf", 0x0645, 1, -1, 0x00, "control register F"}, + {"adc1.intctrl", 0x0646, 1, -1, 0x00, "interrupt control register"}, + {"adc1.intflags", 0x0647, 1, -1, 0x00, "interrupt flags register"}, + {"adc1.status", 0x0648, 1, -1, 0x00, "status register"}, + {"adc1.dbgctrl", 0x0649, 1, -1, 0x00, "debug control register"}, + {"adc1.command", 0x064a, 1, -1, 0x00, "command register"}, + {"adc1.muxpos", 0x064b, 1, -1, 0x00, "positive mux input register"}, + {"adc1.result", 0x064c, 2, -1, -1, "result register (32 bits)"}, + {"adc1.sample", 0x064e, 2, -1, 0x0000, "sample register (16 bits)"}, + {"adc1.winlt", 0x0650, 2, -1, -1, "window comparator low threshold register (16 bits)"}, + {"adc1.winht", 0x0652, 2, -1, -1, "window comparator high threshold register (16 bits)"}, + {"adc1.temp", 0x0654, 1, -1, 0x00, "temporary data register"}, + {"ac0.ctrla", 0x0680, 1, -1, 0x00, "control register A"}, + {"ac0.ctrlb", 0x0681, 1, -1, 0x00, "control register B"}, + {"ac0.muxctrl", 0x0682, 1, -1, 0x00, "mux control A register"}, + {"ac0.dacref", 0x0685, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac0.intctrl", 0x0686, 1, -1, 0x00, "interrupt control register"}, + {"ac0.status", 0x0687, 1, -1, 0x00, "status register"}, + {"ac1.ctrla", 0x0688, 1, -1, 0x00, "control register A"}, + {"ac1.ctrlb", 0x0689, 1, -1, 0x00, "control register B"}, + {"ac1.muxctrl", 0x068a, 1, -1, 0x00, "mux control A register"}, + {"ac1.dacref", 0x068d, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac1.intctrl", 0x068e, 1, -1, 0x00, "interrupt control register"}, + {"ac1.status", 0x068f, 1, -1, 0x00, "status register"}, + {"ac2.ctrla", 0x0690, 1, -1, 0x00, "control register A"}, + {"ac2.ctrlb", 0x0691, 1, -1, 0x00, "control register B"}, + {"ac2.muxctrl", 0x0692, 1, -1, 0x00, "mux control A register"}, + {"ac2.dacref", 0x0695, 1, -1, 0xff, "DAC voltage reference register"}, + {"ac2.intctrl", 0x0696, 1, -1, 0x00, "interrupt control register"}, + {"ac2.status", 0x0697, 1, -1, 0x00, "status register"}, + {"dac0.ctrla", 0x06a0, 1, -1, 0x00, "control register A"}, + {"dac0.data", 0x06a2, 2, -1, -1, "data register (16 bits)"}, + {"zcd0.ctrla", 0x06c0, 1, -1, 0x00, "control register A"}, + {"zcd0.intctrl", 0x06c2, 1, -1, 0x00, "interrupt control register"}, + {"zcd0.status", 0x06c3, 1, -1, 0x00, "status register"}, + {"zcd3.ctrla", 0x06d8, 1, -1, 0x00, "control register A"}, + {"zcd3.intctrl", 0x06da, 1, -1, 0x00, "interrupt control register"}, + {"zcd3.status", 0x06db, 1, -1, 0x00, "status register"}, + {"usart0.rxdatal", 0x0800, 1, -1, 0x00, "receive data low byte"}, + {"usart0.rxdatah", 0x0801, 1, -1, 0x00, "receive data high byte"}, + {"usart0.txdatal", 0x0802, 1, -1, 0x00, "transmit data low byte"}, + {"usart0.txdatah", 0x0803, 1, -1, 0x00, "transmit data high byte"}, + {"usart0.status", 0x0804, 1, -1, 0x20, "status register"}, + {"usart0.ctrla", 0x0805, 1, -1, 0x00, "control register A"}, + {"usart0.ctrlb", 0x0806, 1, -1, 0x00, "control register B"}, + {"usart0.ctrlc", 0x0807, 1, -1, 0x03, "control register C"}, + {"usart0.baud", 0x0808, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart0.ctrld", 0x080a, 1, -1, 0x00, "control register D"}, + {"usart0.dbgctrl", 0x080b, 1, -1, 0x00, "debug control register"}, + {"usart0.evctrl", 0x080c, 1, -1, 0x00, "event control register"}, + {"usart0.txplctrl", 0x080d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart0.rxplctrl", 0x080e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart1.rxdatal", 0x0820, 1, -1, 0x00, "receive data low byte"}, + {"usart1.rxdatah", 0x0821, 1, -1, 0x00, "receive data high byte"}, + {"usart1.txdatal", 0x0822, 1, -1, 0x00, "transmit data low byte"}, + {"usart1.txdatah", 0x0823, 1, -1, 0x00, "transmit data high byte"}, + {"usart1.status", 0x0824, 1, -1, 0x20, "status register"}, + {"usart1.ctrla", 0x0825, 1, -1, 0x00, "control register A"}, + {"usart1.ctrlb", 0x0826, 1, -1, 0x00, "control register B"}, + {"usart1.ctrlc", 0x0827, 1, -1, 0x03, "control register C"}, + {"usart1.baud", 0x0828, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart1.ctrld", 0x082a, 1, -1, 0x00, "control register D"}, + {"usart1.dbgctrl", 0x082b, 1, -1, 0x00, "debug control register"}, + {"usart1.evctrl", 0x082c, 1, -1, 0x00, "event control register"}, + {"usart1.txplctrl", 0x082d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart1.rxplctrl", 0x082e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"usart2.rxdatal", 0x0840, 1, -1, 0x00, "receive data low byte"}, + {"usart2.rxdatah", 0x0841, 1, -1, 0x00, "receive data high byte"}, + {"usart2.txdatal", 0x0842, 1, -1, 0x00, "transmit data low byte"}, + {"usart2.txdatah", 0x0843, 1, -1, 0x00, "transmit data high byte"}, + {"usart2.status", 0x0844, 1, -1, 0x20, "status register"}, + {"usart2.ctrla", 0x0845, 1, -1, 0x00, "control register A"}, + {"usart2.ctrlb", 0x0846, 1, -1, 0x00, "control register B"}, + {"usart2.ctrlc", 0x0847, 1, -1, 0x03, "control register C"}, + {"usart2.baud", 0x0848, 2, -1, 0x0000, "baud rate register (16 bits)"}, + {"usart2.ctrld", 0x084a, 1, -1, 0x00, "control register D"}, + {"usart2.dbgctrl", 0x084b, 1, -1, 0x00, "debug control register"}, + {"usart2.evctrl", 0x084c, 1, -1, 0x00, "event control register"}, + {"usart2.txplctrl", 0x084d, 1, -1, 0x00, "IRCOM transmitter pulse length control register"}, + {"usart2.rxplctrl", 0x084e, 1, -1, 0x00, "IRCOM receiver pulse length control register"}, + {"twi0.ctrla", 0x0900, 1, -1, 0x00, "control register A"}, + {"twi0.dualctrl", 0x0901, 1, -1, 0x00, "dual-mode control register"}, + {"twi0.dbgctrl", 0x0902, 1, -1, 0x00, "debug control register"}, + {"twi0.mctrla", 0x0903, 1, -1, 0x00, "host control A register"}, + {"twi0.mctrlb", 0x0904, 1, -1, 0x00, "host control B register"}, + {"twi0.hstatus", 0x0905, 1, -1, 0x00, "host status register"}, + {"twi0.mbaud", 0x0906, 1, -1, 0x00, "host baud rate register"}, + {"twi0.haddr", 0x0907, 1, -1, 0x00, "host address register"}, + {"twi0.hdata", 0x0908, 1, -1, 0x00, "host data register"}, + {"twi0.sctrla", 0x0909, 1, -1, 0x00, "client control A register"}, + {"twi0.sctrlb", 0x090a, 1, -1, 0x00, "client control B register"}, + {"twi0.sstatus", 0x090b, 1, -1, 0x00, "client status register"}, + {"twi0.saddr", 0x090c, 1, -1, 0x00, "client address register"}, + {"twi0.sdata", 0x090d, 1, -1, 0x00, "client data register"}, + {"twi0.saddrmask", 0x090e, 1, -1, 0x00, "client address mask register"}, + {"twi1.ctrla", 0x0920, 1, -1, 0x00, "control register A"}, + {"twi1.dualctrl", 0x0921, 1, -1, 0x00, "dual-mode control register"}, + {"twi1.dbgctrl", 0x0922, 1, -1, 0x00, "debug control register"}, + {"twi1.mctrla", 0x0923, 1, -1, 0x00, "host control A register"}, + {"twi1.mctrlb", 0x0924, 1, -1, 0x00, "host control B register"}, + {"twi1.hstatus", 0x0925, 1, -1, 0x00, "host status register"}, + {"twi1.mbaud", 0x0926, 1, -1, 0x00, "host baud rate register"}, + {"twi1.haddr", 0x0927, 1, -1, 0x00, "host address register"}, + {"twi1.hdata", 0x0928, 1, -1, 0x00, "host data register"}, + {"twi1.sctrla", 0x0929, 1, -1, 0x00, "client control A register"}, + {"twi1.sctrlb", 0x092a, 1, -1, 0x00, "client control B register"}, + {"twi1.sstatus", 0x092b, 1, -1, 0x00, "client status register"}, + {"twi1.saddr", 0x092c, 1, -1, 0x00, "client address register"}, + {"twi1.sdata", 0x092d, 1, -1, 0x00, "client data register"}, + {"twi1.saddrmask", 0x092e, 1, -1, 0x00, "client address mask register"}, + {"spi0.ctrla", 0x0940, 1, -1, 0x00, "control register A"}, + {"spi0.ctrlb", 0x0941, 1, -1, 0x00, "control register B"}, + {"spi0.intctrl", 0x0942, 1, -1, 0x00, "interrupt control register"}, + {"spi0.intflags", 0x0943, 1, -1, 0x00, "interrupt flags register"}, + {"spi0.data", 0x0944, 1, -1, -1, "data register"}, + {"spi1.ctrla", 0x0960, 1, -1, 0x00, "control register A"}, + {"spi1.ctrlb", 0x0961, 1, -1, 0x00, "control register B"}, + {"spi1.intctrl", 0x0962, 1, -1, 0x00, "interrupt control register"}, + {"spi1.intflags", 0x0963, 1, -1, 0x00, "interrupt flags register"}, + {"spi1.data", 0x0964, 1, -1, -1, "data register"}, + {"tca0.ctrla", 0x0a00, 1, -1, 0x00, "control register A"}, + {"tca0.ctrlb", 0x0a01, 1, -1, 0x00, "control register B"}, + {"tca0.ctrlc", 0x0a02, 1, -1, 0x00, "control register C"}, + {"tca0.ctrld", 0x0a03, 1, -1, 0x00, "control register D"}, + {"tca0.ctrleclr", 0x0a04, 1, -1, 0x00, "control register E clear"}, + {"tca0.ctrleset", 0x0a05, 1, -1, 0x00, "control register E set"}, + {"tca0.ctrlfclr", 0x0a06, 1, -1, 0x00, "control register F clear"}, + {"tca0.ctrlfset", 0x0a07, 1, -1, 0x00, "control register F set"}, + {"tca0.evctrl", 0x0a09, 1, -1, 0x00, "event control register"}, + {"tca0.intctrl", 0x0a0a, 1, -1, 0x00, "interrupt control register"}, + {"tca0.intflags", 0x0a0b, 1, -1, 0x00, "interrupt flags register"}, + {"tca0.dbgctrl", 0x0a0e, 1, -1, 0x00, "debug control register"}, + {"tca0.temp", 0x0a0f, 1, -1, -1, "temporary register for 16-bit access"}, + {"tca0.cnt", 0x0a20, 2, -1, -1, "counter (16 bits)"}, + {"tca0.lcnt", 0x0a20, 1, -1, -1, "low byte counter"}, + {"tca0.hcnt", 0x0a21, 1, -1, -1, "high byte counter"}, + {"tca0.per", 0x0a26, 2, -1, 0xffff, "period register (16 bits)"}, + {"tca0.lper", 0x0a26, 1, -1, 0xff, "low byte period register"}, + {"tca0.hper", 0x0a27, 1, -1, 0xff, "high byte period register"}, + {"tca0.cmp0", 0x0a28, 2, -1, -1, "compare 0 register (16 bits)"}, + {"tca0.lcmp0", 0x0a28, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp0", 0x0a29, 1, -1, -1, "high byte compare register 0"}, + {"tca0.cmp1", 0x0a2a, 2, -1, -1, "compare 1 register (16 bits)"}, + {"tca0.lcmp1", 0x0a2a, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp1", 0x0a2b, 1, -1, -1, "high byte compare register 1"}, + {"tca0.cmp2", 0x0a2c, 2, -1, -1, "compare 2 register (16 bits)"}, + {"tca0.lcmp2", 0x0a2c, 1, -1, -1, "low byte compare register"}, + {"tca0.hcmp2", 0x0a2d, 1, -1, -1, "high byte compare register 2"}, + {"tca0.perbuf", 0x0a36, 2, -1, 0xffff, "period buffer register (16 bits)"}, + {"tca0.cmp0buf", 0x0a38, 2, -1, -1, "compare 0 buffer register (16 bits)"}, + {"tca0.cmp1buf", 0x0a3a, 2, -1, -1, "compare 1 buffer register (16 bits)"}, + {"tca0.cmp2buf", 0x0a3c, 2, -1, -1, "compare 2 buffer register (16 bits)"}, + {"tcb0.ctrla", 0x0b00, 1, -1, 0x00, "control register A"}, + {"tcb0.ctrlb", 0x0b01, 1, -1, 0x00, "control register B"}, + {"tcb0.evctrl", 0x0b04, 1, -1, 0x00, "event control register"}, + {"tcb0.intctrl", 0x0b05, 1, -1, 0x00, "interrupt control register"}, + {"tcb0.intflags", 0x0b06, 1, -1, 0x00, "interrupt flags register"}, + {"tcb0.status", 0x0b07, 1, -1, 0x00, "status register"}, + {"tcb0.dbgctrl", 0x0b08, 1, -1, 0x00, "debug control register"}, + {"tcb0.temp", 0x0b09, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb0.cnt", 0x0b0a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb0.ccmp", 0x0b0c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb1.ctrla", 0x0b10, 1, -1, 0x00, "control register A"}, + {"tcb1.ctrlb", 0x0b11, 1, -1, 0x00, "control register B"}, + {"tcb1.evctrl", 0x0b14, 1, -1, 0x00, "event control register"}, + {"tcb1.intctrl", 0x0b15, 1, -1, 0x00, "interrupt control register"}, + {"tcb1.intflags", 0x0b16, 1, -1, 0x00, "interrupt flags register"}, + {"tcb1.status", 0x0b17, 1, -1, 0x00, "status register"}, + {"tcb1.dbgctrl", 0x0b18, 1, -1, 0x00, "debug control register"}, + {"tcb1.temp", 0x0b19, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb1.cnt", 0x0b1a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb1.ccmp", 0x0b1c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb2.ctrla", 0x0b20, 1, -1, 0x00, "control register A"}, + {"tcb2.ctrlb", 0x0b21, 1, -1, 0x00, "control register B"}, + {"tcb2.evctrl", 0x0b24, 1, -1, 0x00, "event control register"}, + {"tcb2.intctrl", 0x0b25, 1, -1, 0x00, "interrupt control register"}, + {"tcb2.intflags", 0x0b26, 1, -1, 0x00, "interrupt flags register"}, + {"tcb2.status", 0x0b27, 1, -1, 0x00, "status register"}, + {"tcb2.dbgctrl", 0x0b28, 1, -1, 0x00, "debug control register"}, + {"tcb2.temp", 0x0b29, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb2.cnt", 0x0b2a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb2.ccmp", 0x0b2c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcb3.ctrla", 0x0b30, 1, -1, 0x00, "control register A"}, + {"tcb3.ctrlb", 0x0b31, 1, -1, 0x00, "control register B"}, + {"tcb3.evctrl", 0x0b34, 1, -1, 0x00, "event control register"}, + {"tcb3.intctrl", 0x0b35, 1, -1, 0x00, "interrupt control register"}, + {"tcb3.intflags", 0x0b36, 1, -1, 0x00, "interrupt flags register"}, + {"tcb3.status", 0x0b37, 1, -1, 0x00, "status register"}, + {"tcb3.dbgctrl", 0x0b38, 1, -1, 0x00, "debug control register"}, + {"tcb3.temp", 0x0b39, 1, -1, -1, "temporary register for 16-bit access"}, + {"tcb3.cnt", 0x0b3a, 2, -1, 0x0000, "counter (16 bits)"}, + {"tcb3.ccmp", 0x0b3c, 2, -1, -1, "compare or capture register (16 bits)"}, + {"tcd0.ctrla", 0x0b80, 1, -1, 0x00, "control register A"}, + {"tcd0.ctrlb", 0x0b81, 1, -1, 0x00, "control register B"}, + {"tcd0.ctrlc", 0x0b82, 1, -1, 0x00, "control register C"}, + {"tcd0.ctrld", 0x0b83, 1, -1, 0x00, "control register D"}, + {"tcd0.ctrle", 0x0b84, 1, -1, 0x00, "control register E"}, + {"tcd0.evctrla", 0x0b88, 1, -1, 0x00, "event control register A"}, + {"tcd0.evctrlb", 0x0b89, 1, -1, 0x00, "event control register B"}, + {"tcd0.intctrl", 0x0b8c, 1, -1, 0x00, "interrupt control register"}, + {"tcd0.intflags", 0x0b8d, 1, -1, 0x00, "interrupt flags register"}, + {"tcd0.status", 0x0b8e, 1, -1, 0x00, "status register"}, + {"tcd0.inputctrla", 0x0b90, 1, -1, 0x00, "input control register A"}, + {"tcd0.inputctrlb", 0x0b91, 1, -1, 0x00, "input control register B"}, + {"tcd0.faultctrl", 0x0b92, 1, -1, 0x00, "fault control register"}, + {"tcd0.dlyctrl", 0x0b94, 1, -1, 0x00, "delay control register"}, + {"tcd0.dlyval", 0x0b95, 1, -1, 0x00, "delay value register"}, + {"tcd0.ditctrl", 0x0b98, 1, -1, 0x00, "dither control A register"}, + {"tcd0.ditval", 0x0b99, 1, -1, 0x00, "dither value register"}, + {"tcd0.dbgctrl", 0x0b9e, 1, -1, 0x00, "debug control register"}, + {"tcd0.capturea", 0x0ba2, 2, -1, 0x0000, "capture A register (16 bits)"}, + {"tcd0.captureb", 0x0ba4, 2, -1, 0x0000, "capture B register (16 bits)"}, + {"tcd0.cmpaset", 0x0ba8, 2, -1, 0x0000, "compare A set register (16 bits)"}, + {"tcd0.cmpaclr", 0x0baa, 2, -1, 0x0000, "compare A clear register (16 bits)"}, + {"tcd0.cmpbset", 0x0bac, 2, -1, 0x0000, "compare B set register (16 bits)"}, + {"tcd0.cmpbclr", 0x0bae, 2, -1, 0x0000, "compare B clear register (16 bits)"}, + {"swdt.ctrla", 0x0e20, 1, -1, 0x00, "control register A"}, + {"swdt.ctrlb", 0x0e21, 1, -1, 0x00, "control register B"}, + {"swdt.intctrl", 0x0e22, 1, -1, 0x00, "interrupt control register"}, + {"swdt.intflags", 0x0e23, 1, -1, 0x00, "interrupt flags register"}, + {"swdt.cnt", 0x0e24, 4, -1, 0x00000000, "counter (32 bits)"}, + {"swdt.reset", 0x0e28, 4, -1, 0x00000000, "counter reset register (32 bits)"}, + {"swdt.window", 0x0e2c, 2, -1, 0x0000, "counter window register (16 bits)"}, + {"swdt.command", 0x0e2e, 1, -1, 0x00, "command register"}, + {"ramctrl.ctrla", 0x0e30, 1, -1, 0x00, "control register A"}, + {"ramctrl.intflags", 0x0e31, 1, -1, 0x00, "interrupt flags register"}, + {"ramctrl.addr", 0x0e32, 2, -1, 0x0000, "address register (16 bits)"}, + {"ramctrl.syndrome", 0x0e34, 1, -1, 0x00, "ECC syndrome register"}, + {"errctrl.ctrla", 0x0e40, 1, -1, 0x01, "control register A"}, + {"errctrl.statusa", 0x0e41, 1, -1, -1, "status A register"}, + {"errctrl.timeout", 0x0e42, 1, -1, 0xff, "timeout value register"}, + {"errctrl.timecnt", 0x0e43, 1, -1, 0xff, "timeout counter register"}, + {"errctrl.cause", 0x0e44, 1, -1, -1, "reset cause register"}, + {"errctrl.escvregfail", 0x0e50, 1, -1, 0x82, "error source control VREGFAIL register"}, + {"errctrl.escbuserr", 0x0e51, 1, -1, 0x82, "error source control BUSERR register"}, + {"errctrl.escram2", 0x0e52, 1, -1, 0x82, "error source control RAM2 register"}, + {"errctrl.escflash2", 0x0e53, 1, -1, 0x82, "error source control FLASH2 register"}, + {"errctrl.escopc", 0x0e54, 1, -1, 0x82, "error source control OPC register"}, + {"errctrl.escsplim", 0x0e55, 1, -1, 0x82, "error source control SPLIM register"}, + {"errctrl.escram1", 0x0e56, 1, -1, 0x82, "error source control RAM1 register"}, + {"errctrl.escflash1", 0x0e57, 1, -1, 0x82, "error source control FLASH1 register"}, + {"errctrl.escvregwarn", 0x0e58, 1, -1, 0x82, "error source control VREGWARN register"}, + {"errctrl.esccfd0", 0x0e59, 1, -1, 0x82, "error source control CFD0 register"}, + {"errctrl.esccfd1", 0x0e5a, 1, -1, 0x82, "error source control CFD1 register"}, + {"errctrl.esccfm0", 0x0e5b, 1, -1, 0x82, "error source control CFM0 register"}, + {"errctrl.esccfm1", 0x0e5c, 1, -1, 0x82, "error source control CFM1 register"}, + {"errctrl.escswdt", 0x0e5d, 1, -1, 0x82, "error source control SWDT register"}, + {"errctrl.esceeprom", 0x0e5e, 1, -1, 0x82, "error source control EEPROM register"}, + {"errctrl.escevsys0", 0x0e5f, 1, -1, 0x82, "error source control EVSYS0 register"}, + {"errctrl.escevsys1", 0x0e60, 1, -1, 0x82, "error source control EVSYS1 register"}, + {"errctrl.esf", 0x0e70, 4, -1, -1, "error status flags register (32 bits)"}, + {"errctrl.esftest", 0x0e74, 4, -1, 0x00000000, "error status flag test injection register (32 bits)"}, + {"syscfg.revid", 0x0f01, 1, -1, -1, "revision ID register"}, + {"nvmctrl.ctrla", 0x1000, 1, -1, 0x00, "control register A"}, + {"nvmctrl.ctrlb", 0x1001, 1, -1, 0x30, "control register B"}, + {"nvmctrl.ctrlc", 0x1002, 1, -1, 0x00, "control register C"}, + {"nvmctrl.ctrld", 0x1003, 1, -1, 0x00, "control register D"}, + {"nvmctrl.intctrla", 0x1004, 1, -1, 0x00, "interrupt control register A"}, + {"nvmctrl.intflagsa", 0x1005, 1, -1, 0x00, "interrupt flags A register"}, + {"nvmctrl.intflagsb", 0x1006, 1, -1, -1, "interrupt flags B register"}, + {"nvmctrl.status", 0x1007, 1, -1, 0x00, "status register"}, + {"nvmctrl.data", 0x1008, 4, -1, 0x00000000, "data register (32 bits)"}, + {"nvmctrl.addr", 0x100c, 4, -1, -1, "address register (32 bits)"}, + {"nvmctrl.parity", 0x1010, 1, -1, -1, "ECC parity register"}, + {"nvmctrl.syndrome", 0x1011, 1, -1, -1, "ECC syndrome register"}, +}; + // Ports -/* - * ATmega328 ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA - * ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328P ATA6612C ATA6613C ATA6614Q - */ -const Port_bits ports_atmega328[3] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0x7f, 8, 0x7f, 6, 0x7f,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, -}; - -/* - * ATmega16M1 AT90PWM2 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 AT90PWM2B AT90PWM3 - * AT90PWM3B AT90PWM216 AT90PWM316 - */ -const Port_bits ports_atmega16m1[4] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0x07, 14, 0x07, 12, 0x07,}, -}; - -// ATmega16HVA2 ATmega8HVA ATmega16HVA -const Port_bits ports_atmega16hva2[3] = { - { 'A', 1, 0x03, 2, 0x03, 0, 0x03,}, - { 'B', 4, 0x0f, 5, 0x0f, 3, 0x0f,}, - { 'C', -1, -1, 8, 0x01, 6, 0x01,}, -}; - -// ATmega32HVBrevB ATmega16HVB ATmega16HVBrevB ATmega32HVB -const Port_bits ports_atmega32hvbrevb[3] = { - { 'A', 1, 0x0f, 2, 0x0f, 0, 0x0f,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', -1, -1, 8, 0x3f, 6, 0x1f,}, -}; - -// ATmega64HVE ATmega64HVE2 -const Port_bits ports_atmega64hve[2] = { - { 'A', 1, 0x03, 2, 0x03, 0, 0x03,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, -}; - -// ATmega328PB ATmega48PB ATmega88PB ATmega168PB -const Port_bits ports_atmega328pb[4] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0x7f, 8, 0x7f, 6, 0x7f,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0x0f, 14, 0x0f, 12, 0x0f,}, -}; - -// ATmega8515 ATmega161 ATmega162 -const Port_bits ports_atmega8515[5] = { - { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, - { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, - { 'C', 20, 0xff, 21, 0xff, 19, 0xff,}, - { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, - { 'E', 6, 0x07, 7, 0x07, 5, 0x07,}, -}; - -// ATtiny102 -const Port_bits ports_attiny102[2] = { - { 'A', 1, 0x07, 2, 0x07, 0, 0x07,}, - { 'B', 5, 0x0e, 6, 0x0e, 4, 0x0e,}, -}; - -// ATtiny28 -const Port_bits ports_attiny28[3] = { - { 'A', 26, 0x0b, 27, 0x0f, 25, 0x0b,}, - { 'B', -1, -1, -1, -1, 22, 0xff,}, - { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, -}; - -// ATtiny441 ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A ATtiny841 -const Port_bits ports_attiny441[2] = { - { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, - { 'B', 23, 0x0f, 24, 0x0f, 22, 0x0f,}, -}; - -// AT90PWM81 AT90PWM1 AT90PWM161 -const Port_bits ports_at90pwm81[3] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0x07, 14, 0x07, 12, 0x07,}, -}; - -// AT90CAN128 ATmega165 AT90CAN32 AT90CAN64 -const Port_bits ports_at90can128[7] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, - { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, - { 'G', 19, 0x1f, 20, 0x1f, 18, 0x1f,}, -}; - -// AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 AT90USB82 -const Port_bits ports_at90usb162[3] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xf7, 8, 0xf7, 6, 0xf7,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, -}; - -// AT90S1200 AT90S2313 -const Port_bits ports_at90s1200[2] = { - { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, - { 'D', 17, 0x7f, 18, 0x7f, 16, 0x7f,}, -}; - -// ATA5790 ATA5790N ATA5791 -const Port_bits ports_ata5790[3] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, -}; - -// ATA6285 ATA5702M322 ATA6286 -const Port_bits ports_ata6285[3] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0x07, 8, 0x07, 6, 0x07,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, -}; - -// ATxmega16E5 ATxmega8E5 ATxmega32E5 -const Port_bits ports_atxmega16e5[4] = { - { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, - { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, - { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, - { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, -}; - -/* - * ATxmega128A3U ATxmega32C3 ATxmega32D3 ATxmega64A3U ATxmega64C3 ATxmega64D3 ATxmega128C3 - * ATxmega128D3 ATxmega192A3U ATxmega192D3 ATxmega256A3U ATxmega256C3 ATxmega256D3 ATxmega384C3 - * ATxmega384D3 - */ -const Port_bits ports_atxmega128a3u[7] = { - { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, - { 'B', 0x620, 0xff, 0x624, 0xff, 0x628, 0xff,}, - { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, - { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, - { 'E', 0x680, 0xff, 0x684, 0xff, 0x688, 0xff,}, - { 'F', 0x6a0, 0xff, 0x6a4, 0xff, 0x6a8, 0xff,}, - { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, -}; - -/* - * ATtiny204 ATtiny1624 ATtiny214 ATtiny404 ATtiny414 ATtiny424 ATtiny804 ATtiny814 ATtiny824 - * ATtiny1604 ATtiny1614 ATtiny3224 - */ -const Port_bits ports_attiny204[2] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'B', 0x004, 0x0f, 0x005, 0x0f, 0x006, 0x0f,}, -}; - -// AVR32DD14 AVR16DD14 AVR64DD14 -const Port_bits ports_avr32dd14[4] = { - { 'A', 0x000, 0x03, 0x001, 0x03, 0x002, 0x03,}, - { 'C', 0x008, 0x0e, 0x009, 0x0e, 0x00a, 0x0e,}, - { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, - { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, -}; - -// AVR64EA48 AVR16EA48 AVR32EA48 -const Port_bits ports_avr64ea48[6] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'B', 0x004, 0x3f, 0x005, 0x3f, 0x006, 0x3f,}, - { 'C', 0x008, 0xff, 0x009, 0xff, 0x00a, 0xff,}, - { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, - { 'E', 0x010, 0x0f, 0x011, 0x0f, 0x012, 0x0f,}, - { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, -}; - // ATtiny4 ATtiny5 ATtiny9 ATtiny10 const Port_bits ports_attiny4[1] = { { 'B', 1, 0x0f, 2, 0x0f, 0, 0x0f,}, @@ -60239,6 +60075,101 @@ const Port_bits ports_attiny40[3] = { { 'C', 28, 0x3f, 29, 0x3f, 27, 0x3f,}, }; +// ATtiny102 +const Port_bits ports_attiny102[2] = { + { 'A', 1, 0x07, 2, 0x07, 0, 0x07,}, + { 'B', 5, 0x0e, 6, 0x0e, 4, 0x0e,}, +}; + +// AT90S1200 AT90S2313 +const Port_bits ports_at90s1200[2] = { + { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, + { 'D', 17, 0x7f, 18, 0x7f, 16, 0x7f,}, +}; + +// AT90S2323 +const Port_bits ports_at90s2323[1] = { + { 'B', 23, 0x07, 24, 0x07, 22, 0x07,}, +}; + +// AT90S2333 AT90S4433 +const Port_bits ports_at90s2333[3] = { + { 'B', 23, 0x3f, 24, 0x3f, 22, 0x3f,}, + { 'C', 20, 0x3f, 21, 0x3f, 19, 0x3f,}, + { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, +}; + +// AT90S2343 ATtiny22 +const Port_bits ports_at90s2343[1] = { + { 'B', 23, 0x1f, 24, 0x1f, 22, 0x1f,}, +}; + +/* + * AT90S4414 AT90S4434 AT90S8515 AT90S8535 ATmega16 ATmega16A ATmega32 ATmega32A ATmega163 + * ATmega323 ATmega8535 + */ +const Port_bits ports_at90s4414[4] = { + { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, + { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, + { 'C', 20, 0xff, 21, 0xff, 19, 0xff,}, + { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, +}; + +// AT90CAN32 AT90CAN64 AT90CAN128 ATmega165 +const Port_bits ports_at90can32[7] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, + { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, + { 'G', 19, 0x1f, 20, 0x1f, 18, 0x1f,}, +}; + +// AT90PWM1 AT90PWM81 AT90PWM161 +const Port_bits ports_at90pwm1[3] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0x07, 14, 0x07, 12, 0x07,}, +}; + +/* + * AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 ATmega32C1 ATmega64C1 ATmega16M1 + * ATmega32M1 ATmega64M1 ATmegaS64M1 + */ +const Port_bits ports_at90pwm2[4] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0x07, 14, 0x07, 12, 0x07,}, +}; + +// AT90USB82 AT90USB162 ATmega8U2 ATmega16U2 ATmega32U2 +const Port_bits ports_at90usb82[3] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xf7, 8, 0xf7, 6, 0xf7,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, +}; + +// AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 ATmega32U6 +const Port_bits ports_at90usb646[6] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, + { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, +}; + +// AT90SCR100 +const Port_bits ports_at90scr100[5] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, +}; + // ATtiny11 ATtiny12 ATtiny15 const Port_bits ports_attiny11[1] = { { 'B', 23, 0x1f, 24, 0x1f, 22, 0x3f,}, @@ -60249,17 +60180,31 @@ const Port_bits ports_attiny13[1] = { { 'B', 23, 0x3f, 24, 0x3f, 22, 0x3f,}, }; -// ATtiny22 AT90S2343 -const Port_bits ports_attiny22[1] = { - { 'B', 23, 0x1f, 24, 0x1f, 22, 0x1f,}, -}; - -// ATtiny26 ATtiny43U ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A -const Port_bits ports_attiny26[2] = { +// ATtiny43U ATtiny26 ATtiny261 ATtiny261A ATtiny461 ATtiny461A ATtiny861 ATtiny861A +const Port_bits ports_attiny43u[2] = { { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, }; +// ATtiny24 ATtiny24A ATtiny44 ATtiny44A ATtiny84 ATtiny84A ATtiny441 ATtiny841 +const Port_bits ports_attiny24[2] = { + { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, + { 'B', 23, 0x0f, 24, 0x0f, 22, 0x0f,}, +}; + +// ATtiny87 ATtiny167 ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 +const Port_bits ports_attiny87[2] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, +}; + +// ATtiny28 +const Port_bits ports_attiny28[3] = { + { 'A', 26, 0x0b, 27, 0x0f, 25, 0x0b,}, + { 'B', -1, -1, -1, -1, 22, 0xff,}, + { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, +}; + // ATtiny48 ATtiny88 const Port_bits ports_attiny48[4] = { { 'A', 13, 0x0f, 14, 0x0f, 12, 0x0f,}, @@ -60268,12 +60213,6 @@ const Port_bits ports_attiny48[4] = { { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, }; -// ATtiny87 ATtiny167 ATA5272 ATA5505 ATA6616C ATA6617C ATA664251 -const Port_bits ports_attiny87[2] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, -}; - // ATtiny828 const Port_bits ports_attiny828[4] = { { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, @@ -60303,37 +60242,7 @@ const Port_bits ports_atmega8[3] = { { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, }; -/* - * ATmega16 ATmega16A ATmega32 ATmega32A ATmega163 ATmega323 ATmega8535 AT90S4414 AT90S4434 - * AT90S8515 AT90S8535 - */ -const Port_bits ports_atmega16[4] = { - { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, - { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, - { 'C', 20, 0xff, 21, 0xff, 19, 0xff,}, - { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, -}; - -// ATmega16U4 ATmega32U4 -const Port_bits ports_atmega16u4[5] = { - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xc0, 8, 0xc0, 6, 0xc0,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0x44, 14, 0x44, 12, 0x44,}, - { 'F', 16, 0xf3, 17, 0xf3, 15, 0xf3,}, -}; - -// ATmega32U6 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 -const Port_bits ports_atmega32u6[6] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, - { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, -}; - -// ATmega64 ATmega64A ATmega128 ATmegaS128 ATmega128A +// ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 const Port_bits ports_atmega64[7] = { { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, @@ -60344,73 +60253,6 @@ const Port_bits ports_atmega64[7] = { { 'G', 68, 0x1f, 69, 0x1f, 67, 0x1f,}, }; -/* - * ATmega64RFR2 ATmega128RFA1 ATmega128RFR2 ATmega169PA ATmega256RFR2 ATmega644RFR2 ATmega1281 - * ATmega1284RFR2 ATmega2561 ATmega2564RFR2 - */ -const Port_bits ports_atmega64rfr2[7] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, - { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, - { 'G', 19, 0x3f, 20, 0x3f, 18, 0x3f,}, -}; - -// ATmega103 -const Port_bits ports_atmega103[6] = { - { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, - { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, - { 'C', -1, -1, 21, 0xff, -1, -1,}, - { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, - { 'E', 2, 0xff, 3, 0xff, 1, 0xff,}, - { 'F', -1, -1, -1, -1, 0, 0xff,}, -}; - -/* - * ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644 ATmega644A - * ATmega644P ATmega644PA ATmega1284 ATmega1284P - */ -const Port_bits ports_atmega164a[4] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, -}; - -/* - * ATmega165A ATmega165P ATmega165PA ATmega169 ATmega169A ATmega169P ATmega325 ATmega325A - * ATmega325P ATmega325PA ATmega329 ATmega329A ATmega329P ATmega329PA ATmega645 ATmega645A - * ATmega645P ATmega649 ATmega649A ATmega649P - */ -const Port_bits ports_atmega165a[7] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, - { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, - { 'G', 19, 0x1f, 20, 0x1f, 18, 0x3f,}, -}; - -// ATmega324PB -const Port_bits ports_atmega324pb[5] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, - { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0x7f, 14, 0x7f, 12, 0x7f,}, -}; - -// ATmega406 -const Port_bits ports_atmega406[4] = { - { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, - { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', -1, -1, 8, 0x01, -1, -1,}, - { 'D', 10, 0x03, 11, 0x03, 9, 0x03,}, -}; - // ATmega640 ATmega1280 ATmega2560 const Port_bits ports_atmega640[11] = { { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, @@ -60427,8 +60269,75 @@ const Port_bits ports_atmega640[11] = { }; /* - * ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega3290 ATmega3290A ATmega3290P ATmega3290PA - * ATmega6450 ATmega6450A ATmega6450P ATmega6490 ATmega6490A ATmega6490P + * ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega1281 ATmega2561 ATmega644RFR2 + * ATmega1284RFR2 ATmega2564RFR2 ATmega169PA + */ +const Port_bits ports_atmega128rfa1[7] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, + { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, + { 'G', 19, 0x3f, 20, 0x3f, 18, 0x3f,}, +}; + +// ATmega16U4 ATmega32U4 +const Port_bits ports_atmega16u4[5] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xc0, 8, 0xc0, 6, 0xc0,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0x44, 14, 0x44, 12, 0x44,}, + { 'F', 16, 0xf3, 17, 0xf3, 15, 0xf3,}, +}; + +// ATmega161 ATmega162 ATmega8515 +const Port_bits ports_atmega161[5] = { + { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, + { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, + { 'C', 20, 0xff, 21, 0xff, 19, 0xff,}, + { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, + { 'E', 6, 0x07, 7, 0x07, 5, 0x07,}, +}; + +/* + * ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644 ATmega644A + * ATmega644P ATmega644PA ATmega1284 ATmega1284P + */ +const Port_bits ports_atmega164a[4] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, +}; + +// ATmega324PB +const Port_bits ports_atmega324pb[5] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0x7f, 14, 0x7f, 12, 0x7f,}, +}; + +/* + * ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA ATmega645 + * ATmega645A ATmega645P ATmega169 ATmega169A ATmega169P ATmega329 ATmega329A ATmega329P + * ATmega329PA ATmega649 ATmega649A ATmega649P + */ +const Port_bits ports_atmega165a[7] = { + { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, + { 'F', 16, 0xff, 17, 0xff, 15, 0xff,}, + { 'G', 19, 0x1f, 20, 0x1f, 18, 0x3f,}, +}; + +/* + * ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 ATmega6450A ATmega6450P ATmega3290 + * ATmega3290A ATmega3290P ATmega3290PA ATmega6490 ATmega6490A ATmega6490P */ const Port_bits ports_atmega3250[9] = { { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, @@ -60442,25 +60351,67 @@ const Port_bits ports_atmega3250[9] = { { 'J', 188, 0x7f, 189, 0x7f, 187, 0x7f,}, }; -// AT90SCR100 -const Port_bits ports_at90scr100[5] = { +/* + * ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA ATmega168 + * ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P ATA6612C ATA6613C ATA6614Q + */ +const Port_bits ports_atmega48[3] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0x7f, 8, 0x7f, 6, 0x7f,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, +}; + +// ATmega48PB ATmega88PB ATmega168PB ATmega328PB +const Port_bits ports_atmega48pb[4] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0x7f, 8, 0x7f, 6, 0x7f,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, + { 'E', 13, 0x0f, 14, 0x0f, 12, 0x0f,}, +}; + +// ATmega103 +const Port_bits ports_atmega103[6] = { + { 'A', 26, 0xff, 27, 0xff, 25, 0xff,}, + { 'B', 23, 0xff, 24, 0xff, 22, 0xff,}, + { 'C', -1, -1, 21, 0xff, -1, -1,}, + { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, + { 'E', 2, 0xff, 3, 0xff, 1, 0xff,}, + { 'F', -1, -1, -1, -1, 0, 0xff,}, +}; + +// ATmega8HVA ATmega16HVA ATmega16HVA2 +const Port_bits ports_atmega8hva[3] = { + { 'A', 1, 0x03, 2, 0x03, 0, 0x03,}, + { 'B', 4, 0x0f, 5, 0x0f, 3, 0x0f,}, + { 'C', -1, -1, 8, 0x01, 6, 0x01,}, +}; + +// ATmega16HVB ATmega16HVBrevB ATmega32HVB ATmega32HVBrevB +const Port_bits ports_atmega16hvb[3] = { + { 'A', 1, 0x0f, 2, 0x0f, 0, 0x0f,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', -1, -1, 8, 0x3f, 6, 0x1f,}, +}; + +// ATmega64HVE ATmega64HVE2 +const Port_bits ports_atmega64hve[2] = { + { 'A', 1, 0x03, 2, 0x03, 0, 0x03,}, + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, +}; + +// ATmega406 +const Port_bits ports_atmega406[4] = { { 'A', 1, 0xff, 2, 0xff, 0, 0xff,}, { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, - { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'C', -1, -1, 8, 0x01, -1, -1,}, + { 'D', 10, 0x03, 11, 0x03, 9, 0x03,}, +}; + +// ATA5702M322 ATA6285 ATA6286 +const Port_bits ports_ata5702m322[3] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0x07, 8, 0x07, 6, 0x07,}, { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, - { 'E', 13, 0xff, 14, 0xff, 12, 0xff,}, -}; - -// AT90S2323 -const Port_bits ports_at90s2323[1] = { - { 'B', 23, 0x07, 24, 0x07, 22, 0x07,}, -}; - -// AT90S2333 AT90S4433 -const Port_bits ports_at90s2333[3] = { - { 'B', 23, 0x3f, 24, 0x3f, 22, 0x3f,}, - { 'C', 20, 0x3f, 21, 0x3f, 19, 0x3f,}, - { 'D', 17, 0xff, 18, 0xff, 16, 0xff,}, }; // ATA5782 ATA5831 ATA8210 ATA8510 @@ -60469,6 +60420,13 @@ const Port_bits ports_ata5782[2] = { { 'C', 9, 0x3f, 10, 0x3f, 8, 0x3f,}, }; +// ATA5790 ATA5790N ATA5791 +const Port_bits ports_ata5790[3] = { + { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, + { 'C', 7, 0xff, 8, 0xff, 6, 0xff,}, + { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, +}; + // ATA5795 const Port_bits ports_ata5795[3] = { { 'B', 4, 0xff, 5, 0xff, 3, 0xff,}, @@ -60483,19 +60441,6 @@ const Port_bits ports_ata6289[3] = { { 'D', 10, 0xff, 11, 0xff, 9, 0xff,}, }; -/* - * ATxmega16A4U ATxmega16C4 ATxmega16D4 ATxmega32A4U ATxmega32C4 ATxmega32D4 ATxmega64A4U - * ATxmega64D4 ATxmega128A4U ATxmega128D4 - */ -const Port_bits ports_atxmega16a4u[6] = { - { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, - { 'B', 0x620, 0x0f, 0x624, 0x0f, 0x628, 0x0f,}, - { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, - { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, - { 'E', 0x680, 0x0f, 0x684, 0x0f, 0x688, 0x0f,}, - { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, -}; - // ATxmega64A1U ATxmega128A1U const Port_bits ports_atxmega64a1u[11] = { { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, @@ -60511,6 +60456,45 @@ const Port_bits ports_atxmega64a1u[11] = { { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, }; +/* + * ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3U ATxmega32C3 ATxmega64C3 ATxmega128C3 + * ATxmega256C3 ATxmega384C3 ATxmega32D3 ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 + * ATxmega384D3 + */ +const Port_bits ports_atxmega64a3u[7] = { + { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, + { 'B', 0x620, 0xff, 0x624, 0xff, 0x628, 0xff,}, + { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, + { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, + { 'E', 0x680, 0xff, 0x684, 0xff, 0x688, 0xff,}, + { 'F', 0x6a0, 0xff, 0x6a4, 0xff, 0x6a8, 0xff,}, + { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, +}; + +// ATxmega256A3BU +const Port_bits ports_atxmega256a3bu[7] = { + { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, + { 'B', 0x620, 0xff, 0x624, 0xff, 0x628, 0xff,}, + { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, + { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, + { 'E', 0x680, 0x3f, 0x684, 0x3f, 0x688, 0x3f,}, + { 'F', 0x6a0, 0xdf, 0x6a4, 0xdf, 0x6a8, 0xdf,}, + { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, +}; + +/* + * ATxmega16A4U ATxmega32A4U ATxmega64A4U ATxmega128A4U ATxmega16C4 ATxmega32C4 ATxmega16D4 + * ATxmega32D4 ATxmega64D4 ATxmega128D4 + */ +const Port_bits ports_atxmega16a4u[6] = { + { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, + { 'B', 0x620, 0x0f, 0x624, 0x0f, 0x628, 0x0f,}, + { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, + { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, + { 'E', 0x680, 0x0f, 0x684, 0x0f, 0x688, 0x0f,}, + { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, +}; + // ATxmega64B1 ATxmega128B1 const Port_bits ports_atxmega64b1[8] = { { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, @@ -60533,25 +60517,31 @@ const Port_bits ports_atxmega64b3[6] = { { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, }; -// ATxmega256A3BU -const Port_bits ports_atxmega256a3bu[7] = { +// ATxmega8E5 ATxmega16E5 ATxmega32E5 +const Port_bits ports_atxmega8e5[4] = { { 'A', 0x600, 0xff, 0x604, 0xff, 0x608, 0xff,}, - { 'B', 0x620, 0xff, 0x624, 0xff, 0x628, 0xff,}, { 'C', 0x640, 0xff, 0x644, 0xff, 0x648, 0xff,}, { 'D', 0x660, 0xff, 0x664, 0xff, 0x668, 0xff,}, - { 'E', 0x680, 0x3f, 0x684, 0x3f, 0x688, 0x3f,}, - { 'F', 0x6a0, 0xdf, 0x6a4, 0xdf, 0x6a8, 0xdf,}, { 'R', 0x7e0, 0x03, 0x7e4, 0x03, 0x7e8, 0x03,}, }; -// ATtiny202 ATtiny212 ATtiny402 ATtiny412 +// ATtiny202 ATtiny402 ATtiny212 ATtiny412 const Port_bits ports_attiny202[1] = { { 'A', 0x000, 0xcf, 0x001, 0xcf, 0x002, 0xcf,}, }; /* - * ATtiny406 ATtiny416 ATtiny416auto ATtiny426 ATtiny806 ATtiny816 ATtiny826 ATtiny1606 ATtiny1616 - * ATtiny1626 ATtiny3216 ATtiny3226 + * ATtiny204 ATtiny404 ATtiny804 ATtiny1604 ATtiny214 ATtiny414 ATtiny814 ATtiny1614 ATtiny424 + * ATtiny824 ATtiny1624 ATtiny3224 + */ +const Port_bits ports_attiny204[2] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'B', 0x004, 0x0f, 0x005, 0x0f, 0x006, 0x0f,}, +}; + +/* + * ATtiny406 ATtiny806 ATtiny1606 ATtiny416 ATtiny416auto ATtiny816 ATtiny1616 ATtiny3216 ATtiny426 + * ATtiny826 ATtiny1626 ATtiny3226 */ const Port_bits ports_attiny406[3] = { { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, @@ -60560,10 +60550,10 @@ const Port_bits ports_attiny406[3] = { }; /* - * ATtiny417 ATtiny427 ATtiny807 ATtiny817 ATtiny827 ATtiny1607 ATtiny1617 ATtiny1627 ATtiny3217 + * ATtiny807 ATtiny1607 ATtiny417 ATtiny817 ATtiny1617 ATtiny3217 ATtiny427 ATtiny827 ATtiny1627 * ATtiny3227 */ -const Port_bits ports_attiny417[3] = { +const Port_bits ports_attiny807[3] = { { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, { 'B', 0x004, 0xff, 0x005, 0xff, 0x006, 0xff,}, { 'C', 0x008, 0x3f, 0x009, 0x3f, 0x00a, 0x3f,}, @@ -60581,8 +60571,8 @@ const Port_bits ports_atmega808[4] = { }; /* - * ATmega809 ATmega1609 ATmega3209 ATmega4809 AVR32DA48 AVR32DA48S AVR32DB48 AVR64DA48 AVR64DA48S - * AVR64DB48 AVR128DA48 AVR128DA48S AVR128DB48 + * ATmega809 ATmega1609 ATmega3209 ATmega4809 AVR32DA48 AVR32DA48S AVR64DA48 AVR64DA48S AVR128DA48 + * AVR128DA48S AVR32DB48 AVR64DB48 AVR128DB48 */ const Port_bits ports_atmega809[6] = { { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, @@ -60593,94 +60583,6 @@ const Port_bits ports_atmega809[6] = { { 'F', 0x014, 0x7f, 0x015, 0x7f, 0x016, 0x7f,}, }; -// AVR16DU14 AVR32DU14 -const Port_bits ports_avr16du14[4] = { - { 'A', 0x000, 0x03, 0x001, 0x03, 0x002, 0x03,}, - { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, - { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, - { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, -}; - -// AVR16EB14 AVR16LA14 AVR32EB14 AVR32LA14 -const Port_bits ports_avr16eb14[4] = { - { 'A', 0x000, 0x03, 0x001, 0x03, 0x002, 0x03,}, - { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, - { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, - { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, -}; - -// AVR16DD20 AVR32DD20 AVR32SD20 AVR64DD20 -const Port_bits ports_avr16dd20[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x0e, 0x009, 0x0e, 0x00a, 0x0e,}, - { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, - { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, -}; - -// AVR16DU20 AVR32DU20 -const Port_bits ports_avr16du20[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, - { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, - { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, -}; - -// AVR16EB20 AVR16LA20 AVR32EB20 AVR32LA20 -const Port_bits ports_avr16eb20[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, - { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, - { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, -}; - -// AVR16DD28 AVR32DD28 AVR32SD28 AVR64DD28 -const Port_bits ports_avr16dd28[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, - { 'D', 0x00c, 0xfe, 0x00d, 0xfe, 0x00e, 0xfe,}, - { 'F', 0x014, 0xc3, 0x015, 0xc3, 0x016, 0xc3,}, -}; - -// AVR16DU28 AVR32DU28 AVR64DU28 -const Port_bits ports_avr16du28[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, - { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, - { 'F', 0x014, 0xc3, 0x015, 0xc3, 0x016, 0xc3,}, -}; - -// AVR16EA28 AVR16EB28 AVR16LA28 AVR32EA28 AVR32EB28 AVR32LA28 AVR64EA28 -const Port_bits ports_avr16ea28[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, - { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, - { 'F', 0x014, 0xc3, 0x015, 0xc3, 0x016, 0xc3,}, -}; - -// AVR16DD32 AVR32DD32 AVR32SD32 AVR64DD32 -const Port_bits ports_avr16dd32[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, - { 'D', 0x00c, 0xfe, 0x00d, 0xfe, 0x00e, 0xfe,}, - { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, -}; - -// AVR16DU32 AVR32DU32 AVR64DU32 -const Port_bits ports_avr16du32[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, - { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, - { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, -}; - -// AVR16EA32 AVR16EB32 AVR16LA32 AVR32EA32 AVR32EB32 AVR32LA32 AVR64EA32 -const Port_bits ports_avr16ea32[4] = { - { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, - { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, - { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, -}; - // AVR32DA28 AVR32DA28S AVR64DA28 AVR64DA28S AVR128DA28 AVR128DA28S const Port_bits ports_avr32da28[4] = { { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, @@ -60689,6 +60591,17 @@ const Port_bits ports_avr32da28[4] = { { 'F', 0x014, 0x43, 0x015, 0x43, 0x016, 0x43,}, }; +// AVR64DA64 AVR64DA64S AVR128DA64 AVR128DA64S AVR64DB64 AVR128DB64 +const Port_bits ports_avr64da64[7] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'B', 0x004, 0xff, 0x005, 0xff, 0x006, 0xff,}, + { 'C', 0x008, 0xff, 0x009, 0xff, 0x00a, 0xff,}, + { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, + { 'E', 0x010, 0xff, 0x011, 0xff, 0x012, 0xff,}, + { 'F', 0x014, 0x7f, 0x015, 0x7f, 0x016, 0x7f,}, + { 'G', 0x018, 0xff, 0x019, 0xff, 0x01a, 0xff,}, +}; + // AVR32DB28 AVR64DB28 AVR128DB28 const Port_bits ports_avr32db28[4] = { { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, @@ -60705,58 +60618,163 @@ const Port_bits ports_avr32db32[4] = { { 'F', 0x014, 0x7f, 0x015, 0x7f, 0x016, 0x7f,}, }; -// AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA64 AVR128DA64S AVR128DB64 -const Port_bits ports_avr64da64[7] = { +// AVR16DD14 AVR32DD14 AVR64DD14 +const Port_bits ports_avr16dd14[4] = { + { 'A', 0x000, 0x03, 0x001, 0x03, 0x002, 0x03,}, + { 'C', 0x008, 0x0e, 0x009, 0x0e, 0x00a, 0x0e,}, + { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, + { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, +}; + +// AVR16DD20 AVR32DD20 AVR64DD20 AVR32SD20 +const Port_bits ports_avr16dd20[4] = { { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, - { 'B', 0x004, 0xff, 0x005, 0xff, 0x006, 0xff,}, + { 'C', 0x008, 0x0e, 0x009, 0x0e, 0x00a, 0x0e,}, + { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, + { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, +}; + +// AVR16DD28 AVR32DD28 AVR64DD28 AVR32SD28 +const Port_bits ports_avr16dd28[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, + { 'D', 0x00c, 0xfe, 0x00d, 0xfe, 0x00e, 0xfe,}, + { 'F', 0x014, 0xc3, 0x015, 0xc3, 0x016, 0xc3,}, +}; + +// AVR16DD32 AVR32DD32 AVR64DD32 AVR32SD32 +const Port_bits ports_avr16dd32[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, + { 'D', 0x00c, 0xfe, 0x00d, 0xfe, 0x00e, 0xfe,}, + { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, +}; + +// AVR16DU14 AVR32DU14 +const Port_bits ports_avr16du14[4] = { + { 'A', 0x000, 0x03, 0x001, 0x03, 0x002, 0x03,}, + { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, + { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, + { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, +}; + +// AVR16DU20 AVR32DU20 +const Port_bits ports_avr16du20[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, + { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, + { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, +}; + +// AVR16DU28 AVR32DU28 AVR64DU28 +const Port_bits ports_avr16du28[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, + { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, + { 'F', 0x014, 0xc3, 0x015, 0xc3, 0x016, 0xc3,}, +}; + +// AVR16DU32 AVR32DU32 AVR64DU32 +const Port_bits ports_avr16du32[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x08, 0x009, 0x08, 0x00a, 0x08,}, + { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, + { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, +}; + +// AVR16EA28 AVR32EA28 AVR64EA28 AVR16EB28 AVR32EB28 AVR16LA28 AVR32LA28 +const Port_bits ports_avr16ea28[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, + { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, + { 'F', 0x014, 0xc3, 0x015, 0xc3, 0x016, 0xc3,}, +}; + +// AVR16EA32 AVR32EA32 AVR64EA32 AVR16EB32 AVR32EB32 AVR16LA32 AVR32LA32 +const Port_bits ports_avr16ea32[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, + { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, + { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, +}; + +// AVR16EA48 AVR32EA48 AVR64EA48 +const Port_bits ports_avr16ea48[6] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'B', 0x004, 0x3f, 0x005, 0x3f, 0x006, 0x3f,}, { 'C', 0x008, 0xff, 0x009, 0xff, 0x00a, 0xff,}, { 'D', 0x00c, 0xff, 0x00d, 0xff, 0x00e, 0xff,}, - { 'E', 0x010, 0xff, 0x011, 0xff, 0x012, 0xff,}, - { 'F', 0x014, 0x7f, 0x015, 0x7f, 0x016, 0x7f,}, - { 'G', 0x018, 0xff, 0x019, 0xff, 0x01a, 0xff,}, + { 'E', 0x010, 0x0f, 0x011, 0x0f, 0x012, 0x0f,}, + { 'F', 0x014, 0xff, 0x015, 0xff, 0x016, 0xff,}, +}; + +// AVR16EB14 AVR32EB14 AVR16LA14 AVR32LA14 +const Port_bits ports_avr16eb14[4] = { + { 'A', 0x000, 0x03, 0x001, 0x03, 0x002, 0x03,}, + { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, + { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, + { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, +}; + +// AVR16EB20 AVR32EB20 AVR16LA20 AVR32LA20 +const Port_bits ports_avr16eb20[4] = { + { 'A', 0x000, 0xff, 0x001, 0xff, 0x002, 0xff,}, + { 'C', 0x008, 0x0f, 0x009, 0x0f, 0x00a, 0x0f,}, + { 'D', 0x00c, 0xf0, 0x00d, 0xf0, 0x00e, 0xf0,}, + { 'F', 0x014, 0xc0, 0x015, 0xc0, 0x016, 0xc0,}, }; // UART configurations -/* - * ATmega8 ATmega8A ATmega48 ATmega48A ATmega48P ATmega48PA ATmega48PB ATmega88 ATmega88A ATmega88P - * ATmega88PA ATmega88PB ATmega168 ATmega168A ATmega168P ATmega168PA ATmega168PB ATmega328 - * ATmega328P ATA6612C ATA6613C ATA6614Q LGT8F88P LGT8F168P LGT8F328P - */ -const Uart_conf uarts_atmega8[1] = { - { 0, 0, PD0, PD1, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega16M1 ATmega32C1 ATmega32M1 ATmega64C1 ATmegaS64M1 ATmega64M1 -const Uart_conf uarts_atmega16m1[1] = { - { 0, 0, PD4, PD3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega64HVE ATmega64HVE2 -const Uart_conf uarts_atmega64hve[1] = { - { 0, 0, PB1, PB3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega328PB -const Uart_conf uarts_atmega328pb[2] = { - { 0, 0, PD0, PD1, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PB4, PB3, PB5, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -/* - * ATtiny2313 ATtiny2313A ATtiny4313 ATmega163 ATmega323 ATmega8515 ATmega8535 AT90SCR100 - * AT90SCR100H AT90S2313 AT90S2333 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90S8535 - */ -const Uart_conf uarts_attiny2313[1] = { - { 0, 0, PD0, PD1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - // ATtiny102 ATtiny104 const Uart_conf uarts_attiny102[1] = { { 0, 0, PB3, PB2, PB1, PNA, PNA, PNA, PNA, PNA, PNA }, }; +/* + * AT90S2313 AT90S2333 AT90S4414 AT90S4433 AT90S4434 AT90S8515 AT90S8535 AT90SCR100 AT90SCR100H + * ATtiny2313 ATtiny2313A ATtiny4313 ATmega163 ATmega323 ATmega8515 ATmega8535 + */ +const Uart_conf uarts_at90s2313[1] = { + { 0, 0, PD0, PD1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +/* + * AT90CAN32 AT90CAN64 AT90CAN128 ATmega64 ATmega64A ATmega128 ATmega128A ATmegaS128 ATmega1281 + * ATmega2561 + */ +const Uart_conf uarts_at90can32[2] = { + { 0, 0, PE0, PE1, PE2, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PD2, PD3, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AT90PWM2 AT90PWM2B AT90PWM216 AT90PWM3 AT90PWM3B AT90PWM316 +const Uart_conf uarts_at90pwm2[1] = { + { 0, 0, PD4, PD3, PD0, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AT90USB82 AT90USB162 AT90USB646 AT90USB1286 AT90USB647 AT90USB1287 ATmega32U6 +const Uart_conf uarts_at90usb82[1] = { + { 0, 0, PD2, PD3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATtiny87 ATtiny167 ATA5505 ATA6616C ATA6617C ATA664251 +const Uart_conf uarts_attiny87[1] = { + { 0, 0, PA0, PA1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATtiny828 ATtiny828R +const Uart_conf uarts_attiny828[1] = { + { 0, 0, PC2, PC3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATtiny1634 ATtiny1634R +const Uart_conf uarts_attiny1634[2] = { + { 0, 0, PA7, PB0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PB1, PB2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + // ATtiny441 ATtiny841 const Uart_conf uarts_attiny441[3] = { { 0, 0, PA2, PA1, PA3, PNA, PNA, PNA, PNA, PNA, PNA }, @@ -60764,31 +60782,101 @@ const Uart_conf uarts_attiny441[3] = { { 1, 0, PA4, PA5, PA6, PNA, PNA, PNA, PNA, PNA, PNA }, }; -// AT90PWM2 AT90PWM2B AT90PWM3 AT90PWM3B AT90PWM216 AT90PWM316 -const Uart_conf uarts_at90pwm2[1] = { - { 0, 0, PD4, PD3, PD0, PNA, PNA, PNA, PNA, PNA, PNA }, +/* + * ATmega8 ATmega8A ATmega48 ATmega48A ATmega48P ATmega48PA ATmega88 ATmega88A ATmega88P ATmega88PA + * ATmega168 ATmega168A ATmega168P ATmega168PA ATmega328 ATmega328P ATmega48PB ATmega88PB + * ATmega168PB LGT8F88P LGT8F168P LGT8F328P ATA6612C ATA6613C ATA6614Q + */ +const Uart_conf uarts_atmega8[1] = { + { 0, 0, PD0, PD1, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATmega16 ATmega16A ATmega32 ATmega32A ATmega644 +const Uart_conf uarts_atmega16[1] = { + { 0, 0, PD0, PD1, PB0, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATmega640 ATmega1280 ATmega2560 +const Uart_conf uarts_atmega640[4] = { + { 0, 0, PE0, PE1, PE2, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PD2, PD3, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, + { 2, 0, PH0, PH1, PH2, PNA, PNA, PNA, PNA, PNA, PNA }, + { 3, 0, PJ0, PJ1, PJ2, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATmega32C1 ATmega64C1 ATmega16M1 ATmega32M1 ATmega64M1 ATmegaS64M1 +const Uart_conf uarts_atmega32c1[1] = { + { 0, 0, PD4, PD3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; /* - * ATmega64 ATmega64A ATmega128 ATmegaS128 ATmega128A ATmega1281 ATmega2561 AT90CAN32 AT90CAN64 - * AT90CAN128 + * ATmega128RFA1 ATmega64RFR2 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 + * ATmega2564RFR2 */ -const Uart_conf uarts_atmega64[2] = { - { 0, 0, PE0, PE1, PE2, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PD2, PD3, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, +const Uart_conf uarts_atmega128rfa1[2] = { + { 0, 0, PE0, PE1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PD2, PD3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; -// ATmega32U6 AT90USB82 AT90USB162 AT90USB646 AT90USB647 AT90USB1286 AT90USB1287 -const Uart_conf uarts_atmega32u6[1] = { - { 0, 0, PD2, PD3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +// ATmega8U2 ATmega16U2 ATmega32U2 +const Uart_conf uarts_atmega8u2[1] = { + { 0, 0, PD2, PD3, PD5, PNA, PNA, PD6, PD7, PNA, PNA }, }; -// ATxmega8E5 ATxmega16E5 ATxmega32E5 -const Uart_conf uarts_atxmega8e5[4] = { - { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 - { 2, 1, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 +// ATmega16U4 ATmega32U4 +const Uart_conf uarts_atmega16u4[1] = { + { 0, 0, PD2, PD3, PD5, PNA, PNA, PB7, PD5, PNA, PNA }, +}; + +// ATmega161 ATmega162 +const Uart_conf uarts_atmega161[2] = { + { 0, 0, PD0, PD1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PB2, PB3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +/* + * ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644A ATmega644P + * ATmega644PA ATmega1284 ATmega1284P + */ +const Uart_conf uarts_atmega164a[2] = { + { 0, 0, PD0, PD1, PB0, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PD2, PD3, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATmega324PB +const Uart_conf uarts_atmega324pb[3] = { + { 0, 0, PD0, PD1, PB0, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PD2, PD3, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, + { 2, 0, PE2, PE3, PD7, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +/* + * ATmega165 ATmega165A ATmega165P ATmega165PA ATmega325 ATmega325A ATmega325P ATmega325PA + * ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA ATmega6450 + * ATmega6450A ATmega6450P ATmega169 ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6490 + * ATmega6490A ATmega6490P ATmega103 + */ +const Uart_conf uarts_atmega165[1] = { + { 0, 0, PE0, PE1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATmega328PB +const Uart_conf uarts_atmega328pb[2] = { + { 0, 0, PD0, PD1, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PB4, PB3, PB5, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +/* + * ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 + * ATmega649A ATmega649P + */ +const Uart_conf uarts_atmega169a[1] = { + { 0, 0, PE0, PE1, PE2, PNA, PE4, PNA, PNA, PNA, PNA }, +}; + +// ATmega64HVE ATmega64HVE2 +const Uart_conf uarts_atmega64hve[1] = { + { 0, 0, PB1, PB3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; // ATxmega64A1 ATxmega128A1 ATxmega128A1revD ATxmega192A1 ATxmega256A1 @@ -60803,6 +60891,19 @@ const Uart_conf uarts_atxmega64a1[8] = { { 7, 0, PF6, PF7, PF5, PNA, PNA, PNA, PNA, PNA, PNA }, // F1 }; +// ATxmega64A1U ATxmega128A1U +const Uart_conf uarts_atxmega64a1u[9] = { + { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 1, 0, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C1 + { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 + { 3, 0, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D1 + { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 + { 5, 0, PE6, PE7, PE5, PNA, PNA, PNA, PNA, PNA, PNA }, // E1 + { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 + { 7, 0, PF6, PF7, PF5, PNA, PNA, PNA, PNA, PNA, PNA }, // F1 +}; + // ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 const Uart_conf uarts_atxmega64a3[7] = { { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 @@ -60814,6 +60915,16 @@ const Uart_conf uarts_atxmega64a3[7] = { { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 }; +// ATxmega256A3B +const Uart_conf uarts_atxmega256a3b[6] = { + { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 1, 0, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C1 + { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 + { 3, 0, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D1 + { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 + { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 +}; + // ATxmega64A3U ATxmega128A3U ATxmega192A3U ATxmega256A3U const Uart_conf uarts_atxmega64a3u[11] = { { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 @@ -60829,8 +60940,20 @@ const Uart_conf uarts_atxmega64a3u[11] = { { 6, 1, PF6, PF7, PF5, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 }; +// ATxmega256A3BU +const Uart_conf uarts_atxmega256a3bu[8] = { + { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 1, 0, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C1 + { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 + { 2, 1, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 + { 3, 0, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D1 + { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 + { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 +}; + /* - * ATxmega16A4 ATxmega16A4U ATxmega32A4 ATxmega32A4U ATxmega64A4 ATxmega64A4U ATxmega128A4 + * ATxmega16A4 ATxmega32A4 ATxmega64A4 ATxmega128A4 ATxmega16A4U ATxmega32A4U ATxmega64A4U * ATxmega128A4U */ const Uart_conf uarts_atxmega16a4[7] = { @@ -60843,132 +60966,29 @@ const Uart_conf uarts_atxmega16a4[7] = { { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 }; -/* - * ATtiny204 ATtiny214 ATtiny404 ATtiny406 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny804 - * ATtiny806 ATtiny807 ATtiny814 ATtiny816 ATtiny817 ATtiny1604 ATtiny1606 ATtiny1607 ATtiny1614 - * ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 - */ -const Uart_conf uarts_attiny204[2] = { - { 0, 0, PB3, PB2, PB1, PB0, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA2, PA1, PA3, PA4, PNA, PNA, PNA, PNA, PNA }, +// ATxmega64B1 ATxmega128B1 +const Uart_conf uarts_atxmega64b1[4] = { + { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 + { 4, 1, PE6, PE7, PE5, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 }; -// ATtiny424 ATtiny824 ATtiny1624 ATtiny3224 -const Uart_conf uarts_attiny424[3] = { - { 0, 0, PB3, PB2, PB1, PB0, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA2, PA1, PA3, PA4, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PA2, PA1, PA3, PA4, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16DD14 AVR32DD14 AVR64DD14 -const Uart_conf uarts_avr16dd14[5] = { - { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PC1, PNA, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, - { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16EA48 AVR32EA48 AVR64EA48 -const Uart_conf uarts_avr16ea48[10] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, - { 1, 1, PC5, PC4, PC6, PC7, PNA, PNA, PNA, PNA, PNA }, - { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 2, 0, PF1, PF0, PF2, PF3, PNA, PNA, PNA, PNA, PNA }, - { 2, 1, PF5, PF4, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATtiny87 ATtiny167 ATA5505 ATA6616C ATA6617C ATA664251 -const Uart_conf uarts_attiny87[1] = { - { 0, 0, PA0, PA1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATtiny828 ATtiny828R -const Uart_conf uarts_attiny828[1] = { - { 0, 0, PC2, PC3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATtiny1634 ATtiny1634R -const Uart_conf uarts_attiny1634[2] = { - { 0, 0, PA7, PB0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PB1, PB2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega8U2 ATmega16U2 ATmega32U2 -const Uart_conf uarts_atmega8u2[1] = { - { 0, 0, PD2, PD3, PD5, PNA, PNA, PD6, PD7, PNA, PNA }, -}; - -// ATmega16 ATmega16A ATmega32 ATmega32A ATmega644 -const Uart_conf uarts_atmega16[1] = { - { 0, 0, PD0, PD1, PB0, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega16U4 ATmega32U4 -const Uart_conf uarts_atmega16u4[1] = { - { 0, 0, PD2, PD3, PD5, PNA, PNA, PB7, PD5, PNA, PNA }, +// ATxmega64B3 ATxmega128B3 +const Uart_conf uarts_atxmega64b3[2] = { + { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 }; /* - * ATmega64RFR2 ATmega128RFA1 ATmega128RFR2 ATmega256RFR2 ATmega644RFR2 ATmega1284RFR2 - * ATmega2564RFR2 + * ATxmega32C3 ATxmega64C3 ATxmega128C3 ATxmega192C3 ATxmega256C3 ATxmega384C3 ATxmega32D3 + * ATxmega64D3 ATxmega128D3 ATxmega192D3 ATxmega256D3 ATxmega384D3 */ -const Uart_conf uarts_atmega64rfr2[2] = { - { 0, 0, PE0, PE1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PD2, PD3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -/* - * ATmega103 ATmega165 ATmega165A ATmega165P ATmega165PA ATmega169 ATmega325 ATmega325A ATmega325P - * ATmega325PA ATmega645 ATmega645A ATmega645P ATmega3250 ATmega3250A ATmega3250P ATmega3250PA - * ATmega3290 ATmega3290A ATmega3290P ATmega3290PA ATmega6450 ATmega6450A ATmega6450P ATmega6490 - * ATmega6490A ATmega6490P - */ -const Uart_conf uarts_atmega103[1] = { - { 0, 0, PE0, PE1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega161 ATmega162 -const Uart_conf uarts_atmega161[2] = { - { 0, 0, PD0, PD1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PB2, PB3, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -/* - * ATmega164A ATmega164P ATmega164PA ATmega324A ATmega324P ATmega324PA ATmega644A ATmega644P - * ATmega644PA ATmega1284 ATmega1284P - */ -const Uart_conf uarts_atmega164a[2] = { - { 0, 0, PD0, PD1, PB0, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PD2, PD3, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -/* - * ATmega169A ATmega169P ATmega169PA ATmega329 ATmega329A ATmega329P ATmega329PA ATmega649 - * ATmega649A ATmega649P - */ -const Uart_conf uarts_atmega169a[1] = { - { 0, 0, PE0, PE1, PE2, PNA, PE4, PNA, PNA, PNA, PNA }, -}; - -// ATmega324PB -const Uart_conf uarts_atmega324pb[3] = { - { 0, 0, PD0, PD1, PB0, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PD2, PD3, PD4, PNA, PNA, PNA, PNA, PNA, PNA }, - { 2, 0, PE2, PE3, PD7, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// ATmega640 ATmega1280 ATmega2560 -const Uart_conf uarts_atmega640[4] = { - { 0, 0, PE0, PE1, PE2, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PD2, PD3, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, - { 2, 0, PH0, PH1, PH2, PNA, PNA, PNA, PNA, PNA, PNA }, - { 3, 0, PJ0, PJ1, PJ2, PNA, PNA, PNA, PNA, PNA, PNA }, +const Uart_conf uarts_atxmega32c3[4] = { + { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 + { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 + { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 }; // ATxmega16C4 ATxmega32C4 @@ -60986,72 +61006,37 @@ const Uart_conf uarts_atxmega16d4[3] = { { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 }; -/* - * ATxmega32C3 ATxmega32D3 ATxmega64C3 ATxmega64D3 ATxmega128C3 ATxmega128D3 ATxmega192C3 - * ATxmega192D3 ATxmega256C3 ATxmega256D3 ATxmega384C3 ATxmega384D3 - */ -const Uart_conf uarts_atxmega32c3[4] = { +// ATxmega8E5 ATxmega16E5 ATxmega32E5 +const Uart_conf uarts_atxmega8e5[4] = { { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 - { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 -}; - -// ATxmega64A1U ATxmega128A1U -const Uart_conf uarts_atxmega64a1u[9] = { - { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 1, 0, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C1 - { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 - { 3, 0, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D1 - { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 - { 5, 0, PE6, PE7, PE5, PNA, PNA, PNA, PNA, PNA, PNA }, // E1 - { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 - { 7, 0, PF6, PF7, PF5, PNA, PNA, PNA, PNA, PNA, PNA }, // F1 -}; - -// ATxmega64B1 ATxmega128B1 -const Uart_conf uarts_atxmega64b1[4] = { - { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 - { 4, 1, PE6, PE7, PE5, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 -}; - -// ATxmega64B3 ATxmega128B3 -const Uart_conf uarts_atxmega64b3[2] = { - { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 -}; - -// ATxmega256A3B -const Uart_conf uarts_atxmega256a3b[6] = { - { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 1, 0, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C1 - { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 - { 3, 0, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D1 - { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 - { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 -}; - -// ATxmega256A3BU -const Uart_conf uarts_atxmega256a3bu[8] = { - { 0, 0, PC2, PC3, PC1, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 0, 1, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C0 - { 1, 0, PC6, PC7, PC5, PNA, PNA, PNA, PNA, PNA, PNA }, // C1 - { 2, 0, PD2, PD3, PD1, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 { 2, 1, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D0 - { 3, 0, PD6, PD7, PD5, PNA, PNA, PNA, PNA, PNA, PNA }, // D1 - { 4, 0, PE2, PE3, PE1, PNA, PNA, PNA, PNA, PNA, PNA }, // E0 - { 6, 0, PF2, PF3, PF1, PNA, PNA, PNA, PNA, PNA, PNA }, // F0 }; -// ATtiny202 ATtiny212 ATtiny402 ATtiny412 +// ATtiny202 ATtiny402 ATtiny212 ATtiny412 const Uart_conf uarts_attiny202[2] = { { 0, 0, PA7, PA6, PA3, PA0, PNA, PNA, PNA, PNA, PNA }, { 0, 1, PA2, PA1, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; +/* + * ATtiny204 ATtiny404 ATtiny406 ATtiny804 ATtiny806 ATtiny807 ATtiny1604 ATtiny1606 ATtiny1607 + * ATtiny214 ATtiny414 ATtiny416 ATtiny416auto ATtiny417 ATtiny814 ATtiny816 ATtiny817 ATtiny1614 + * ATtiny1616 ATtiny1617 ATtiny3216 ATtiny3217 + */ +const Uart_conf uarts_attiny204[2] = { + { 0, 0, PB3, PB2, PB1, PB0, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA2, PA1, PA3, PA4, PNA, PNA, PNA, PNA, PNA }, +}; + +// ATtiny424 ATtiny824 ATtiny1624 ATtiny3224 +const Uart_conf uarts_attiny424[3] = { + { 0, 0, PB3, PB2, PB1, PB0, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA2, PA1, PA3, PA4, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PA2, PA1, PA3, PA4, PNA, PNA, PNA, PNA, PNA }, +}; + // ATtiny426 ATtiny427 ATtiny826 ATtiny827 ATtiny1626 ATtiny1627 ATtiny3226 ATtiny3227 const Uart_conf uarts_attiny426[4] = { { 0, 0, PB3, PB2, PB1, PB0, PNA, PNA, PNA, PNA, PNA }, @@ -61081,102 +61066,7 @@ const Uart_conf uarts_atmega809[8] = { { 3, 1, PB5, PB4, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; -// AVR16DU14 AVR32DU14 -const Uart_conf uarts_avr16du14[3] = { - { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16EB14 AVR32EB14 -const Uart_conf uarts_avr16eb14[4] = { - { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 6, PF6, PF7, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16LA14 AVR32LA14 -const Uart_conf uarts_avr16la14[3] = { - { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PNA, PNA, PNA, PNA, PNA, PD6, PD7 }, - { 0, 4, PC2, PC1, PNA, PNA, PNA, PNA, PNA, PC3, PNA }, -}; - -// AVR16DD20 AVR32DD20 AVR32SD20 AVR64DD20 -const Uart_conf uarts_avr16dd20[7] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PC1, PNA, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, - { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 -const Uart_conf uarts_avr16du20[5] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB20 AVR32EB28 AVR32EB32 -const Uart_conf uarts_avr16eb20[6] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 6, PF6, PF7, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA20 AVR32LA28 AVR32LA32 -const Uart_conf uarts_avr16la20[5] = { - { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PA2, PA3 }, - { 0, 1, PA5, PA4, PNA, PNA, PNA, PNA, PNA, PA6, PA7 }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PNA, PNA, PNA, PNA, PNA, PD6, PD7 }, - { 0, 4, PC2, PC1, PNA, PNA, PNA, PNA, PNA, PC3, PNA }, -}; - -// AVR16DD28 AVR16DD32 AVR32DD28 AVR32DD32 AVR64DD28 AVR64DD32 -const Uart_conf uarts_avr16dd28[7] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, - { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16EA28 AVR32EA28 AVR32SD28 AVR64EA28 -const Uart_conf uarts_avr16ea28[8] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, - { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 2, 0, PF1, PF0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR16EA32 AVR32EA32 AVR32SD32 AVR64EA32 -const Uart_conf uarts_avr16ea32[9] = { - { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, - { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, - { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, - { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, - { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, - { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, - { 2, 0, PF1, PF0, PF2, PF3, PNA, PNA, PNA, PNA, PNA }, - { 2, 1, PF5, PF4, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, -}; - -// AVR32DA28 AVR32DA28S AVR32DB28 AVR64DA28 AVR64DA28S AVR64DB28 AVR128DA28 AVR128DA28S AVR128DB28 +// AVR32DA28 AVR32DA28S AVR64DA28 AVR64DA28S AVR128DA28 AVR128DA28S AVR32DB28 AVR64DB28 AVR128DB28 const Uart_conf uarts_avr32da28[4] = { { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, @@ -61184,7 +61074,7 @@ const Uart_conf uarts_avr32da28[4] = { { 2, 0, PF1, PF0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; -// AVR32DA32 AVR32DA32S AVR32DB32 AVR64DA32 AVR64DA32S AVR64DB32 AVR128DA32 AVR128DA32S AVR128DB32 +// AVR32DA32 AVR32DA32S AVR64DA32 AVR64DA32S AVR128DA32 AVR128DA32S AVR32DB32 AVR64DB32 AVR128DB32 const Uart_conf uarts_avr32da32[5] = { { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, @@ -61193,7 +61083,7 @@ const Uart_conf uarts_avr32da32[5] = { { 2, 1, PF5, PF4, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, }; -// AVR32DA48 AVR32DA48S AVR32DB48 AVR64DA48 AVR64DA48S AVR64DB48 AVR128DA48 AVR128DA48S AVR128DB48 +// AVR32DA48 AVR32DA48S AVR64DA48 AVR64DA48S AVR128DA48 AVR128DA48S AVR32DB48 AVR64DB48 AVR128DB48 const Uart_conf uarts_avr32da48[9] = { { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, @@ -61206,7 +61096,7 @@ const Uart_conf uarts_avr32da48[9] = { { 4, 0, PE1, PE0, PE2, PE3, PNA, PNA, PNA, PNA, PNA }, }; -// AVR64DA64 AVR64DA64S AVR64DB64 AVR128DA64 AVR128DA64S AVR128DB64 +// AVR64DA64 AVR64DA64S AVR128DA64 AVR128DA64S AVR64DB64 AVR128DB64 const Uart_conf uarts_avr64da64[12] = { { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, @@ -61221,3 +61111,121 @@ const Uart_conf uarts_avr64da64[12] = { { 5, 0, PG1, PG0, PG2, PG3, PNA, PNA, PNA, PNA, PNA }, { 5, 1, PG5, PG4, PG6, PG7, PNA, PNA, PNA, PNA, PNA }, }; + +// AVR16DD14 AVR32DD14 AVR64DD14 +const Uart_conf uarts_avr16dd14[5] = { + { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PC1, PNA, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, + { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16DD20 AVR32DD20 AVR64DD20 AVR32SD20 +const Uart_conf uarts_avr16dd20[7] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PC1, PNA, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, + { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16DD28 AVR16DD32 AVR32DD28 AVR32DD32 AVR64DD28 AVR64DD32 +const Uart_conf uarts_avr16dd28[7] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, + { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16DU14 AVR32DU14 +const Uart_conf uarts_avr16du14[3] = { + { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16DU20 AVR16DU28 AVR16DU32 AVR32DU20 AVR32DU28 AVR32DU32 AVR64DU28 AVR64DU32 +const Uart_conf uarts_avr16du20[5] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16EA28 AVR32EA28 AVR64EA28 AVR32SD28 +const Uart_conf uarts_avr16ea28[8] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, + { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 2, 0, PF1, PF0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16EA32 AVR32EA32 AVR64EA32 AVR32SD32 +const Uart_conf uarts_avr16ea32[9] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, + { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 2, 0, PF1, PF0, PF2, PF3, PNA, PNA, PNA, PNA, PNA }, + { 2, 1, PF5, PF4, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16EA48 AVR32EA48 AVR64EA48 +const Uart_conf uarts_avr16ea48[10] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 1, 0, PC1, PC0, PC2, PC3, PNA, PNA, PNA, PNA, PNA }, + { 1, 1, PC5, PC4, PC6, PC7, PNA, PNA, PNA, PNA, PNA }, + { 1, 2, PD7, PD6, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 2, 0, PF1, PF0, PF2, PF3, PNA, PNA, PNA, PNA, PNA }, + { 2, 1, PF5, PF4, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16EB14 AVR32EB14 +const Uart_conf uarts_avr16eb14[4] = { + { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 6, PF6, PF7, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16EB20 AVR16EB28 AVR16EB32 AVR32EB20 AVR32EB28 AVR32EB32 +const Uart_conf uarts_avr16eb20[6] = { + { 0, 0, PA1, PA0, PA2, PA3, PNA, PNA, PNA, PNA, PNA }, + { 0, 1, PA5, PA4, PA6, PA7, PNA, PNA, PNA, PNA, PNA }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PD6, PD7, PNA, PNA, PNA, PNA, PNA }, + { 0, 4, PC2, PC1, PC3, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 6, PF6, PF7, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, +}; + +// AVR16LA14 AVR32LA14 +const Uart_conf uarts_avr16la14[3] = { + { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PNA, PNA, PNA, PNA, PNA, PD6, PD7 }, + { 0, 4, PC2, PC1, PNA, PNA, PNA, PNA, PNA, PC3, PNA }, +}; + +// AVR16LA20 AVR16LA28 AVR16LA32 AVR32LA20 AVR32LA28 AVR32LA32 +const Uart_conf uarts_avr16la20[5] = { + { 0, 0, PA1, PA0, PNA, PNA, PNA, PNA, PNA, PA2, PA3 }, + { 0, 1, PA5, PA4, PNA, PNA, PNA, PNA, PNA, PA6, PA7 }, + { 0, 2, PA3, PA2, PNA, PNA, PNA, PNA, PNA, PNA, PNA }, + { 0, 3, PD5, PD4, PNA, PNA, PNA, PNA, PNA, PD6, PD7 }, + { 0, 4, PC2, PC1, PNA, PNA, PNA, PNA, PNA, PC3, PNA }, +}; diff --git a/src/libavrdude-avrintel.h b/src/libavrdude-avrintel.h index afecd56b..1a65f666 100644 --- a/src/libavrdude-avrintel.h +++ b/src/libavrdude-avrintel.h @@ -11,8 +11,8 @@ * Published under GNU General Public License, version 3 (GPL-3.0) * Meta-author Stefan Rueger * - * v 1.46 - * 15.04.2026 + * v 1.50 + * 17.04.2026 * */ @@ -161,190 +161,7 @@ extern const Avrintel uP_table[422]; #define id_attiny40 5u #define id_attiny102 6u #define id_attiny104 7u -#define id_attiny11 8u -#define id_attiny12 9u -#define id_attiny13 10u -#define id_attiny13a 11u -#define id_attiny15 12u -#define id_attiny22 13u -#define id_attiny24 14u -#define id_attiny24a 15u -#define id_attiny25 16u -#define id_attiny26 17u -#define id_attiny28 18u -#define id_attiny43u 19u -#define id_attiny44 20u -#define id_attiny44a 21u -#define id_attiny45 22u -#define id_attiny48 23u -#define id_attiny84 24u -#define id_attiny84a 25u -#define id_attiny85 26u -#define id_attiny87 27u -#define id_attiny88 28u -#define id_attiny167 29u -#define id_attiny261 30u -#define id_attiny261a 31u -#define id_attiny441 32u -#define id_attiny461 33u -#define id_attiny461a 34u -#define id_attiny828 35u -#define id_attiny828r 36u -#define id_attiny841 37u -#define id_attiny861 38u -#define id_attiny861a 39u -#define id_attiny1634 40u -#define id_attiny1634r 41u -#define id_attiny2313 42u -#define id_attiny2313a 43u -#define id_attiny4313 44u -#define id_atmega8 45u -#define id_atmega8a 46u -#define id_atmega8hva 47u -#define id_atmega8u2 48u -#define id_atmega16 49u -#define id_atmega16a 50u -#define id_atmega16hva 51u -#define id_atmega16hvb 52u -#define id_atmega16hvbrevb 53u -#define id_atmega16m1 54u -#define id_atmega16hva2 55u -#define id_atmega16u2 56u -#define id_atmega16u4 57u -#define id_atmega32 58u -#define id_atmega32a 59u -#define id_atmega32hvb 60u -#define id_atmega32hvbrevb 61u -#define id_atmega32c1 62u -#define id_atmega32m1 63u -#define id_atmega32hve2 379u -#define id_atmega32u2 64u -#define id_atmega32u4 65u -#define id_atmega32u6 66u -#define id_atmega48 67u -#define id_atmega48a 68u -#define id_atmega48p 69u -#define id_atmega48pa 70u -#define id_atmega48pb 71u -#define id_atmega64 72u -#define id_atmega64a 73u -#define id_atmega64hve 74u -#define id_atmega64c1 75u -#define id_atmegas64m1 412u -#define id_atmega64m1 76u -#define id_atmega64hve2 77u -#define id_atmega64rfr2 78u -#define id_atmega88 79u -#define id_atmega88a 80u -#define id_atmega88p 81u -#define id_atmega88pa 82u -#define id_atmega88pb 83u -#define id_atmega103 84u -#define id_atmega103comp 374u -#define id_atmega128 85u -#define id_atmegas128 413u -#define id_atmega128a 86u -#define id_atmega128rfa1 87u -#define id_atmega128rfr2 88u -#define id_atmega161 89u -#define id_atmega161comp 375u -#define id_atmega162 90u -#define id_atmega163 91u -#define id_atmega164a 92u -#define id_atmega164p 93u -#define id_atmega164pa 94u -#define id_atmega165 95u -#define id_atmega165a 96u -#define id_atmega165p 97u -#define id_atmega165pa 98u -#define id_atmega168 99u -#define id_atmega168a 100u -#define id_atmega168p 101u -#define id_atmega168pa 102u -#define id_atmega168pb 103u -#define id_atmega169 104u -#define id_atmega169a 105u -#define id_atmega169p 106u -#define id_atmega169pa 107u -#define id_atmega256rfr2 108u -#define id_atmega323 109u -#define id_atmega324a 110u -#define id_atmega324p 111u -#define id_atmega324pa 112u -#define id_atmega324pb 113u -#define id_atmega325 114u -#define id_atmega325a 115u -#define id_atmega325p 116u -#define id_atmega325pa 117u -#define id_atmega328 118u -#define id_atmega328p 119u -#define id_atmega328pb 120u -#define id_atmega329 121u -#define id_atmega329a 122u -#define id_atmega329p 123u -#define id_atmega329pa 124u -#define id_atmega406 125u -#define id_atmega640 126u -#define id_atmega644 127u -#define id_atmega644a 128u -#define id_atmega644p 129u -#define id_atmega644pa 130u -#define id_atmega644rfr2 131u -#define id_atmega645 132u -#define id_atmega645a 133u -#define id_atmega645p 134u -#define id_atmega649 135u -#define id_atmega649a 136u -#define id_atmega649p 137u -#define id_atmega1280 138u -#define id_atmega1281 139u -#define id_atmega1284 140u -#define id_atmega1284p 141u -#define id_atmega1284rfr2 142u -#define id_atmega2560 143u -#define id_atmega2561 144u -#define id_atmega2564rfr2 145u -#define id_atmega3250 146u -#define id_atmega3250a 147u -#define id_atmega3250p 148u -#define id_atmega3250pa 149u -#define id_atmega3290 150u -#define id_atmega3290a 151u -#define id_atmega3290p 152u -#define id_atmega3290pa 153u -#define id_atmega6450 154u -#define id_atmega6450a 155u -#define id_atmega6450p 156u -#define id_atmega6490 157u -#define id_atmega6490a 158u -#define id_atmega6490p 159u -#define id_atmega8515 160u -#define id_atmega8535 161u -#define id_at43usb320 162u -#define id_at43usb355 163u -#define id_at76c711 164u -#define id_at86rf401 165u -#define id_at90pwm1 166u -#define id_at90pwm2 167u -#define id_at90pwm2b 168u -#define id_at90pwm3 169u -#define id_at90pwm3b 170u -#define id_at90can32 171u -#define id_at90can64 172u -#define id_at90pwm81 173u -#define id_at90usb82 174u -#define id_at90scr100 175u -#define id_at90scr100h 376u -#define id_at90can128 176u -#define id_at90pwm161 177u -#define id_at90usb162 178u -#define id_at90pwm216 179u -#define id_at90pwm316 180u -#define id_at90usb646 181u -#define id_at90usb647 182u #define id_at90s1200 183u -#define id_at90usb1286 184u -#define id_at90usb1287 185u #define id_at90s2313 186u #define id_at90s2323 187u #define id_at90s2333 188u @@ -352,12 +169,201 @@ extern const Avrintel uP_table[422]; #define id_at90s4414 190u #define id_at90s4433 191u #define id_at90s4434 192u +#define id_at90c8534 194u #define id_at90s8515 193u #define id_at90s8515comp 377u -#define id_at90c8534 194u #define id_at90s8535 195u #define id_at90s8535comp 378u +#define id_at90can32 171u +#define id_at90can64 172u +#define id_at90can128 176u +#define id_at90pwm1 166u +#define id_at90pwm81 173u +#define id_at90pwm161 177u +#define id_at90pwm2 167u +#define id_at90pwm2b 168u +#define id_at90pwm216 179u +#define id_at90pwm3 169u +#define id_at90pwm3b 170u +#define id_at90pwm316 180u +#define id_at90usb82 174u +#define id_at90usb162 178u +#define id_at90usb646 181u +#define id_at90usb1286 184u +#define id_at90usb647 182u +#define id_at90usb1287 185u +#define id_at90scr100 175u +#define id_at90scr100h 376u +#define id_at86rf401 165u +#define id_at89s51 372u +#define id_at89s52 373u +#define id_at76c711 164u +#define id_at43usb355 163u #define id_at94k 196u +#define id_at43usb320 162u +#define id_m3000 226u +#define id_attiny11 8u +#define id_attiny12 9u +#define id_attiny22 13u +#define id_attiny13 10u +#define id_attiny13a 11u +#define id_attiny43u 19u +#define id_attiny24 14u +#define id_attiny24a 15u +#define id_attiny44 20u +#define id_attiny44a 21u +#define id_attiny84 24u +#define id_attiny84a 25u +#define id_attiny15 12u +#define id_attiny25 16u +#define id_attiny45 22u +#define id_attiny85 26u +#define id_attiny26 17u +#define id_attiny87 27u +#define id_attiny167 29u +#define id_attiny28 18u +#define id_attiny48 23u +#define id_attiny88 28u +#define id_attiny828 35u +#define id_attiny828r 36u +#define id_attiny1634 40u +#define id_attiny1634r 41u +#define id_attiny441 32u +#define id_attiny841 37u +#define id_attiny261 30u +#define id_attiny261a 31u +#define id_attiny461 33u +#define id_attiny461a 34u +#define id_attiny861 38u +#define id_attiny861a 39u +#define id_attiny2313 42u +#define id_attiny2313a 43u +#define id_attiny4313 44u +#define id_atmega8 45u +#define id_atmega8a 46u +#define id_atmega16 49u +#define id_atmega16a 50u +#define id_atmega32 58u +#define id_atmega32a 59u +#define id_atmega64 72u +#define id_atmega64a 73u +#define id_atmega128 85u +#define id_atmega128a 86u +#define id_atmegas128 413u +#define id_atmega640 126u +#define id_atmega1280 138u +#define id_atmega2560 143u +#define id_atmega32c1 62u +#define id_atmega64c1 75u +#define id_atmega16m1 54u +#define id_atmega32m1 63u +#define id_atmega64m1 76u +#define id_atmegas64m1 412u +#define id_atmega128rfa1 87u +#define id_atmega64rfr2 78u +#define id_atmega128rfr2 88u +#define id_atmega256rfr2 108u +#define id_atmega8u2 48u +#define id_atmega16u2 56u +#define id_atmega32u2 64u +#define id_atmega16u4 57u +#define id_atmega32u4 65u +#define id_atmega32u6 66u +#define id_atmega161 89u +#define id_atmega161comp 375u +#define id_atmega1281 139u +#define id_atmega2561 144u +#define id_atmega162 90u +#define id_atmega163 91u +#define id_atmega323 109u +#define id_atmega164a 92u +#define id_atmega164p 93u +#define id_atmega164pa 94u +#define id_atmega324a 110u +#define id_atmega324p 111u +#define id_atmega324pa 112u +#define id_atmega644 127u +#define id_atmega644a 128u +#define id_atmega644p 129u +#define id_atmega644pa 130u +#define id_atmega1284 140u +#define id_atmega1284p 141u +#define id_atmega324pb 113u +#define id_atmega644rfr2 131u +#define id_atmega1284rfr2 142u +#define id_atmega2564rfr2 145u +#define id_atmega165 95u +#define id_atmega165a 96u +#define id_atmega165p 97u +#define id_atmega165pa 98u +#define id_atmega325 114u +#define id_atmega325a 115u +#define id_atmega325p 116u +#define id_atmega325pa 117u +#define id_atmega645 132u +#define id_atmega645a 133u +#define id_atmega645p 134u +#define id_atmega3250 146u +#define id_atmega3250a 147u +#define id_atmega3250p 148u +#define id_atmega3250pa 149u +#define id_atmega6450 154u +#define id_atmega6450a 155u +#define id_atmega6450p 156u +#define id_atmega8515 160u +#define id_atmega8535 161u +#define id_atmega48 67u +#define id_atmega48a 68u +#define id_atmega48p 69u +#define id_atmega48pa 70u +#define id_atmega88 79u +#define id_atmega88a 80u +#define id_atmega88p 81u +#define id_atmega88pa 82u +#define id_atmega168 99u +#define id_atmega168a 100u +#define id_atmega168p 101u +#define id_atmega168pa 102u +#define id_atmega328 118u +#define id_atmega328p 119u +#define id_atmega48pb 71u +#define id_atmega88pb 83u +#define id_atmega168pb 103u +#define id_atmega328pb 120u +#define id_atmega169 104u +#define id_atmega169a 105u +#define id_atmega169p 106u +#define id_atmega169pa 107u +#define id_atmega329 121u +#define id_atmega329a 122u +#define id_atmega329p 123u +#define id_atmega329pa 124u +#define id_atmega649 135u +#define id_atmega649a 136u +#define id_atmega649p 137u +#define id_atmega3290 150u +#define id_atmega3290a 151u +#define id_atmega3290p 152u +#define id_atmega3290pa 153u +#define id_atmega6490 157u +#define id_atmega6490a 158u +#define id_atmega6490p 159u +#define id_lgt8f88p 227u +#define id_lgt8f168p 228u +#define id_lgt8f328p 229u +#define id_atmega103 84u +#define id_atmega103comp 374u +#define id_atmega8hva 47u +#define id_atmega16hva 51u +#define id_atmega16hva2 55u +#define id_atmega16hvb 52u +#define id_atmega16hvbrevb 53u +#define id_atmega32hvb 60u +#define id_atmega32hvbrevb 61u +#define id_atmega64hve 74u +#define id_atmega32hve2 379u +#define id_atmega64hve2 77u +#define id_atmega406 125u #define id_ata5272 197u #define id_ata5505 198u #define id_ata5700m322 199u @@ -382,101 +388,97 @@ extern const Avrintel uP_table[422]; #define id_ata6614q 218u #define id_ata6616c 219u #define id_ata6617c 220u +#define id_ata664251 225u #define id_ata8210 221u #define id_ata8215 222u #define id_ata8510 223u #define id_ata8515 224u -#define id_ata664251 225u -#define id_m3000 226u -#define id_lgt8f88p 227u -#define id_lgt8f168p 228u -#define id_lgt8f328p 229u -#define id_atxmega8e5 230u -#define id_atxmega16a4 231u -#define id_atxmega16a4u 232u -#define id_atxmega16c4 233u -#define id_atxmega16d4 234u -#define id_atxmega16e5 235u -#define id_atxmega32c3 236u -#define id_atxmega32d3 237u -#define id_atxmega32a4 238u -#define id_atxmega32a4u 239u -#define id_atxmega32c4 240u -#define id_atxmega32d4 241u -#define id_atxmega32e5 242u #define id_atxmega64a1 243u -#define id_atxmega64a1u 244u -#define id_atxmega64b1 245u -#define id_atxmega64a3 246u -#define id_atxmega64a3u 247u -#define id_atxmega64b3 248u -#define id_atxmega64c3 249u -#define id_atxmega64d3 250u -#define id_atxmega64a4 251u -#define id_atxmega64a4u 252u -#define id_atxmega64d4 253u #define id_atxmega128a1 254u #define id_atxmega128a1revd 255u -#define id_atxmega128a1u 256u -#define id_atxmega128b1 257u -#define id_atxmega128a3 258u -#define id_atxmega128a3u 259u -#define id_atxmega128b3 260u -#define id_atxmega128c3 261u -#define id_atxmega128d3 262u -#define id_atxmega128a4 263u -#define id_atxmega128a4u 264u -#define id_atxmega128d4 265u #define id_atxmega192a1 266u -#define id_atxmega192a3 267u -#define id_atxmega192a3u 268u -#define id_atxmega192c3 269u -#define id_atxmega192d3 270u #define id_atxmega256a1 271u +#define id_atxmega64a1u 244u +#define id_atxmega128a1u 256u +#define id_atxmega64a3 246u +#define id_atxmega128a3 258u +#define id_atxmega192a3 267u #define id_atxmega256a3 272u #define id_atxmega256a3b 273u +#define id_atxmega64a3u 247u +#define id_atxmega128a3u 259u +#define id_atxmega192a3u 268u #define id_atxmega256a3bu 274u #define id_atxmega256a3u 275u +#define id_atxmega16a4 231u +#define id_atxmega32a4 238u +#define id_atxmega64a4 251u +#define id_atxmega128a4 263u +#define id_atxmega16a4u 232u +#define id_atxmega32a4u 239u +#define id_atxmega64a4u 252u +#define id_atxmega128a4u 264u +#define id_atxmega64b1 245u +#define id_atxmega128b1 257u +#define id_atxmega64b3 248u +#define id_atxmega128b3 260u +#define id_atxmega32c3 236u +#define id_atxmega64c3 249u +#define id_atxmega128c3 261u +#define id_atxmega192c3 269u #define id_atxmega256c3 276u -#define id_atxmega256d3 277u #define id_atxmega384c3 278u +#define id_atxmega16c4 233u +#define id_atxmega32c4 240u +#define id_atxmega32d3 237u +#define id_atxmega64d3 250u +#define id_atxmega128d3 262u +#define id_atxmega192d3 270u +#define id_atxmega256d3 277u #define id_atxmega384d3 279u +#define id_atxmega16d4 234u +#define id_atxmega32d4 241u +#define id_atxmega64d4 253u +#define id_atxmega128d4 265u +#define id_atxmega8e5 230u +#define id_atxmega16e5 235u +#define id_atxmega32e5 242u #define id_attiny202 280u #define id_attiny204 281u -#define id_attiny212 282u -#define id_attiny214 283u #define id_attiny402 284u #define id_attiny404 285u #define id_attiny406 286u +#define id_attiny804 295u +#define id_attiny806 296u +#define id_attiny807 297u +#define id_attiny1604 304u +#define id_attiny1606 305u +#define id_attiny1607 306u +#define id_attiny212 282u +#define id_attiny214 283u #define id_attiny412 287u #define id_attiny414 288u #define id_attiny416 289u #define id_attiny416auto 290u #define id_attiny417 291u -#define id_attiny424 292u -#define id_attiny426 293u -#define id_attiny427 294u -#define id_attiny804 295u -#define id_attiny806 296u -#define id_attiny807 297u #define id_attiny814 298u #define id_attiny816 299u #define id_attiny817 300u -#define id_attiny824 301u -#define id_attiny826 302u -#define id_attiny827 303u -#define id_attiny1604 304u -#define id_attiny1606 305u -#define id_attiny1607 306u #define id_attiny1614 307u #define id_attiny1616 308u #define id_attiny1617 309u -#define id_attiny1624 310u -#define id_attiny1626 311u -#define id_attiny1627 312u #define id_attiny3214 313u #define id_attiny3216 314u #define id_attiny3217 315u +#define id_attiny424 292u +#define id_attiny426 293u +#define id_attiny427 294u +#define id_attiny824 301u +#define id_attiny826 302u +#define id_attiny827 303u +#define id_attiny1624 310u +#define id_attiny1626 311u +#define id_attiny1627 312u #define id_attiny3224 316u #define id_attiny3226 317u #define id_attiny3227 318u @@ -488,93 +490,91 @@ extern const Avrintel uP_table[422]; #define id_atmega3209 324u #define id_atmega4808 325u #define id_atmega4809 326u -#define id_avr8ea28 327u -#define id_avr8ea32 328u -#define id_avr16dd14 329u -#define id_avr16du14 386u -#define id_avr16eb14 380u -#define id_avr16la14 414u -#define id_avr16dd20 330u -#define id_avr16du20 387u -#define id_avr16eb20 381u -#define id_avr16la20 415u -#define id_avr16dd28 331u -#define id_avr16du28 388u -#define id_avr16ea28 332u -#define id_avr16eb28 382u -#define id_avr16la28 416u -#define id_avr16dd32 333u -#define id_avr16du32 389u -#define id_avr16ea32 334u -#define id_avr16eb32 383u -#define id_avr16la32 417u -#define id_avr16ea48 335u -#define id_avr32dd14 336u -#define id_avr32du14 390u -#define id_avr32eb14 398u -#define id_avr32la14 418u -#define id_avr32dd20 337u -#define id_avr32du20 391u -#define id_avr32eb20 399u -#define id_avr32la20 419u -#define id_avr32sd20 402u #define id_avr32da28 338u #define id_avr32da28s 405u -#define id_avr32db28 339u -#define id_avr32dd28 340u -#define id_avr32du28 392u -#define id_avr32ea28 341u -#define id_avr32eb28 400u -#define id_avr32la28 420u -#define id_avr32sd28 403u #define id_avr32da32 342u #define id_avr32da32s 406u -#define id_avr32db32 343u -#define id_avr32dd32 344u -#define id_avr32du32 393u -#define id_avr32ea32 345u -#define id_avr32eb32 401u -#define id_avr32la32 421u -#define id_avr32sd32 404u #define id_avr32da48 346u #define id_avr32da48s 407u -#define id_avr32db48 347u -#define id_avr32ea48 348u -#define id_avr64dd14 349u -#define id_avr64dd20 350u #define id_avr64da28 351u #define id_avr64da28s 408u -#define id_avr64db28 352u -#define id_avr64dd28 353u -#define id_avr64du28 384u -#define id_avr64ea28 354u #define id_avr64da32 355u #define id_avr64da32s 409u -#define id_avr64db32 356u -#define id_avr64dd32 357u -#define id_avr64du32 385u -#define id_avr64ea32 358u #define id_avr64da48 359u #define id_avr64da48s 410u -#define id_avr64db48 360u -#define id_avr64ea48 361u #define id_avr64da64 362u #define id_avr64da64s 411u -#define id_avr64db64 363u #define id_avr128da28 364u #define id_avr128da28s 394u -#define id_avr128db28 365u #define id_avr128da32 366u #define id_avr128da32s 395u -#define id_avr128db32 367u #define id_avr128da48 368u #define id_avr128da48s 396u -#define id_avr128db48 369u #define id_avr128da64 370u #define id_avr128da64s 397u +#define id_avr32db28 339u +#define id_avr32db32 343u +#define id_avr32db48 347u +#define id_avr64db28 352u +#define id_avr64db32 356u +#define id_avr64db48 360u +#define id_avr64db64 363u +#define id_avr128db28 365u +#define id_avr128db32 367u +#define id_avr128db48 369u #define id_avr128db64 371u -#define id_at89s51 372u -#define id_at89s52 373u +#define id_avr16dd14 329u +#define id_avr16dd20 330u +#define id_avr16dd28 331u +#define id_avr16dd32 333u +#define id_avr32dd14 336u +#define id_avr32dd20 337u +#define id_avr32dd28 340u +#define id_avr32dd32 344u +#define id_avr64dd14 349u +#define id_avr64dd20 350u +#define id_avr64dd28 353u +#define id_avr64dd32 357u +#define id_avr16du14 386u +#define id_avr16du20 387u +#define id_avr16du28 388u +#define id_avr16du32 389u +#define id_avr32du14 390u +#define id_avr32du20 391u +#define id_avr32du28 392u +#define id_avr32du32 393u +#define id_avr64du28 384u +#define id_avr64du32 385u +#define id_avr8ea28 327u +#define id_avr8ea32 328u +#define id_avr16ea28 332u +#define id_avr16ea32 334u +#define id_avr16ea48 335u +#define id_avr32ea28 341u +#define id_avr32ea32 345u +#define id_avr32ea48 348u +#define id_avr64ea28 354u +#define id_avr64ea32 358u +#define id_avr64ea48 361u +#define id_avr16eb14 380u +#define id_avr16eb20 381u +#define id_avr16eb28 382u +#define id_avr16eb32 383u +#define id_avr32eb14 398u +#define id_avr32eb20 399u +#define id_avr32eb28 400u +#define id_avr32eb32 401u +#define id_avr16la14 414u +#define id_avr16la20 415u +#define id_avr16la28 416u +#define id_avr16la32 417u +#define id_avr32la14 418u +#define id_avr32la20 419u +#define id_avr32la28 420u +#define id_avr32la32 421u +#define id_avr32sd20 402u +#define id_avr32sd28 403u +#define id_avr32sd32 404u // Interrupt vector table sizes (number of vectors) @@ -587,185 +587,7 @@ extern const Avrintel uP_table[422]; #define vts_attiny40 18 #define vts_attiny102 16 #define vts_attiny104 16 -#define vts_attiny11 5 -#define vts_attiny12 6 -#define vts_attiny13 10 -#define vts_attiny13a 10 -#define vts_attiny15 9 -#define vts_attiny22 3 -#define vts_attiny24 17 -#define vts_attiny24a 17 -#define vts_attiny25 15 -#define vts_attiny26 12 -#define vts_attiny28 6 -#define vts_attiny43u 16 -#define vts_attiny44 17 -#define vts_attiny44a 17 -#define vts_attiny45 15 -#define vts_attiny48 20 -#define vts_attiny84 17 -#define vts_attiny84a 17 -#define vts_attiny85 15 -#define vts_attiny87 20 -#define vts_attiny88 20 -#define vts_attiny167 20 -#define vts_attiny261 19 -#define vts_attiny261a 19 -#define vts_attiny441 30 -#define vts_attiny461 19 -#define vts_attiny461a 19 -#define vts_attiny828 26 -#define vts_attiny828r 26 -#define vts_attiny841 30 -#define vts_attiny861 19 -#define vts_attiny861a 19 -#define vts_attiny1634 28 -#define vts_attiny1634r 28 -#define vts_attiny2313 19 -#define vts_attiny2313a 21 -#define vts_attiny4313 21 -#define vts_atmega8 19 -#define vts_atmega8a 19 -#define vts_atmega8hva 21 -#define vts_atmega8u2 29 -#define vts_atmega16 21 -#define vts_atmega16a 21 -#define vts_atmega16hva 21 -#define vts_atmega16hvb 29 -#define vts_atmega16hvbrevb 29 -#define vts_atmega16m1 31 -#define vts_atmega16hva2 22 -#define vts_atmega16u2 29 -#define vts_atmega16u4 43 -#define vts_atmega32 21 -#define vts_atmega32a 21 -#define vts_atmega32hvb 29 -#define vts_atmega32hvbrevb 29 -#define vts_atmega32c1 31 -#define vts_atmega32m1 31 -#define vts_atmega32hve2 25 -#define vts_atmega32u2 29 -#define vts_atmega32u4 43 -#define vts_atmega32u6 38 -#define vts_atmega48 26 -#define vts_atmega48a 26 -#define vts_atmega48p 26 -#define vts_atmega48pa 26 -#define vts_atmega48pb 27 -#define vts_atmega64 35 -#define vts_atmega64a 35 -#define vts_atmega64hve 25 -#define vts_atmega64c1 31 -#define vts_atmegas64m1 31 -#define vts_atmega64m1 31 -#define vts_atmega64hve2 25 -#define vts_atmega64rfr2 77 -#define vts_atmega88 26 -#define vts_atmega88a 26 -#define vts_atmega88p 26 -#define vts_atmega88pa 26 -#define vts_atmega88pb 27 -#define vts_atmega103 24 -#define vts_atmega128 35 -#define vts_atmegas128 35 -#define vts_atmega128a 35 -#define vts_atmega128rfa1 72 -#define vts_atmega128rfr2 77 -#define vts_atmega161 21 -#define vts_atmega162 28 -#define vts_atmega163 18 -#define vts_atmega164a 31 -#define vts_atmega164p 31 -#define vts_atmega164pa 31 -#define vts_atmega165 22 -#define vts_atmega165a 22 -#define vts_atmega165p 22 -#define vts_atmega165pa 22 -#define vts_atmega168 26 -#define vts_atmega168a 26 -#define vts_atmega168p 26 -#define vts_atmega168pa 26 -#define vts_atmega168pb 27 -#define vts_atmega169 23 -#define vts_atmega169a 23 -#define vts_atmega169p 23 -#define vts_atmega169pa 23 -#define vts_atmega256rfr2 77 -#define vts_atmega323 21 -#define vts_atmega324a 31 -#define vts_atmega324p 31 -#define vts_atmega324pa 31 -#define vts_atmega324pb 51 -#define vts_atmega325 22 -#define vts_atmega325a 22 -#define vts_atmega325p 22 -#define vts_atmega325pa 22 -#define vts_atmega328 26 -#define vts_atmega328p 26 -#define vts_atmega328pb 45 -#define vts_atmega329 23 -#define vts_atmega329a 23 -#define vts_atmega329p 23 -#define vts_atmega329pa 23 -#define vts_atmega406 23 -#define vts_atmega640 57 -#define vts_atmega644 28 -#define vts_atmega644a 31 -#define vts_atmega644p 31 -#define vts_atmega644pa 31 -#define vts_atmega644rfr2 77 -#define vts_atmega645 22 -#define vts_atmega645a 22 -#define vts_atmega645p 22 -#define vts_atmega649 23 -#define vts_atmega649a 23 -#define vts_atmega649p 23 -#define vts_atmega1280 57 -#define vts_atmega1281 57 -#define vts_atmega1284 35 -#define vts_atmega1284p 35 -#define vts_atmega1284rfr2 77 -#define vts_atmega2560 57 -#define vts_atmega2561 57 -#define vts_atmega2564rfr2 77 -#define vts_atmega3250 25 -#define vts_atmega3250a 25 -#define vts_atmega3250p 25 -#define vts_atmega3250pa 25 -#define vts_atmega3290 25 -#define vts_atmega3290a 25 -#define vts_atmega3290p 25 -#define vts_atmega3290pa 25 -#define vts_atmega6450 25 -#define vts_atmega6450a 25 -#define vts_atmega6450p 25 -#define vts_atmega6490 25 -#define vts_atmega6490a 25 -#define vts_atmega6490p 25 -#define vts_atmega8515 17 -#define vts_atmega8535 21 -#define vts_at86rf401 3 -#define vts_at90pwm1 32 -#define vts_at90pwm2 32 -#define vts_at90pwm2b 32 -#define vts_at90pwm3 32 -#define vts_at90pwm3b 32 -#define vts_at90can32 37 -#define vts_at90can64 37 -#define vts_at90pwm81 20 -#define vts_at90usb82 29 -#define vts_at90scr100 38 -#define vts_at90scr100h 38 -#define vts_at90can128 37 -#define vts_at90pwm161 20 -#define vts_at90usb162 29 -#define vts_at90pwm216 32 -#define vts_at90pwm316 32 -#define vts_at90usb646 38 -#define vts_at90usb647 38 #define vts_at90s1200 4 -#define vts_at90usb1286 38 -#define vts_at90usb1287 38 #define vts_at90s2313 11 #define vts_at90s2323 3 #define vts_at90s2333 14 @@ -775,6 +597,187 @@ extern const Avrintel uP_table[422]; #define vts_at90s4434 17 #define vts_at90s8515 13 #define vts_at90s8535 17 +#define vts_at90can32 37 +#define vts_at90can64 37 +#define vts_at90can128 37 +#define vts_at90pwm1 32 +#define vts_at90pwm81 20 +#define vts_at90pwm161 20 +#define vts_at90pwm2 32 +#define vts_at90pwm2b 32 +#define vts_at90pwm216 32 +#define vts_at90pwm3 32 +#define vts_at90pwm3b 32 +#define vts_at90pwm316 32 +#define vts_at90usb82 29 +#define vts_at90usb162 29 +#define vts_at90usb646 38 +#define vts_at90usb1286 38 +#define vts_at90usb647 38 +#define vts_at90usb1287 38 +#define vts_at90scr100 38 +#define vts_at90scr100h 38 +#define vts_at86rf401 3 +#define vts_attiny11 5 +#define vts_attiny12 6 +#define vts_attiny22 3 +#define vts_attiny13 10 +#define vts_attiny13a 10 +#define vts_attiny43u 16 +#define vts_attiny24 17 +#define vts_attiny24a 17 +#define vts_attiny44 17 +#define vts_attiny44a 17 +#define vts_attiny84 17 +#define vts_attiny84a 17 +#define vts_attiny15 9 +#define vts_attiny25 15 +#define vts_attiny45 15 +#define vts_attiny85 15 +#define vts_attiny26 12 +#define vts_attiny87 20 +#define vts_attiny167 20 +#define vts_attiny28 6 +#define vts_attiny48 20 +#define vts_attiny88 20 +#define vts_attiny828 26 +#define vts_attiny828r 26 +#define vts_attiny1634 28 +#define vts_attiny1634r 28 +#define vts_attiny441 30 +#define vts_attiny841 30 +#define vts_attiny261 19 +#define vts_attiny261a 19 +#define vts_attiny461 19 +#define vts_attiny461a 19 +#define vts_attiny861 19 +#define vts_attiny861a 19 +#define vts_attiny2313 19 +#define vts_attiny2313a 21 +#define vts_attiny4313 21 +#define vts_atmega8 19 +#define vts_atmega8a 19 +#define vts_atmega16 21 +#define vts_atmega16a 21 +#define vts_atmega32 21 +#define vts_atmega32a 21 +#define vts_atmega64 35 +#define vts_atmega64a 35 +#define vts_atmega128 35 +#define vts_atmega128a 35 +#define vts_atmegas128 35 +#define vts_atmega640 57 +#define vts_atmega1280 57 +#define vts_atmega2560 57 +#define vts_atmega32c1 31 +#define vts_atmega64c1 31 +#define vts_atmega16m1 31 +#define vts_atmega32m1 31 +#define vts_atmega64m1 31 +#define vts_atmegas64m1 31 +#define vts_atmega128rfa1 72 +#define vts_atmega64rfr2 77 +#define vts_atmega128rfr2 77 +#define vts_atmega256rfr2 77 +#define vts_atmega8u2 29 +#define vts_atmega16u2 29 +#define vts_atmega32u2 29 +#define vts_atmega16u4 43 +#define vts_atmega32u4 43 +#define vts_atmega32u6 38 +#define vts_atmega161 21 +#define vts_atmega1281 57 +#define vts_atmega2561 57 +#define vts_atmega162 28 +#define vts_atmega163 18 +#define vts_atmega323 21 +#define vts_atmega164a 31 +#define vts_atmega164p 31 +#define vts_atmega164pa 31 +#define vts_atmega324a 31 +#define vts_atmega324p 31 +#define vts_atmega324pa 31 +#define vts_atmega644 28 +#define vts_atmega644a 31 +#define vts_atmega644p 31 +#define vts_atmega644pa 31 +#define vts_atmega1284 35 +#define vts_atmega1284p 35 +#define vts_atmega324pb 51 +#define vts_atmega644rfr2 77 +#define vts_atmega1284rfr2 77 +#define vts_atmega2564rfr2 77 +#define vts_atmega165 22 +#define vts_atmega165a 22 +#define vts_atmega165p 22 +#define vts_atmega165pa 22 +#define vts_atmega325 22 +#define vts_atmega325a 22 +#define vts_atmega325p 22 +#define vts_atmega325pa 22 +#define vts_atmega645 22 +#define vts_atmega645a 22 +#define vts_atmega645p 22 +#define vts_atmega3250 25 +#define vts_atmega3250a 25 +#define vts_atmega3250p 25 +#define vts_atmega3250pa 25 +#define vts_atmega6450 25 +#define vts_atmega6450a 25 +#define vts_atmega6450p 25 +#define vts_atmega8515 17 +#define vts_atmega8535 21 +#define vts_atmega48 26 +#define vts_atmega48a 26 +#define vts_atmega48p 26 +#define vts_atmega48pa 26 +#define vts_atmega88 26 +#define vts_atmega88a 26 +#define vts_atmega88p 26 +#define vts_atmega88pa 26 +#define vts_atmega168 26 +#define vts_atmega168a 26 +#define vts_atmega168p 26 +#define vts_atmega168pa 26 +#define vts_atmega328 26 +#define vts_atmega328p 26 +#define vts_atmega48pb 27 +#define vts_atmega88pb 27 +#define vts_atmega168pb 27 +#define vts_atmega328pb 45 +#define vts_atmega169 23 +#define vts_atmega169a 23 +#define vts_atmega169p 23 +#define vts_atmega169pa 23 +#define vts_atmega329 23 +#define vts_atmega329a 23 +#define vts_atmega329p 23 +#define vts_atmega329pa 23 +#define vts_atmega649 23 +#define vts_atmega649a 23 +#define vts_atmega649p 23 +#define vts_atmega3290 25 +#define vts_atmega3290a 25 +#define vts_atmega3290p 25 +#define vts_atmega3290pa 25 +#define vts_atmega6490 25 +#define vts_atmega6490a 25 +#define vts_atmega6490p 25 +#define vts_lgt8f88p 26 +#define vts_lgt8f168p 26 +#define vts_lgt8f328p 26 +#define vts_atmega103 24 +#define vts_atmega8hva 21 +#define vts_atmega16hva 21 +#define vts_atmega16hva2 22 +#define vts_atmega16hvb 29 +#define vts_atmega16hvbrevb 29 +#define vts_atmega32hvb 29 +#define vts_atmega32hvbrevb 29 +#define vts_atmega64hve 25 +#define vts_atmega32hve2 25 +#define vts_atmega64hve2 25 +#define vts_atmega406 23 #define vts_ata5272 37 #define vts_ata5505 20 #define vts_ata5700m322 51 @@ -799,96 +802,93 @@ extern const Avrintel uP_table[422]; #define vts_ata6614q 26 #define vts_ata6616c 20 #define vts_ata6617c 20 +#define vts_ata664251 20 #define vts_ata8210 42 #define vts_ata8215 42 #define vts_ata8510 42 #define vts_ata8515 42 -#define vts_ata664251 20 -#define vts_lgt8f88p 26 -#define vts_lgt8f168p 26 -#define vts_lgt8f328p 26 -#define vts_atxmega8e5 43 -#define vts_atxmega16a4 94 -#define vts_atxmega16a4u 127 -#define vts_atxmega16c4 127 -#define vts_atxmega16d4 91 -#define vts_atxmega16e5 43 -#define vts_atxmega32c3 127 -#define vts_atxmega32d3 114 -#define vts_atxmega32a4 94 -#define vts_atxmega32a4u 127 -#define vts_atxmega32c4 127 -#define vts_atxmega32d4 91 -#define vts_atxmega32e5 43 #define vts_atxmega64a1 125 -#define vts_atxmega64a1u 127 -#define vts_atxmega64b1 81 -#define vts_atxmega64a3 122 -#define vts_atxmega64a3u 127 -#define vts_atxmega64b3 54 -#define vts_atxmega64c3 127 -#define vts_atxmega64d3 114 -#define vts_atxmega64a4u 127 -#define vts_atxmega64d4 91 #define vts_atxmega128a1 125 #define vts_atxmega128a1revd 125 +#define vts_atxmega64a1u 127 #define vts_atxmega128a1u 127 -#define vts_atxmega128b1 81 +#define vts_atxmega64a3 122 #define vts_atxmega128a3 122 -#define vts_atxmega128a3u 127 -#define vts_atxmega128b3 54 -#define vts_atxmega128c3 127 -#define vts_atxmega128d3 114 -#define vts_atxmega128a4u 127 -#define vts_atxmega128d4 91 #define vts_atxmega192a3 122 -#define vts_atxmega192a3u 127 -#define vts_atxmega192c3 127 -#define vts_atxmega192d3 114 #define vts_atxmega256a3 122 #define vts_atxmega256a3b 122 +#define vts_atxmega64a3u 127 +#define vts_atxmega128a3u 127 +#define vts_atxmega192a3u 127 #define vts_atxmega256a3bu 127 #define vts_atxmega256a3u 127 +#define vts_atxmega16a4 94 +#define vts_atxmega32a4 94 +#define vts_atxmega16a4u 127 +#define vts_atxmega32a4u 127 +#define vts_atxmega64a4u 127 +#define vts_atxmega128a4u 127 +#define vts_atxmega64b1 81 +#define vts_atxmega128b1 81 +#define vts_atxmega64b3 54 +#define vts_atxmega128b3 54 +#define vts_atxmega32c3 127 +#define vts_atxmega64c3 127 +#define vts_atxmega128c3 127 +#define vts_atxmega192c3 127 #define vts_atxmega256c3 127 -#define vts_atxmega256d3 114 #define vts_atxmega384c3 127 +#define vts_atxmega16c4 127 +#define vts_atxmega32c4 127 +#define vts_atxmega32d3 114 +#define vts_atxmega64d3 114 +#define vts_atxmega128d3 114 +#define vts_atxmega192d3 114 +#define vts_atxmega256d3 114 #define vts_atxmega384d3 114 +#define vts_atxmega16d4 91 +#define vts_atxmega32d4 91 +#define vts_atxmega64d4 91 +#define vts_atxmega128d4 91 +#define vts_atxmega8e5 43 +#define vts_atxmega16e5 43 +#define vts_atxmega32e5 43 #define vts_attiny202 26 #define vts_attiny204 26 -#define vts_attiny212 26 -#define vts_attiny214 26 #define vts_attiny402 26 #define vts_attiny404 26 #define vts_attiny406 26 +#define vts_attiny804 31 +#define vts_attiny806 31 +#define vts_attiny807 31 +#define vts_attiny1604 31 +#define vts_attiny1606 31 +#define vts_attiny1607 31 +#define vts_attiny212 26 +#define vts_attiny214 26 #define vts_attiny412 26 #define vts_attiny414 26 #define vts_attiny416 26 #define vts_attiny416auto 26 #define vts_attiny417 26 -#define vts_attiny424 30 -#define vts_attiny426 30 -#define vts_attiny427 30 -#define vts_attiny804 31 -#define vts_attiny806 31 -#define vts_attiny807 31 #define vts_attiny814 26 #define vts_attiny816 26 #define vts_attiny817 26 -#define vts_attiny824 30 -#define vts_attiny826 30 -#define vts_attiny827 30 -#define vts_attiny1604 31 -#define vts_attiny1606 31 -#define vts_attiny1607 31 #define vts_attiny1614 31 #define vts_attiny1616 31 #define vts_attiny1617 31 -#define vts_attiny1624 30 -#define vts_attiny1626 30 -#define vts_attiny1627 30 #define vts_attiny3214 31 #define vts_attiny3216 31 #define vts_attiny3217 31 +#define vts_attiny424 30 +#define vts_attiny426 30 +#define vts_attiny427 30 +#define vts_attiny824 30 +#define vts_attiny826 30 +#define vts_attiny827 30 +#define vts_attiny1624 30 +#define vts_attiny1626 30 +#define vts_attiny1627 30 #define vts_attiny3224 30 #define vts_attiny3226 30 #define vts_attiny3227 30 @@ -900,89 +900,89 @@ extern const Avrintel uP_table[422]; #define vts_atmega3209 40 #define vts_atmega4808 36 #define vts_atmega4809 40 -#define vts_avr16dd14 36 -#define vts_avr16du14 34 -#define vts_avr16eb14 31 -#define vts_avr16la14 29 -#define vts_avr16dd20 36 -#define vts_avr16du20 34 -#define vts_avr16eb20 31 -#define vts_avr16la20 29 -#define vts_avr16dd28 36 -#define vts_avr16du28 34 -#define vts_avr16ea28 43 -#define vts_avr16eb28 31 -#define vts_avr16la28 29 -#define vts_avr16dd32 36 -#define vts_avr16du32 34 -#define vts_avr16ea32 43 -#define vts_avr16eb32 31 -#define vts_avr16la32 29 -#define vts_avr16ea48 45 -#define vts_avr32dd14 36 -#define vts_avr32du14 34 -#define vts_avr32eb14 31 -#define vts_avr32la14 29 -#define vts_avr32dd20 36 -#define vts_avr32du20 34 -#define vts_avr32eb20 31 -#define vts_avr32la20 29 -#define vts_avr32sd20 50 #define vts_avr32da28 41 #define vts_avr32da28s 41 -#define vts_avr32db28 42 -#define vts_avr32dd28 36 -#define vts_avr32du28 34 -#define vts_avr32ea28 43 -#define vts_avr32eb28 31 -#define vts_avr32la28 29 -#define vts_avr32sd28 54 #define vts_avr32da32 44 #define vts_avr32da32s 44 -#define vts_avr32db32 44 -#define vts_avr32dd32 36 -#define vts_avr32du32 34 -#define vts_avr32ea32 43 -#define vts_avr32eb32 31 -#define vts_avr32la32 29 -#define vts_avr32sd32 56 #define vts_avr32da48 61 #define vts_avr32da48s 61 -#define vts_avr32db48 61 -#define vts_avr32ea48 45 -#define vts_avr64dd14 36 -#define vts_avr64dd20 36 #define vts_avr64da28 41 #define vts_avr64da28s 41 -#define vts_avr64db28 42 -#define vts_avr64dd28 36 -#define vts_avr64du28 34 -#define vts_avr64ea28 43 #define vts_avr64da32 44 #define vts_avr64da32s 44 -#define vts_avr64db32 44 -#define vts_avr64dd32 36 -#define vts_avr64du32 34 -#define vts_avr64ea32 43 #define vts_avr64da48 58 #define vts_avr64da48s 58 -#define vts_avr64db48 61 -#define vts_avr64ea48 45 #define vts_avr64da64 64 #define vts_avr64da64s 64 -#define vts_avr64db64 65 #define vts_avr128da28 41 #define vts_avr128da28s 41 -#define vts_avr128db28 42 #define vts_avr128da32 44 #define vts_avr128da32s 44 -#define vts_avr128db32 44 #define vts_avr128da48 58 #define vts_avr128da48s 58 -#define vts_avr128db48 61 #define vts_avr128da64 64 #define vts_avr128da64s 64 +#define vts_avr32db28 42 +#define vts_avr32db32 44 +#define vts_avr32db48 61 +#define vts_avr64db28 42 +#define vts_avr64db32 44 +#define vts_avr64db48 61 +#define vts_avr64db64 65 +#define vts_avr128db28 42 +#define vts_avr128db32 44 +#define vts_avr128db48 61 #define vts_avr128db64 65 +#define vts_avr16dd14 36 +#define vts_avr16dd20 36 +#define vts_avr16dd28 36 +#define vts_avr16dd32 36 +#define vts_avr32dd14 36 +#define vts_avr32dd20 36 +#define vts_avr32dd28 36 +#define vts_avr32dd32 36 +#define vts_avr64dd14 36 +#define vts_avr64dd20 36 +#define vts_avr64dd28 36 +#define vts_avr64dd32 36 +#define vts_avr16du14 34 +#define vts_avr16du20 34 +#define vts_avr16du28 34 +#define vts_avr16du32 34 +#define vts_avr32du14 34 +#define vts_avr32du20 34 +#define vts_avr32du28 34 +#define vts_avr32du32 34 +#define vts_avr64du28 34 +#define vts_avr64du32 34 +#define vts_avr16ea28 43 +#define vts_avr16ea32 43 +#define vts_avr16ea48 45 +#define vts_avr32ea28 43 +#define vts_avr32ea32 43 +#define vts_avr32ea48 45 +#define vts_avr64ea28 43 +#define vts_avr64ea32 43 +#define vts_avr64ea48 45 +#define vts_avr16eb14 31 +#define vts_avr16eb20 31 +#define vts_avr16eb28 31 +#define vts_avr16eb32 31 +#define vts_avr32eb14 31 +#define vts_avr32eb20 31 +#define vts_avr32eb28 31 +#define vts_avr32eb32 31 +#define vts_avr16la14 29 +#define vts_avr16la20 29 +#define vts_avr16la28 29 +#define vts_avr16la32 29 +#define vts_avr32la14 29 +#define vts_avr32la20 29 +#define vts_avr32la28 29 +#define vts_avr32la32 29 +#define vts_avr32sd20 50 +#define vts_avr32sd28 54 +#define vts_avr32sd32 56 // Suggested vector bootloader interrupt: first unused vector or slot just above vector table @@ -995,185 +995,7 @@ extern const Avrintel uP_table[422]; #define vbu_attiny40 18 #define vbu_attiny102 16 #define vbu_attiny104 16 -#define vbu_attiny11 5 -#define vbu_attiny12 6 -#define vbu_attiny13 10 -#define vbu_attiny13a 10 -#define vbu_attiny15 9 -#define vbu_attiny22 3 -#define vbu_attiny24 17 -#define vbu_attiny24a 17 -#define vbu_attiny25 15 -#define vbu_attiny26 12 -#define vbu_attiny28 6 -#define vbu_attiny43u 16 -#define vbu_attiny44 17 -#define vbu_attiny44a 17 -#define vbu_attiny45 15 -#define vbu_attiny48 20 -#define vbu_attiny84 17 -#define vbu_attiny84a 17 -#define vbu_attiny85 15 -#define vbu_attiny87 20 -#define vbu_attiny88 20 -#define vbu_attiny167 20 -#define vbu_attiny261 19 -#define vbu_attiny261a 19 -#define vbu_attiny441 30 -#define vbu_attiny461 19 -#define vbu_attiny461a 19 -#define vbu_attiny828 26 -#define vbu_attiny828r 26 -#define vbu_attiny841 30 -#define vbu_attiny861 19 -#define vbu_attiny861a 19 -#define vbu_attiny1634 28 -#define vbu_attiny1634r 28 -#define vbu_attiny2313 19 -#define vbu_attiny2313a 21 -#define vbu_attiny4313 21 -#define vbu_atmega8 19 -#define vbu_atmega8a 19 -#define vbu_atmega8hva 21 -#define vbu_atmega8u2 29 -#define vbu_atmega16 21 -#define vbu_atmega16a 21 -#define vbu_atmega16hva 21 -#define vbu_atmega16hvb 29 -#define vbu_atmega16hvbrevb 29 -#define vbu_atmega16m1 31 -#define vbu_atmega16hva2 22 -#define vbu_atmega16u2 29 -#define vbu_atmega16u4 5 -#define vbu_atmega32 21 -#define vbu_atmega32a 21 -#define vbu_atmega32hvb 29 -#define vbu_atmega32hvbrevb 29 -#define vbu_atmega32c1 31 -#define vbu_atmega32m1 31 -#define vbu_atmega32hve2 25 -#define vbu_atmega32u2 29 -#define vbu_atmega32u4 5 -#define vbu_atmega32u6 38 -#define vbu_atmega48 26 -#define vbu_atmega48a 26 -#define vbu_atmega48p 26 -#define vbu_atmega48pa 26 -#define vbu_atmega48pb 27 -#define vbu_atmega64 35 -#define vbu_atmega64a 35 -#define vbu_atmega64hve 25 -#define vbu_atmega64c1 31 -#define vbu_atmegas64m1 31 -#define vbu_atmega64m1 31 -#define vbu_atmega64hve2 25 -#define vbu_atmega64rfr2 51 -#define vbu_atmega88 26 -#define vbu_atmega88a 26 -#define vbu_atmega88p 26 -#define vbu_atmega88pa 26 -#define vbu_atmega88pb 27 -#define vbu_atmega103 24 -#define vbu_atmega128 35 -#define vbu_atmegas128 35 -#define vbu_atmega128a 35 -#define vbu_atmega128rfa1 51 -#define vbu_atmega128rfr2 51 -#define vbu_atmega161 21 -#define vbu_atmega162 28 -#define vbu_atmega163 18 -#define vbu_atmega164a 31 -#define vbu_atmega164p 31 -#define vbu_atmega164pa 31 -#define vbu_atmega165 22 -#define vbu_atmega165a 22 -#define vbu_atmega165p 22 -#define vbu_atmega165pa 22 -#define vbu_atmega168 26 -#define vbu_atmega168a 26 -#define vbu_atmega168p 26 -#define vbu_atmega168pa 26 -#define vbu_atmega168pb 27 -#define vbu_atmega169 23 -#define vbu_atmega169a 23 -#define vbu_atmega169p 23 -#define vbu_atmega169pa 23 -#define vbu_atmega256rfr2 51 -#define vbu_atmega323 21 -#define vbu_atmega324a 31 -#define vbu_atmega324p 31 -#define vbu_atmega324pa 31 -#define vbu_atmega324pb 51 -#define vbu_atmega325 22 -#define vbu_atmega325a 22 -#define vbu_atmega325p 22 -#define vbu_atmega325pa 22 -#define vbu_atmega328 26 -#define vbu_atmega328p 26 -#define vbu_atmega328pb 45 -#define vbu_atmega329 23 -#define vbu_atmega329a 23 -#define vbu_atmega329p 23 -#define vbu_atmega329pa 23 -#define vbu_atmega406 23 -#define vbu_atmega640 57 -#define vbu_atmega644 28 -#define vbu_atmega644a 31 -#define vbu_atmega644p 31 -#define vbu_atmega644pa 31 -#define vbu_atmega644rfr2 51 -#define vbu_atmega645 22 -#define vbu_atmega645a 22 -#define vbu_atmega645p 22 -#define vbu_atmega649 23 -#define vbu_atmega649a 23 -#define vbu_atmega649p 23 -#define vbu_atmega1280 57 -#define vbu_atmega1281 51 -#define vbu_atmega1284 35 -#define vbu_atmega1284p 35 -#define vbu_atmega1284rfr2 51 -#define vbu_atmega2560 57 -#define vbu_atmega2561 51 -#define vbu_atmega2564rfr2 51 -#define vbu_atmega3250 22 -#define vbu_atmega3250a 22 -#define vbu_atmega3250p 22 -#define vbu_atmega3250pa 22 -#define vbu_atmega3290 25 -#define vbu_atmega3290a 25 -#define vbu_atmega3290p 25 -#define vbu_atmega3290pa 25 -#define vbu_atmega6450 22 -#define vbu_atmega6450a 22 -#define vbu_atmega6450p 22 -#define vbu_atmega6490 25 -#define vbu_atmega6490a 25 -#define vbu_atmega6490p 25 -#define vbu_atmega8515 17 -#define vbu_atmega8535 21 -#define vbu_at86rf401 3 -#define vbu_at90pwm1 14 -#define vbu_at90pwm2 14 -#define vbu_at90pwm2b 14 -#define vbu_at90pwm3 14 -#define vbu_at90pwm3b 14 -#define vbu_at90can32 37 -#define vbu_at90can64 37 -#define vbu_at90pwm81 20 -#define vbu_at90usb82 29 -#define vbu_at90scr100 24 -#define vbu_at90scr100h 24 -#define vbu_at90can128 37 -#define vbu_at90pwm161 20 -#define vbu_at90usb162 29 -#define vbu_at90pwm216 14 -#define vbu_at90pwm316 14 -#define vbu_at90usb646 38 -#define vbu_at90usb647 38 #define vbu_at90s1200 4 -#define vbu_at90usb1286 38 -#define vbu_at90usb1287 38 #define vbu_at90s2313 11 #define vbu_at90s2323 3 #define vbu_at90s2333 14 @@ -1183,6 +1005,187 @@ extern const Avrintel uP_table[422]; #define vbu_at90s4434 17 #define vbu_at90s8515 13 #define vbu_at90s8535 17 +#define vbu_at90can32 37 +#define vbu_at90can64 37 +#define vbu_at90can128 37 +#define vbu_at90pwm1 14 +#define vbu_at90pwm81 20 +#define vbu_at90pwm161 20 +#define vbu_at90pwm2 14 +#define vbu_at90pwm2b 14 +#define vbu_at90pwm216 14 +#define vbu_at90pwm3 14 +#define vbu_at90pwm3b 14 +#define vbu_at90pwm316 14 +#define vbu_at90usb82 29 +#define vbu_at90usb162 29 +#define vbu_at90usb646 38 +#define vbu_at90usb1286 38 +#define vbu_at90usb647 38 +#define vbu_at90usb1287 38 +#define vbu_at90scr100 24 +#define vbu_at90scr100h 24 +#define vbu_at86rf401 3 +#define vbu_attiny11 5 +#define vbu_attiny12 6 +#define vbu_attiny22 3 +#define vbu_attiny13 10 +#define vbu_attiny13a 10 +#define vbu_attiny43u 16 +#define vbu_attiny24 17 +#define vbu_attiny24a 17 +#define vbu_attiny44 17 +#define vbu_attiny44a 17 +#define vbu_attiny84 17 +#define vbu_attiny84a 17 +#define vbu_attiny15 9 +#define vbu_attiny25 15 +#define vbu_attiny45 15 +#define vbu_attiny85 15 +#define vbu_attiny26 12 +#define vbu_attiny87 20 +#define vbu_attiny167 20 +#define vbu_attiny28 6 +#define vbu_attiny48 20 +#define vbu_attiny88 20 +#define vbu_attiny828 26 +#define vbu_attiny828r 26 +#define vbu_attiny1634 28 +#define vbu_attiny1634r 28 +#define vbu_attiny441 30 +#define vbu_attiny841 30 +#define vbu_attiny261 19 +#define vbu_attiny261a 19 +#define vbu_attiny461 19 +#define vbu_attiny461a 19 +#define vbu_attiny861 19 +#define vbu_attiny861a 19 +#define vbu_attiny2313 19 +#define vbu_attiny2313a 21 +#define vbu_attiny4313 21 +#define vbu_atmega8 19 +#define vbu_atmega8a 19 +#define vbu_atmega16 21 +#define vbu_atmega16a 21 +#define vbu_atmega32 21 +#define vbu_atmega32a 21 +#define vbu_atmega64 35 +#define vbu_atmega64a 35 +#define vbu_atmega128 35 +#define vbu_atmega128a 35 +#define vbu_atmegas128 35 +#define vbu_atmega640 57 +#define vbu_atmega1280 57 +#define vbu_atmega2560 57 +#define vbu_atmega32c1 31 +#define vbu_atmega64c1 31 +#define vbu_atmega16m1 31 +#define vbu_atmega32m1 31 +#define vbu_atmega64m1 31 +#define vbu_atmegas64m1 31 +#define vbu_atmega128rfa1 51 +#define vbu_atmega64rfr2 51 +#define vbu_atmega128rfr2 51 +#define vbu_atmega256rfr2 51 +#define vbu_atmega8u2 29 +#define vbu_atmega16u2 29 +#define vbu_atmega32u2 29 +#define vbu_atmega16u4 5 +#define vbu_atmega32u4 5 +#define vbu_atmega32u6 38 +#define vbu_atmega161 21 +#define vbu_atmega1281 51 +#define vbu_atmega2561 51 +#define vbu_atmega162 28 +#define vbu_atmega163 18 +#define vbu_atmega323 21 +#define vbu_atmega164a 31 +#define vbu_atmega164p 31 +#define vbu_atmega164pa 31 +#define vbu_atmega324a 31 +#define vbu_atmega324p 31 +#define vbu_atmega324pa 31 +#define vbu_atmega644 28 +#define vbu_atmega644a 31 +#define vbu_atmega644p 31 +#define vbu_atmega644pa 31 +#define vbu_atmega1284 35 +#define vbu_atmega1284p 35 +#define vbu_atmega324pb 51 +#define vbu_atmega644rfr2 51 +#define vbu_atmega1284rfr2 51 +#define vbu_atmega2564rfr2 51 +#define vbu_atmega165 22 +#define vbu_atmega165a 22 +#define vbu_atmega165p 22 +#define vbu_atmega165pa 22 +#define vbu_atmega325 22 +#define vbu_atmega325a 22 +#define vbu_atmega325p 22 +#define vbu_atmega325pa 22 +#define vbu_atmega645 22 +#define vbu_atmega645a 22 +#define vbu_atmega645p 22 +#define vbu_atmega3250 22 +#define vbu_atmega3250a 22 +#define vbu_atmega3250p 22 +#define vbu_atmega3250pa 22 +#define vbu_atmega6450 22 +#define vbu_atmega6450a 22 +#define vbu_atmega6450p 22 +#define vbu_atmega8515 17 +#define vbu_atmega8535 21 +#define vbu_atmega48 26 +#define vbu_atmega48a 26 +#define vbu_atmega48p 26 +#define vbu_atmega48pa 26 +#define vbu_atmega88 26 +#define vbu_atmega88a 26 +#define vbu_atmega88p 26 +#define vbu_atmega88pa 26 +#define vbu_atmega168 26 +#define vbu_atmega168a 26 +#define vbu_atmega168p 26 +#define vbu_atmega168pa 26 +#define vbu_atmega328 26 +#define vbu_atmega328p 26 +#define vbu_atmega48pb 27 +#define vbu_atmega88pb 27 +#define vbu_atmega168pb 27 +#define vbu_atmega328pb 45 +#define vbu_atmega169 23 +#define vbu_atmega169a 23 +#define vbu_atmega169p 23 +#define vbu_atmega169pa 23 +#define vbu_atmega329 23 +#define vbu_atmega329a 23 +#define vbu_atmega329p 23 +#define vbu_atmega329pa 23 +#define vbu_atmega649 23 +#define vbu_atmega649a 23 +#define vbu_atmega649p 23 +#define vbu_atmega3290 25 +#define vbu_atmega3290a 25 +#define vbu_atmega3290p 25 +#define vbu_atmega3290pa 25 +#define vbu_atmega6490 25 +#define vbu_atmega6490a 25 +#define vbu_atmega6490p 25 +#define vbu_lgt8f88p 26 +#define vbu_lgt8f168p 26 +#define vbu_lgt8f328p 26 +#define vbu_atmega103 24 +#define vbu_atmega8hva 21 +#define vbu_atmega16hva 21 +#define vbu_atmega16hva2 22 +#define vbu_atmega16hvb 29 +#define vbu_atmega16hvbrevb 29 +#define vbu_atmega32hvb 29 +#define vbu_atmega32hvbrevb 29 +#define vbu_atmega64hve 25 +#define vbu_atmega32hve2 25 +#define vbu_atmega64hve2 25 +#define vbu_atmega406 23 #define vbu_ata5272 17 #define vbu_ata5505 20 #define vbu_ata5700m322 51 @@ -1207,96 +1210,93 @@ extern const Avrintel uP_table[422]; #define vbu_ata6614q 26 #define vbu_ata6616c 20 #define vbu_ata6617c 20 +#define vbu_ata664251 20 #define vbu_ata8210 42 #define vbu_ata8215 42 #define vbu_ata8510 42 #define vbu_ata8515 42 -#define vbu_ata664251 20 -#define vbu_lgt8f88p 26 -#define vbu_lgt8f168p 26 -#define vbu_lgt8f328p 26 -#define vbu_atxmega8e5 43 -#define vbu_atxmega16a4 36 -#define vbu_atxmega16a4u 36 -#define vbu_atxmega16c4 6 -#define vbu_atxmega16d4 6 -#define vbu_atxmega16e5 43 -#define vbu_atxmega32c3 6 -#define vbu_atxmega32d3 6 -#define vbu_atxmega32a4 36 -#define vbu_atxmega32a4u 36 -#define vbu_atxmega32c4 6 -#define vbu_atxmega32d4 6 -#define vbu_atxmega32e5 43 #define vbu_atxmega64a1 102 -#define vbu_atxmega64a1u 102 -#define vbu_atxmega64b1 8 -#define vbu_atxmega64a3 75 -#define vbu_atxmega64a3u 75 -#define vbu_atxmega64b3 8 -#define vbu_atxmega64c3 6 -#define vbu_atxmega64d3 6 -#define vbu_atxmega64a4u 36 -#define vbu_atxmega64d4 6 #define vbu_atxmega128a1 102 #define vbu_atxmega128a1revd 102 +#define vbu_atxmega64a1u 102 #define vbu_atxmega128a1u 102 -#define vbu_atxmega128b1 8 +#define vbu_atxmega64a3 75 #define vbu_atxmega128a3 75 -#define vbu_atxmega128a3u 75 -#define vbu_atxmega128b3 8 -#define vbu_atxmega128c3 6 -#define vbu_atxmega128d3 6 -#define vbu_atxmega128a4u 36 -#define vbu_atxmega128d4 6 #define vbu_atxmega192a3 75 -#define vbu_atxmega192a3u 75 -#define vbu_atxmega192c3 6 -#define vbu_atxmega192d3 6 #define vbu_atxmega256a3 75 #define vbu_atxmega256a3b 57 +#define vbu_atxmega64a3u 75 +#define vbu_atxmega128a3u 75 +#define vbu_atxmega192a3u 75 #define vbu_atxmega256a3bu 57 #define vbu_atxmega256a3u 75 +#define vbu_atxmega16a4 36 +#define vbu_atxmega32a4 36 +#define vbu_atxmega16a4u 36 +#define vbu_atxmega32a4u 36 +#define vbu_atxmega64a4u 36 +#define vbu_atxmega128a4u 36 +#define vbu_atxmega64b1 8 +#define vbu_atxmega128b1 8 +#define vbu_atxmega64b3 8 +#define vbu_atxmega128b3 8 +#define vbu_atxmega32c3 6 +#define vbu_atxmega64c3 6 +#define vbu_atxmega128c3 6 +#define vbu_atxmega192c3 6 #define vbu_atxmega256c3 6 -#define vbu_atxmega256d3 6 #define vbu_atxmega384c3 8 +#define vbu_atxmega16c4 6 +#define vbu_atxmega32c4 6 +#define vbu_atxmega32d3 6 +#define vbu_atxmega64d3 6 +#define vbu_atxmega128d3 6 +#define vbu_atxmega192d3 6 +#define vbu_atxmega256d3 6 #define vbu_atxmega384d3 6 +#define vbu_atxmega16d4 6 +#define vbu_atxmega32d4 6 +#define vbu_atxmega64d4 6 +#define vbu_atxmega128d4 6 +#define vbu_atxmega8e5 43 +#define vbu_atxmega16e5 43 +#define vbu_atxmega32e5 43 #define vbu_attiny202 4 #define vbu_attiny204 5 -#define vbu_attiny212 4 -#define vbu_attiny214 5 #define vbu_attiny402 4 #define vbu_attiny404 5 #define vbu_attiny406 14 +#define vbu_attiny804 14 +#define vbu_attiny806 14 +#define vbu_attiny807 14 +#define vbu_attiny1604 14 +#define vbu_attiny1606 14 +#define vbu_attiny1607 14 +#define vbu_attiny212 4 +#define vbu_attiny214 5 #define vbu_attiny412 4 #define vbu_attiny414 5 #define vbu_attiny416 26 #define vbu_attiny416auto 26 #define vbu_attiny417 26 -#define vbu_attiny424 30 -#define vbu_attiny426 30 -#define vbu_attiny427 30 -#define vbu_attiny804 14 -#define vbu_attiny806 14 -#define vbu_attiny807 14 #define vbu_attiny814 5 #define vbu_attiny816 26 #define vbu_attiny817 26 -#define vbu_attiny824 30 -#define vbu_attiny826 30 -#define vbu_attiny827 30 -#define vbu_attiny1604 14 -#define vbu_attiny1606 14 -#define vbu_attiny1607 14 #define vbu_attiny1614 5 #define vbu_attiny1616 31 #define vbu_attiny1617 31 -#define vbu_attiny1624 30 -#define vbu_attiny1626 30 -#define vbu_attiny1627 30 #define vbu_attiny3214 31 #define vbu_attiny3216 31 #define vbu_attiny3217 31 +#define vbu_attiny424 30 +#define vbu_attiny426 30 +#define vbu_attiny427 30 +#define vbu_attiny824 30 +#define vbu_attiny826 30 +#define vbu_attiny827 30 +#define vbu_attiny1624 30 +#define vbu_attiny1626 30 +#define vbu_attiny1627 30 #define vbu_attiny3224 30 #define vbu_attiny3226 30 #define vbu_attiny3227 30 @@ -1308,786 +1308,629 @@ extern const Avrintel uP_table[422]; #define vbu_atmega3209 40 #define vbu_atmega4808 36 #define vbu_atmega4809 40 -#define vbu_avr16dd14 30 -#define vbu_avr16du14 34 -#define vbu_avr16eb14 31 -#define vbu_avr16la14 29 -#define vbu_avr16dd20 30 -#define vbu_avr16du20 34 -#define vbu_avr16eb20 31 -#define vbu_avr16la20 29 -#define vbu_avr16dd28 36 -#define vbu_avr16du28 34 -#define vbu_avr16ea28 43 -#define vbu_avr16eb28 31 -#define vbu_avr16la28 29 -#define vbu_avr16dd32 36 -#define vbu_avr16du32 34 -#define vbu_avr16ea32 43 -#define vbu_avr16eb32 31 -#define vbu_avr16la32 29 -#define vbu_avr16ea48 45 -#define vbu_avr32dd14 30 -#define vbu_avr32du14 34 -#define vbu_avr32eb14 31 -#define vbu_avr32la14 29 -#define vbu_avr32dd20 30 -#define vbu_avr32du20 34 -#define vbu_avr32eb20 31 -#define vbu_avr32la20 29 -#define vbu_avr32sd20 50 #define vbu_avr32da28 41 #define vbu_avr32da28s 41 -#define vbu_avr32db28 42 -#define vbu_avr32dd28 36 -#define vbu_avr32du28 34 -#define vbu_avr32ea28 43 -#define vbu_avr32eb28 31 -#define vbu_avr32la28 29 -#define vbu_avr32sd28 54 #define vbu_avr32da32 41 #define vbu_avr32da32s 41 -#define vbu_avr32db32 44 -#define vbu_avr32dd32 36 -#define vbu_avr32du32 34 -#define vbu_avr32ea32 43 -#define vbu_avr32eb32 31 -#define vbu_avr32la32 29 -#define vbu_avr32sd32 56 #define vbu_avr32da48 58 #define vbu_avr32da48s 58 -#define vbu_avr32db48 59 -#define vbu_avr32ea48 45 -#define vbu_avr64dd14 30 -#define vbu_avr64dd20 30 #define vbu_avr64da28 41 #define vbu_avr64da28s 41 -#define vbu_avr64db28 42 -#define vbu_avr64dd28 36 -#define vbu_avr64du28 34 -#define vbu_avr64ea28 43 #define vbu_avr64da32 41 #define vbu_avr64da32s 41 -#define vbu_avr64db32 44 -#define vbu_avr64dd32 36 -#define vbu_avr64du32 34 -#define vbu_avr64ea32 43 #define vbu_avr64da48 58 #define vbu_avr64da48s 58 -#define vbu_avr64db48 59 -#define vbu_avr64ea48 45 #define vbu_avr64da64 64 #define vbu_avr64da64s 64 -#define vbu_avr64db64 65 #define vbu_avr128da28 41 #define vbu_avr128da28s 41 -#define vbu_avr128db28 42 #define vbu_avr128da32 41 #define vbu_avr128da32s 41 -#define vbu_avr128db32 44 #define vbu_avr128da48 58 #define vbu_avr128da48s 58 -#define vbu_avr128db48 59 #define vbu_avr128da64 64 #define vbu_avr128da64s 64 +#define vbu_avr32db28 42 +#define vbu_avr32db32 44 +#define vbu_avr32db48 59 +#define vbu_avr64db28 42 +#define vbu_avr64db32 44 +#define vbu_avr64db48 59 +#define vbu_avr64db64 65 +#define vbu_avr128db28 42 +#define vbu_avr128db32 44 +#define vbu_avr128db48 59 #define vbu_avr128db64 65 +#define vbu_avr16dd14 30 +#define vbu_avr16dd20 30 +#define vbu_avr16dd28 36 +#define vbu_avr16dd32 36 +#define vbu_avr32dd14 30 +#define vbu_avr32dd20 30 +#define vbu_avr32dd28 36 +#define vbu_avr32dd32 36 +#define vbu_avr64dd14 30 +#define vbu_avr64dd20 30 +#define vbu_avr64dd28 36 +#define vbu_avr64dd32 36 +#define vbu_avr16du14 34 +#define vbu_avr16du20 34 +#define vbu_avr16du28 34 +#define vbu_avr16du32 34 +#define vbu_avr32du14 34 +#define vbu_avr32du20 34 +#define vbu_avr32du28 34 +#define vbu_avr32du32 34 +#define vbu_avr64du28 34 +#define vbu_avr64du32 34 +#define vbu_avr16ea28 43 +#define vbu_avr16ea32 43 +#define vbu_avr16ea48 45 +#define vbu_avr32ea28 43 +#define vbu_avr32ea32 43 +#define vbu_avr32ea48 45 +#define vbu_avr64ea28 43 +#define vbu_avr64ea32 43 +#define vbu_avr64ea48 45 +#define vbu_avr16eb14 31 +#define vbu_avr16eb20 31 +#define vbu_avr16eb28 31 +#define vbu_avr16eb32 31 +#define vbu_avr32eb14 31 +#define vbu_avr32eb20 31 +#define vbu_avr32eb28 31 +#define vbu_avr32eb32 31 +#define vbu_avr16la14 29 +#define vbu_avr16la20 29 +#define vbu_avr16la28 29 +#define vbu_avr16la32 29 +#define vbu_avr32la14 29 +#define vbu_avr32la20 29 +#define vbu_avr32la28 29 +#define vbu_avr32la32 29 +#define vbu_avr32sd20 50 +#define vbu_avr32sd28 54 +#define vbu_avr32sd32 56 // Interrupt vector table interrupt names -extern const char * const vtab_attiny9[10]; -#define vtab_attiny4 vtab_attiny9 +extern const char * const vtab_attiny4[10]; +#define vtab_attiny9 vtab_attiny4 -extern const char * const vtab_attiny10[11]; -#define vtab_attiny5 vtab_attiny10 +extern const char * const vtab_attiny5[11]; +#define vtab_attiny10 vtab_attiny5 extern const char * const vtab_attiny20[17]; extern const char * const vtab_attiny40[18]; -extern const char * const vtab_attiny104[16]; -#define vtab_attiny102 vtab_attiny104 - -extern const char * const vtab_attiny11[5]; - -extern const char * const vtab_attiny12[6]; - -extern const char * const vtab_attiny13a[10]; -#define vtab_attiny13 vtab_attiny13a - -extern const char * const vtab_attiny15[9]; - -extern const char * const vtab_attiny22[3]; -#define vtab_at90s2343 vtab_attiny22 -#define vtab_at90s2323 vtab_attiny22 - -extern const char * const vtab_attiny26[12]; - -extern const char * const vtab_attiny28[6]; - -extern const char * const vtab_attiny43u[16]; - -extern const char * const vtab_attiny84a[17]; -#define vtab_attiny84 vtab_attiny84a -#define vtab_attiny44a vtab_attiny84a -#define vtab_attiny44 vtab_attiny84a -#define vtab_attiny24a vtab_attiny84a -#define vtab_attiny24 vtab_attiny84a - -extern const char * const vtab_attiny85[15]; -#define vtab_attiny45 vtab_attiny85 -#define vtab_attiny25 vtab_attiny85 - -extern const char * const vtab_attiny88[20]; -#define vtab_attiny48 vtab_attiny88 - -extern const char * const vtab_attiny167[20]; -#define vtab_attiny87 vtab_attiny167 -#define vtab_ata664251 vtab_attiny167 -#define vtab_ata6617c vtab_attiny167 -#define vtab_ata6616c vtab_attiny167 -#define vtab_ata5505 vtab_attiny167 - -extern const char * const vtab_attiny828r[26]; -#define vtab_attiny828 vtab_attiny828r - -extern const char * const vtab_attiny841[30]; -#define vtab_attiny441 vtab_attiny841 - -extern const char * const vtab_attiny861a[19]; -#define vtab_attiny861 vtab_attiny861a -#define vtab_attiny461a vtab_attiny861a -#define vtab_attiny461 vtab_attiny861a -#define vtab_attiny261a vtab_attiny861a -#define vtab_attiny261 vtab_attiny861a - -extern const char * const vtab_attiny1634r[28]; -#define vtab_attiny1634 vtab_attiny1634r - -extern const char * const vtab_attiny2313[19]; - -extern const char * const vtab_attiny4313[21]; -#define vtab_attiny2313a vtab_attiny4313 - -extern const char * const vtab_atmega8a[19]; -#define vtab_atmega8 vtab_atmega8a - -extern const char * const vtab_atmega16a[21]; -#define vtab_atmega16 vtab_atmega16a - -extern const char * const vtab_atmega16hva[21]; -#define vtab_atmega8hva vtab_atmega16hva - -extern const char * const vtab_atmega16hva2[22]; - -extern const char * const vtab_atmega32hvbrevb[29]; -#define vtab_atmega32hvb vtab_atmega32hvbrevb -#define vtab_atmega16hvbrevb vtab_atmega32hvbrevb -#define vtab_atmega16hvb vtab_atmega32hvbrevb - -extern const char * const vtab_atmega32u2[29]; -#define vtab_atmega16u2 vtab_atmega32u2 -#define vtab_atmega8u2 vtab_atmega32u2 -#define vtab_at90usb162 vtab_atmega32u2 -#define vtab_at90usb82 vtab_atmega32u2 - -extern const char * const vtab_atmega32u4[43]; -#define vtab_atmega16u4 vtab_atmega32u4 - -extern const char * const vtab_atmega32u6[38]; -#define vtab_at90usb1287 vtab_atmega32u6 -#define vtab_at90usb1286 vtab_atmega32u6 -#define vtab_at90usb647 vtab_atmega32u6 -#define vtab_at90usb646 vtab_atmega32u6 - -extern const char * const vtab_atmega64m1[31]; -#define vtab_atmegas64m1 vtab_atmega64m1 -#define vtab_atmega64c1 vtab_atmega64m1 -#define vtab_atmega32m1 vtab_atmega64m1 -#define vtab_atmega32c1 vtab_atmega64m1 -#define vtab_atmega16m1 vtab_atmega64m1 - -extern const char * const vtab_atmega64hve2[25]; -#define vtab_atmega64hve vtab_atmega64hve2 -#define vtab_atmega32hve2 vtab_atmega64hve2 - -extern const char * const vtab_atmega103[24]; - -extern const char * const vtab_atmega128a[35]; -#define vtab_atmegas128 vtab_atmega128a -#define vtab_atmega128 vtab_atmega128a -#define vtab_atmega64a vtab_atmega128a -#define vtab_atmega64 vtab_atmega128a - -extern const char * const vtab_atmega128rfa1[72]; - -extern const char * const vtab_atmega161[21]; - -extern const char * const vtab_atmega162[28]; - -extern const char * const vtab_atmega163[18]; - -extern const char * const vtab_atmega168pb[27]; -#define vtab_atmega88pb vtab_atmega168pb -#define vtab_atmega48pb vtab_atmega168pb - -extern const char * const vtab_atmega323[21]; -#define vtab_atmega32a vtab_atmega323 -#define vtab_atmega32 vtab_atmega323 - -extern const char * const vtab_atmega324pb[51]; - -extern const char * const vtab_atmega328[26]; -#define vtab_atmega168 vtab_atmega328 - -extern const char * const vtab_atmega328p[26]; -#define vtab_atmega168pa vtab_atmega328p -#define vtab_atmega168p vtab_atmega328p -#define vtab_atmega168a vtab_atmega328p -#define vtab_atmega88pa vtab_atmega328p -#define vtab_atmega88p vtab_atmega328p -#define vtab_atmega88a vtab_atmega328p -#define vtab_atmega88 vtab_atmega328p -#define vtab_atmega48pa vtab_atmega328p -#define vtab_atmega48p vtab_atmega328p -#define vtab_atmega48a vtab_atmega328p -#define vtab_atmega48 vtab_atmega328p -#define vtab_ata6614q vtab_atmega328p -#define vtab_ata6613c vtab_atmega328p -#define vtab_ata6612c vtab_atmega328p -#define vtab_lgt8f328p vtab_atmega328p -#define vtab_lgt8f168p vtab_atmega328p -#define vtab_lgt8f88p vtab_atmega328p - -extern const char * const vtab_atmega328pb[45]; - -extern const char * const vtab_atmega406[23]; - -extern const char * const vtab_atmega644[28]; - -extern const char * const vtab_atmega644pa[31]; -#define vtab_atmega644p vtab_atmega644pa -#define vtab_atmega644a vtab_atmega644pa -#define vtab_atmega324pa vtab_atmega644pa -#define vtab_atmega324p vtab_atmega644pa -#define vtab_atmega324a vtab_atmega644pa -#define vtab_atmega164pa vtab_atmega644pa -#define vtab_atmega164p vtab_atmega644pa -#define vtab_atmega164a vtab_atmega644pa - -extern const char * const vtab_atmega645p[22]; -#define vtab_atmega645a vtab_atmega645p -#define vtab_atmega645 vtab_atmega645p -#define vtab_atmega325pa vtab_atmega645p -#define vtab_atmega325p vtab_atmega645p -#define vtab_atmega325a vtab_atmega645p -#define vtab_atmega325 vtab_atmega645p -#define vtab_atmega165pa vtab_atmega645p -#define vtab_atmega165p vtab_atmega645p -#define vtab_atmega165a vtab_atmega645p -#define vtab_atmega165 vtab_atmega645p - -extern const char * const vtab_atmega649p[23]; -#define vtab_atmega649a vtab_atmega649p -#define vtab_atmega649 vtab_atmega649p -#define vtab_atmega329pa vtab_atmega649p -#define vtab_atmega329p vtab_atmega649p -#define vtab_atmega329a vtab_atmega649p -#define vtab_atmega329 vtab_atmega649p -#define vtab_atmega169pa vtab_atmega649p -#define vtab_atmega169p vtab_atmega649p -#define vtab_atmega169a vtab_atmega649p -#define vtab_atmega169 vtab_atmega649p - -extern const char * const vtab_atmega1284p[35]; -#define vtab_atmega1284 vtab_atmega1284p - -extern const char * const vtab_atmega2560[57]; -#define vtab_atmega1280 vtab_atmega2560 -#define vtab_atmega640 vtab_atmega2560 - -extern const char * const vtab_atmega2561[57]; -#define vtab_atmega1281 vtab_atmega2561 - -extern const char * const vtab_atmega2564rfr2[77]; -#define vtab_atmega1284rfr2 vtab_atmega2564rfr2 -#define vtab_atmega644rfr2 vtab_atmega2564rfr2 -#define vtab_atmega256rfr2 vtab_atmega2564rfr2 -#define vtab_atmega128rfr2 vtab_atmega2564rfr2 -#define vtab_atmega64rfr2 vtab_atmega2564rfr2 - -extern const char * const vtab_atmega6450p[25]; -#define vtab_atmega6450a vtab_atmega6450p -#define vtab_atmega6450 vtab_atmega6450p -#define vtab_atmega3250pa vtab_atmega6450p -#define vtab_atmega3250p vtab_atmega6450p -#define vtab_atmega3250a vtab_atmega6450p -#define vtab_atmega3250 vtab_atmega6450p - -extern const char * const vtab_atmega6490p[25]; -#define vtab_atmega6490a vtab_atmega6490p -#define vtab_atmega6490 vtab_atmega6490p -#define vtab_atmega3290pa vtab_atmega6490p -#define vtab_atmega3290p vtab_atmega6490p -#define vtab_atmega3290a vtab_atmega6490p -#define vtab_atmega3290 vtab_atmega6490p - -extern const char * const vtab_atmega8515[17]; - -extern const char * const vtab_atmega8535[21]; - -extern const char * const vtab_at86rf401[3]; - -extern const char * const vtab_at90pwm1[32]; - -extern const char * const vtab_at90pwm2[32]; - -extern const char * const vtab_at90pwm3b[32]; -#define vtab_at90pwm3 vtab_at90pwm3b -#define vtab_at90pwm2b vtab_at90pwm3b - -extern const char * const vtab_at90scr100h[38]; -#define vtab_at90scr100 vtab_at90scr100h - -extern const char * const vtab_at90can128[37]; -#define vtab_at90can64 vtab_at90can128 -#define vtab_at90can32 vtab_at90can128 - -extern const char * const vtab_at90pwm161[20]; -#define vtab_at90pwm81 vtab_at90pwm161 - -extern const char * const vtab_at90pwm316[32]; -#define vtab_at90pwm216 vtab_at90pwm316 +extern const char * const vtab_attiny102[16]; +#define vtab_attiny104 vtab_attiny102 extern const char * const vtab_at90s1200[4]; extern const char * const vtab_at90s2313[11]; -extern const char * const vtab_at90s4433[14]; -#define vtab_at90s2333 vtab_at90s4433 +extern const char * const vtab_at90s2323[3]; +#define vtab_at90s2343 vtab_at90s2323 +#define vtab_attiny22 vtab_at90s2323 -extern const char * const vtab_at90s8515[13]; -#define vtab_at90s4414 vtab_at90s8515 +extern const char * const vtab_at90s2333[14]; +#define vtab_at90s4433 vtab_at90s2333 -extern const char * const vtab_at90s8535[17]; -#define vtab_at90s4434 vtab_at90s8535 +extern const char * const vtab_at90s4414[13]; +#define vtab_at90s8515 vtab_at90s4414 + +extern const char * const vtab_at90s4434[17]; +#define vtab_at90s8535 vtab_at90s4434 + +extern const char * const vtab_at90can32[37]; +#define vtab_at90can64 vtab_at90can32 +#define vtab_at90can128 vtab_at90can32 + +extern const char * const vtab_at90pwm1[32]; + +extern const char * const vtab_at90pwm81[20]; +#define vtab_at90pwm161 vtab_at90pwm81 + +extern const char * const vtab_at90pwm2[32]; + +extern const char * const vtab_at90pwm2b[32]; +#define vtab_at90pwm3 vtab_at90pwm2b +#define vtab_at90pwm3b vtab_at90pwm2b + +extern const char * const vtab_at90pwm216[32]; +#define vtab_at90pwm316 vtab_at90pwm216 + +extern const char * const vtab_at90usb82[29]; +#define vtab_at90usb162 vtab_at90usb82 +#define vtab_atmega8u2 vtab_at90usb82 +#define vtab_atmega16u2 vtab_at90usb82 +#define vtab_atmega32u2 vtab_at90usb82 + +extern const char * const vtab_at90usb646[38]; +#define vtab_at90usb1286 vtab_at90usb646 +#define vtab_at90usb647 vtab_at90usb646 +#define vtab_at90usb1287 vtab_at90usb646 +#define vtab_atmega32u6 vtab_at90usb646 + +extern const char * const vtab_at90scr100[38]; +#define vtab_at90scr100h vtab_at90scr100 + +extern const char * const vtab_at86rf401[3]; + +extern const char * const vtab_attiny11[5]; + +extern const char * const vtab_attiny12[6]; + +extern const char * const vtab_attiny13[10]; +#define vtab_attiny13a vtab_attiny13 + +extern const char * const vtab_attiny43u[16]; + +extern const char * const vtab_attiny24[17]; +#define vtab_attiny24a vtab_attiny24 +#define vtab_attiny44 vtab_attiny24 +#define vtab_attiny44a vtab_attiny24 +#define vtab_attiny84 vtab_attiny24 +#define vtab_attiny84a vtab_attiny24 + +extern const char * const vtab_attiny15[9]; + +extern const char * const vtab_attiny25[15]; +#define vtab_attiny45 vtab_attiny25 +#define vtab_attiny85 vtab_attiny25 + +extern const char * const vtab_attiny26[12]; + +extern const char * const vtab_attiny87[20]; +#define vtab_attiny167 vtab_attiny87 +#define vtab_ata5505 vtab_attiny87 +#define vtab_ata6616c vtab_attiny87 +#define vtab_ata6617c vtab_attiny87 +#define vtab_ata664251 vtab_attiny87 + +extern const char * const vtab_attiny28[6]; + +extern const char * const vtab_attiny48[20]; +#define vtab_attiny88 vtab_attiny48 + +extern const char * const vtab_attiny828[26]; +#define vtab_attiny828r vtab_attiny828 + +extern const char * const vtab_attiny1634[28]; +#define vtab_attiny1634r vtab_attiny1634 + +extern const char * const vtab_attiny441[30]; +#define vtab_attiny841 vtab_attiny441 + +extern const char * const vtab_attiny261[19]; +#define vtab_attiny261a vtab_attiny261 +#define vtab_attiny461 vtab_attiny261 +#define vtab_attiny461a vtab_attiny261 +#define vtab_attiny861 vtab_attiny261 +#define vtab_attiny861a vtab_attiny261 + +extern const char * const vtab_attiny2313[19]; + +extern const char * const vtab_attiny2313a[21]; +#define vtab_attiny4313 vtab_attiny2313a + +extern const char * const vtab_atmega8[19]; +#define vtab_atmega8a vtab_atmega8 + +extern const char * const vtab_atmega16[21]; +#define vtab_atmega16a vtab_atmega16 + +extern const char * const vtab_atmega32[21]; +#define vtab_atmega32a vtab_atmega32 +#define vtab_atmega323 vtab_atmega32 + +extern const char * const vtab_atmega64[35]; +#define vtab_atmega64a vtab_atmega64 +#define vtab_atmega128 vtab_atmega64 +#define vtab_atmega128a vtab_atmega64 +#define vtab_atmegas128 vtab_atmega64 + +extern const char * const vtab_atmega640[57]; +#define vtab_atmega1280 vtab_atmega640 +#define vtab_atmega2560 vtab_atmega640 + +extern const char * const vtab_atmega32c1[31]; +#define vtab_atmega64c1 vtab_atmega32c1 +#define vtab_atmega16m1 vtab_atmega32c1 +#define vtab_atmega32m1 vtab_atmega32c1 +#define vtab_atmega64m1 vtab_atmega32c1 +#define vtab_atmegas64m1 vtab_atmega32c1 + +extern const char * const vtab_atmega128rfa1[72]; + +extern const char * const vtab_atmega64rfr2[77]; +#define vtab_atmega128rfr2 vtab_atmega64rfr2 +#define vtab_atmega256rfr2 vtab_atmega64rfr2 +#define vtab_atmega644rfr2 vtab_atmega64rfr2 +#define vtab_atmega1284rfr2 vtab_atmega64rfr2 +#define vtab_atmega2564rfr2 vtab_atmega64rfr2 + +extern const char * const vtab_atmega16u4[43]; +#define vtab_atmega32u4 vtab_atmega16u4 + +extern const char * const vtab_atmega161[21]; + +extern const char * const vtab_atmega1281[57]; +#define vtab_atmega2561 vtab_atmega1281 + +extern const char * const vtab_atmega162[28]; + +extern const char * const vtab_atmega163[18]; + +extern const char * const vtab_atmega164a[31]; +#define vtab_atmega164p vtab_atmega164a +#define vtab_atmega164pa vtab_atmega164a +#define vtab_atmega324a vtab_atmega164a +#define vtab_atmega324p vtab_atmega164a +#define vtab_atmega324pa vtab_atmega164a +#define vtab_atmega644a vtab_atmega164a +#define vtab_atmega644p vtab_atmega164a +#define vtab_atmega644pa vtab_atmega164a + +extern const char * const vtab_atmega644[28]; + +extern const char * const vtab_atmega1284[35]; +#define vtab_atmega1284p vtab_atmega1284 + +extern const char * const vtab_atmega324pb[51]; + +extern const char * const vtab_atmega165[22]; +#define vtab_atmega165a vtab_atmega165 +#define vtab_atmega165p vtab_atmega165 +#define vtab_atmega165pa vtab_atmega165 +#define vtab_atmega325 vtab_atmega165 +#define vtab_atmega325a vtab_atmega165 +#define vtab_atmega325p vtab_atmega165 +#define vtab_atmega325pa vtab_atmega165 +#define vtab_atmega645 vtab_atmega165 +#define vtab_atmega645a vtab_atmega165 +#define vtab_atmega645p vtab_atmega165 + +extern const char * const vtab_atmega3250[25]; +#define vtab_atmega3250a vtab_atmega3250 +#define vtab_atmega3250p vtab_atmega3250 +#define vtab_atmega3250pa vtab_atmega3250 +#define vtab_atmega6450 vtab_atmega3250 +#define vtab_atmega6450a vtab_atmega3250 +#define vtab_atmega6450p vtab_atmega3250 + +extern const char * const vtab_atmega8515[17]; + +extern const char * const vtab_atmega8535[21]; + +extern const char * const vtab_atmega48[26]; +#define vtab_atmega48a vtab_atmega48 +#define vtab_atmega48p vtab_atmega48 +#define vtab_atmega48pa vtab_atmega48 +#define vtab_atmega88 vtab_atmega48 +#define vtab_atmega88a vtab_atmega48 +#define vtab_atmega88p vtab_atmega48 +#define vtab_atmega88pa vtab_atmega48 +#define vtab_atmega168a vtab_atmega48 +#define vtab_atmega168p vtab_atmega48 +#define vtab_atmega168pa vtab_atmega48 +#define vtab_atmega328p vtab_atmega48 +#define vtab_lgt8f88p vtab_atmega48 +#define vtab_lgt8f168p vtab_atmega48 +#define vtab_lgt8f328p vtab_atmega48 +#define vtab_ata6612c vtab_atmega48 +#define vtab_ata6613c vtab_atmega48 +#define vtab_ata6614q vtab_atmega48 + +extern const char * const vtab_atmega168[26]; +#define vtab_atmega328 vtab_atmega168 + +extern const char * const vtab_atmega48pb[27]; +#define vtab_atmega88pb vtab_atmega48pb +#define vtab_atmega168pb vtab_atmega48pb + +extern const char * const vtab_atmega328pb[45]; + +extern const char * const vtab_atmega169[23]; +#define vtab_atmega169a vtab_atmega169 +#define vtab_atmega169p vtab_atmega169 +#define vtab_atmega169pa vtab_atmega169 +#define vtab_atmega329 vtab_atmega169 +#define vtab_atmega329a vtab_atmega169 +#define vtab_atmega329p vtab_atmega169 +#define vtab_atmega329pa vtab_atmega169 +#define vtab_atmega649 vtab_atmega169 +#define vtab_atmega649a vtab_atmega169 +#define vtab_atmega649p vtab_atmega169 + +extern const char * const vtab_atmega3290[25]; +#define vtab_atmega3290a vtab_atmega3290 +#define vtab_atmega3290p vtab_atmega3290 +#define vtab_atmega3290pa vtab_atmega3290 +#define vtab_atmega6490 vtab_atmega3290 +#define vtab_atmega6490a vtab_atmega3290 +#define vtab_atmega6490p vtab_atmega3290 + +extern const char * const vtab_atmega103[24]; + +extern const char * const vtab_atmega8hva[21]; +#define vtab_atmega16hva vtab_atmega8hva + +extern const char * const vtab_atmega16hva2[22]; + +extern const char * const vtab_atmega16hvb[29]; +#define vtab_atmega16hvbrevb vtab_atmega16hvb +#define vtab_atmega32hvb vtab_atmega16hvb +#define vtab_atmega32hvbrevb vtab_atmega16hvb + +extern const char * const vtab_atmega64hve[25]; +#define vtab_atmega32hve2 vtab_atmega64hve +#define vtab_atmega64hve2 vtab_atmega64hve + +extern const char * const vtab_atmega406[23]; extern const char * const vtab_ata5272[37]; -extern const char * const vtab_ata5702m322[51]; -#define vtab_ata5700m322 vtab_ata5702m322 +extern const char * const vtab_ata5700m322[51]; +#define vtab_ata5702m322 vtab_ata5700m322 + +extern const char * const vtab_ata5781[42]; +#define vtab_ata5782 vtab_ata5781 +#define vtab_ata5783 vtab_ata5781 +#define vtab_ata5831 vtab_ata5781 +#define vtab_ata5832 vtab_ata5781 +#define vtab_ata5833 vtab_ata5781 +#define vtab_ata8210 vtab_ata5781 +#define vtab_ata8215 vtab_ata5781 +#define vtab_ata8510 vtab_ata5781 +#define vtab_ata8515 vtab_ata5781 + +extern const char * const vtab_ata5787[44]; +#define vtab_ata5835 vtab_ata5787 extern const char * const vtab_ata5790[30]; -extern const char * const vtab_ata5791[31]; -#define vtab_ata5790n vtab_ata5791 +extern const char * const vtab_ata5790n[31]; +#define vtab_ata5791 vtab_ata5790n extern const char * const vtab_ata5795[23]; -extern const char * const vtab_ata5835[44]; -#define vtab_ata5787 vtab_ata5835 +extern const char * const vtab_ata6285[27]; +#define vtab_ata6286 vtab_ata6285 +#define vtab_ata6289 vtab_ata6285 -extern const char * const vtab_ata6289[27]; -#define vtab_ata6286 vtab_ata6289 -#define vtab_ata6285 vtab_ata6289 +extern const char * const vtab_atxmega64a1[125]; +#define vtab_atxmega128a1 vtab_atxmega64a1 +#define vtab_atxmega128a1revd vtab_atxmega64a1 -extern const char * const vtab_ata8515[42]; -#define vtab_ata8510 vtab_ata8515 -#define vtab_ata8215 vtab_ata8515 -#define vtab_ata8210 vtab_ata8515 -#define vtab_ata5833 vtab_ata8515 -#define vtab_ata5832 vtab_ata8515 -#define vtab_ata5831 vtab_ata8515 -#define vtab_ata5783 vtab_ata8515 -#define vtab_ata5782 vtab_ata8515 -#define vtab_ata5781 vtab_ata8515 +extern const char * const vtab_atxmega64a1u[127]; +#define vtab_atxmega128a1u vtab_atxmega64a1u -extern const char * const vtab_atxmega32a4[94]; -#define vtab_atxmega16a4 vtab_atxmega32a4 - -extern const char * const vtab_atxmega32c4[127]; -#define vtab_atxmega16c4 vtab_atxmega32c4 - -extern const char * const vtab_atxmega32d4[91]; -#define vtab_atxmega16d4 vtab_atxmega32d4 - -extern const char * const vtab_atxmega32e5[43]; -#define vtab_atxmega16e5 vtab_atxmega32e5 -#define vtab_atxmega8e5 vtab_atxmega32e5 - -extern const char * const vtab_atxmega128a1revd[125]; -#define vtab_atxmega128a1 vtab_atxmega128a1revd -#define vtab_atxmega64a1 vtab_atxmega128a1revd - -extern const char * const vtab_atxmega128a1u[127]; -#define vtab_atxmega64a1u vtab_atxmega128a1u - -extern const char * const vtab_atxmega128b1[81]; -#define vtab_atxmega64b1 vtab_atxmega128b1 - -extern const char * const vtab_atxmega128b3[54]; -#define vtab_atxmega64b3 vtab_atxmega128b3 - -extern const char * const vtab_atxmega128a4u[127]; -#define vtab_atxmega64a4u vtab_atxmega128a4u -#define vtab_atxmega32a4u vtab_atxmega128a4u -#define vtab_atxmega16a4u vtab_atxmega128a4u - -extern const char * const vtab_atxmega128d4[91]; -#define vtab_atxmega64d4 vtab_atxmega128d4 - -extern const char * const vtab_atxmega256a3[122]; -#define vtab_atxmega192a3 vtab_atxmega256a3 -#define vtab_atxmega128a3 vtab_atxmega256a3 -#define vtab_atxmega64a3 vtab_atxmega256a3 +extern const char * const vtab_atxmega64a3[122]; +#define vtab_atxmega128a3 vtab_atxmega64a3 +#define vtab_atxmega192a3 vtab_atxmega64a3 +#define vtab_atxmega256a3 vtab_atxmega64a3 extern const char * const vtab_atxmega256a3b[122]; +extern const char * const vtab_atxmega64a3u[127]; +#define vtab_atxmega128a3u vtab_atxmega64a3u +#define vtab_atxmega192a3u vtab_atxmega64a3u +#define vtab_atxmega256a3u vtab_atxmega64a3u + extern const char * const vtab_atxmega256a3bu[127]; -extern const char * const vtab_atxmega256a3u[127]; -#define vtab_atxmega192a3u vtab_atxmega256a3u -#define vtab_atxmega128a3u vtab_atxmega256a3u -#define vtab_atxmega64a3u vtab_atxmega256a3u +extern const char * const vtab_atxmega16a4[94]; +#define vtab_atxmega32a4 vtab_atxmega16a4 -extern const char * const vtab_atxmega256c3[127]; -#define vtab_atxmega192c3 vtab_atxmega256c3 -#define vtab_atxmega128c3 vtab_atxmega256c3 -#define vtab_atxmega64c3 vtab_atxmega256c3 -#define vtab_atxmega32c3 vtab_atxmega256c3 +extern const char * const vtab_atxmega16a4u[127]; +#define vtab_atxmega32a4u vtab_atxmega16a4u +#define vtab_atxmega64a4u vtab_atxmega16a4u +#define vtab_atxmega128a4u vtab_atxmega16a4u + +extern const char * const vtab_atxmega64b1[81]; +#define vtab_atxmega128b1 vtab_atxmega64b1 + +extern const char * const vtab_atxmega64b3[54]; +#define vtab_atxmega128b3 vtab_atxmega64b3 + +extern const char * const vtab_atxmega32c3[127]; +#define vtab_atxmega64c3 vtab_atxmega32c3 +#define vtab_atxmega128c3 vtab_atxmega32c3 +#define vtab_atxmega192c3 vtab_atxmega32c3 +#define vtab_atxmega256c3 vtab_atxmega32c3 extern const char * const vtab_atxmega384c3[127]; -extern const char * const vtab_atxmega384d3[114]; -#define vtab_atxmega256d3 vtab_atxmega384d3 -#define vtab_atxmega192d3 vtab_atxmega384d3 -#define vtab_atxmega128d3 vtab_atxmega384d3 -#define vtab_atxmega64d3 vtab_atxmega384d3 -#define vtab_atxmega32d3 vtab_atxmega384d3 +extern const char * const vtab_atxmega16c4[127]; +#define vtab_atxmega32c4 vtab_atxmega16c4 -extern const char * const vtab_attiny402[26]; -#define vtab_attiny202 vtab_attiny402 +extern const char * const vtab_atxmega32d3[114]; +#define vtab_atxmega64d3 vtab_atxmega32d3 +#define vtab_atxmega128d3 vtab_atxmega32d3 +#define vtab_atxmega192d3 vtab_atxmega32d3 +#define vtab_atxmega256d3 vtab_atxmega32d3 +#define vtab_atxmega384d3 vtab_atxmega32d3 -extern const char * const vtab_attiny404[26]; -#define vtab_attiny204 vtab_attiny404 +extern const char * const vtab_atxmega16d4[91]; +#define vtab_atxmega32d4 vtab_atxmega16d4 + +extern const char * const vtab_atxmega64d4[91]; +#define vtab_atxmega128d4 vtab_atxmega64d4 + +extern const char * const vtab_atxmega8e5[43]; +#define vtab_atxmega16e5 vtab_atxmega8e5 +#define vtab_atxmega32e5 vtab_atxmega8e5 + +extern const char * const vtab_attiny202[26]; +#define vtab_attiny402 vtab_attiny202 + +extern const char * const vtab_attiny204[26]; +#define vtab_attiny404 vtab_attiny204 extern const char * const vtab_attiny406[26]; -extern const char * const vtab_attiny412[26]; -#define vtab_attiny212 vtab_attiny412 +extern const char * const vtab_attiny804[31]; +#define vtab_attiny806 vtab_attiny804 +#define vtab_attiny807 vtab_attiny804 +#define vtab_attiny1604 vtab_attiny804 +#define vtab_attiny1606 vtab_attiny804 +#define vtab_attiny1607 vtab_attiny804 -extern const char * const vtab_attiny814[26]; -#define vtab_attiny414 vtab_attiny814 -#define vtab_attiny214 vtab_attiny814 +extern const char * const vtab_attiny212[26]; +#define vtab_attiny412 vtab_attiny212 -extern const char * const vtab_attiny817[26]; -#define vtab_attiny816 vtab_attiny817 -#define vtab_attiny417 vtab_attiny817 -#define vtab_attiny416auto vtab_attiny817 -#define vtab_attiny416 vtab_attiny817 +extern const char * const vtab_attiny214[26]; +#define vtab_attiny414 vtab_attiny214 +#define vtab_attiny814 vtab_attiny214 -extern const char * const vtab_attiny1607[31]; -#define vtab_attiny1606 vtab_attiny1607 -#define vtab_attiny1604 vtab_attiny1607 -#define vtab_attiny807 vtab_attiny1607 -#define vtab_attiny806 vtab_attiny1607 -#define vtab_attiny804 vtab_attiny1607 +extern const char * const vtab_attiny416[26]; +#define vtab_attiny416auto vtab_attiny416 +#define vtab_attiny417 vtab_attiny416 +#define vtab_attiny816 vtab_attiny416 +#define vtab_attiny817 vtab_attiny416 extern const char * const vtab_attiny1614[31]; +extern const char * const vtab_attiny1616[31]; +#define vtab_attiny1617 vtab_attiny1616 +#define vtab_attiny3216 vtab_attiny1616 +#define vtab_attiny3217 vtab_attiny1616 + extern const char * const vtab_attiny3214[31]; -extern const char * const vtab_attiny3217[31]; -#define vtab_attiny3216 vtab_attiny3217 -#define vtab_attiny1617 vtab_attiny3217 -#define vtab_attiny1616 vtab_attiny3217 +extern const char * const vtab_attiny424[30]; +#define vtab_attiny426 vtab_attiny424 +#define vtab_attiny427 vtab_attiny424 +#define vtab_attiny824 vtab_attiny424 +#define vtab_attiny826 vtab_attiny424 +#define vtab_attiny827 vtab_attiny424 +#define vtab_attiny1624 vtab_attiny424 +#define vtab_attiny1626 vtab_attiny424 +#define vtab_attiny1627 vtab_attiny424 +#define vtab_attiny3224 vtab_attiny424 +#define vtab_attiny3226 vtab_attiny424 +#define vtab_attiny3227 vtab_attiny424 -extern const char * const vtab_attiny3227[30]; -#define vtab_attiny3226 vtab_attiny3227 -#define vtab_attiny3224 vtab_attiny3227 -#define vtab_attiny1627 vtab_attiny3227 -#define vtab_attiny1626 vtab_attiny3227 -#define vtab_attiny1624 vtab_attiny3227 -#define vtab_attiny827 vtab_attiny3227 -#define vtab_attiny826 vtab_attiny3227 -#define vtab_attiny824 vtab_attiny3227 -#define vtab_attiny427 vtab_attiny3227 -#define vtab_attiny426 vtab_attiny3227 -#define vtab_attiny424 vtab_attiny3227 +extern const char * const vtab_atmega808[36]; +#define vtab_atmega1608 vtab_atmega808 +#define vtab_atmega3208 vtab_atmega808 +#define vtab_atmega4808 vtab_atmega808 -extern const char * const vtab_atmega4808[36]; -#define vtab_atmega3208 vtab_atmega4808 -#define vtab_atmega1608 vtab_atmega4808 -#define vtab_atmega808 vtab_atmega4808 +extern const char * const vtab_atmega809[40]; +#define vtab_atmega1609 vtab_atmega809 +#define vtab_atmega3209 vtab_atmega809 +#define vtab_atmega4809 vtab_atmega809 -extern const char * const vtab_atmega4809[40]; -#define vtab_atmega3209 vtab_atmega4809 -#define vtab_atmega1609 vtab_atmega4809 -#define vtab_atmega809 vtab_atmega4809 +extern const char * const vtab_avr32da28[41]; +#define vtab_avr32da28s vtab_avr32da28 +#define vtab_avr64da28 vtab_avr32da28 +#define vtab_avr64da28s vtab_avr32da28 +#define vtab_avr128da28 vtab_avr32da28 +#define vtab_avr128da28s vtab_avr32da28 -extern const char * const vtab_avr16eb32[31]; -#define vtab_avr16eb28 vtab_avr16eb32 -#define vtab_avr16eb20 vtab_avr16eb32 -#define vtab_avr16eb14 vtab_avr16eb32 +extern const char * const vtab_avr32da32[44]; +#define vtab_avr32da32s vtab_avr32da32 +#define vtab_avr64da32 vtab_avr32da32 +#define vtab_avr64da32s vtab_avr32da32 +#define vtab_avr128da32 vtab_avr32da32 +#define vtab_avr128da32s vtab_avr32da32 + +extern const char * const vtab_avr32da48[61]; +#define vtab_avr32da48s vtab_avr32da48 + +extern const char * const vtab_avr64da48[58]; +#define vtab_avr64da48s vtab_avr64da48 +#define vtab_avr128da48 vtab_avr64da48 +#define vtab_avr128da48s vtab_avr64da48 + +extern const char * const vtab_avr64da64[64]; +#define vtab_avr64da64s vtab_avr64da64 +#define vtab_avr128da64 vtab_avr64da64 +#define vtab_avr128da64s vtab_avr64da64 + +extern const char * const vtab_avr32db28[42]; +#define vtab_avr64db28 vtab_avr32db28 +#define vtab_avr128db28 vtab_avr32db28 + +extern const char * const vtab_avr32db32[44]; +#define vtab_avr64db32 vtab_avr32db32 +#define vtab_avr128db32 vtab_avr32db32 + +extern const char * const vtab_avr32db48[61]; +#define vtab_avr64db48 vtab_avr32db48 +#define vtab_avr128db48 vtab_avr32db48 + +extern const char * const vtab_avr64db64[65]; +#define vtab_avr128db64 vtab_avr64db64 + +extern const char * const vtab_avr16dd14[36]; +#define vtab_avr16dd20 vtab_avr16dd14 +#define vtab_avr32dd14 vtab_avr16dd14 +#define vtab_avr32dd20 vtab_avr16dd14 +#define vtab_avr64dd14 vtab_avr16dd14 +#define vtab_avr64dd20 vtab_avr16dd14 + +extern const char * const vtab_avr16dd28[36]; +#define vtab_avr16dd32 vtab_avr16dd28 +#define vtab_avr32dd28 vtab_avr16dd28 +#define vtab_avr32dd32 vtab_avr16dd28 +#define vtab_avr64dd28 vtab_avr16dd28 +#define vtab_avr64dd32 vtab_avr16dd28 + +extern const char * const vtab_avr16du14[34]; +#define vtab_avr16du20 vtab_avr16du14 +#define vtab_avr16du28 vtab_avr16du14 +#define vtab_avr16du32 vtab_avr16du14 +#define vtab_avr32du14 vtab_avr16du14 +#define vtab_avr32du20 vtab_avr16du14 +#define vtab_avr32du28 vtab_avr16du14 +#define vtab_avr32du32 vtab_avr16du14 +#define vtab_avr64du28 vtab_avr16du14 +#define vtab_avr64du32 vtab_avr16du14 + +extern const char * const vtab_avr16ea28[43]; +#define vtab_avr16ea32 vtab_avr16ea28 +#define vtab_avr32ea28 vtab_avr16ea28 +#define vtab_avr32ea32 vtab_avr16ea28 +#define vtab_avr64ea28 vtab_avr16ea28 +#define vtab_avr64ea32 vtab_avr16ea28 + +extern const char * const vtab_avr16ea48[45]; +#define vtab_avr32ea48 vtab_avr16ea48 +#define vtab_avr64ea48 vtab_avr16ea48 + +extern const char * const vtab_avr16eb14[31]; +#define vtab_avr16eb20 vtab_avr16eb14 +#define vtab_avr16eb28 vtab_avr16eb14 +#define vtab_avr16eb32 vtab_avr16eb14 + +extern const char * const vtab_avr32eb14[31]; +#define vtab_avr32eb20 vtab_avr32eb14 +#define vtab_avr32eb28 vtab_avr32eb14 +#define vtab_avr32eb32 vtab_avr32eb14 + +extern const char * const vtab_avr16la14[29]; +#define vtab_avr16la20 vtab_avr16la14 +#define vtab_avr16la28 vtab_avr16la14 +#define vtab_avr16la32 vtab_avr16la14 +#define vtab_avr32la14 vtab_avr16la14 +#define vtab_avr32la20 vtab_avr16la14 +#define vtab_avr32la28 vtab_avr16la14 +#define vtab_avr32la32 vtab_avr16la14 extern const char * const vtab_avr32sd20[50]; extern const char * const vtab_avr32sd28[54]; -extern const char * const vtab_avr32eb32[31]; -#define vtab_avr32eb28 vtab_avr32eb32 -#define vtab_avr32eb20 vtab_avr32eb32 -#define vtab_avr32eb14 vtab_avr32eb32 - -extern const char * const vtab_avr32la32[29]; -#define vtab_avr32la28 vtab_avr32la32 -#define vtab_avr32la20 vtab_avr32la32 -#define vtab_avr32la14 vtab_avr32la32 -#define vtab_avr16la32 vtab_avr32la32 -#define vtab_avr16la28 vtab_avr32la32 -#define vtab_avr16la20 vtab_avr32la32 -#define vtab_avr16la14 vtab_avr32la32 - extern const char * const vtab_avr32sd32[56]; -extern const char * const vtab_avr32da48s[61]; -#define vtab_avr32da48 vtab_avr32da48s - -extern const char * const vtab_avr64dd20[36]; -#define vtab_avr64dd14 vtab_avr64dd20 -#define vtab_avr32dd20 vtab_avr64dd20 -#define vtab_avr32dd14 vtab_avr64dd20 -#define vtab_avr16dd20 vtab_avr64dd20 -#define vtab_avr16dd14 vtab_avr64dd20 - -extern const char * const vtab_avr64dd32[36]; -#define vtab_avr64dd28 vtab_avr64dd32 -#define vtab_avr32dd32 vtab_avr64dd32 -#define vtab_avr32dd28 vtab_avr64dd32 -#define vtab_avr16dd32 vtab_avr64dd32 -#define vtab_avr16dd28 vtab_avr64dd32 - -extern const char * const vtab_avr64du32[34]; -#define vtab_avr64du28 vtab_avr64du32 -#define vtab_avr32du32 vtab_avr64du32 -#define vtab_avr32du28 vtab_avr64du32 -#define vtab_avr32du20 vtab_avr64du32 -#define vtab_avr32du14 vtab_avr64du32 -#define vtab_avr16du32 vtab_avr64du32 -#define vtab_avr16du28 vtab_avr64du32 -#define vtab_avr16du20 vtab_avr64du32 -#define vtab_avr16du14 vtab_avr64du32 - -extern const char * const vtab_avr64ea32[43]; -#define vtab_avr64ea28 vtab_avr64ea32 -#define vtab_avr32ea32 vtab_avr64ea32 -#define vtab_avr32ea28 vtab_avr64ea32 -#define vtab_avr16ea32 vtab_avr64ea32 -#define vtab_avr16ea28 vtab_avr64ea32 - -extern const char * const vtab_avr64ea48[45]; -#define vtab_avr32ea48 vtab_avr64ea48 -#define vtab_avr16ea48 vtab_avr64ea48 - -extern const char * const vtab_avr128da28s[41]; -#define vtab_avr128da28 vtab_avr128da28s -#define vtab_avr64da28s vtab_avr128da28s -#define vtab_avr64da28 vtab_avr128da28s -#define vtab_avr32da28s vtab_avr128da28s -#define vtab_avr32da28 vtab_avr128da28s - -extern const char * const vtab_avr128db28[42]; -#define vtab_avr64db28 vtab_avr128db28 -#define vtab_avr32db28 vtab_avr128db28 - -extern const char * const vtab_avr128da32s[44]; -#define vtab_avr128da32 vtab_avr128da32s -#define vtab_avr64da32s vtab_avr128da32s -#define vtab_avr64da32 vtab_avr128da32s -#define vtab_avr32da32s vtab_avr128da32s -#define vtab_avr32da32 vtab_avr128da32s - -extern const char * const vtab_avr128db32[44]; -#define vtab_avr64db32 vtab_avr128db32 -#define vtab_avr32db32 vtab_avr128db32 - -extern const char * const vtab_avr128da48s[58]; -#define vtab_avr128da48 vtab_avr128da48s -#define vtab_avr64da48s vtab_avr128da48s -#define vtab_avr64da48 vtab_avr128da48s - -extern const char * const vtab_avr128db48[61]; -#define vtab_avr64db48 vtab_avr128db48 -#define vtab_avr32db48 vtab_avr128db48 - -extern const char * const vtab_avr128da64s[64]; -#define vtab_avr128da64 vtab_avr128da64s -#define vtab_avr64da64s vtab_avr128da64s -#define vtab_avr64da64 vtab_avr128da64s - -extern const char * const vtab_avr128db64[65]; -#define vtab_avr64db64 vtab_avr128db64 - // Configuration table names -extern const Configitem cfgtab_atmega328[14]; -#define cfgtab_atmega328p cfgtab_atmega328 -#define cfgtab_ata6614q cfgtab_atmega328 - -extern const Configitem cfgtab_atmega16m1[17]; - -extern const Configitem cfgtab_atmega16hva2[9]; - -extern const Configitem cfgtab_atmega32hvbrevb[12]; - -extern const Configitem cfgtab_atmega64hve[13]; - -extern const Configitem cfgtab_atmega328pb[15]; - -extern const Configitem cfgtab_atmega8515[13]; - -extern const Configitem cfgtab_attiny102[5]; -#define cfgtab_attiny104 cfgtab_attiny102 - -extern const Configitem cfgtab_attiny28[3]; - -extern const Configitem cfgtab_attiny441[14]; -#define cfgtab_attiny841 cfgtab_attiny441 - -extern const Configitem cfgtab_at90pwm2[18]; -#define cfgtab_at90pwm3 cfgtab_at90pwm2 - -extern const Configitem cfgtab_at90pwm81[19]; -#define cfgtab_at90pwm161 cfgtab_at90pwm81 - -extern const Configitem cfgtab_at90can128[15]; - -extern const Configitem cfgtab_at90usb162[15]; -#define cfgtab_atmega16u2 cfgtab_at90usb162 -#define cfgtab_at90usb82 cfgtab_at90usb162 - -extern const Configitem cfgtab_at90s1200[3]; - -extern const Configitem cfgtab_at90s2313[3]; -#define cfgtab_at90s4414 cfgtab_at90s2313 -#define cfgtab_at90s4434 cfgtab_at90s2313 -#define cfgtab_at90s8515 cfgtab_at90s2313 -#define cfgtab_at90s8535 cfgtab_at90s2313 - -extern const Configitem cfgtab_ata5700m322[9]; -#define cfgtab_ata5702m322 cfgtab_ata5700m322 - -extern const Configitem cfgtab_ata5781[11]; -#define cfgtab_ata5782 cfgtab_ata5781 -#define cfgtab_ata5783 cfgtab_ata5781 -#define cfgtab_ata5831 cfgtab_ata5781 -#define cfgtab_ata5832 cfgtab_ata5781 -#define cfgtab_ata5833 cfgtab_ata5781 - -extern const Configitem cfgtab_ata5790[11]; -#define cfgtab_ata5791 cfgtab_ata5790 - -extern const Configitem cfgtab_ata6285[17]; -#define cfgtab_ata6286 cfgtab_ata6285 - -extern const Configitem cfgtab_atxmega16e5[17]; -#define cfgtab_atxmega8e5 cfgtab_atxmega16e5 -#define cfgtab_atxmega32e5 cfgtab_atxmega16e5 - -extern const Configitem cfgtab_atxmega192a1[16]; -#define cfgtab_atxmega256a1 cfgtab_atxmega192a1 -#define cfgtab_atxmega128a3 cfgtab_atxmega192a1 -#define cfgtab_atxmega64a1 cfgtab_atxmega192a1 -#define cfgtab_atxmega64a3 cfgtab_atxmega192a1 -#define cfgtab_atxmega128a1 cfgtab_atxmega192a1 -#define cfgtab_atxmega128a1revd cfgtab_atxmega192a1 -#define cfgtab_atxmega192a3 cfgtab_atxmega192a1 -#define cfgtab_atxmega256a3 cfgtab_atxmega192a1 -#define cfgtab_atxmega256a3b cfgtab_atxmega192a1 - -extern const Configitem cfgtab_atxmega128a3u[17]; -#define cfgtab_atxmega16a4u cfgtab_atxmega128a3u -#define cfgtab_atxmega32a4u cfgtab_atxmega128a3u -#define cfgtab_atxmega64a1u cfgtab_atxmega128a3u -#define cfgtab_atxmega64a3u cfgtab_atxmega128a3u -#define cfgtab_atxmega64a4u cfgtab_atxmega128a3u -#define cfgtab_atxmega128a1u cfgtab_atxmega128a3u -#define cfgtab_atxmega128a4u cfgtab_atxmega128a3u -#define cfgtab_atxmega192a3u cfgtab_atxmega128a3u -#define cfgtab_atxmega256a3bu cfgtab_atxmega128a3u -#define cfgtab_atxmega256a3u cfgtab_atxmega128a3u - -extern const Configitem cfgtab_atxmega64a4[16]; -#define cfgtab_atxmega128a4 cfgtab_atxmega64a4 -#define cfgtab_atxmega16a4 cfgtab_atxmega64a4 -#define cfgtab_atxmega32a4 cfgtab_atxmega64a4 - -extern const Configitem cfgtab_attiny204[23]; -#define cfgtab_attiny202 cfgtab_attiny204 -#define cfgtab_attiny212 cfgtab_attiny204 -#define cfgtab_attiny214 cfgtab_attiny204 -#define cfgtab_attiny402 cfgtab_attiny204 -#define cfgtab_attiny404 cfgtab_attiny204 -#define cfgtab_attiny406 cfgtab_attiny204 -#define cfgtab_attiny412 cfgtab_attiny204 -#define cfgtab_attiny414 cfgtab_attiny204 -#define cfgtab_attiny416 cfgtab_attiny204 -#define cfgtab_attiny417 cfgtab_attiny204 -#define cfgtab_attiny814 cfgtab_attiny204 -#define cfgtab_attiny816 cfgtab_attiny204 -#define cfgtab_attiny817 cfgtab_attiny204 -#define cfgtab_attiny1614 cfgtab_attiny204 -#define cfgtab_attiny1616 cfgtab_attiny204 -#define cfgtab_attiny1617 cfgtab_attiny204 -#define cfgtab_attiny3216 cfgtab_attiny204 -#define cfgtab_attiny3217 cfgtab_attiny204 - -extern const Configitem cfgtab_attiny1624[16]; -#define cfgtab_attiny424 cfgtab_attiny1624 -#define cfgtab_attiny426 cfgtab_attiny1624 -#define cfgtab_attiny427 cfgtab_attiny1624 -#define cfgtab_attiny824 cfgtab_attiny1624 -#define cfgtab_attiny826 cfgtab_attiny1624 -#define cfgtab_attiny827 cfgtab_attiny1624 -#define cfgtab_attiny1626 cfgtab_attiny1624 -#define cfgtab_attiny1627 cfgtab_attiny1624 -#define cfgtab_attiny3224 cfgtab_attiny1624 -#define cfgtab_attiny3226 cfgtab_attiny1624 -#define cfgtab_attiny3227 cfgtab_attiny1624 - -extern const Configitem cfgtab_avr32dd14[17]; -#define cfgtab_avr16dd14 cfgtab_avr32dd14 -#define cfgtab_avr16dd20 cfgtab_avr32dd14 -#define cfgtab_avr16dd28 cfgtab_avr32dd14 -#define cfgtab_avr16dd32 cfgtab_avr32dd14 -#define cfgtab_avr32dd20 cfgtab_avr32dd14 -#define cfgtab_avr32dd28 cfgtab_avr32dd14 -#define cfgtab_avr32dd32 cfgtab_avr32dd14 -#define cfgtab_avr64dd14 cfgtab_avr32dd14 -#define cfgtab_avr64dd20 cfgtab_avr32dd14 -#define cfgtab_avr64dd28 cfgtab_avr32dd14 -#define cfgtab_avr64dd32 cfgtab_avr32dd14 - -extern const Configitem cfgtab_avr64ea48[16]; -#define cfgtab_avr16ea28 cfgtab_avr64ea48 -#define cfgtab_avr16ea32 cfgtab_avr64ea48 -#define cfgtab_avr16ea48 cfgtab_avr64ea48 -#define cfgtab_avr32ea28 cfgtab_avr64ea48 -#define cfgtab_avr32ea32 cfgtab_avr64ea48 -#define cfgtab_avr32ea48 cfgtab_avr64ea48 -#define cfgtab_avr64ea28 cfgtab_avr64ea48 -#define cfgtab_avr64ea32 cfgtab_avr64ea48 - -extern const Configitem cfgtab_atmega103comp[15]; - -extern const Configitem cfgtab_at90scr100h[13]; -#define cfgtab_at90scr100 cfgtab_at90scr100h - -extern const Configitem cfgtab_atmega161comp[15]; - -extern const Configitem cfgtab_at90s8535comp[13]; - extern const Configitem cfgtab_attiny4[4]; #define cfgtab_attiny5 cfgtab_attiny4 #define cfgtab_attiny9 cfgtab_attiny4 @@ -2097,238 +1940,16 @@ extern const Configitem cfgtab_attiny20[5]; extern const Configitem cfgtab_attiny40[5]; -extern const Configitem cfgtab_attiny11[4]; +extern const Configitem cfgtab_attiny102[5]; +#define cfgtab_attiny104 cfgtab_attiny102 -extern const Configitem cfgtab_attiny12[6]; +extern const Configitem cfgtab_at90s1200[3]; -extern const Configitem cfgtab_attiny13[10]; -#define cfgtab_attiny13a cfgtab_attiny13 - -extern const Configitem cfgtab_attiny15[6]; - -extern const Configitem cfgtab_attiny22[3]; - -extern const Configitem cfgtab_attiny24[11]; -#define cfgtab_attiny24a cfgtab_attiny24 -#define cfgtab_attiny44 cfgtab_attiny24 -#define cfgtab_attiny44a cfgtab_attiny24 -#define cfgtab_attiny84 cfgtab_attiny24 -#define cfgtab_attiny84a cfgtab_attiny24 - -extern const Configitem cfgtab_attiny25[11]; -#define cfgtab_attiny45 cfgtab_attiny25 -#define cfgtab_attiny85 cfgtab_attiny25 - -extern const Configitem cfgtab_attiny26[8]; - -extern const Configitem cfgtab_attiny43u[11]; - -extern const Configitem cfgtab_attiny48[11]; -#define cfgtab_attiny88 cfgtab_attiny48 - -extern const Configitem cfgtab_attiny87[11]; -#define cfgtab_attiny167 cfgtab_attiny87 -#define cfgtab_ata5272 cfgtab_attiny87 -#define cfgtab_ata5505 cfgtab_attiny87 -#define cfgtab_ata6616c cfgtab_attiny87 -#define cfgtab_ata6617c cfgtab_attiny87 -#define cfgtab_ata664251 cfgtab_attiny87 - -extern const Configitem cfgtab_attiny261[11]; -#define cfgtab_attiny261a cfgtab_attiny261 -#define cfgtab_attiny461 cfgtab_attiny261 -#define cfgtab_attiny461a cfgtab_attiny261 -#define cfgtab_attiny861 cfgtab_attiny261 -#define cfgtab_attiny861a cfgtab_attiny261 - -extern const Configitem cfgtab_attiny828[16]; -#define cfgtab_attiny828r cfgtab_attiny828 - -extern const Configitem cfgtab_attiny1634[13]; -#define cfgtab_attiny1634r cfgtab_attiny1634 - -extern const Configitem cfgtab_attiny2313[11]; - -extern const Configitem cfgtab_attiny2313a[11]; -#define cfgtab_attiny4313 cfgtab_attiny2313a - -extern const Configitem cfgtab_atmega8[13]; -#define cfgtab_atmega8a cfgtab_atmega8 - -extern const Configitem cfgtab_atmega8hva[7]; -#define cfgtab_atmega16hva cfgtab_atmega8hva - -extern const Configitem cfgtab_atmega8u2[15]; - -extern const Configitem cfgtab_atmega16[13]; -#define cfgtab_atmega16a cfgtab_atmega16 - -extern const Configitem cfgtab_atmega16hvb[12]; - -extern const Configitem cfgtab_atmega16hvbrevb[12]; - -extern const Configitem cfgtab_atmega16u4[15]; - -extern const Configitem cfgtab_atmega32[13]; -#define cfgtab_atmega32a cfgtab_atmega32 - -extern const Configitem cfgtab_atmega32hvb[12]; - -extern const Configitem cfgtab_atmega32c1[17]; -#define cfgtab_atmega32m1 cfgtab_atmega32c1 - -extern const Configitem cfgtab_atmega32u2[15]; - -extern const Configitem cfgtab_atmega32u4[15]; - -extern const Configitem cfgtab_atmega32u6[15]; - -extern const Configitem cfgtab_atmega48[11]; -#define cfgtab_atmega48a cfgtab_atmega48 -#define cfgtab_atmega48p cfgtab_atmega48 -#define cfgtab_atmega48pa cfgtab_atmega48 - -extern const Configitem cfgtab_atmega48pb[11]; - -extern const Configitem cfgtab_atmega64[15]; -#define cfgtab_atmega64a cfgtab_atmega64 - -extern const Configitem cfgtab_atmega64c1[17]; -#define cfgtab_atmegas64m1 cfgtab_atmega64c1 -#define cfgtab_atmega64m1 cfgtab_atmega64c1 - -extern const Configitem cfgtab_atmega64hve2[13]; -#define cfgtab_atmega32hve2 cfgtab_atmega64hve2 - -extern const Configitem cfgtab_atmega64rfr2[14]; -#define cfgtab_atmega644rfr2 cfgtab_atmega64rfr2 - -extern const Configitem cfgtab_atmega88[14]; -#define cfgtab_atmega88a cfgtab_atmega88 -#define cfgtab_atmega88p cfgtab_atmega88 -#define cfgtab_atmega88pa cfgtab_atmega88 -#define cfgtab_ata6612c cfgtab_atmega88 - -extern const Configitem cfgtab_atmega88pb[14]; - -extern const Configitem cfgtab_atmega103[4]; - -extern const Configitem cfgtab_atmega128[15]; -#define cfgtab_atmegas128 cfgtab_atmega128 -#define cfgtab_atmega128a cfgtab_atmega128 - -extern const Configitem cfgtab_atmega128rfa1[14]; - -extern const Configitem cfgtab_atmega128rfr2[14]; -#define cfgtab_atmega1284rfr2 cfgtab_atmega128rfr2 - -extern const Configitem cfgtab_atmega161[7]; - -extern const Configitem cfgtab_atmega162[15]; - -extern const Configitem cfgtab_atmega163[9]; - -extern const Configitem cfgtab_atmega164a[14]; -#define cfgtab_atmega164p cfgtab_atmega164a -#define cfgtab_atmega164pa cfgtab_atmega164a - -extern const Configitem cfgtab_atmega165[15]; -#define cfgtab_atmega169 cfgtab_atmega165 - -extern const Configitem cfgtab_atmega165a[15]; -#define cfgtab_atmega165p cfgtab_atmega165a -#define cfgtab_atmega165pa cfgtab_atmega165a -#define cfgtab_atmega169a cfgtab_atmega165a -#define cfgtab_atmega169p cfgtab_atmega165a -#define cfgtab_atmega169pa cfgtab_atmega165a - -extern const Configitem cfgtab_atmega168[14]; -#define cfgtab_atmega168a cfgtab_atmega168 -#define cfgtab_atmega168p cfgtab_atmega168 -#define cfgtab_atmega168pa cfgtab_atmega168 -#define cfgtab_ata6613c cfgtab_atmega168 - -extern const Configitem cfgtab_atmega168pb[14]; - -extern const Configitem cfgtab_atmega256rfr2[14]; -#define cfgtab_atmega2564rfr2 cfgtab_atmega256rfr2 - -extern const Configitem cfgtab_atmega323[12]; - -extern const Configitem cfgtab_atmega324a[14]; -#define cfgtab_atmega324p cfgtab_atmega324a -#define cfgtab_atmega324pa cfgtab_atmega324a - -extern const Configitem cfgtab_atmega324pb[15]; - -extern const Configitem cfgtab_atmega325[15]; -#define cfgtab_atmega325a cfgtab_atmega325 -#define cfgtab_atmega325p cfgtab_atmega325 -#define cfgtab_atmega325pa cfgtab_atmega325 -#define cfgtab_atmega329 cfgtab_atmega325 -#define cfgtab_atmega329a cfgtab_atmega325 -#define cfgtab_atmega329p cfgtab_atmega325 -#define cfgtab_atmega329pa cfgtab_atmega325 -#define cfgtab_atmega3250 cfgtab_atmega325 -#define cfgtab_atmega3250a cfgtab_atmega325 -#define cfgtab_atmega3250p cfgtab_atmega325 -#define cfgtab_atmega3250pa cfgtab_atmega325 -#define cfgtab_atmega3290 cfgtab_atmega325 -#define cfgtab_atmega3290a cfgtab_atmega325 -#define cfgtab_atmega3290p cfgtab_atmega325 -#define cfgtab_atmega3290pa cfgtab_atmega325 - -extern const Configitem cfgtab_atmega406[10]; - -extern const Configitem cfgtab_atmega640[14]; - -extern const Configitem cfgtab_atmega644[14]; -#define cfgtab_atmega644a cfgtab_atmega644 -#define cfgtab_atmega644p cfgtab_atmega644 -#define cfgtab_atmega644pa cfgtab_atmega644 - -extern const Configitem cfgtab_atmega645[15]; -#define cfgtab_atmega645a cfgtab_atmega645 -#define cfgtab_atmega645p cfgtab_atmega645 -#define cfgtab_atmega649 cfgtab_atmega645 -#define cfgtab_atmega649a cfgtab_atmega645 -#define cfgtab_atmega649p cfgtab_atmega645 -#define cfgtab_atmega6450 cfgtab_atmega645 -#define cfgtab_atmega6450a cfgtab_atmega645 -#define cfgtab_atmega6450p cfgtab_atmega645 -#define cfgtab_atmega6490 cfgtab_atmega645 -#define cfgtab_atmega6490a cfgtab_atmega645 -#define cfgtab_atmega6490p cfgtab_atmega645 - -extern const Configitem cfgtab_atmega1280[14]; -#define cfgtab_atmega1281 cfgtab_atmega1280 - -extern const Configitem cfgtab_atmega1284[14]; -#define cfgtab_atmega1284p cfgtab_atmega1284 - -extern const Configitem cfgtab_atmega2560[14]; -#define cfgtab_atmega2561 cfgtab_atmega2560 - -extern const Configitem cfgtab_atmega8535[13]; - -extern const Configitem cfgtab_at90pwm1[17]; - -extern const Configitem cfgtab_at90pwm2b[18]; -#define cfgtab_at90pwm3b cfgtab_at90pwm2b - -extern const Configitem cfgtab_at90can32[15]; - -extern const Configitem cfgtab_at90can64[15]; - -extern const Configitem cfgtab_at90pwm216[18]; - -extern const Configitem cfgtab_at90pwm316[18]; - -extern const Configitem cfgtab_at90usb646[15]; -#define cfgtab_at90usb647 cfgtab_at90usb646 - -extern const Configitem cfgtab_at90usb1286[15]; -#define cfgtab_at90usb1287 cfgtab_at90usb1286 +extern const Configitem cfgtab_at90s2313[3]; +#define cfgtab_at90s4414 cfgtab_at90s2313 +#define cfgtab_at90s4434 cfgtab_at90s2313 +#define cfgtab_at90s8515 cfgtab_at90s2313 +#define cfgtab_at90s8535 cfgtab_at90s2313 extern const Configitem cfgtab_at90s2323[3]; @@ -2340,13 +1961,304 @@ extern const Configitem cfgtab_at90s4433[5]; extern const Configitem cfgtab_at90s8515comp[13]; +extern const Configitem cfgtab_at90s8535comp[13]; + +extern const Configitem cfgtab_at90can32[15]; + +extern const Configitem cfgtab_at90can64[15]; + +extern const Configitem cfgtab_at90can128[15]; + +extern const Configitem cfgtab_at90pwm1[17]; + +extern const Configitem cfgtab_at90pwm81[19]; +#define cfgtab_at90pwm161 cfgtab_at90pwm81 + +extern const Configitem cfgtab_at90pwm2[18]; +#define cfgtab_at90pwm3 cfgtab_at90pwm2 + +extern const Configitem cfgtab_at90pwm2b[18]; +#define cfgtab_at90pwm3b cfgtab_at90pwm2b + +extern const Configitem cfgtab_at90pwm216[18]; + +extern const Configitem cfgtab_at90pwm316[18]; + +extern const Configitem cfgtab_at90usb82[15]; +#define cfgtab_at90usb162 cfgtab_at90usb82 +#define cfgtab_atmega16u2 cfgtab_at90usb82 + +extern const Configitem cfgtab_at90usb646[15]; +#define cfgtab_at90usb647 cfgtab_at90usb646 + +extern const Configitem cfgtab_at90usb1286[15]; +#define cfgtab_at90usb1287 cfgtab_at90usb1286 + +extern const Configitem cfgtab_at90scr100[13]; +#define cfgtab_at90scr100h cfgtab_at90scr100 + +extern const Configitem cfgtab_attiny11[4]; + +extern const Configitem cfgtab_attiny12[6]; + +extern const Configitem cfgtab_attiny22[3]; + +extern const Configitem cfgtab_attiny13[10]; +#define cfgtab_attiny13a cfgtab_attiny13 + +extern const Configitem cfgtab_attiny43u[11]; + +extern const Configitem cfgtab_attiny24[11]; +#define cfgtab_attiny24a cfgtab_attiny24 +#define cfgtab_attiny44 cfgtab_attiny24 +#define cfgtab_attiny44a cfgtab_attiny24 +#define cfgtab_attiny84 cfgtab_attiny24 +#define cfgtab_attiny84a cfgtab_attiny24 + +extern const Configitem cfgtab_attiny15[6]; + +extern const Configitem cfgtab_attiny25[11]; +#define cfgtab_attiny45 cfgtab_attiny25 +#define cfgtab_attiny85 cfgtab_attiny25 + +extern const Configitem cfgtab_attiny26[8]; + +extern const Configitem cfgtab_attiny87[11]; +#define cfgtab_attiny167 cfgtab_attiny87 +#define cfgtab_ata5272 cfgtab_attiny87 +#define cfgtab_ata5505 cfgtab_attiny87 +#define cfgtab_ata6616c cfgtab_attiny87 +#define cfgtab_ata6617c cfgtab_attiny87 +#define cfgtab_ata664251 cfgtab_attiny87 + +extern const Configitem cfgtab_attiny28[3]; + +extern const Configitem cfgtab_attiny48[11]; +#define cfgtab_attiny88 cfgtab_attiny48 + +extern const Configitem cfgtab_attiny828[16]; +#define cfgtab_attiny828r cfgtab_attiny828 + +extern const Configitem cfgtab_attiny1634[13]; +#define cfgtab_attiny1634r cfgtab_attiny1634 + +extern const Configitem cfgtab_attiny441[14]; +#define cfgtab_attiny841 cfgtab_attiny441 + +extern const Configitem cfgtab_attiny261[11]; +#define cfgtab_attiny261a cfgtab_attiny261 +#define cfgtab_attiny461 cfgtab_attiny261 +#define cfgtab_attiny461a cfgtab_attiny261 +#define cfgtab_attiny861 cfgtab_attiny261 +#define cfgtab_attiny861a cfgtab_attiny261 + +extern const Configitem cfgtab_attiny2313[11]; + +extern const Configitem cfgtab_attiny2313a[11]; +#define cfgtab_attiny4313 cfgtab_attiny2313a + +extern const Configitem cfgtab_atmega8[13]; +#define cfgtab_atmega8a cfgtab_atmega8 + +extern const Configitem cfgtab_atmega16[13]; +#define cfgtab_atmega16a cfgtab_atmega16 + +extern const Configitem cfgtab_atmega32[13]; +#define cfgtab_atmega32a cfgtab_atmega32 + +extern const Configitem cfgtab_atmega64[15]; +#define cfgtab_atmega64a cfgtab_atmega64 + +extern const Configitem cfgtab_atmega128[15]; +#define cfgtab_atmega128a cfgtab_atmega128 +#define cfgtab_atmegas128 cfgtab_atmega128 + +extern const Configitem cfgtab_atmega640[14]; + +extern const Configitem cfgtab_atmega1280[14]; +#define cfgtab_atmega1281 cfgtab_atmega1280 + +extern const Configitem cfgtab_atmega2560[14]; +#define cfgtab_atmega2561 cfgtab_atmega2560 + +extern const Configitem cfgtab_atmega32c1[17]; +#define cfgtab_atmega32m1 cfgtab_atmega32c1 + +extern const Configitem cfgtab_atmega64c1[17]; +#define cfgtab_atmega64m1 cfgtab_atmega64c1 +#define cfgtab_atmegas64m1 cfgtab_atmega64c1 + +extern const Configitem cfgtab_atmega16m1[17]; + +extern const Configitem cfgtab_atmega128rfa1[14]; + +extern const Configitem cfgtab_atmega64rfr2[14]; +#define cfgtab_atmega644rfr2 cfgtab_atmega64rfr2 + +extern const Configitem cfgtab_atmega128rfr2[14]; +#define cfgtab_atmega1284rfr2 cfgtab_atmega128rfr2 + +extern const Configitem cfgtab_atmega256rfr2[14]; +#define cfgtab_atmega2564rfr2 cfgtab_atmega256rfr2 + +extern const Configitem cfgtab_atmega8u2[15]; + +extern const Configitem cfgtab_atmega32u2[15]; + +extern const Configitem cfgtab_atmega16u4[15]; + +extern const Configitem cfgtab_atmega32u4[15]; + +extern const Configitem cfgtab_atmega32u6[15]; + +extern const Configitem cfgtab_atmega161[7]; + +extern const Configitem cfgtab_atmega161comp[15]; + +extern const Configitem cfgtab_atmega162[15]; + +extern const Configitem cfgtab_atmega163[9]; + +extern const Configitem cfgtab_atmega323[12]; + +extern const Configitem cfgtab_atmega164a[14]; +#define cfgtab_atmega164p cfgtab_atmega164a +#define cfgtab_atmega164pa cfgtab_atmega164a + +extern const Configitem cfgtab_atmega324a[14]; +#define cfgtab_atmega324p cfgtab_atmega324a +#define cfgtab_atmega324pa cfgtab_atmega324a + +extern const Configitem cfgtab_atmega644[14]; +#define cfgtab_atmega644a cfgtab_atmega644 +#define cfgtab_atmega644p cfgtab_atmega644 +#define cfgtab_atmega644pa cfgtab_atmega644 + +extern const Configitem cfgtab_atmega1284[14]; +#define cfgtab_atmega1284p cfgtab_atmega1284 + +extern const Configitem cfgtab_atmega324pb[15]; + +extern const Configitem cfgtab_atmega165[15]; +#define cfgtab_atmega169 cfgtab_atmega165 + +extern const Configitem cfgtab_atmega165a[15]; +#define cfgtab_atmega165p cfgtab_atmega165a +#define cfgtab_atmega165pa cfgtab_atmega165a +#define cfgtab_atmega169a cfgtab_atmega165a +#define cfgtab_atmega169p cfgtab_atmega165a +#define cfgtab_atmega169pa cfgtab_atmega165a + +extern const Configitem cfgtab_atmega325[15]; +#define cfgtab_atmega325a cfgtab_atmega325 +#define cfgtab_atmega325p cfgtab_atmega325 +#define cfgtab_atmega325pa cfgtab_atmega325 +#define cfgtab_atmega3250 cfgtab_atmega325 +#define cfgtab_atmega3250a cfgtab_atmega325 +#define cfgtab_atmega3250p cfgtab_atmega325 +#define cfgtab_atmega3250pa cfgtab_atmega325 +#define cfgtab_atmega329 cfgtab_atmega325 +#define cfgtab_atmega329a cfgtab_atmega325 +#define cfgtab_atmega329p cfgtab_atmega325 +#define cfgtab_atmega329pa cfgtab_atmega325 +#define cfgtab_atmega3290 cfgtab_atmega325 +#define cfgtab_atmega3290a cfgtab_atmega325 +#define cfgtab_atmega3290p cfgtab_atmega325 +#define cfgtab_atmega3290pa cfgtab_atmega325 + +extern const Configitem cfgtab_atmega645[15]; +#define cfgtab_atmega645a cfgtab_atmega645 +#define cfgtab_atmega645p cfgtab_atmega645 +#define cfgtab_atmega6450 cfgtab_atmega645 +#define cfgtab_atmega6450a cfgtab_atmega645 +#define cfgtab_atmega6450p cfgtab_atmega645 +#define cfgtab_atmega649 cfgtab_atmega645 +#define cfgtab_atmega649a cfgtab_atmega645 +#define cfgtab_atmega649p cfgtab_atmega645 +#define cfgtab_atmega6490 cfgtab_atmega645 +#define cfgtab_atmega6490a cfgtab_atmega645 +#define cfgtab_atmega6490p cfgtab_atmega645 + +extern const Configitem cfgtab_atmega8515[13]; + +extern const Configitem cfgtab_atmega8535[13]; + +extern const Configitem cfgtab_atmega48[11]; +#define cfgtab_atmega48a cfgtab_atmega48 +#define cfgtab_atmega48p cfgtab_atmega48 +#define cfgtab_atmega48pa cfgtab_atmega48 + +extern const Configitem cfgtab_atmega88[14]; +#define cfgtab_atmega88a cfgtab_atmega88 +#define cfgtab_atmega88p cfgtab_atmega88 +#define cfgtab_atmega88pa cfgtab_atmega88 +#define cfgtab_ata6612c cfgtab_atmega88 + +extern const Configitem cfgtab_atmega168[14]; +#define cfgtab_atmega168a cfgtab_atmega168 +#define cfgtab_atmega168p cfgtab_atmega168 +#define cfgtab_atmega168pa cfgtab_atmega168 +#define cfgtab_ata6613c cfgtab_atmega168 + +extern const Configitem cfgtab_atmega328[14]; +#define cfgtab_atmega328p cfgtab_atmega328 +#define cfgtab_ata6614q cfgtab_atmega328 + +extern const Configitem cfgtab_atmega48pb[11]; + +extern const Configitem cfgtab_atmega88pb[14]; + +extern const Configitem cfgtab_atmega168pb[14]; + +extern const Configitem cfgtab_atmega328pb[15]; + +extern const Configitem cfgtab_atmega103[4]; + +extern const Configitem cfgtab_atmega103comp[15]; + +extern const Configitem cfgtab_atmega8hva[7]; +#define cfgtab_atmega16hva cfgtab_atmega8hva + +extern const Configitem cfgtab_atmega16hva2[9]; + +extern const Configitem cfgtab_atmega16hvb[12]; + +extern const Configitem cfgtab_atmega16hvbrevb[12]; + +extern const Configitem cfgtab_atmega32hvb[12]; + +extern const Configitem cfgtab_atmega32hvbrevb[12]; + +extern const Configitem cfgtab_atmega64hve[13]; + +extern const Configitem cfgtab_atmega32hve2[13]; +#define cfgtab_atmega64hve2 cfgtab_atmega32hve2 + +extern const Configitem cfgtab_atmega406[10]; + +extern const Configitem cfgtab_ata5700m322[9]; +#define cfgtab_ata5702m322 cfgtab_ata5700m322 + +extern const Configitem cfgtab_ata5781[11]; +#define cfgtab_ata5782 cfgtab_ata5781 +#define cfgtab_ata5783 cfgtab_ata5781 +#define cfgtab_ata5831 cfgtab_ata5781 +#define cfgtab_ata5832 cfgtab_ata5781 +#define cfgtab_ata5833 cfgtab_ata5781 + extern const Configitem cfgtab_ata5787[11]; +extern const Configitem cfgtab_ata5790[11]; +#define cfgtab_ata5791 cfgtab_ata5790 + extern const Configitem cfgtab_ata5790n[10]; #define cfgtab_ata5795 cfgtab_ata5790n extern const Configitem cfgtab_ata5835[11]; +extern const Configitem cfgtab_ata6285[17]; +#define cfgtab_ata6286 cfgtab_ata6285 + extern const Configitem cfgtab_ata6289[17]; extern const Configitem cfgtab_ata8210[11]; @@ -2354,31 +2266,81 @@ extern const Configitem cfgtab_ata8210[11]; #define cfgtab_ata8510 cfgtab_ata8210 #define cfgtab_ata8515 cfgtab_ata8210 -extern const Configitem cfgtab_atxmega16c4[15]; -#define cfgtab_atxmega16d4 cfgtab_atxmega16c4 -#define cfgtab_atxmega32c3 cfgtab_atxmega16c4 -#define cfgtab_atxmega32d3 cfgtab_atxmega16c4 -#define cfgtab_atxmega32c4 cfgtab_atxmega16c4 -#define cfgtab_atxmega32d4 cfgtab_atxmega16c4 -#define cfgtab_atxmega64c3 cfgtab_atxmega16c4 -#define cfgtab_atxmega64d3 cfgtab_atxmega16c4 -#define cfgtab_atxmega64d4 cfgtab_atxmega16c4 -#define cfgtab_atxmega128c3 cfgtab_atxmega16c4 -#define cfgtab_atxmega128d3 cfgtab_atxmega16c4 -#define cfgtab_atxmega128d4 cfgtab_atxmega16c4 -#define cfgtab_atxmega192c3 cfgtab_atxmega16c4 -#define cfgtab_atxmega192d3 cfgtab_atxmega16c4 -#define cfgtab_atxmega256c3 cfgtab_atxmega16c4 -#define cfgtab_atxmega256d3 cfgtab_atxmega16c4 -#define cfgtab_atxmega384c3 cfgtab_atxmega16c4 -#define cfgtab_atxmega384d3 cfgtab_atxmega16c4 +extern const Configitem cfgtab_atxmega64a1[16]; +#define cfgtab_atxmega128a1 cfgtab_atxmega64a1 +#define cfgtab_atxmega128a1revd cfgtab_atxmega64a1 +#define cfgtab_atxmega192a1 cfgtab_atxmega64a1 +#define cfgtab_atxmega256a1 cfgtab_atxmega64a1 +#define cfgtab_atxmega64a3 cfgtab_atxmega64a1 +#define cfgtab_atxmega128a3 cfgtab_atxmega64a1 +#define cfgtab_atxmega192a3 cfgtab_atxmega64a1 +#define cfgtab_atxmega256a3 cfgtab_atxmega64a1 +#define cfgtab_atxmega256a3b cfgtab_atxmega64a1 + +extern const Configitem cfgtab_atxmega64a1u[17]; +#define cfgtab_atxmega128a1u cfgtab_atxmega64a1u +#define cfgtab_atxmega64a3u cfgtab_atxmega64a1u +#define cfgtab_atxmega128a3u cfgtab_atxmega64a1u +#define cfgtab_atxmega192a3u cfgtab_atxmega64a1u +#define cfgtab_atxmega256a3bu cfgtab_atxmega64a1u +#define cfgtab_atxmega256a3u cfgtab_atxmega64a1u +#define cfgtab_atxmega16a4u cfgtab_atxmega64a1u +#define cfgtab_atxmega32a4u cfgtab_atxmega64a1u +#define cfgtab_atxmega64a4u cfgtab_atxmega64a1u +#define cfgtab_atxmega128a4u cfgtab_atxmega64a1u + +extern const Configitem cfgtab_atxmega16a4[16]; +#define cfgtab_atxmega32a4 cfgtab_atxmega16a4 +#define cfgtab_atxmega64a4 cfgtab_atxmega16a4 +#define cfgtab_atxmega128a4 cfgtab_atxmega16a4 extern const Configitem cfgtab_atxmega64b1[17]; -#define cfgtab_atxmega64b3 cfgtab_atxmega64b1 #define cfgtab_atxmega128b1 cfgtab_atxmega64b1 +#define cfgtab_atxmega64b3 cfgtab_atxmega64b1 #define cfgtab_atxmega128b3 cfgtab_atxmega64b1 -extern const Configitem cfgtab_attiny416auto[23]; +extern const Configitem cfgtab_atxmega32c3[15]; +#define cfgtab_atxmega64c3 cfgtab_atxmega32c3 +#define cfgtab_atxmega128c3 cfgtab_atxmega32c3 +#define cfgtab_atxmega192c3 cfgtab_atxmega32c3 +#define cfgtab_atxmega256c3 cfgtab_atxmega32c3 +#define cfgtab_atxmega384c3 cfgtab_atxmega32c3 +#define cfgtab_atxmega16c4 cfgtab_atxmega32c3 +#define cfgtab_atxmega32c4 cfgtab_atxmega32c3 +#define cfgtab_atxmega32d3 cfgtab_atxmega32c3 +#define cfgtab_atxmega64d3 cfgtab_atxmega32c3 +#define cfgtab_atxmega128d3 cfgtab_atxmega32c3 +#define cfgtab_atxmega192d3 cfgtab_atxmega32c3 +#define cfgtab_atxmega256d3 cfgtab_atxmega32c3 +#define cfgtab_atxmega384d3 cfgtab_atxmega32c3 +#define cfgtab_atxmega16d4 cfgtab_atxmega32c3 +#define cfgtab_atxmega32d4 cfgtab_atxmega32c3 +#define cfgtab_atxmega64d4 cfgtab_atxmega32c3 +#define cfgtab_atxmega128d4 cfgtab_atxmega32c3 + +extern const Configitem cfgtab_atxmega8e5[17]; +#define cfgtab_atxmega16e5 cfgtab_atxmega8e5 +#define cfgtab_atxmega32e5 cfgtab_atxmega8e5 + +extern const Configitem cfgtab_attiny202[23]; +#define cfgtab_attiny204 cfgtab_attiny202 +#define cfgtab_attiny402 cfgtab_attiny202 +#define cfgtab_attiny404 cfgtab_attiny202 +#define cfgtab_attiny406 cfgtab_attiny202 +#define cfgtab_attiny212 cfgtab_attiny202 +#define cfgtab_attiny214 cfgtab_attiny202 +#define cfgtab_attiny412 cfgtab_attiny202 +#define cfgtab_attiny414 cfgtab_attiny202 +#define cfgtab_attiny416 cfgtab_attiny202 +#define cfgtab_attiny417 cfgtab_attiny202 +#define cfgtab_attiny814 cfgtab_attiny202 +#define cfgtab_attiny816 cfgtab_attiny202 +#define cfgtab_attiny817 cfgtab_attiny202 +#define cfgtab_attiny1614 cfgtab_attiny202 +#define cfgtab_attiny1616 cfgtab_attiny202 +#define cfgtab_attiny1617 cfgtab_attiny202 +#define cfgtab_attiny3216 cfgtab_attiny202 +#define cfgtab_attiny3217 cfgtab_attiny202 extern const Configitem cfgtab_attiny804[15]; #define cfgtab_attiny806 cfgtab_attiny804 @@ -2387,6 +2349,21 @@ extern const Configitem cfgtab_attiny804[15]; #define cfgtab_attiny1606 cfgtab_attiny804 #define cfgtab_attiny1607 cfgtab_attiny804 +extern const Configitem cfgtab_attiny416auto[23]; + +extern const Configitem cfgtab_attiny424[16]; +#define cfgtab_attiny426 cfgtab_attiny424 +#define cfgtab_attiny427 cfgtab_attiny424 +#define cfgtab_attiny824 cfgtab_attiny424 +#define cfgtab_attiny826 cfgtab_attiny424 +#define cfgtab_attiny827 cfgtab_attiny424 +#define cfgtab_attiny1624 cfgtab_attiny424 +#define cfgtab_attiny1626 cfgtab_attiny424 +#define cfgtab_attiny1627 cfgtab_attiny424 +#define cfgtab_attiny3224 cfgtab_attiny424 +#define cfgtab_attiny3226 cfgtab_attiny424 +#define cfgtab_attiny3227 cfgtab_attiny424 + extern const Configitem cfgtab_atmega808[15]; #define cfgtab_atmega809 cfgtab_atmega808 #define cfgtab_atmega1608 cfgtab_atmega808 @@ -2396,39 +2373,6 @@ extern const Configitem cfgtab_atmega808[15]; #define cfgtab_atmega4808 cfgtab_atmega808 #define cfgtab_atmega4809 cfgtab_atmega808 -extern const Configitem cfgtab_avr16du14[20]; -#define cfgtab_avr16du20 cfgtab_avr16du14 -#define cfgtab_avr16du28 cfgtab_avr16du14 -#define cfgtab_avr16du32 cfgtab_avr16du14 -#define cfgtab_avr32du14 cfgtab_avr16du14 -#define cfgtab_avr32du20 cfgtab_avr16du14 -#define cfgtab_avr32du28 cfgtab_avr16du14 -#define cfgtab_avr32du32 cfgtab_avr16du14 -#define cfgtab_avr64du28 cfgtab_avr16du14 -#define cfgtab_avr64du32 cfgtab_avr16du14 - -extern const Configitem cfgtab_avr16eb14[18]; -#define cfgtab_avr16eb20 cfgtab_avr16eb14 -#define cfgtab_avr16eb28 cfgtab_avr16eb14 -#define cfgtab_avr16eb32 cfgtab_avr16eb14 -#define cfgtab_avr32eb14 cfgtab_avr16eb14 -#define cfgtab_avr32eb20 cfgtab_avr16eb14 -#define cfgtab_avr32eb28 cfgtab_avr16eb14 -#define cfgtab_avr32eb32 cfgtab_avr16eb14 - -extern const Configitem cfgtab_avr16la14[20]; -#define cfgtab_avr16la20 cfgtab_avr16la14 -#define cfgtab_avr16la28 cfgtab_avr16la14 -#define cfgtab_avr16la32 cfgtab_avr16la14 -#define cfgtab_avr32la14 cfgtab_avr16la14 -#define cfgtab_avr32la20 cfgtab_avr16la14 -#define cfgtab_avr32la28 cfgtab_avr16la14 -#define cfgtab_avr32la32 cfgtab_avr16la14 - -extern const Configitem cfgtab_avr32sd20[18]; -#define cfgtab_avr32sd28 cfgtab_avr32sd20 -#define cfgtab_avr32sd32 cfgtab_avr32sd20 - extern const Configitem cfgtab_avr32da28[15]; #define cfgtab_avr32da32 cfgtab_avr32da28 #define cfgtab_avr32da48 cfgtab_avr32da28 @@ -2465,84 +2409,65 @@ extern const Configitem cfgtab_avr32db28[16]; #define cfgtab_avr128db48 cfgtab_avr32db28 #define cfgtab_avr128db64 cfgtab_avr32db28 +extern const Configitem cfgtab_avr16dd14[17]; +#define cfgtab_avr16dd20 cfgtab_avr16dd14 +#define cfgtab_avr16dd28 cfgtab_avr16dd14 +#define cfgtab_avr16dd32 cfgtab_avr16dd14 +#define cfgtab_avr32dd14 cfgtab_avr16dd14 +#define cfgtab_avr32dd20 cfgtab_avr16dd14 +#define cfgtab_avr32dd28 cfgtab_avr16dd14 +#define cfgtab_avr32dd32 cfgtab_avr16dd14 +#define cfgtab_avr64dd14 cfgtab_avr16dd14 +#define cfgtab_avr64dd20 cfgtab_avr16dd14 +#define cfgtab_avr64dd28 cfgtab_avr16dd14 +#define cfgtab_avr64dd32 cfgtab_avr16dd14 + +extern const Configitem cfgtab_avr16du14[20]; +#define cfgtab_avr16du20 cfgtab_avr16du14 +#define cfgtab_avr16du28 cfgtab_avr16du14 +#define cfgtab_avr16du32 cfgtab_avr16du14 +#define cfgtab_avr32du14 cfgtab_avr16du14 +#define cfgtab_avr32du20 cfgtab_avr16du14 +#define cfgtab_avr32du28 cfgtab_avr16du14 +#define cfgtab_avr32du32 cfgtab_avr16du14 +#define cfgtab_avr64du28 cfgtab_avr16du14 +#define cfgtab_avr64du32 cfgtab_avr16du14 + +extern const Configitem cfgtab_avr16ea28[16]; +#define cfgtab_avr16ea32 cfgtab_avr16ea28 +#define cfgtab_avr16ea48 cfgtab_avr16ea28 +#define cfgtab_avr32ea28 cfgtab_avr16ea28 +#define cfgtab_avr32ea32 cfgtab_avr16ea28 +#define cfgtab_avr32ea48 cfgtab_avr16ea28 +#define cfgtab_avr64ea28 cfgtab_avr16ea28 +#define cfgtab_avr64ea32 cfgtab_avr16ea28 +#define cfgtab_avr64ea48 cfgtab_avr16ea28 + +extern const Configitem cfgtab_avr16eb14[18]; +#define cfgtab_avr16eb20 cfgtab_avr16eb14 +#define cfgtab_avr16eb28 cfgtab_avr16eb14 +#define cfgtab_avr16eb32 cfgtab_avr16eb14 +#define cfgtab_avr32eb14 cfgtab_avr16eb14 +#define cfgtab_avr32eb20 cfgtab_avr16eb14 +#define cfgtab_avr32eb28 cfgtab_avr16eb14 +#define cfgtab_avr32eb32 cfgtab_avr16eb14 + +extern const Configitem cfgtab_avr16la14[20]; +#define cfgtab_avr16la20 cfgtab_avr16la14 +#define cfgtab_avr16la28 cfgtab_avr16la14 +#define cfgtab_avr16la32 cfgtab_avr16la14 +#define cfgtab_avr32la14 cfgtab_avr16la14 +#define cfgtab_avr32la20 cfgtab_avr16la14 +#define cfgtab_avr32la28 cfgtab_avr16la14 +#define cfgtab_avr32la32 cfgtab_avr16la14 + +extern const Configitem cfgtab_avr32sd20[18]; +#define cfgtab_avr32sd28 cfgtab_avr32sd20 +#define cfgtab_avr32sd32 cfgtab_avr32sd20 + // I/O Register files -extern const Register_file rgftab_atmega328[81]; -#define rgftab_atmega328p rgftab_atmega328 - -extern const Register_file rgftab_atmega16m1[136]; -#define rgftab_atmega32m1 rgftab_atmega16m1 - -extern const Register_file rgftab_atmega32hvbrevb[91]; -#define rgftab_atmega16hvb rgftab_atmega32hvbrevb -#define rgftab_atmega16hvbrevb rgftab_atmega32hvbrevb -#define rgftab_atmega32hvb rgftab_atmega32hvbrevb - -extern const Register_file rgftab_atmega328pb[125]; - -extern const Register_file rgftab_atmega8515[52]; - -extern const Register_file rgftab_attiny102[55]; -#define rgftab_attiny104 rgftab_attiny102 - -extern const Register_file rgftab_attiny28[20]; - -extern const Register_file rgftab_attiny441[101]; -#define rgftab_attiny841 rgftab_attiny441 - -extern const Register_file rgftab_at90pwm81[84]; - -extern const Register_file rgftab_at90can128[137]; -#define rgftab_at90can32 rgftab_at90can128 -#define rgftab_at90can64 rgftab_at90can128 - -extern const Register_file rgftab_at90usb162[92]; -#define rgftab_at90usb82 rgftab_at90usb162 - -extern const Register_file rgftab_ata5700m322[337]; - -extern const Register_file rgftab_ata5781[262]; -#define rgftab_ata5782 rgftab_ata5781 -#define rgftab_ata5783 rgftab_ata5781 -#define rgftab_ata8210 rgftab_ata5781 -#define rgftab_ata8215 rgftab_ata5781 - -extern const Register_file rgftab_ata5790[112]; - -extern const Register_file rgftab_ata6285[79]; -#define rgftab_ata6286 rgftab_ata6285 - -extern const Register_file rgftab_atxmega16e5[438]; -#define rgftab_atxmega8e5 rgftab_atxmega16e5 -#define rgftab_atxmega32e5 rgftab_atxmega16e5 - -extern const Register_file rgftab_atxmega128a3[680]; -#define rgftab_atxmega64a3 rgftab_atxmega128a3 -#define rgftab_atxmega192a3 rgftab_atxmega128a3 -#define rgftab_atxmega256a3 rgftab_atxmega128a3 - -extern const Register_file rgftab_atxmega128a3u[792]; -#define rgftab_atxmega64a3u rgftab_atxmega128a3u -#define rgftab_atxmega192a3u rgftab_atxmega128a3u -#define rgftab_atxmega256a3u rgftab_atxmega128a3u - -extern const Register_file rgftab_attiny204[235]; -#define rgftab_attiny404 rgftab_attiny204 - -extern const Register_file rgftab_attiny1624[307]; -#define rgftab_attiny424 rgftab_attiny1624 -#define rgftab_attiny824 rgftab_attiny1624 -#define rgftab_attiny3224 rgftab_attiny1624 - -extern const Register_file rgftab_avr32dd14[390]; -#define rgftab_avr16dd14 rgftab_avr32dd14 -#define rgftab_avr64dd14 rgftab_avr32dd14 - -extern const Register_file rgftab_avr64ea48[502]; -#define rgftab_avr16ea48 rgftab_avr64ea48 -#define rgftab_avr32ea48 rgftab_avr64ea48 - extern const Register_file rgftab_attiny4[36]; #define rgftab_attiny9 rgftab_attiny4 @@ -2553,6 +2478,38 @@ extern const Register_file rgftab_attiny20[61]; extern const Register_file rgftab_attiny40[63]; +extern const Register_file rgftab_attiny102[55]; +#define rgftab_attiny104 rgftab_attiny102 + +extern const Register_file rgftab_at90can32[137]; +#define rgftab_at90can64 rgftab_at90can32 +#define rgftab_at90can128 rgftab_at90can32 + +extern const Register_file rgftab_at90pwm1[92]; + +extern const Register_file rgftab_at90pwm81[84]; + +extern const Register_file rgftab_at90pwm161[86]; + +extern const Register_file rgftab_at90pwm2b[100]; + +extern const Register_file rgftab_at90pwm216[102]; + +extern const Register_file rgftab_at90pwm3[115]; + +extern const Register_file rgftab_at90pwm3b[115]; + +extern const Register_file rgftab_at90pwm316[117]; + +extern const Register_file rgftab_at90usb82[92]; +#define rgftab_at90usb162 rgftab_at90usb82 + +extern const Register_file rgftab_at90usb646[157]; +#define rgftab_at90usb647 rgftab_at90usb646 +#define rgftab_at90usb1287 rgftab_at90usb646 + +extern const Register_file rgftab_at90usb1286[132]; + extern const Register_file rgftab_attiny11[14]; extern const Register_file rgftab_attiny12[18]; @@ -2561,46 +2518,51 @@ extern const Register_file rgftab_attiny13[35]; extern const Register_file rgftab_attiny13a[37]; -extern const Register_file rgftab_attiny15[28]; +extern const Register_file rgftab_attiny43u[54]; extern const Register_file rgftab_attiny24[55]; #define rgftab_attiny24a rgftab_attiny24 -extern const Register_file rgftab_attiny25[55]; - -extern const Register_file rgftab_attiny26[37]; - -extern const Register_file rgftab_attiny43u[54]; - extern const Register_file rgftab_attiny44[55]; #define rgftab_attiny44a rgftab_attiny44 -extern const Register_file rgftab_attiny45[55]; -#define rgftab_attiny85 rgftab_attiny45 - -extern const Register_file rgftab_attiny48[74]; - extern const Register_file rgftab_attiny84[55]; #define rgftab_attiny84a rgftab_attiny84 +extern const Register_file rgftab_attiny15[28]; + +extern const Register_file rgftab_attiny25[55]; + +extern const Register_file rgftab_attiny45[55]; +#define rgftab_attiny85 rgftab_attiny45 + +extern const Register_file rgftab_attiny26[37]; + extern const Register_file rgftab_attiny87[80]; #define rgftab_attiny167 rgftab_attiny87 +extern const Register_file rgftab_attiny28[20]; + +extern const Register_file rgftab_attiny48[74]; + extern const Register_file rgftab_attiny88[74]; +extern const Register_file rgftab_attiny828[94]; + +extern const Register_file rgftab_attiny1634[89]; + +extern const Register_file rgftab_attiny441[101]; +#define rgftab_attiny841 rgftab_attiny441 + extern const Register_file rgftab_attiny261[63]; #define rgftab_attiny261a rgftab_attiny261 extern const Register_file rgftab_attiny461[63]; #define rgftab_attiny461a rgftab_attiny461 -extern const Register_file rgftab_attiny828[94]; - extern const Register_file rgftab_attiny861[63]; #define rgftab_attiny861a rgftab_attiny861 -extern const Register_file rgftab_attiny1634[89]; - extern const Register_file rgftab_attiny2313[54]; extern const Register_file rgftab_attiny2313a[58]; @@ -2610,69 +2572,58 @@ extern const Register_file rgftab_attiny4313[58]; extern const Register_file rgftab_atmega8[61]; #define rgftab_atmega8a rgftab_atmega8 -extern const Register_file rgftab_atmega8hva[74]; -#define rgftab_atmega16hva rgftab_atmega8hva - -extern const Register_file rgftab_atmega8u2[92]; -#define rgftab_atmega16u2 rgftab_atmega8u2 -#define rgftab_atmega32u2 rgftab_atmega8u2 - extern const Register_file rgftab_atmega16[70]; extern const Register_file rgftab_atmega16a[70]; -extern const Register_file rgftab_atmega16u4[139]; -#define rgftab_atmega32u4 rgftab_atmega16u4 - extern const Register_file rgftab_atmega32[68]; extern const Register_file rgftab_atmega32a[66]; -extern const Register_file rgftab_atmega32c1[117]; - -extern const Register_file rgftab_atmega48[81]; -#define rgftab_atmega48p rgftab_atmega48 - -extern const Register_file rgftab_atmega48a[82]; -#define rgftab_atmega48pa rgftab_atmega48a - -extern const Register_file rgftab_atmega48pb[95]; - extern const Register_file rgftab_atmega64[103]; #define rgftab_atmega64a rgftab_atmega64 -extern const Register_file rgftab_atmega64c1[122]; - -extern const Register_file rgftab_atmegas64m1[136]; -#define rgftab_atmega64m1 rgftab_atmegas64m1 - -extern const Register_file rgftab_atmega64hve2[89]; - -extern const Register_file rgftab_atmega64rfr2[269]; -#define rgftab_atmega644rfr2 rgftab_atmega64rfr2 - -extern const Register_file rgftab_atmega88[81]; -#define rgftab_atmega88a rgftab_atmega88 -#define rgftab_atmega88p rgftab_atmega88 -#define rgftab_atmega88pa rgftab_atmega88 -#define rgftab_atmega168 rgftab_atmega88 -#define rgftab_atmega168a rgftab_atmega88 -#define rgftab_atmega168p rgftab_atmega88 -#define rgftab_atmega168pa rgftab_atmega88 - -extern const Register_file rgftab_atmega88pb[95]; -#define rgftab_atmega168pb rgftab_atmega88pb - extern const Register_file rgftab_atmega128[103]; #define rgftab_atmegas128 rgftab_atmega128 extern const Register_file rgftab_atmega128a[103]; +extern const Register_file rgftab_atmega640[160]; + +extern const Register_file rgftab_atmega1280[161]; +#define rgftab_atmega2560 rgftab_atmega1280 + +extern const Register_file rgftab_atmega32c1[117]; + +extern const Register_file rgftab_atmega64c1[122]; + +extern const Register_file rgftab_atmega16m1[136]; +#define rgftab_atmega32m1 rgftab_atmega16m1 + +extern const Register_file rgftab_atmega64m1[136]; +#define rgftab_atmegas64m1 rgftab_atmega64m1 + extern const Register_file rgftab_atmega128rfa1[237]; +extern const Register_file rgftab_atmega64rfr2[269]; +#define rgftab_atmega644rfr2 rgftab_atmega64rfr2 + extern const Register_file rgftab_atmega128rfr2[270]; #define rgftab_atmega1284rfr2 rgftab_atmega128rfr2 +extern const Register_file rgftab_atmega256rfr2[271]; + +extern const Register_file rgftab_atmega8u2[92]; +#define rgftab_atmega16u2 rgftab_atmega8u2 +#define rgftab_atmega32u2 rgftab_atmega8u2 + +extern const Register_file rgftab_atmega16u4[139]; +#define rgftab_atmega32u4 rgftab_atmega16u4 + +extern const Register_file rgftab_atmega1281[138]; + +extern const Register_file rgftab_atmega2561[139]; + extern const Register_file rgftab_atmega162[79]; extern const Register_file rgftab_atmega164a[96]; @@ -2682,23 +2633,74 @@ extern const Register_file rgftab_atmega164a[96]; #define rgftab_atmega324p rgftab_atmega164a #define rgftab_atmega324pa rgftab_atmega164a +extern const Register_file rgftab_atmega644[88]; + +extern const Register_file rgftab_atmega644a[93]; +#define rgftab_atmega644p rgftab_atmega644a +#define rgftab_atmega644pa rgftab_atmega644a + +extern const Register_file rgftab_atmega1284[104]; +#define rgftab_atmega1284p rgftab_atmega1284 + +extern const Register_file rgftab_atmega324pb[134]; + +extern const Register_file rgftab_atmega2564rfr2[271]; + extern const Register_file rgftab_atmega165a[86]; #define rgftab_atmega165p rgftab_atmega165a #define rgftab_atmega165pa rgftab_atmega165a -extern const Register_file rgftab_atmega169a[106]; -#define rgftab_atmega169p rgftab_atmega169a -#define rgftab_atmega169pa rgftab_atmega169a - -extern const Register_file rgftab_atmega256rfr2[271]; - -extern const Register_file rgftab_atmega324pb[134]; - extern const Register_file rgftab_atmega325[86]; #define rgftab_atmega325a rgftab_atmega325 #define rgftab_atmega325p rgftab_atmega325 #define rgftab_atmega325pa rgftab_atmega325 +extern const Register_file rgftab_atmega645[86]; +#define rgftab_atmega645a rgftab_atmega645 +#define rgftab_atmega645p rgftab_atmega645 + +extern const Register_file rgftab_atmega3250[94]; +#define rgftab_atmega3250a rgftab_atmega3250 +#define rgftab_atmega3250p rgftab_atmega3250 +#define rgftab_atmega3250pa rgftab_atmega3250 + +extern const Register_file rgftab_atmega6450[94]; +#define rgftab_atmega6450a rgftab_atmega6450 +#define rgftab_atmega6450p rgftab_atmega6450 + +extern const Register_file rgftab_atmega8515[52]; + +extern const Register_file rgftab_atmega8535[67]; + +extern const Register_file rgftab_atmega48[81]; +#define rgftab_atmega48p rgftab_atmega48 + +extern const Register_file rgftab_atmega48a[82]; +#define rgftab_atmega48pa rgftab_atmega48a + +extern const Register_file rgftab_atmega88[81]; +#define rgftab_atmega88a rgftab_atmega88 +#define rgftab_atmega88p rgftab_atmega88 +#define rgftab_atmega88pa rgftab_atmega88 +#define rgftab_atmega168 rgftab_atmega88 +#define rgftab_atmega168a rgftab_atmega88 +#define rgftab_atmega168p rgftab_atmega88 +#define rgftab_atmega168pa rgftab_atmega88 + +extern const Register_file rgftab_atmega328[81]; +#define rgftab_atmega328p rgftab_atmega328 + +extern const Register_file rgftab_atmega48pb[95]; + +extern const Register_file rgftab_atmega88pb[95]; +#define rgftab_atmega168pb rgftab_atmega88pb + +extern const Register_file rgftab_atmega328pb[125]; + +extern const Register_file rgftab_atmega169a[106]; +#define rgftab_atmega169p rgftab_atmega169a +#define rgftab_atmega169pa rgftab_atmega169a + extern const Register_file rgftab_atmega329[106]; extern const Register_file rgftab_atmega329a[106]; @@ -2706,41 +2708,10 @@ extern const Register_file rgftab_atmega329a[106]; extern const Register_file rgftab_atmega329p[106]; -extern const Register_file rgftab_atmega406[79]; - -extern const Register_file rgftab_atmega640[160]; - -extern const Register_file rgftab_atmega644[88]; - -extern const Register_file rgftab_atmega644a[93]; -#define rgftab_atmega644p rgftab_atmega644a -#define rgftab_atmega644pa rgftab_atmega644a - -extern const Register_file rgftab_atmega645[86]; -#define rgftab_atmega645a rgftab_atmega645 -#define rgftab_atmega645p rgftab_atmega645 - extern const Register_file rgftab_atmega649[106]; #define rgftab_atmega649a rgftab_atmega649 #define rgftab_atmega649p rgftab_atmega649 -extern const Register_file rgftab_atmega1280[161]; -#define rgftab_atmega2560 rgftab_atmega1280 - -extern const Register_file rgftab_atmega1281[138]; - -extern const Register_file rgftab_atmega1284[104]; -#define rgftab_atmega1284p rgftab_atmega1284 - -extern const Register_file rgftab_atmega2561[139]; - -extern const Register_file rgftab_atmega2564rfr2[271]; - -extern const Register_file rgftab_atmega3250[94]; -#define rgftab_atmega3250a rgftab_atmega3250 -#define rgftab_atmega3250p rgftab_atmega3250 -#define rgftab_atmega3250pa rgftab_atmega3250 - extern const Register_file rgftab_atmega3290[118]; #define rgftab_atmega3290a rgftab_atmega3290 @@ -2748,43 +2719,39 @@ extern const Register_file rgftab_atmega3290p[118]; extern const Register_file rgftab_atmega3290pa[118]; -extern const Register_file rgftab_atmega6450[94]; -#define rgftab_atmega6450a rgftab_atmega6450 -#define rgftab_atmega6450p rgftab_atmega6450 - extern const Register_file rgftab_atmega6490[118]; #define rgftab_atmega6490a rgftab_atmega6490 #define rgftab_atmega6490p rgftab_atmega6490 -extern const Register_file rgftab_atmega8535[67]; +extern const Register_file rgftab_atmega8hva[74]; +#define rgftab_atmega16hva rgftab_atmega8hva -extern const Register_file rgftab_at90pwm1[92]; +extern const Register_file rgftab_atmega16hvb[91]; +#define rgftab_atmega16hvbrevb rgftab_atmega16hvb +#define rgftab_atmega32hvb rgftab_atmega16hvb +#define rgftab_atmega32hvbrevb rgftab_atmega16hvb -extern const Register_file rgftab_at90pwm2b[100]; +extern const Register_file rgftab_atmega64hve2[89]; -extern const Register_file rgftab_at90pwm3[115]; - -extern const Register_file rgftab_at90pwm3b[115]; - -extern const Register_file rgftab_at90pwm161[86]; - -extern const Register_file rgftab_at90pwm216[102]; - -extern const Register_file rgftab_at90pwm316[117]; - -extern const Register_file rgftab_at90usb646[157]; -#define rgftab_at90usb647 rgftab_at90usb646 -#define rgftab_at90usb1287 rgftab_at90usb646 - -extern const Register_file rgftab_at90usb1286[132]; +extern const Register_file rgftab_atmega406[79]; extern const Register_file rgftab_ata5272[80]; #define rgftab_ata5505 rgftab_ata5272 +extern const Register_file rgftab_ata5700m322[337]; + extern const Register_file rgftab_ata5702m322[378]; +extern const Register_file rgftab_ata5781[262]; +#define rgftab_ata5782 rgftab_ata5781 +#define rgftab_ata5783 rgftab_ata5781 +#define rgftab_ata8210 rgftab_ata5781 +#define rgftab_ata8215 rgftab_ata5781 + extern const Register_file rgftab_ata5787[292]; +extern const Register_file rgftab_ata5790[112]; + extern const Register_file rgftab_ata5790n[117]; #define rgftab_ata5791 rgftab_ata5790n @@ -2798,6 +2765,9 @@ extern const Register_file rgftab_ata5831[279]; extern const Register_file rgftab_ata5835[307]; +extern const Register_file rgftab_ata6285[79]; +#define rgftab_ata6286 rgftab_ata6285 + extern const Register_file rgftab_ata6612c[81]; #define rgftab_ata6613c rgftab_ata6612c @@ -2807,35 +2777,34 @@ extern const Register_file rgftab_ata6616c[81]; #define rgftab_ata6617c rgftab_ata6616c #define rgftab_ata664251 rgftab_ata6616c +extern const Register_file rgftab_atxmega64a1[814]; +#define rgftab_atxmega128a1 rgftab_atxmega64a1 + +extern const Register_file rgftab_atxmega64a1u[943]; +#define rgftab_atxmega128a1u rgftab_atxmega64a1u + +extern const Register_file rgftab_atxmega64a3[680]; +#define rgftab_atxmega128a3 rgftab_atxmega64a3 +#define rgftab_atxmega192a3 rgftab_atxmega64a3 +#define rgftab_atxmega256a3 rgftab_atxmega64a3 + +extern const Register_file rgftab_atxmega256a3b[665]; + +extern const Register_file rgftab_atxmega64a3u[792]; +#define rgftab_atxmega128a3u rgftab_atxmega64a3u +#define rgftab_atxmega192a3u rgftab_atxmega64a3u +#define rgftab_atxmega256a3u rgftab_atxmega64a3u + +extern const Register_file rgftab_atxmega256a3bu[780]; + extern const Register_file rgftab_atxmega16a4[553]; #define rgftab_atxmega32a4 rgftab_atxmega16a4 extern const Register_file rgftab_atxmega16a4u[630]; #define rgftab_atxmega32a4u rgftab_atxmega16a4u -extern const Register_file rgftab_atxmega16c4[482]; -#define rgftab_atxmega32c4 rgftab_atxmega16c4 - -extern const Register_file rgftab_atxmega16d4[460]; -#define rgftab_atxmega32d4 rgftab_atxmega16d4 - -extern const Register_file rgftab_atxmega32c3[569]; -#define rgftab_atxmega64c3 rgftab_atxmega32c3 -#define rgftab_atxmega128c3 rgftab_atxmega32c3 -#define rgftab_atxmega192c3 rgftab_atxmega32c3 -#define rgftab_atxmega256c3 rgftab_atxmega32c3 - -extern const Register_file rgftab_atxmega32d3[567]; -#define rgftab_atxmega64d3 rgftab_atxmega32d3 -#define rgftab_atxmega128d3 rgftab_atxmega32d3 -#define rgftab_atxmega192d3 rgftab_atxmega32d3 -#define rgftab_atxmega256d3 rgftab_atxmega32d3 - -extern const Register_file rgftab_atxmega64a1[814]; -#define rgftab_atxmega128a1 rgftab_atxmega64a1 - -extern const Register_file rgftab_atxmega64a1u[943]; -#define rgftab_atxmega128a1u rgftab_atxmega64a1u +extern const Register_file rgftab_atxmega64a4u[632]; +#define rgftab_atxmega128a4u rgftab_atxmega64a4u extern const Register_file rgftab_atxmega64b1[574]; #define rgftab_atxmega128b1 rgftab_atxmega64b1 @@ -2843,31 +2812,56 @@ extern const Register_file rgftab_atxmega64b1[574]; extern const Register_file rgftab_atxmega64b3[458]; #define rgftab_atxmega128b3 rgftab_atxmega64b3 -extern const Register_file rgftab_atxmega64a4u[632]; -#define rgftab_atxmega128a4u rgftab_atxmega64a4u +extern const Register_file rgftab_atxmega32c3[569]; +#define rgftab_atxmega64c3 rgftab_atxmega32c3 +#define rgftab_atxmega128c3 rgftab_atxmega32c3 +#define rgftab_atxmega192c3 rgftab_atxmega32c3 +#define rgftab_atxmega256c3 rgftab_atxmega32c3 + +extern const Register_file rgftab_atxmega384c3[603]; + +extern const Register_file rgftab_atxmega16c4[482]; +#define rgftab_atxmega32c4 rgftab_atxmega16c4 + +extern const Register_file rgftab_atxmega32d3[567]; +#define rgftab_atxmega64d3 rgftab_atxmega32d3 +#define rgftab_atxmega128d3 rgftab_atxmega32d3 +#define rgftab_atxmega192d3 rgftab_atxmega32d3 +#define rgftab_atxmega256d3 rgftab_atxmega32d3 + +extern const Register_file rgftab_atxmega384d3[560]; + +extern const Register_file rgftab_atxmega16d4[460]; +#define rgftab_atxmega32d4 rgftab_atxmega16d4 extern const Register_file rgftab_atxmega64d4[460]; #define rgftab_atxmega128d4 rgftab_atxmega64d4 -extern const Register_file rgftab_atxmega256a3b[665]; - -extern const Register_file rgftab_atxmega256a3bu[780]; - -extern const Register_file rgftab_atxmega384c3[603]; - -extern const Register_file rgftab_atxmega384d3[560]; +extern const Register_file rgftab_atxmega8e5[438]; +#define rgftab_atxmega16e5 rgftab_atxmega8e5 +#define rgftab_atxmega32e5 rgftab_atxmega8e5 extern const Register_file rgftab_attiny202[217]; #define rgftab_attiny402 rgftab_attiny202 +extern const Register_file rgftab_attiny204[235]; +#define rgftab_attiny404 rgftab_attiny204 + +extern const Register_file rgftab_attiny406[253]; + +extern const Register_file rgftab_attiny804[255]; +#define rgftab_attiny806 rgftab_attiny804 +#define rgftab_attiny807 rgftab_attiny804 +#define rgftab_attiny1604 rgftab_attiny804 +#define rgftab_attiny1606 rgftab_attiny804 +#define rgftab_attiny1607 rgftab_attiny804 + extern const Register_file rgftab_attiny212[247]; #define rgftab_attiny412 rgftab_attiny212 extern const Register_file rgftab_attiny214[265]; #define rgftab_attiny414 rgftab_attiny214 -extern const Register_file rgftab_attiny406[253]; - extern const Register_file rgftab_attiny416[283]; extern const Register_file rgftab_attiny416auto[283]; @@ -2876,22 +2870,6 @@ extern const Register_file rgftab_attiny417[283]; #define rgftab_attiny816 rgftab_attiny417 #define rgftab_attiny817 rgftab_attiny417 -extern const Register_file rgftab_attiny426[308]; -#define rgftab_attiny427 rgftab_attiny426 -#define rgftab_attiny826 rgftab_attiny426 -#define rgftab_attiny827 rgftab_attiny426 -#define rgftab_attiny1626 rgftab_attiny426 -#define rgftab_attiny1627 rgftab_attiny426 -#define rgftab_attiny3226 rgftab_attiny426 -#define rgftab_attiny3227 rgftab_attiny426 - -extern const Register_file rgftab_attiny804[255]; -#define rgftab_attiny806 rgftab_attiny804 -#define rgftab_attiny807 rgftab_attiny804 -#define rgftab_attiny1604 rgftab_attiny804 -#define rgftab_attiny1606 rgftab_attiny804 -#define rgftab_attiny1607 rgftab_attiny804 - extern const Register_file rgftab_attiny814[265]; extern const Register_file rgftab_attiny1614[308]; @@ -2902,6 +2880,20 @@ extern const Register_file rgftab_attiny1616[326]; extern const Register_file rgftab_attiny3216[326]; #define rgftab_attiny3217 rgftab_attiny3216 +extern const Register_file rgftab_attiny424[307]; +#define rgftab_attiny824 rgftab_attiny424 +#define rgftab_attiny1624 rgftab_attiny424 +#define rgftab_attiny3224 rgftab_attiny424 + +extern const Register_file rgftab_attiny426[308]; +#define rgftab_attiny427 rgftab_attiny426 +#define rgftab_attiny826 rgftab_attiny426 +#define rgftab_attiny827 rgftab_attiny426 +#define rgftab_attiny1626 rgftab_attiny426 +#define rgftab_attiny1627 rgftab_attiny426 +#define rgftab_attiny3226 rgftab_attiny426 +#define rgftab_attiny3227 rgftab_attiny426 + extern const Register_file rgftab_atmega808[406]; #define rgftab_atmega1608 rgftab_atmega808 @@ -2914,19 +2906,74 @@ extern const Register_file rgftab_atmega3208[406]; extern const Register_file rgftab_atmega3209[432]; #define rgftab_atmega4809 rgftab_atmega3209 -extern const Register_file rgftab_avr16du14[370]; -#define rgftab_avr32du14 rgftab_avr16du14 +extern const Register_file rgftab_avr32da28[432]; +#define rgftab_avr32da28s rgftab_avr32da28 +#define rgftab_avr64da28 rgftab_avr32da28 +#define rgftab_avr64da28s rgftab_avr32da28 -extern const Register_file rgftab_avr16eb14[390]; -#define rgftab_avr32eb14 rgftab_avr16eb14 +extern const Register_file rgftab_avr32da32[447]; +#define rgftab_avr32da32s rgftab_avr32da32 +#define rgftab_avr64da32 rgftab_avr32da32 +#define rgftab_avr64da32s rgftab_avr32da32 -extern const Register_file rgftab_avr16la14[339]; -#define rgftab_avr32la14 rgftab_avr16la14 +extern const Register_file rgftab_avr32da48[610]; +#define rgftab_avr32da48s rgftab_avr32da48 + +extern const Register_file rgftab_avr64da48[600]; +#define rgftab_avr64da48s rgftab_avr64da48 + +extern const Register_file rgftab_avr64da64[658]; +#define rgftab_avr64da64s rgftab_avr64da64 + +extern const Register_file rgftab_avr128da28[433]; +#define rgftab_avr128da28s rgftab_avr128da28 + +extern const Register_file rgftab_avr128da32[448]; +#define rgftab_avr128da32s rgftab_avr128da32 + +extern const Register_file rgftab_avr128da48[601]; +#define rgftab_avr128da48s rgftab_avr128da48 + +extern const Register_file rgftab_avr128da64[659]; +#define rgftab_avr128da64s rgftab_avr128da64 + +extern const Register_file rgftab_avr32db28[461]; +#define rgftab_avr64db28 rgftab_avr32db28 + +extern const Register_file rgftab_avr32db32[476]; +#define rgftab_avr64db32 rgftab_avr32db32 + +extern const Register_file rgftab_avr32db48[642]; +#define rgftab_avr64db48 rgftab_avr32db48 + +extern const Register_file rgftab_avr64db64[697]; + +extern const Register_file rgftab_avr128db28[462]; + +extern const Register_file rgftab_avr128db32[477]; + +extern const Register_file rgftab_avr128db48[643]; + +extern const Register_file rgftab_avr128db64[698]; + +extern const Register_file rgftab_avr16dd14[390]; +#define rgftab_avr32dd14 rgftab_avr16dd14 +#define rgftab_avr64dd14 rgftab_avr16dd14 extern const Register_file rgftab_avr16dd20[391]; #define rgftab_avr32dd20 rgftab_avr16dd20 #define rgftab_avr64dd20 rgftab_avr16dd20 +extern const Register_file rgftab_avr16dd28[401]; +#define rgftab_avr16dd32 rgftab_avr16dd28 +#define rgftab_avr32dd28 rgftab_avr16dd28 +#define rgftab_avr32dd32 rgftab_avr16dd28 +#define rgftab_avr64dd28 rgftab_avr16dd28 +#define rgftab_avr64dd32 rgftab_avr16dd28 + +extern const Register_file rgftab_avr16du14[370]; +#define rgftab_avr32du14 rgftab_avr16du14 + extern const Register_file rgftab_avr16du20[371]; #define rgftab_avr16du28 rgftab_avr16du20 #define rgftab_avr16du32 rgftab_avr16du20 @@ -2936,6 +2983,20 @@ extern const Register_file rgftab_avr16du20[371]; #define rgftab_avr64du28 rgftab_avr16du20 #define rgftab_avr64du32 rgftab_avr16du20 +extern const Register_file rgftab_avr16ea28[444]; +#define rgftab_avr16ea32 rgftab_avr16ea28 +#define rgftab_avr32ea28 rgftab_avr16ea28 +#define rgftab_avr32ea32 rgftab_avr16ea28 +#define rgftab_avr64ea28 rgftab_avr16ea28 +#define rgftab_avr64ea32 rgftab_avr16ea28 + +extern const Register_file rgftab_avr16ea48[502]; +#define rgftab_avr32ea48 rgftab_avr16ea48 +#define rgftab_avr64ea48 rgftab_avr16ea48 + +extern const Register_file rgftab_avr16eb14[390]; +#define rgftab_avr32eb14 rgftab_avr16eb14 + extern const Register_file rgftab_avr16eb20[391]; #define rgftab_avr16eb28 rgftab_avr16eb20 #define rgftab_avr16eb32 rgftab_avr16eb20 @@ -2943,6 +3004,9 @@ extern const Register_file rgftab_avr16eb20[391]; #define rgftab_avr32eb28 rgftab_avr16eb20 #define rgftab_avr32eb32 rgftab_avr16eb20 +extern const Register_file rgftab_avr16la14[339]; +#define rgftab_avr32la14 rgftab_avr16la14 + extern const Register_file rgftab_avr16la20[341]; #define rgftab_avr16la28 rgftab_avr16la20 #define rgftab_avr16la32 rgftab_avr16la20 @@ -2950,211 +3014,15 @@ extern const Register_file rgftab_avr16la20[341]; #define rgftab_avr32la28 rgftab_avr16la20 #define rgftab_avr32la32 rgftab_avr16la20 -extern const Register_file rgftab_avr16dd28[401]; -#define rgftab_avr16dd32 rgftab_avr16dd28 -#define rgftab_avr32dd28 rgftab_avr16dd28 -#define rgftab_avr32dd32 rgftab_avr16dd28 -#define rgftab_avr64dd28 rgftab_avr16dd28 -#define rgftab_avr64dd32 rgftab_avr16dd28 - -extern const Register_file rgftab_avr16ea28[444]; -#define rgftab_avr16ea32 rgftab_avr16ea28 -#define rgftab_avr32ea28 rgftab_avr16ea28 -#define rgftab_avr32ea32 rgftab_avr16ea28 -#define rgftab_avr64ea28 rgftab_avr16ea28 -#define rgftab_avr64ea32 rgftab_avr16ea28 - extern const Register_file rgftab_avr32sd20[540]; -extern const Register_file rgftab_avr32da28[432]; -#define rgftab_avr32da28s rgftab_avr32da28 -#define rgftab_avr64da28 rgftab_avr32da28 -#define rgftab_avr64da28s rgftab_avr32da28 - -extern const Register_file rgftab_avr32db28[461]; -#define rgftab_avr64db28 rgftab_avr32db28 - extern const Register_file rgftab_avr32sd28[559]; -extern const Register_file rgftab_avr32da32[447]; -#define rgftab_avr32da32s rgftab_avr32da32 -#define rgftab_avr64da32 rgftab_avr32da32 -#define rgftab_avr64da32s rgftab_avr32da32 - -extern const Register_file rgftab_avr32db32[476]; -#define rgftab_avr64db32 rgftab_avr32db32 - extern const Register_file rgftab_avr32sd32[575]; -extern const Register_file rgftab_avr32da48[610]; -#define rgftab_avr32da48s rgftab_avr32da48 - -extern const Register_file rgftab_avr32db48[642]; -#define rgftab_avr64db48 rgftab_avr32db48 - -extern const Register_file rgftab_avr64da48[600]; -#define rgftab_avr64da48s rgftab_avr64da48 - -extern const Register_file rgftab_avr64da64[658]; -#define rgftab_avr64da64s rgftab_avr64da64 - -extern const Register_file rgftab_avr64db64[697]; - -extern const Register_file rgftab_avr128da28[433]; -#define rgftab_avr128da28s rgftab_avr128da28 - -extern const Register_file rgftab_avr128db28[462]; - -extern const Register_file rgftab_avr128da32[448]; -#define rgftab_avr128da32s rgftab_avr128da32 - -extern const Register_file rgftab_avr128db32[477]; - -extern const Register_file rgftab_avr128da48[601]; -#define rgftab_avr128da48s rgftab_avr128da48 - -extern const Register_file rgftab_avr128db48[643]; - -extern const Register_file rgftab_avr128da64[659]; -#define rgftab_avr128da64s rgftab_avr128da64 - -extern const Register_file rgftab_avr128db64[698]; - // Ports -extern const Port_bits ports_atmega328[3]; -#define ports_atmega48 ports_atmega328 -#define ports_atmega48a ports_atmega328 -#define ports_atmega48p ports_atmega328 -#define ports_atmega48pa ports_atmega328 -#define ports_atmega88 ports_atmega328 -#define ports_atmega88a ports_atmega328 -#define ports_atmega88p ports_atmega328 -#define ports_atmega88pa ports_atmega328 -#define ports_atmega168 ports_atmega328 -#define ports_atmega168a ports_atmega328 -#define ports_atmega168p ports_atmega328 -#define ports_atmega168pa ports_atmega328 -#define ports_atmega328p ports_atmega328 -#define ports_ata6612c ports_atmega328 -#define ports_ata6613c ports_atmega328 -#define ports_ata6614q ports_atmega328 - -extern const Port_bits ports_atmega16m1[4]; -#define ports_at90pwm2 ports_atmega16m1 -#define ports_atmega32c1 ports_atmega16m1 -#define ports_atmega32m1 ports_atmega16m1 -#define ports_atmega64c1 ports_atmega16m1 -#define ports_atmegas64m1 ports_atmega16m1 -#define ports_atmega64m1 ports_atmega16m1 -#define ports_at90pwm2b ports_atmega16m1 -#define ports_at90pwm3 ports_atmega16m1 -#define ports_at90pwm3b ports_atmega16m1 -#define ports_at90pwm216 ports_atmega16m1 -#define ports_at90pwm316 ports_atmega16m1 - -extern const Port_bits ports_atmega16hva2[3]; -#define ports_atmega8hva ports_atmega16hva2 -#define ports_atmega16hva ports_atmega16hva2 - -extern const Port_bits ports_atmega32hvbrevb[3]; -#define ports_atmega16hvb ports_atmega32hvbrevb -#define ports_atmega16hvbrevb ports_atmega32hvbrevb -#define ports_atmega32hvb ports_atmega32hvbrevb - -extern const Port_bits ports_atmega64hve[2]; -#define ports_atmega64hve2 ports_atmega64hve - -extern const Port_bits ports_atmega328pb[4]; -#define ports_atmega48pb ports_atmega328pb -#define ports_atmega88pb ports_atmega328pb -#define ports_atmega168pb ports_atmega328pb - -extern const Port_bits ports_atmega8515[5]; -#define ports_atmega161 ports_atmega8515 -#define ports_atmega162 ports_atmega8515 - -extern const Port_bits ports_attiny102[2]; - -extern const Port_bits ports_attiny28[3]; - -extern const Port_bits ports_attiny441[2]; -#define ports_attiny24 ports_attiny441 -#define ports_attiny24a ports_attiny441 -#define ports_attiny44 ports_attiny441 -#define ports_attiny44a ports_attiny441 -#define ports_attiny84 ports_attiny441 -#define ports_attiny84a ports_attiny441 -#define ports_attiny841 ports_attiny441 - -extern const Port_bits ports_at90pwm81[3]; -#define ports_at90pwm1 ports_at90pwm81 -#define ports_at90pwm161 ports_at90pwm81 - -extern const Port_bits ports_at90can128[7]; -#define ports_atmega165 ports_at90can128 -#define ports_at90can32 ports_at90can128 -#define ports_at90can64 ports_at90can128 - -extern const Port_bits ports_at90usb162[3]; -#define ports_atmega8u2 ports_at90usb162 -#define ports_atmega16u2 ports_at90usb162 -#define ports_atmega32u2 ports_at90usb162 -#define ports_at90usb82 ports_at90usb162 - -extern const Port_bits ports_at90s1200[2]; -#define ports_at90s2313 ports_at90s1200 - -extern const Port_bits ports_ata5790[3]; -#define ports_ata5790n ports_ata5790 -#define ports_ata5791 ports_ata5790 - -extern const Port_bits ports_ata6285[3]; -#define ports_ata5702m322 ports_ata6285 -#define ports_ata6286 ports_ata6285 - -extern const Port_bits ports_atxmega16e5[4]; -#define ports_atxmega8e5 ports_atxmega16e5 -#define ports_atxmega32e5 ports_atxmega16e5 - -extern const Port_bits ports_atxmega128a3u[7]; -#define ports_atxmega32c3 ports_atxmega128a3u -#define ports_atxmega32d3 ports_atxmega128a3u -#define ports_atxmega64a3u ports_atxmega128a3u -#define ports_atxmega64c3 ports_atxmega128a3u -#define ports_atxmega64d3 ports_atxmega128a3u -#define ports_atxmega128c3 ports_atxmega128a3u -#define ports_atxmega128d3 ports_atxmega128a3u -#define ports_atxmega192a3u ports_atxmega128a3u -#define ports_atxmega192d3 ports_atxmega128a3u -#define ports_atxmega256a3u ports_atxmega128a3u -#define ports_atxmega256c3 ports_atxmega128a3u -#define ports_atxmega256d3 ports_atxmega128a3u -#define ports_atxmega384c3 ports_atxmega128a3u -#define ports_atxmega384d3 ports_atxmega128a3u - -extern const Port_bits ports_attiny204[2]; -#define ports_attiny1624 ports_attiny204 -#define ports_attiny214 ports_attiny204 -#define ports_attiny404 ports_attiny204 -#define ports_attiny414 ports_attiny204 -#define ports_attiny424 ports_attiny204 -#define ports_attiny804 ports_attiny204 -#define ports_attiny814 ports_attiny204 -#define ports_attiny824 ports_attiny204 -#define ports_attiny1604 ports_attiny204 -#define ports_attiny1614 ports_attiny204 -#define ports_attiny3224 ports_attiny204 - -extern const Port_bits ports_avr32dd14[4]; -#define ports_avr16dd14 ports_avr32dd14 -#define ports_avr64dd14 ports_avr32dd14 - -extern const Port_bits ports_avr64ea48[6]; -#define ports_avr16ea48 ports_avr64ea48 -#define ports_avr32ea48 ports_avr64ea48 - extern const Port_bits ports_attiny4[1]; #define ports_attiny5 ports_attiny4 #define ports_attiny9 ports_attiny4 @@ -3165,6 +3033,67 @@ extern const Port_bits ports_attiny20[2]; extern const Port_bits ports_attiny40[3]; +extern const Port_bits ports_attiny102[2]; + +extern const Port_bits ports_at90s1200[2]; +#define ports_at90s2313 ports_at90s1200 + +extern const Port_bits ports_at90s2323[1]; + +extern const Port_bits ports_at90s2333[3]; +#define ports_at90s4433 ports_at90s2333 + +extern const Port_bits ports_at90s2343[1]; +#define ports_attiny22 ports_at90s2343 + +extern const Port_bits ports_at90s4414[4]; +#define ports_at90s4434 ports_at90s4414 +#define ports_at90s8515 ports_at90s4414 +#define ports_at90s8535 ports_at90s4414 +#define ports_atmega16 ports_at90s4414 +#define ports_atmega16a ports_at90s4414 +#define ports_atmega32 ports_at90s4414 +#define ports_atmega32a ports_at90s4414 +#define ports_atmega163 ports_at90s4414 +#define ports_atmega323 ports_at90s4414 +#define ports_atmega8535 ports_at90s4414 + +extern const Port_bits ports_at90can32[7]; +#define ports_at90can64 ports_at90can32 +#define ports_at90can128 ports_at90can32 +#define ports_atmega165 ports_at90can32 + +extern const Port_bits ports_at90pwm1[3]; +#define ports_at90pwm81 ports_at90pwm1 +#define ports_at90pwm161 ports_at90pwm1 + +extern const Port_bits ports_at90pwm2[4]; +#define ports_at90pwm2b ports_at90pwm2 +#define ports_at90pwm216 ports_at90pwm2 +#define ports_at90pwm3 ports_at90pwm2 +#define ports_at90pwm3b ports_at90pwm2 +#define ports_at90pwm316 ports_at90pwm2 +#define ports_atmega32c1 ports_at90pwm2 +#define ports_atmega64c1 ports_at90pwm2 +#define ports_atmega16m1 ports_at90pwm2 +#define ports_atmega32m1 ports_at90pwm2 +#define ports_atmega64m1 ports_at90pwm2 +#define ports_atmegas64m1 ports_at90pwm2 + +extern const Port_bits ports_at90usb82[3]; +#define ports_at90usb162 ports_at90usb82 +#define ports_atmega8u2 ports_at90usb82 +#define ports_atmega16u2 ports_at90usb82 +#define ports_atmega32u2 ports_at90usb82 + +extern const Port_bits ports_at90usb646[6]; +#define ports_at90usb1286 ports_at90usb646 +#define ports_at90usb647 ports_at90usb646 +#define ports_at90usb1287 ports_at90usb646 +#define ports_atmega32u6 ports_at90usb646 + +extern const Port_bits ports_at90scr100[5]; + extern const Port_bits ports_attiny11[1]; #define ports_attiny12 ports_attiny11 #define ports_attiny15 ports_attiny11 @@ -3175,20 +3104,23 @@ extern const Port_bits ports_attiny13[1]; #define ports_attiny45 ports_attiny13 #define ports_attiny85 ports_attiny13 -extern const Port_bits ports_attiny22[1]; -#define ports_at90s2343 ports_attiny22 +extern const Port_bits ports_attiny43u[2]; +#define ports_attiny26 ports_attiny43u +#define ports_attiny261 ports_attiny43u +#define ports_attiny261a ports_attiny43u +#define ports_attiny461 ports_attiny43u +#define ports_attiny461a ports_attiny43u +#define ports_attiny861 ports_attiny43u +#define ports_attiny861a ports_attiny43u -extern const Port_bits ports_attiny26[2]; -#define ports_attiny43u ports_attiny26 -#define ports_attiny261 ports_attiny26 -#define ports_attiny261a ports_attiny26 -#define ports_attiny461 ports_attiny26 -#define ports_attiny461a ports_attiny26 -#define ports_attiny861 ports_attiny26 -#define ports_attiny861a ports_attiny26 - -extern const Port_bits ports_attiny48[4]; -#define ports_attiny88 ports_attiny48 +extern const Port_bits ports_attiny24[2]; +#define ports_attiny24a ports_attiny24 +#define ports_attiny44 ports_attiny24 +#define ports_attiny44a ports_attiny24 +#define ports_attiny84 ports_attiny24 +#define ports_attiny84a ports_attiny24 +#define ports_attiny441 ports_attiny24 +#define ports_attiny841 ports_attiny24 extern const Port_bits ports_attiny87[2]; #define ports_attiny167 ports_attiny87 @@ -3198,6 +3130,11 @@ extern const Port_bits ports_attiny87[2]; #define ports_ata6617c ports_attiny87 #define ports_ata664251 ports_attiny87 +extern const Port_bits ports_attiny28[3]; + +extern const Port_bits ports_attiny48[4]; +#define ports_attiny88 ports_attiny48 + extern const Port_bits ports_attiny828[4]; extern const Port_bits ports_attiny1634[3]; @@ -3209,45 +3146,33 @@ extern const Port_bits ports_attiny2313[3]; extern const Port_bits ports_atmega8[3]; #define ports_atmega8a ports_atmega8 -extern const Port_bits ports_atmega16[4]; -#define ports_atmega16a ports_atmega16 -#define ports_atmega32 ports_atmega16 -#define ports_atmega32a ports_atmega16 -#define ports_atmega163 ports_atmega16 -#define ports_atmega323 ports_atmega16 -#define ports_atmega8535 ports_atmega16 -#define ports_at90s4414 ports_atmega16 -#define ports_at90s4434 ports_atmega16 -#define ports_at90s8515 ports_atmega16 -#define ports_at90s8535 ports_atmega16 +extern const Port_bits ports_atmega64[7]; +#define ports_atmega64a ports_atmega64 +#define ports_atmega128 ports_atmega64 +#define ports_atmega128a ports_atmega64 +#define ports_atmegas128 ports_atmega64 + +extern const Port_bits ports_atmega640[11]; +#define ports_atmega1280 ports_atmega640 +#define ports_atmega2560 ports_atmega640 + +extern const Port_bits ports_atmega128rfa1[7]; +#define ports_atmega64rfr2 ports_atmega128rfa1 +#define ports_atmega128rfr2 ports_atmega128rfa1 +#define ports_atmega256rfr2 ports_atmega128rfa1 +#define ports_atmega1281 ports_atmega128rfa1 +#define ports_atmega2561 ports_atmega128rfa1 +#define ports_atmega644rfr2 ports_atmega128rfa1 +#define ports_atmega1284rfr2 ports_atmega128rfa1 +#define ports_atmega2564rfr2 ports_atmega128rfa1 +#define ports_atmega169pa ports_atmega128rfa1 extern const Port_bits ports_atmega16u4[5]; #define ports_atmega32u4 ports_atmega16u4 -extern const Port_bits ports_atmega32u6[6]; -#define ports_at90usb646 ports_atmega32u6 -#define ports_at90usb647 ports_atmega32u6 -#define ports_at90usb1286 ports_atmega32u6 -#define ports_at90usb1287 ports_atmega32u6 - -extern const Port_bits ports_atmega64[7]; -#define ports_atmega64a ports_atmega64 -#define ports_atmega128 ports_atmega64 -#define ports_atmegas128 ports_atmega64 -#define ports_atmega128a ports_atmega64 - -extern const Port_bits ports_atmega64rfr2[7]; -#define ports_atmega128rfa1 ports_atmega64rfr2 -#define ports_atmega128rfr2 ports_atmega64rfr2 -#define ports_atmega169pa ports_atmega64rfr2 -#define ports_atmega256rfr2 ports_atmega64rfr2 -#define ports_atmega644rfr2 ports_atmega64rfr2 -#define ports_atmega1281 ports_atmega64rfr2 -#define ports_atmega1284rfr2 ports_atmega64rfr2 -#define ports_atmega2561 ports_atmega64rfr2 -#define ports_atmega2564rfr2 ports_atmega64rfr2 - -extern const Port_bits ports_atmega103[6]; +extern const Port_bits ports_atmega161[5]; +#define ports_atmega162 ports_atmega161 +#define ports_atmega8515 ports_atmega161 extern const Port_bits ports_atmega164a[4]; #define ports_atmega164p ports_atmega164a @@ -3262,116 +3187,183 @@ extern const Port_bits ports_atmega164a[4]; #define ports_atmega1284 ports_atmega164a #define ports_atmega1284p ports_atmega164a +extern const Port_bits ports_atmega324pb[5]; + extern const Port_bits ports_atmega165a[7]; #define ports_atmega165p ports_atmega165a #define ports_atmega165pa ports_atmega165a -#define ports_atmega169 ports_atmega165a -#define ports_atmega169a ports_atmega165a -#define ports_atmega169p ports_atmega165a #define ports_atmega325 ports_atmega165a #define ports_atmega325a ports_atmega165a #define ports_atmega325p ports_atmega165a #define ports_atmega325pa ports_atmega165a +#define ports_atmega645 ports_atmega165a +#define ports_atmega645a ports_atmega165a +#define ports_atmega645p ports_atmega165a +#define ports_atmega169 ports_atmega165a +#define ports_atmega169a ports_atmega165a +#define ports_atmega169p ports_atmega165a #define ports_atmega329 ports_atmega165a #define ports_atmega329a ports_atmega165a #define ports_atmega329p ports_atmega165a #define ports_atmega329pa ports_atmega165a -#define ports_atmega645 ports_atmega165a -#define ports_atmega645a ports_atmega165a -#define ports_atmega645p ports_atmega165a #define ports_atmega649 ports_atmega165a #define ports_atmega649a ports_atmega165a #define ports_atmega649p ports_atmega165a -extern const Port_bits ports_atmega324pb[5]; - -extern const Port_bits ports_atmega406[4]; - -extern const Port_bits ports_atmega640[11]; -#define ports_atmega1280 ports_atmega640 -#define ports_atmega2560 ports_atmega640 - extern const Port_bits ports_atmega3250[9]; #define ports_atmega3250a ports_atmega3250 #define ports_atmega3250p ports_atmega3250 #define ports_atmega3250pa ports_atmega3250 +#define ports_atmega6450 ports_atmega3250 +#define ports_atmega6450a ports_atmega3250 +#define ports_atmega6450p ports_atmega3250 #define ports_atmega3290 ports_atmega3250 #define ports_atmega3290a ports_atmega3250 #define ports_atmega3290p ports_atmega3250 #define ports_atmega3290pa ports_atmega3250 -#define ports_atmega6450 ports_atmega3250 -#define ports_atmega6450a ports_atmega3250 -#define ports_atmega6450p ports_atmega3250 #define ports_atmega6490 ports_atmega3250 #define ports_atmega6490a ports_atmega3250 #define ports_atmega6490p ports_atmega3250 -extern const Port_bits ports_at90scr100[5]; +extern const Port_bits ports_atmega48[3]; +#define ports_atmega48a ports_atmega48 +#define ports_atmega48p ports_atmega48 +#define ports_atmega48pa ports_atmega48 +#define ports_atmega88 ports_atmega48 +#define ports_atmega88a ports_atmega48 +#define ports_atmega88p ports_atmega48 +#define ports_atmega88pa ports_atmega48 +#define ports_atmega168 ports_atmega48 +#define ports_atmega168a ports_atmega48 +#define ports_atmega168p ports_atmega48 +#define ports_atmega168pa ports_atmega48 +#define ports_atmega328 ports_atmega48 +#define ports_atmega328p ports_atmega48 +#define ports_ata6612c ports_atmega48 +#define ports_ata6613c ports_atmega48 +#define ports_ata6614q ports_atmega48 -extern const Port_bits ports_at90s2323[1]; +extern const Port_bits ports_atmega48pb[4]; +#define ports_atmega88pb ports_atmega48pb +#define ports_atmega168pb ports_atmega48pb +#define ports_atmega328pb ports_atmega48pb -extern const Port_bits ports_at90s2333[3]; -#define ports_at90s4433 ports_at90s2333 +extern const Port_bits ports_atmega103[6]; + +extern const Port_bits ports_atmega8hva[3]; +#define ports_atmega16hva ports_atmega8hva +#define ports_atmega16hva2 ports_atmega8hva + +extern const Port_bits ports_atmega16hvb[3]; +#define ports_atmega16hvbrevb ports_atmega16hvb +#define ports_atmega32hvb ports_atmega16hvb +#define ports_atmega32hvbrevb ports_atmega16hvb + +extern const Port_bits ports_atmega64hve[2]; +#define ports_atmega64hve2 ports_atmega64hve + +extern const Port_bits ports_atmega406[4]; + +extern const Port_bits ports_ata5702m322[3]; +#define ports_ata6285 ports_ata5702m322 +#define ports_ata6286 ports_ata5702m322 extern const Port_bits ports_ata5782[2]; #define ports_ata5831 ports_ata5782 #define ports_ata8210 ports_ata5782 #define ports_ata8510 ports_ata5782 +extern const Port_bits ports_ata5790[3]; +#define ports_ata5790n ports_ata5790 +#define ports_ata5791 ports_ata5790 + extern const Port_bits ports_ata5795[3]; extern const Port_bits ports_ata6289[3]; -extern const Port_bits ports_atxmega16a4u[6]; -#define ports_atxmega16c4 ports_atxmega16a4u -#define ports_atxmega16d4 ports_atxmega16a4u -#define ports_atxmega32a4u ports_atxmega16a4u -#define ports_atxmega32c4 ports_atxmega16a4u -#define ports_atxmega32d4 ports_atxmega16a4u -#define ports_atxmega64a4u ports_atxmega16a4u -#define ports_atxmega64d4 ports_atxmega16a4u -#define ports_atxmega128a4u ports_atxmega16a4u -#define ports_atxmega128d4 ports_atxmega16a4u - extern const Port_bits ports_atxmega64a1u[11]; #define ports_atxmega128a1u ports_atxmega64a1u +extern const Port_bits ports_atxmega64a3u[7]; +#define ports_atxmega128a3u ports_atxmega64a3u +#define ports_atxmega192a3u ports_atxmega64a3u +#define ports_atxmega256a3u ports_atxmega64a3u +#define ports_atxmega32c3 ports_atxmega64a3u +#define ports_atxmega64c3 ports_atxmega64a3u +#define ports_atxmega128c3 ports_atxmega64a3u +#define ports_atxmega256c3 ports_atxmega64a3u +#define ports_atxmega384c3 ports_atxmega64a3u +#define ports_atxmega32d3 ports_atxmega64a3u +#define ports_atxmega64d3 ports_atxmega64a3u +#define ports_atxmega128d3 ports_atxmega64a3u +#define ports_atxmega192d3 ports_atxmega64a3u +#define ports_atxmega256d3 ports_atxmega64a3u +#define ports_atxmega384d3 ports_atxmega64a3u + +extern const Port_bits ports_atxmega256a3bu[7]; + +extern const Port_bits ports_atxmega16a4u[6]; +#define ports_atxmega32a4u ports_atxmega16a4u +#define ports_atxmega64a4u ports_atxmega16a4u +#define ports_atxmega128a4u ports_atxmega16a4u +#define ports_atxmega16c4 ports_atxmega16a4u +#define ports_atxmega32c4 ports_atxmega16a4u +#define ports_atxmega16d4 ports_atxmega16a4u +#define ports_atxmega32d4 ports_atxmega16a4u +#define ports_atxmega64d4 ports_atxmega16a4u +#define ports_atxmega128d4 ports_atxmega16a4u + extern const Port_bits ports_atxmega64b1[8]; #define ports_atxmega128b1 ports_atxmega64b1 extern const Port_bits ports_atxmega64b3[6]; #define ports_atxmega128b3 ports_atxmega64b3 -extern const Port_bits ports_atxmega256a3bu[7]; +extern const Port_bits ports_atxmega8e5[4]; +#define ports_atxmega16e5 ports_atxmega8e5 +#define ports_atxmega32e5 ports_atxmega8e5 extern const Port_bits ports_attiny202[1]; -#define ports_attiny212 ports_attiny202 #define ports_attiny402 ports_attiny202 +#define ports_attiny212 ports_attiny202 #define ports_attiny412 ports_attiny202 +extern const Port_bits ports_attiny204[2]; +#define ports_attiny404 ports_attiny204 +#define ports_attiny804 ports_attiny204 +#define ports_attiny1604 ports_attiny204 +#define ports_attiny214 ports_attiny204 +#define ports_attiny414 ports_attiny204 +#define ports_attiny814 ports_attiny204 +#define ports_attiny1614 ports_attiny204 +#define ports_attiny424 ports_attiny204 +#define ports_attiny824 ports_attiny204 +#define ports_attiny1624 ports_attiny204 +#define ports_attiny3224 ports_attiny204 + extern const Port_bits ports_attiny406[3]; +#define ports_attiny806 ports_attiny406 +#define ports_attiny1606 ports_attiny406 #define ports_attiny416 ports_attiny406 #define ports_attiny416auto ports_attiny406 -#define ports_attiny426 ports_attiny406 -#define ports_attiny806 ports_attiny406 #define ports_attiny816 ports_attiny406 -#define ports_attiny826 ports_attiny406 -#define ports_attiny1606 ports_attiny406 #define ports_attiny1616 ports_attiny406 -#define ports_attiny1626 ports_attiny406 #define ports_attiny3216 ports_attiny406 +#define ports_attiny426 ports_attiny406 +#define ports_attiny826 ports_attiny406 +#define ports_attiny1626 ports_attiny406 #define ports_attiny3226 ports_attiny406 -extern const Port_bits ports_attiny417[3]; -#define ports_attiny427 ports_attiny417 -#define ports_attiny807 ports_attiny417 -#define ports_attiny817 ports_attiny417 -#define ports_attiny827 ports_attiny417 -#define ports_attiny1607 ports_attiny417 -#define ports_attiny1617 ports_attiny417 -#define ports_attiny1627 ports_attiny417 -#define ports_attiny3217 ports_attiny417 -#define ports_attiny3227 ports_attiny417 +extern const Port_bits ports_attiny807[3]; +#define ports_attiny1607 ports_attiny807 +#define ports_attiny417 ports_attiny807 +#define ports_attiny817 ports_attiny807 +#define ports_attiny1617 ports_attiny807 +#define ports_attiny3217 ports_attiny807 +#define ports_attiny427 ports_attiny807 +#define ports_attiny827 ports_attiny807 +#define ports_attiny1627 ports_attiny807 +#define ports_attiny3227 ports_attiny807 extern const Port_bits ports_atmega808[4]; #define ports_atmega1608 ports_atmega808 @@ -3390,69 +3382,14 @@ extern const Port_bits ports_atmega809[6]; #define ports_atmega4809 ports_atmega809 #define ports_avr32da48 ports_atmega809 #define ports_avr32da48s ports_atmega809 -#define ports_avr32db48 ports_atmega809 #define ports_avr64da48 ports_atmega809 #define ports_avr64da48s ports_atmega809 -#define ports_avr64db48 ports_atmega809 #define ports_avr128da48 ports_atmega809 #define ports_avr128da48s ports_atmega809 +#define ports_avr32db48 ports_atmega809 +#define ports_avr64db48 ports_atmega809 #define ports_avr128db48 ports_atmega809 -extern const Port_bits ports_avr16du14[4]; -#define ports_avr32du14 ports_avr16du14 - -extern const Port_bits ports_avr16eb14[4]; -#define ports_avr16la14 ports_avr16eb14 -#define ports_avr32eb14 ports_avr16eb14 -#define ports_avr32la14 ports_avr16eb14 - -extern const Port_bits ports_avr16dd20[4]; -#define ports_avr32dd20 ports_avr16dd20 -#define ports_avr32sd20 ports_avr16dd20 -#define ports_avr64dd20 ports_avr16dd20 - -extern const Port_bits ports_avr16du20[4]; -#define ports_avr32du20 ports_avr16du20 - -extern const Port_bits ports_avr16eb20[4]; -#define ports_avr16la20 ports_avr16eb20 -#define ports_avr32eb20 ports_avr16eb20 -#define ports_avr32la20 ports_avr16eb20 - -extern const Port_bits ports_avr16dd28[4]; -#define ports_avr32dd28 ports_avr16dd28 -#define ports_avr32sd28 ports_avr16dd28 -#define ports_avr64dd28 ports_avr16dd28 - -extern const Port_bits ports_avr16du28[4]; -#define ports_avr32du28 ports_avr16du28 -#define ports_avr64du28 ports_avr16du28 - -extern const Port_bits ports_avr16ea28[4]; -#define ports_avr16eb28 ports_avr16ea28 -#define ports_avr16la28 ports_avr16ea28 -#define ports_avr32ea28 ports_avr16ea28 -#define ports_avr32eb28 ports_avr16ea28 -#define ports_avr32la28 ports_avr16ea28 -#define ports_avr64ea28 ports_avr16ea28 - -extern const Port_bits ports_avr16dd32[4]; -#define ports_avr32dd32 ports_avr16dd32 -#define ports_avr32sd32 ports_avr16dd32 -#define ports_avr64dd32 ports_avr16dd32 - -extern const Port_bits ports_avr16du32[4]; -#define ports_avr32du32 ports_avr16du32 -#define ports_avr64du32 ports_avr16du32 - -extern const Port_bits ports_avr16ea32[4]; -#define ports_avr16eb32 ports_avr16ea32 -#define ports_avr16la32 ports_avr16ea32 -#define ports_avr32ea32 ports_avr16ea32 -#define ports_avr32eb32 ports_avr16ea32 -#define ports_avr32la32 ports_avr16ea32 -#define ports_avr64ea32 ports_avr16ea32 - extern const Port_bits ports_avr32da28[4]; #define ports_avr32da28s ports_avr32da28 #define ports_avr64da28 ports_avr32da28 @@ -3460,6 +3397,13 @@ extern const Port_bits ports_avr32da28[4]; #define ports_avr128da28 ports_avr32da28 #define ports_avr128da28s ports_avr32da28 +extern const Port_bits ports_avr64da64[7]; +#define ports_avr64da64s ports_avr64da64 +#define ports_avr128da64 ports_avr64da64 +#define ports_avr128da64s ports_avr64da64 +#define ports_avr64db64 ports_avr64da64 +#define ports_avr128db64 ports_avr64da64 + extern const Port_bits ports_avr32db28[4]; #define ports_avr64db28 ports_avr32db28 #define ports_avr128db28 ports_avr32db28 @@ -3468,167 +3412,117 @@ extern const Port_bits ports_avr32db32[4]; #define ports_avr64db32 ports_avr32db32 #define ports_avr128db32 ports_avr32db32 -extern const Port_bits ports_avr64da64[7]; -#define ports_avr64da64s ports_avr64da64 -#define ports_avr64db64 ports_avr64da64 -#define ports_avr128da64 ports_avr64da64 -#define ports_avr128da64s ports_avr64da64 -#define ports_avr128db64 ports_avr64da64 +extern const Port_bits ports_avr16dd14[4]; +#define ports_avr32dd14 ports_avr16dd14 +#define ports_avr64dd14 ports_avr16dd14 + +extern const Port_bits ports_avr16dd20[4]; +#define ports_avr32dd20 ports_avr16dd20 +#define ports_avr64dd20 ports_avr16dd20 +#define ports_avr32sd20 ports_avr16dd20 + +extern const Port_bits ports_avr16dd28[4]; +#define ports_avr32dd28 ports_avr16dd28 +#define ports_avr64dd28 ports_avr16dd28 +#define ports_avr32sd28 ports_avr16dd28 + +extern const Port_bits ports_avr16dd32[4]; +#define ports_avr32dd32 ports_avr16dd32 +#define ports_avr64dd32 ports_avr16dd32 +#define ports_avr32sd32 ports_avr16dd32 + +extern const Port_bits ports_avr16du14[4]; +#define ports_avr32du14 ports_avr16du14 + +extern const Port_bits ports_avr16du20[4]; +#define ports_avr32du20 ports_avr16du20 + +extern const Port_bits ports_avr16du28[4]; +#define ports_avr32du28 ports_avr16du28 +#define ports_avr64du28 ports_avr16du28 + +extern const Port_bits ports_avr16du32[4]; +#define ports_avr32du32 ports_avr16du32 +#define ports_avr64du32 ports_avr16du32 + +extern const Port_bits ports_avr16ea28[4]; +#define ports_avr32ea28 ports_avr16ea28 +#define ports_avr64ea28 ports_avr16ea28 +#define ports_avr16eb28 ports_avr16ea28 +#define ports_avr32eb28 ports_avr16ea28 +#define ports_avr16la28 ports_avr16ea28 +#define ports_avr32la28 ports_avr16ea28 + +extern const Port_bits ports_avr16ea32[4]; +#define ports_avr32ea32 ports_avr16ea32 +#define ports_avr64ea32 ports_avr16ea32 +#define ports_avr16eb32 ports_avr16ea32 +#define ports_avr32eb32 ports_avr16ea32 +#define ports_avr16la32 ports_avr16ea32 +#define ports_avr32la32 ports_avr16ea32 + +extern const Port_bits ports_avr16ea48[6]; +#define ports_avr32ea48 ports_avr16ea48 +#define ports_avr64ea48 ports_avr16ea48 + +extern const Port_bits ports_avr16eb14[4]; +#define ports_avr32eb14 ports_avr16eb14 +#define ports_avr16la14 ports_avr16eb14 +#define ports_avr32la14 ports_avr16eb14 + +extern const Port_bits ports_avr16eb20[4]; +#define ports_avr32eb20 ports_avr16eb20 +#define ports_avr16la20 ports_avr16eb20 +#define ports_avr32la20 ports_avr16eb20 // UART configurations -extern const Uart_conf uarts_atmega8[1]; -#define uarts_atmega8a uarts_atmega8 -#define uarts_atmega48 uarts_atmega8 -#define uarts_atmega48a uarts_atmega8 -#define uarts_atmega48p uarts_atmega8 -#define uarts_atmega48pa uarts_atmega8 -#define uarts_atmega48pb uarts_atmega8 -#define uarts_atmega88 uarts_atmega8 -#define uarts_atmega88a uarts_atmega8 -#define uarts_atmega88p uarts_atmega8 -#define uarts_atmega88pa uarts_atmega8 -#define uarts_atmega88pb uarts_atmega8 -#define uarts_atmega168 uarts_atmega8 -#define uarts_atmega168a uarts_atmega8 -#define uarts_atmega168p uarts_atmega8 -#define uarts_atmega168pa uarts_atmega8 -#define uarts_atmega168pb uarts_atmega8 -#define uarts_atmega328 uarts_atmega8 -#define uarts_atmega328p uarts_atmega8 -#define uarts_ata6612c uarts_atmega8 -#define uarts_ata6613c uarts_atmega8 -#define uarts_ata6614q uarts_atmega8 -#define uarts_lgt8f88p uarts_atmega8 -#define uarts_lgt8f168p uarts_atmega8 -#define uarts_lgt8f328p uarts_atmega8 - -extern const Uart_conf uarts_atmega16m1[1]; -#define uarts_atmega32c1 uarts_atmega16m1 -#define uarts_atmega32m1 uarts_atmega16m1 -#define uarts_atmega64c1 uarts_atmega16m1 -#define uarts_atmegas64m1 uarts_atmega16m1 -#define uarts_atmega64m1 uarts_atmega16m1 - -extern const Uart_conf uarts_atmega64hve[1]; -#define uarts_atmega64hve2 uarts_atmega64hve - -extern const Uart_conf uarts_atmega328pb[2]; - -extern const Uart_conf uarts_attiny2313[1]; -#define uarts_attiny2313a uarts_attiny2313 -#define uarts_attiny4313 uarts_attiny2313 -#define uarts_atmega163 uarts_attiny2313 -#define uarts_atmega323 uarts_attiny2313 -#define uarts_atmega8515 uarts_attiny2313 -#define uarts_atmega8535 uarts_attiny2313 -#define uarts_at90scr100 uarts_attiny2313 -#define uarts_at90scr100h uarts_attiny2313 -#define uarts_at90s2313 uarts_attiny2313 -#define uarts_at90s2333 uarts_attiny2313 -#define uarts_at90s4414 uarts_attiny2313 -#define uarts_at90s4433 uarts_attiny2313 -#define uarts_at90s4434 uarts_attiny2313 -#define uarts_at90s8515 uarts_attiny2313 -#define uarts_at90s8535 uarts_attiny2313 - extern const Uart_conf uarts_attiny102[1]; #define uarts_attiny104 uarts_attiny102 -extern const Uart_conf uarts_attiny441[3]; -#define uarts_attiny841 uarts_attiny441 +extern const Uart_conf uarts_at90s2313[1]; +#define uarts_at90s2333 uarts_at90s2313 +#define uarts_at90s4414 uarts_at90s2313 +#define uarts_at90s4433 uarts_at90s2313 +#define uarts_at90s4434 uarts_at90s2313 +#define uarts_at90s8515 uarts_at90s2313 +#define uarts_at90s8535 uarts_at90s2313 +#define uarts_at90scr100 uarts_at90s2313 +#define uarts_at90scr100h uarts_at90s2313 +#define uarts_attiny2313 uarts_at90s2313 +#define uarts_attiny2313a uarts_at90s2313 +#define uarts_attiny4313 uarts_at90s2313 +#define uarts_atmega163 uarts_at90s2313 +#define uarts_atmega323 uarts_at90s2313 +#define uarts_atmega8515 uarts_at90s2313 +#define uarts_atmega8535 uarts_at90s2313 + +extern const Uart_conf uarts_at90can32[2]; +#define uarts_at90can64 uarts_at90can32 +#define uarts_at90can128 uarts_at90can32 +#define uarts_atmega64 uarts_at90can32 +#define uarts_atmega64a uarts_at90can32 +#define uarts_atmega128 uarts_at90can32 +#define uarts_atmega128a uarts_at90can32 +#define uarts_atmegas128 uarts_at90can32 +#define uarts_atmega1281 uarts_at90can32 +#define uarts_atmega2561 uarts_at90can32 extern const Uart_conf uarts_at90pwm2[1]; #define uarts_at90pwm2b uarts_at90pwm2 +#define uarts_at90pwm216 uarts_at90pwm2 #define uarts_at90pwm3 uarts_at90pwm2 #define uarts_at90pwm3b uarts_at90pwm2 -#define uarts_at90pwm216 uarts_at90pwm2 #define uarts_at90pwm316 uarts_at90pwm2 -extern const Uart_conf uarts_atmega64[2]; -#define uarts_atmega64a uarts_atmega64 -#define uarts_atmega128 uarts_atmega64 -#define uarts_atmegas128 uarts_atmega64 -#define uarts_atmega128a uarts_atmega64 -#define uarts_atmega1281 uarts_atmega64 -#define uarts_atmega2561 uarts_atmega64 -#define uarts_at90can32 uarts_atmega64 -#define uarts_at90can64 uarts_atmega64 -#define uarts_at90can128 uarts_atmega64 - -extern const Uart_conf uarts_atmega32u6[1]; -#define uarts_at90usb82 uarts_atmega32u6 -#define uarts_at90usb162 uarts_atmega32u6 -#define uarts_at90usb646 uarts_atmega32u6 -#define uarts_at90usb647 uarts_atmega32u6 -#define uarts_at90usb1286 uarts_atmega32u6 -#define uarts_at90usb1287 uarts_atmega32u6 - -extern const Uart_conf uarts_atxmega8e5[4]; -#define uarts_atxmega16e5 uarts_atxmega8e5 -#define uarts_atxmega32e5 uarts_atxmega8e5 - -extern const Uart_conf uarts_atxmega64a1[8]; -#define uarts_atxmega128a1 uarts_atxmega64a1 -#define uarts_atxmega128a1revd uarts_atxmega64a1 -#define uarts_atxmega192a1 uarts_atxmega64a1 -#define uarts_atxmega256a1 uarts_atxmega64a1 - -extern const Uart_conf uarts_atxmega64a3[7]; -#define uarts_atxmega128a3 uarts_atxmega64a3 -#define uarts_atxmega192a3 uarts_atxmega64a3 -#define uarts_atxmega256a3 uarts_atxmega64a3 - -extern const Uart_conf uarts_atxmega64a3u[11]; -#define uarts_atxmega128a3u uarts_atxmega64a3u -#define uarts_atxmega192a3u uarts_atxmega64a3u -#define uarts_atxmega256a3u uarts_atxmega64a3u - -extern const Uart_conf uarts_atxmega16a4[7]; -#define uarts_atxmega16a4u uarts_atxmega16a4 -#define uarts_atxmega32a4 uarts_atxmega16a4 -#define uarts_atxmega32a4u uarts_atxmega16a4 -#define uarts_atxmega64a4 uarts_atxmega16a4 -#define uarts_atxmega64a4u uarts_atxmega16a4 -#define uarts_atxmega128a4 uarts_atxmega16a4 -#define uarts_atxmega128a4u uarts_atxmega16a4 - -extern const Uart_conf uarts_attiny204[2]; -#define uarts_attiny214 uarts_attiny204 -#define uarts_attiny404 uarts_attiny204 -#define uarts_attiny406 uarts_attiny204 -#define uarts_attiny414 uarts_attiny204 -#define uarts_attiny416 uarts_attiny204 -#define uarts_attiny416auto uarts_attiny204 -#define uarts_attiny417 uarts_attiny204 -#define uarts_attiny804 uarts_attiny204 -#define uarts_attiny806 uarts_attiny204 -#define uarts_attiny807 uarts_attiny204 -#define uarts_attiny814 uarts_attiny204 -#define uarts_attiny816 uarts_attiny204 -#define uarts_attiny817 uarts_attiny204 -#define uarts_attiny1604 uarts_attiny204 -#define uarts_attiny1606 uarts_attiny204 -#define uarts_attiny1607 uarts_attiny204 -#define uarts_attiny1614 uarts_attiny204 -#define uarts_attiny1616 uarts_attiny204 -#define uarts_attiny1617 uarts_attiny204 -#define uarts_attiny3216 uarts_attiny204 -#define uarts_attiny3217 uarts_attiny204 - -extern const Uart_conf uarts_attiny424[3]; -#define uarts_attiny824 uarts_attiny424 -#define uarts_attiny1624 uarts_attiny424 -#define uarts_attiny3224 uarts_attiny424 - -extern const Uart_conf uarts_avr16dd14[5]; -#define uarts_avr32dd14 uarts_avr16dd14 -#define uarts_avr64dd14 uarts_avr16dd14 - -extern const Uart_conf uarts_avr16ea48[10]; -#define uarts_avr32ea48 uarts_avr16ea48 -#define uarts_avr64ea48 uarts_avr16ea48 +extern const Uart_conf uarts_at90usb82[1]; +#define uarts_at90usb162 uarts_at90usb82 +#define uarts_at90usb646 uarts_at90usb82 +#define uarts_at90usb1286 uarts_at90usb82 +#define uarts_at90usb647 uarts_at90usb82 +#define uarts_at90usb1287 uarts_at90usb82 +#define uarts_atmega32u6 uarts_at90usb82 extern const Uart_conf uarts_attiny87[1]; #define uarts_attiny167 uarts_attiny87 @@ -3643,9 +3537,34 @@ extern const Uart_conf uarts_attiny828[1]; extern const Uart_conf uarts_attiny1634[2]; #define uarts_attiny1634r uarts_attiny1634 -extern const Uart_conf uarts_atmega8u2[1]; -#define uarts_atmega16u2 uarts_atmega8u2 -#define uarts_atmega32u2 uarts_atmega8u2 +extern const Uart_conf uarts_attiny441[3]; +#define uarts_attiny841 uarts_attiny441 + +extern const Uart_conf uarts_atmega8[1]; +#define uarts_atmega8a uarts_atmega8 +#define uarts_atmega48 uarts_atmega8 +#define uarts_atmega48a uarts_atmega8 +#define uarts_atmega48p uarts_atmega8 +#define uarts_atmega48pa uarts_atmega8 +#define uarts_atmega88 uarts_atmega8 +#define uarts_atmega88a uarts_atmega8 +#define uarts_atmega88p uarts_atmega8 +#define uarts_atmega88pa uarts_atmega8 +#define uarts_atmega168 uarts_atmega8 +#define uarts_atmega168a uarts_atmega8 +#define uarts_atmega168p uarts_atmega8 +#define uarts_atmega168pa uarts_atmega8 +#define uarts_atmega328 uarts_atmega8 +#define uarts_atmega328p uarts_atmega8 +#define uarts_atmega48pb uarts_atmega8 +#define uarts_atmega88pb uarts_atmega8 +#define uarts_atmega168pb uarts_atmega8 +#define uarts_lgt8f88p uarts_atmega8 +#define uarts_lgt8f168p uarts_atmega8 +#define uarts_lgt8f328p uarts_atmega8 +#define uarts_ata6612c uarts_atmega8 +#define uarts_ata6613c uarts_atmega8 +#define uarts_ata6614q uarts_atmega8 extern const Uart_conf uarts_atmega16[1]; #define uarts_atmega16a uarts_atmega16 @@ -3653,45 +3572,32 @@ extern const Uart_conf uarts_atmega16[1]; #define uarts_atmega32a uarts_atmega16 #define uarts_atmega644 uarts_atmega16 +extern const Uart_conf uarts_atmega640[4]; +#define uarts_atmega1280 uarts_atmega640 +#define uarts_atmega2560 uarts_atmega640 + +extern const Uart_conf uarts_atmega32c1[1]; +#define uarts_atmega64c1 uarts_atmega32c1 +#define uarts_atmega16m1 uarts_atmega32c1 +#define uarts_atmega32m1 uarts_atmega32c1 +#define uarts_atmega64m1 uarts_atmega32c1 +#define uarts_atmegas64m1 uarts_atmega32c1 + +extern const Uart_conf uarts_atmega128rfa1[2]; +#define uarts_atmega64rfr2 uarts_atmega128rfa1 +#define uarts_atmega128rfr2 uarts_atmega128rfa1 +#define uarts_atmega256rfr2 uarts_atmega128rfa1 +#define uarts_atmega644rfr2 uarts_atmega128rfa1 +#define uarts_atmega1284rfr2 uarts_atmega128rfa1 +#define uarts_atmega2564rfr2 uarts_atmega128rfa1 + +extern const Uart_conf uarts_atmega8u2[1]; +#define uarts_atmega16u2 uarts_atmega8u2 +#define uarts_atmega32u2 uarts_atmega8u2 + extern const Uart_conf uarts_atmega16u4[1]; #define uarts_atmega32u4 uarts_atmega16u4 -extern const Uart_conf uarts_atmega64rfr2[2]; -#define uarts_atmega128rfa1 uarts_atmega64rfr2 -#define uarts_atmega128rfr2 uarts_atmega64rfr2 -#define uarts_atmega256rfr2 uarts_atmega64rfr2 -#define uarts_atmega644rfr2 uarts_atmega64rfr2 -#define uarts_atmega1284rfr2 uarts_atmega64rfr2 -#define uarts_atmega2564rfr2 uarts_atmega64rfr2 - -extern const Uart_conf uarts_atmega103[1]; -#define uarts_atmega165 uarts_atmega103 -#define uarts_atmega165a uarts_atmega103 -#define uarts_atmega165p uarts_atmega103 -#define uarts_atmega165pa uarts_atmega103 -#define uarts_atmega169 uarts_atmega103 -#define uarts_atmega325 uarts_atmega103 -#define uarts_atmega325a uarts_atmega103 -#define uarts_atmega325p uarts_atmega103 -#define uarts_atmega325pa uarts_atmega103 -#define uarts_atmega645 uarts_atmega103 -#define uarts_atmega645a uarts_atmega103 -#define uarts_atmega645p uarts_atmega103 -#define uarts_atmega3250 uarts_atmega103 -#define uarts_atmega3250a uarts_atmega103 -#define uarts_atmega3250p uarts_atmega103 -#define uarts_atmega3250pa uarts_atmega103 -#define uarts_atmega3290 uarts_atmega103 -#define uarts_atmega3290a uarts_atmega103 -#define uarts_atmega3290p uarts_atmega103 -#define uarts_atmega3290pa uarts_atmega103 -#define uarts_atmega6450 uarts_atmega103 -#define uarts_atmega6450a uarts_atmega103 -#define uarts_atmega6450p uarts_atmega103 -#define uarts_atmega6490 uarts_atmega103 -#define uarts_atmega6490a uarts_atmega103 -#define uarts_atmega6490p uarts_atmega103 - extern const Uart_conf uarts_atmega161[2]; #define uarts_atmega162 uarts_atmega161 @@ -3707,6 +3613,38 @@ extern const Uart_conf uarts_atmega164a[2]; #define uarts_atmega1284 uarts_atmega164a #define uarts_atmega1284p uarts_atmega164a +extern const Uart_conf uarts_atmega324pb[3]; + +extern const Uart_conf uarts_atmega165[1]; +#define uarts_atmega165a uarts_atmega165 +#define uarts_atmega165p uarts_atmega165 +#define uarts_atmega165pa uarts_atmega165 +#define uarts_atmega325 uarts_atmega165 +#define uarts_atmega325a uarts_atmega165 +#define uarts_atmega325p uarts_atmega165 +#define uarts_atmega325pa uarts_atmega165 +#define uarts_atmega645 uarts_atmega165 +#define uarts_atmega645a uarts_atmega165 +#define uarts_atmega645p uarts_atmega165 +#define uarts_atmega3250 uarts_atmega165 +#define uarts_atmega3250a uarts_atmega165 +#define uarts_atmega3250p uarts_atmega165 +#define uarts_atmega3250pa uarts_atmega165 +#define uarts_atmega6450 uarts_atmega165 +#define uarts_atmega6450a uarts_atmega165 +#define uarts_atmega6450p uarts_atmega165 +#define uarts_atmega169 uarts_atmega165 +#define uarts_atmega3290 uarts_atmega165 +#define uarts_atmega3290a uarts_atmega165 +#define uarts_atmega3290p uarts_atmega165 +#define uarts_atmega3290pa uarts_atmega165 +#define uarts_atmega6490 uarts_atmega165 +#define uarts_atmega6490a uarts_atmega165 +#define uarts_atmega6490p uarts_atmega165 +#define uarts_atmega103 uarts_atmega165 + +extern const Uart_conf uarts_atmega328pb[2]; + extern const Uart_conf uarts_atmega169a[1]; #define uarts_atmega169p uarts_atmega169a #define uarts_atmega169pa uarts_atmega169a @@ -3718,11 +3656,59 @@ extern const Uart_conf uarts_atmega169a[1]; #define uarts_atmega649a uarts_atmega169a #define uarts_atmega649p uarts_atmega169a -extern const Uart_conf uarts_atmega324pb[3]; +extern const Uart_conf uarts_atmega64hve[1]; +#define uarts_atmega64hve2 uarts_atmega64hve -extern const Uart_conf uarts_atmega640[4]; -#define uarts_atmega1280 uarts_atmega640 -#define uarts_atmega2560 uarts_atmega640 +extern const Uart_conf uarts_atxmega64a1[8]; +#define uarts_atxmega128a1 uarts_atxmega64a1 +#define uarts_atxmega128a1revd uarts_atxmega64a1 +#define uarts_atxmega192a1 uarts_atxmega64a1 +#define uarts_atxmega256a1 uarts_atxmega64a1 + +extern const Uart_conf uarts_atxmega64a1u[9]; +#define uarts_atxmega128a1u uarts_atxmega64a1u + +extern const Uart_conf uarts_atxmega64a3[7]; +#define uarts_atxmega128a3 uarts_atxmega64a3 +#define uarts_atxmega192a3 uarts_atxmega64a3 +#define uarts_atxmega256a3 uarts_atxmega64a3 + +extern const Uart_conf uarts_atxmega256a3b[6]; + +extern const Uart_conf uarts_atxmega64a3u[11]; +#define uarts_atxmega128a3u uarts_atxmega64a3u +#define uarts_atxmega192a3u uarts_atxmega64a3u +#define uarts_atxmega256a3u uarts_atxmega64a3u + +extern const Uart_conf uarts_atxmega256a3bu[8]; + +extern const Uart_conf uarts_atxmega16a4[7]; +#define uarts_atxmega32a4 uarts_atxmega16a4 +#define uarts_atxmega64a4 uarts_atxmega16a4 +#define uarts_atxmega128a4 uarts_atxmega16a4 +#define uarts_atxmega16a4u uarts_atxmega16a4 +#define uarts_atxmega32a4u uarts_atxmega16a4 +#define uarts_atxmega64a4u uarts_atxmega16a4 +#define uarts_atxmega128a4u uarts_atxmega16a4 + +extern const Uart_conf uarts_atxmega64b1[4]; +#define uarts_atxmega128b1 uarts_atxmega64b1 + +extern const Uart_conf uarts_atxmega64b3[2]; +#define uarts_atxmega128b3 uarts_atxmega64b3 + +extern const Uart_conf uarts_atxmega32c3[4]; +#define uarts_atxmega64c3 uarts_atxmega32c3 +#define uarts_atxmega128c3 uarts_atxmega32c3 +#define uarts_atxmega192c3 uarts_atxmega32c3 +#define uarts_atxmega256c3 uarts_atxmega32c3 +#define uarts_atxmega384c3 uarts_atxmega32c3 +#define uarts_atxmega32d3 uarts_atxmega32c3 +#define uarts_atxmega64d3 uarts_atxmega32c3 +#define uarts_atxmega128d3 uarts_atxmega32c3 +#define uarts_atxmega192d3 uarts_atxmega32c3 +#define uarts_atxmega256d3 uarts_atxmega32c3 +#define uarts_atxmega384d3 uarts_atxmega32c3 extern const Uart_conf uarts_atxmega16c4[4]; #define uarts_atxmega32c4 uarts_atxmega16c4 @@ -3732,37 +3718,43 @@ extern const Uart_conf uarts_atxmega16d4[3]; #define uarts_atxmega64d4 uarts_atxmega16d4 #define uarts_atxmega128d4 uarts_atxmega16d4 -extern const Uart_conf uarts_atxmega32c3[4]; -#define uarts_atxmega32d3 uarts_atxmega32c3 -#define uarts_atxmega64c3 uarts_atxmega32c3 -#define uarts_atxmega64d3 uarts_atxmega32c3 -#define uarts_atxmega128c3 uarts_atxmega32c3 -#define uarts_atxmega128d3 uarts_atxmega32c3 -#define uarts_atxmega192c3 uarts_atxmega32c3 -#define uarts_atxmega192d3 uarts_atxmega32c3 -#define uarts_atxmega256c3 uarts_atxmega32c3 -#define uarts_atxmega256d3 uarts_atxmega32c3 -#define uarts_atxmega384c3 uarts_atxmega32c3 -#define uarts_atxmega384d3 uarts_atxmega32c3 - -extern const Uart_conf uarts_atxmega64a1u[9]; -#define uarts_atxmega128a1u uarts_atxmega64a1u - -extern const Uart_conf uarts_atxmega64b1[4]; -#define uarts_atxmega128b1 uarts_atxmega64b1 - -extern const Uart_conf uarts_atxmega64b3[2]; -#define uarts_atxmega128b3 uarts_atxmega64b3 - -extern const Uart_conf uarts_atxmega256a3b[6]; - -extern const Uart_conf uarts_atxmega256a3bu[8]; +extern const Uart_conf uarts_atxmega8e5[4]; +#define uarts_atxmega16e5 uarts_atxmega8e5 +#define uarts_atxmega32e5 uarts_atxmega8e5 extern const Uart_conf uarts_attiny202[2]; -#define uarts_attiny212 uarts_attiny202 #define uarts_attiny402 uarts_attiny202 +#define uarts_attiny212 uarts_attiny202 #define uarts_attiny412 uarts_attiny202 +extern const Uart_conf uarts_attiny204[2]; +#define uarts_attiny404 uarts_attiny204 +#define uarts_attiny406 uarts_attiny204 +#define uarts_attiny804 uarts_attiny204 +#define uarts_attiny806 uarts_attiny204 +#define uarts_attiny807 uarts_attiny204 +#define uarts_attiny1604 uarts_attiny204 +#define uarts_attiny1606 uarts_attiny204 +#define uarts_attiny1607 uarts_attiny204 +#define uarts_attiny214 uarts_attiny204 +#define uarts_attiny414 uarts_attiny204 +#define uarts_attiny416 uarts_attiny204 +#define uarts_attiny416auto uarts_attiny204 +#define uarts_attiny417 uarts_attiny204 +#define uarts_attiny814 uarts_attiny204 +#define uarts_attiny816 uarts_attiny204 +#define uarts_attiny817 uarts_attiny204 +#define uarts_attiny1614 uarts_attiny204 +#define uarts_attiny1616 uarts_attiny204 +#define uarts_attiny1617 uarts_attiny204 +#define uarts_attiny3216 uarts_attiny204 +#define uarts_attiny3217 uarts_attiny204 + +extern const Uart_conf uarts_attiny424[3]; +#define uarts_attiny824 uarts_attiny424 +#define uarts_attiny1624 uarts_attiny424 +#define uarts_attiny3224 uarts_attiny424 + extern const Uart_conf uarts_attiny426[4]; #define uarts_attiny427 uarts_attiny426 #define uarts_attiny826 uarts_attiny426 @@ -3782,19 +3774,61 @@ extern const Uart_conf uarts_atmega809[8]; #define uarts_atmega3209 uarts_atmega809 #define uarts_atmega4809 uarts_atmega809 -extern const Uart_conf uarts_avr16du14[3]; -#define uarts_avr32du14 uarts_avr16du14 +extern const Uart_conf uarts_avr32da28[4]; +#define uarts_avr32da28s uarts_avr32da28 +#define uarts_avr64da28 uarts_avr32da28 +#define uarts_avr64da28s uarts_avr32da28 +#define uarts_avr128da28 uarts_avr32da28 +#define uarts_avr128da28s uarts_avr32da28 +#define uarts_avr32db28 uarts_avr32da28 +#define uarts_avr64db28 uarts_avr32da28 +#define uarts_avr128db28 uarts_avr32da28 -extern const Uart_conf uarts_avr16eb14[4]; -#define uarts_avr32eb14 uarts_avr16eb14 +extern const Uart_conf uarts_avr32da32[5]; +#define uarts_avr32da32s uarts_avr32da32 +#define uarts_avr64da32 uarts_avr32da32 +#define uarts_avr64da32s uarts_avr32da32 +#define uarts_avr128da32 uarts_avr32da32 +#define uarts_avr128da32s uarts_avr32da32 +#define uarts_avr32db32 uarts_avr32da32 +#define uarts_avr64db32 uarts_avr32da32 +#define uarts_avr128db32 uarts_avr32da32 -extern const Uart_conf uarts_avr16la14[3]; -#define uarts_avr32la14 uarts_avr16la14 +extern const Uart_conf uarts_avr32da48[9]; +#define uarts_avr32da48s uarts_avr32da48 +#define uarts_avr64da48 uarts_avr32da48 +#define uarts_avr64da48s uarts_avr32da48 +#define uarts_avr128da48 uarts_avr32da48 +#define uarts_avr128da48s uarts_avr32da48 +#define uarts_avr32db48 uarts_avr32da48 +#define uarts_avr64db48 uarts_avr32da48 +#define uarts_avr128db48 uarts_avr32da48 + +extern const Uart_conf uarts_avr64da64[12]; +#define uarts_avr64da64s uarts_avr64da64 +#define uarts_avr128da64 uarts_avr64da64 +#define uarts_avr128da64s uarts_avr64da64 +#define uarts_avr64db64 uarts_avr64da64 +#define uarts_avr128db64 uarts_avr64da64 + +extern const Uart_conf uarts_avr16dd14[5]; +#define uarts_avr32dd14 uarts_avr16dd14 +#define uarts_avr64dd14 uarts_avr16dd14 extern const Uart_conf uarts_avr16dd20[7]; #define uarts_avr32dd20 uarts_avr16dd20 -#define uarts_avr32sd20 uarts_avr16dd20 #define uarts_avr64dd20 uarts_avr16dd20 +#define uarts_avr32sd20 uarts_avr16dd20 + +extern const Uart_conf uarts_avr16dd28[7]; +#define uarts_avr16dd32 uarts_avr16dd28 +#define uarts_avr32dd28 uarts_avr16dd28 +#define uarts_avr32dd32 uarts_avr16dd28 +#define uarts_avr64dd28 uarts_avr16dd28 +#define uarts_avr64dd32 uarts_avr16dd28 + +extern const Uart_conf uarts_avr16du14[3]; +#define uarts_avr32du14 uarts_avr16du14 extern const Uart_conf uarts_avr16du20[5]; #define uarts_avr16du28 uarts_avr16du20 @@ -3805,6 +3839,23 @@ extern const Uart_conf uarts_avr16du20[5]; #define uarts_avr64du28 uarts_avr16du20 #define uarts_avr64du32 uarts_avr16du20 +extern const Uart_conf uarts_avr16ea28[8]; +#define uarts_avr32ea28 uarts_avr16ea28 +#define uarts_avr64ea28 uarts_avr16ea28 +#define uarts_avr32sd28 uarts_avr16ea28 + +extern const Uart_conf uarts_avr16ea32[9]; +#define uarts_avr32ea32 uarts_avr16ea32 +#define uarts_avr64ea32 uarts_avr16ea32 +#define uarts_avr32sd32 uarts_avr16ea32 + +extern const Uart_conf uarts_avr16ea48[10]; +#define uarts_avr32ea48 uarts_avr16ea48 +#define uarts_avr64ea48 uarts_avr16ea48 + +extern const Uart_conf uarts_avr16eb14[4]; +#define uarts_avr32eb14 uarts_avr16eb14 + extern const Uart_conf uarts_avr16eb20[6]; #define uarts_avr16eb28 uarts_avr16eb20 #define uarts_avr16eb32 uarts_avr16eb20 @@ -3812,6 +3863,9 @@ extern const Uart_conf uarts_avr16eb20[6]; #define uarts_avr32eb28 uarts_avr16eb20 #define uarts_avr32eb32 uarts_avr16eb20 +extern const Uart_conf uarts_avr16la14[3]; +#define uarts_avr32la14 uarts_avr16la14 + extern const Uart_conf uarts_avr16la20[5]; #define uarts_avr16la28 uarts_avr16la20 #define uarts_avr16la32 uarts_avr16la20 @@ -3819,60 +3873,6 @@ extern const Uart_conf uarts_avr16la20[5]; #define uarts_avr32la28 uarts_avr16la20 #define uarts_avr32la32 uarts_avr16la20 -extern const Uart_conf uarts_avr16dd28[7]; -#define uarts_avr16dd32 uarts_avr16dd28 -#define uarts_avr32dd28 uarts_avr16dd28 -#define uarts_avr32dd32 uarts_avr16dd28 -#define uarts_avr64dd28 uarts_avr16dd28 -#define uarts_avr64dd32 uarts_avr16dd28 - -extern const Uart_conf uarts_avr16ea28[8]; -#define uarts_avr32ea28 uarts_avr16ea28 -#define uarts_avr32sd28 uarts_avr16ea28 -#define uarts_avr64ea28 uarts_avr16ea28 - -extern const Uart_conf uarts_avr16ea32[9]; -#define uarts_avr32ea32 uarts_avr16ea32 -#define uarts_avr32sd32 uarts_avr16ea32 -#define uarts_avr64ea32 uarts_avr16ea32 - -extern const Uart_conf uarts_avr32da28[4]; -#define uarts_avr32da28s uarts_avr32da28 -#define uarts_avr32db28 uarts_avr32da28 -#define uarts_avr64da28 uarts_avr32da28 -#define uarts_avr64da28s uarts_avr32da28 -#define uarts_avr64db28 uarts_avr32da28 -#define uarts_avr128da28 uarts_avr32da28 -#define uarts_avr128da28s uarts_avr32da28 -#define uarts_avr128db28 uarts_avr32da28 - -extern const Uart_conf uarts_avr32da32[5]; -#define uarts_avr32da32s uarts_avr32da32 -#define uarts_avr32db32 uarts_avr32da32 -#define uarts_avr64da32 uarts_avr32da32 -#define uarts_avr64da32s uarts_avr32da32 -#define uarts_avr64db32 uarts_avr32da32 -#define uarts_avr128da32 uarts_avr32da32 -#define uarts_avr128da32s uarts_avr32da32 -#define uarts_avr128db32 uarts_avr32da32 - -extern const Uart_conf uarts_avr32da48[9]; -#define uarts_avr32da48s uarts_avr32da48 -#define uarts_avr32db48 uarts_avr32da48 -#define uarts_avr64da48 uarts_avr32da48 -#define uarts_avr64da48s uarts_avr32da48 -#define uarts_avr64db48 uarts_avr32da48 -#define uarts_avr128da48 uarts_avr32da48 -#define uarts_avr128da48s uarts_avr32da48 -#define uarts_avr128db48 uarts_avr32da48 - -extern const Uart_conf uarts_avr64da64[12]; -#define uarts_avr64da64s uarts_avr64da64 -#define uarts_avr64db64 uarts_avr64da64 -#define uarts_avr128da64 uarts_avr64da64 -#define uarts_avr128da64s uarts_avr64da64 -#define uarts_avr128db64 uarts_avr64da64 - int upidxmcuid(int mcuid); int upidxsig(const uint8_t *sigs); int upidxname(const char *name);