/* Please get help from ddrbin_tool_user_guide.txt and './ddrbin_tool -h' */
start tag=0x12345678
ddr2_freq=
lp2_freq=
ddr3_freq=
lp3_freq=
ddr4_freq=
lp4_freq=
lp4x_freq=
lp5_freq=

uart id=
uart iomux=
uart baudrate=

sr_idle=
pd_idle=

first scan channel=
channel mask=
stride type=
standby_idle=

ext_temp_ref=
link_ecc_en=
per_bank_ref_en=
derate_en=
auto_precharge_en=

res_space_remap_all=
res_space_remap_portion=

rd_vref_scan_en=
wr_vref_scan_en=
eye_2d_scan_en=

dis_train_print=

ssmod_downspread=
ssmod_div=
ssmod_spread=

ddr_2t=

pstore_base_addr=
pstore_buf_size=
uboot_log_en=
atf_log_en=
optee_log_en=
spl_log_en=
tpl_log_en=

first_init_dram_type=
dfs_disable=
pageclose=
boot_fsp=

ddr2_f1_freq_mhz=
ddr2_f2_freq_mhz=
ddr2_f3_freq_mhz=
ddr2_f4_freq_mhz=
ddr2_f5_freq_mhz=
phy_ddr2_dq_drv_when_odten_ohm=
phy_ddr2_ca_drv_when_odten_ohm=
phy_ddr2_clk_drv_when_odten_ohm=
ddr2_dq_drv_when_odten_ohm=
phy_ddr2_dq_drv_when_odtoff_ohm=
phy_ddr2_ca_drv_when_odtoff_ohm=
phy_ddr2_clk_drv_when_odtoff_ohm=
ddr2_dq_drv_when_odtoff_ohm=
phy_ddr2_odt_ohm=
ddr2_odt_ohm=
phy_ddr2_odt_pull_up_en=
phy_ddr2_odt_pull_dn_en=
phy_ddr2_odten_freq_mhz=
ddr2_odten_freq_mhz=
phy_ddr2_dq_sr_when_odten=
phy_ddr2_ca_sr_when_odten=
phy_ddr2_clk_sr_when_odten=
phy_ddr2_dq_sr_when_odtoff=
phy_ddr2_ca_sr_when_odtoff=
phy_ddr2_clk_sr_when_odtoff=
phy_ddr2_dq_vref_when_odten=
ddr2_dq_vref_when_odten=
ddr2_ca_vref_when_odten=
phy_ddr2_dq_vref_when_odtoff=
ddr2_dq_vref_when_odtoff=
ddr2_ca_vref_when_odtoff=

ddr3_f1_freq_mhz=
ddr3_f2_freq_mhz=
ddr3_f3_freq_mhz=
ddr3_f4_freq_mhz=
ddr3_f5_freq_mhz=
phy_ddr3_dq_drv_when_odten_ohm=
phy_ddr3_ca_drv_when_odten_ohm=
phy_ddr3_clk_drv_when_odten_ohm=
ddr3_dq_drv_when_odten_ohm=
phy_ddr3_dq_drv_when_odtoff_ohm=
phy_ddr3_ca_drv_when_odtoff_ohm=
phy_ddr3_clk_drv_when_odtoff_ohm=
ddr3_dq_drv_when_odtoff_ohm=
phy_ddr3_odt_ohm=
ddr3_odt_ohm=
phy_ddr3_odt_pull_up_en=
phy_ddr3_odt_pull_dn_en=
phy_ddr3_odten_freq_mhz=
ddr3_odten_freq_mhz=
phy_ddr3_dq_sr_when_odten=
phy_ddr3_ca_sr_when_odten=
phy_ddr3_clk_sr_when_odten=
phy_ddr3_dq_sr_when_odtoff=
phy_ddr3_ca_sr_when_odtoff=
phy_ddr3_clk_sr_when_odtoff=
phy_ddr3_dq_vref_when_odten=
ddr3_dq_vref_when_odten=
ddr3_ca_vref_when_odten=
phy_ddr3_dq_vref_when_odtoff=
ddr3_dq_vref_when_odtoff=
ddr3_ca_vref_when_odtoff=

ddr4_f1_freq_mhz=
ddr4_f2_freq_mhz=
ddr4_f3_freq_mhz=
ddr4_f4_freq_mhz=
ddr4_f5_freq_mhz=
phy_ddr4_dq_drv_when_odten_ohm=
phy_ddr4_ca_drv_when_odten_ohm=
phy_ddr4_clk_drv_when_odten_ohm=
ddr4_dq_drv_when_odten_ohm=
phy_ddr4_dq_drv_when_odtoff_ohm=
phy_ddr4_ca_drv_when_odtoff_ohm=
phy_ddr4_clk_drv_when_odtoff_ohm=
ddr4_dq_drv_when_odtoff_ohm=
phy_ddr4_odt_ohm=
ddr4_odt_ohm=
phy_ddr4_odt_pull_up_en=
phy_ddr4_odt_pull_dn_en=
phy_ddr4_odten_freq_mhz=
ddr4_odten_freq_mhz=
phy_ddr4_dq_sr_when_odten=
phy_ddr4_ca_sr_when_odten=
phy_ddr4_clk_sr_when_odten=
phy_ddr4_dq_sr_when_odtoff=
phy_ddr4_ca_sr_when_odtoff=
phy_ddr4_clk_sr_when_odtoff=
phy_ddr4_dq_vref_when_odten=
ddr4_dq_vref_when_odten=
ddr4_ca_vref_when_odten=
phy_ddr4_dq_vref_when_odtoff=
ddr4_dq_vref_when_odtoff=
ddr4_ca_vref_when_odtoff=

lp2_f1_freq_mhz=
lp2_f2_freq_mhz=
lp2_f3_freq_mhz=
lp2_f4_freq_mhz=
lp2_f5_freq_mhz=
phy_lp2_dq_drv_when_odten_ohm=
phy_lp2_ca_drv_when_odten_ohm=
phy_lp2_clk_drv_when_odten_ohm=
lp2_dq_drv_when_odten_ohm=
phy_lp2_dq_drv_when_odtoff_ohm=
phy_lp2_ca_drv_when_odtoff_ohm=
phy_lp2_clk_drv_when_odtoff_ohm=
lp2_dq_drv_when_odtoff_ohm=
phy_lp2_odt_ohm=
lp2_odt_ohm=
phy_lp2_odt_pull_up_en=
phy_lp2_odt_pull_dn_en=
phy_lp2_odten_freq_mhz=
lp2_odten_freq_mhz=
phy_lp2_dq_sr_when_odten=
phy_lp2_ca_sr_when_odten=
phy_lp2_clk_sr_when_odten=
phy_lp2_dq_sr_when_odtoff=
phy_lp2_ca_sr_when_odtoff=
phy_lp2_clk_sr_when_odtoff=
phy_lp2_dq_vref_when_odten=
lp2_dq_vref_when_odten=
lp2_ca_vref_when_odten=
phy_lp2_dq_vref_when_odtoff=
lp2_dq_vref_when_odtoff=
lp2_ca_vref_when_odtoff=

lp3_f1_freq_mhz=
lp3_f2_freq_mhz=
lp3_f3_freq_mhz=
lp3_f4_freq_mhz=
lp3_f5_freq_mhz=
phy_lp3_dq_drv_when_odten_ohm=
phy_lp3_ca_drv_when_odten_ohm=
phy_lp3_clk_drv_when_odten_ohm=
lp3_dq_drv_when_odten_ohm=
phy_lp3_dq_drv_when_odtoff_ohm=
phy_lp3_ca_drv_when_odtoff_ohm=
phy_lp3_clk_drv_when_odtoff_ohm=
lp3_dq_drv_when_odtoff_ohm=
phy_lp3_odt_ohm=
lp3_odt_ohm=
phy_lp3_odt_pull_up_en=
phy_lp3_odt_pull_dn_en=
phy_lp3_odten_freq_mhz=
lp3_odten_freq_mhz=
phy_lp3_dq_sr_when_odten=
phy_lp3_ca_sr_when_odten=
phy_lp3_clk_sr_when_odten=
phy_lp3_dq_sr_when_odtoff=
phy_lp3_ca_sr_when_odtoff=
phy_lp3_clk_sr_when_odtoff=
phy_lp3_dq_vref_when_odten=
lp3_dq_vref_when_odten=
lp3_ca_vref_when_odten=
phy_lp3_dq_vref_when_odtoff=
lp3_dq_vref_when_odtoff=
lp3_ca_vref_when_odtoff=

lp4_f1_freq_mhz=
lp4_f2_freq_mhz=
lp4_f3_freq_mhz=
lp4_f4_freq_mhz=
lp4_f5_freq_mhz=
phy_lp4_dq_drv_when_odten_ohm=
phy_lp4_ca_drv_when_odten_ohm=
phy_lp4_clk_drv_when_odten_ohm=
lp4_dq_drv_when_odten_ohm=
phy_lp4_dq_drv_when_odtoff_ohm=
phy_lp4_ca_drv_when_odtoff_ohm=
phy_lp4_clk_drv_when_odtoff_ohm=
lp4_dq_drv_when_odtoff_ohm=
phy_lp4_odt_ohm=
lp4_odt_ohm=
lp4_ca_odt_ohm=
lp4_drv_pu_cal_odten=
lp4_drv_pu_cal_odtoff=
phy_lp4_drv_pull_dn_en_odten=
phy_lp4_drv_pull_dn_en_odtoff=
phy_lp4_odten_freq_mhz=
lp4_dq_odten_freq_mhz=
phy_lp4_dq_sr_when_odten=
phy_lp4_ca_sr_when_odten=
phy_lp4_clk_sr_when_odten=
phy_lp4_dq_sr_when_odtoff=
phy_lp4_ca_sr_when_odtoff=
phy_lp4_clk_sr_when_odtoff=
lp4_ca_odten_freq_mhz=
phy_lp4_cs_drv_odten=
phy_lp4_cs_drv_odtoff=
lp4_odte_ck=
lp4_odte_cs_en=
lp4_odtd_ca_en=
phy_lp4_dq_vref_when_odten=
lp4_dq_vref_when_odten=
lp4_ca_vref_when_odten=
phy_lp4_dq_vref_when_odtoff=
lp4_dq_vref_when_odtoff=
lp4_ca_vref_when_odtoff=

ddr2_bytes_map=
ddr3_bytes_map=
ddr4_bytes_map=
lp2_bytes_map=
lp3_bytes_map=
lp4_bytes_map=
lp3_dq0_7_map=
lp2_dq0_7_map=
ddr4_cs0_dq0_dq15_map=
ddr4_cs0_dq16_dq31_map=
ddr4_cs1_dq0_dq15_map=
ddr4_cs1_dq16_dq31_map=

lp4x_f1_freq_mhz=
lp4x_f2_freq_mhz=
lp4x_f3_freq_mhz=
lp4x_f4_freq_mhz=
lp4x_f5_freq_mhz=
phy_lp4x_dq_drv_when_odten_ohm=
phy_lp4x_ca_drv_when_odten_ohm=
phy_lp4x_clk_drv_when_odten_ohm=
lp4x_dq_drv_when_odten_ohm=
phy_lp4x_dq_drv_when_odtoff_ohm=
phy_lp4x_ca_drv_when_odtoff_ohm=
phy_lp4x_clk_drv_when_odtoff_ohm=
lp4x_dq_drv_when_odtoff_ohm=
phy_lp4x_odt_ohm=
lp4x_odt_ohm=
lp4x_ca_odt_ohm=
lp4x_drv_pu_cal_odten=
lp4x_drv_pu_cal_odtoff=
phy_lp4x_drv_pull_dn_en_odten=
phy_lp4x_drv_pull_dn_en_odtoff=
phy_lp4x_odten_freq_mhz=
lp4x_dq_odten_freq_mhz=
phy_lp4x_dq_sr_when_odten=
phy_lp4x_ca_sr_when_odten=
phy_lp4x_clk_sr_when_odten=
phy_lp4x_dq_sr_when_odtoff=
phy_lp4x_ca_sr_when_odtoff=
phy_lp4x_clk_sr_when_odtoff=
lp4x_ca_odten_freq_mhz=
phy_lp4x_cs_drv_odten=
phy_lp4x_cs_drv_odtoff=
lp4x_odte_ck=
lp4x_odte_cs_en=
lp4x_odtd_ca_en=
phy_lp4x_dq_vref_when_odten=
lp4x_dq_vref_when_odten=
lp4x_ca_vref_when_odten=
phy_lp4x_dq_vref_when_odtoff=
lp4x_dq_vref_when_odtoff=
lp4x_ca_vref_when_odtoff=

lp5_f1_freq_mhz=
lp5_f2_freq_mhz=
lp5_f3_freq_mhz=
lp5_f4_freq_mhz=
lp5_f5_freq_mhz=
phy_lp5_dq_drv_when_odten_ohm=
phy_lp5_ca_drv_when_odten_ohm=
phy_lp5_clk_drv_when_odten_ohm=
lp5_dq_drv_when_odten_ohm=
phy_lp5_dq_drv_when_odtoff_ohm=
phy_lp5_ca_drv_when_odtoff_ohm=
phy_lp5_clk_drv_when_odtoff_ohm=
lp5_dq_drv_when_odtoff_ohm=
phy_lp5_odt_ohm=
lp5_odt_ohm=
lp5_ca_odt_ohm=
lp5_drv_pu_cal_odten=
lp5_drv_pu_cal_odtoff=
phy_lp5_drv_pull_dn_en_odten=
phy_lp5_drv_pull_dn_en_odtoff=
phy_lp5_odten_freq_mhz=
lp5_dq_odten_freq_mhz=
phy_lp5_dq_sr_when_odten=
phy_lp5_ca_sr_when_odten=
phy_lp5_clk_sr_when_odten=
phy_lp5_dq_sr_when_odtoff=
phy_lp5_ca_sr_when_odtoff=
phy_lp5_clk_sr_when_odtoff=
lp5_ca_odten_freq_mhz=
lp5_wck_odt_en_freq=
lp5_wck_odt=
phy_lp5_cs_drv_odten=
phy_lp5_cs_drv_odtoff=
lp5_odte_ck=
lp5_odte_cs_en=
lp5_odtd_ca_en=
lp5_nt_odt=
phy_lp5_dq_vref_when_odten=
lp5_dq_vref_when_odten=
lp5_ca_vref_when_odten=
phy_lp5_dq_vref_when_odtoff=
lp5_dq_vref_when_odtoff=
lp5_ca_vref_when_odtoff=

lp4_4x_ch_mask0=
lp4_4x_ch_mask1=
lp4_4x_bank_mask0=
lp4_4x_bank_mask1=
lp4_4x_bank_mask2=
lp4_4x_bank_mask3=
lp4_4x_rank_mask0=
lp4_4x_rank_mask1=
lp5_ch_mask0=
lp5_ch_mask1=
lp5_bank_mask0=
lp5_bank_mask1=
lp5_bank_mask2=
lp5_bank_mask3=
lp5_rank_mask0=
lp5_rank_mask1=
ddr4_ch_mask0=
ddr4_ch_mask1=
ddr4_bank_mask0=
ddr4_bank_mask1=
ddr4_bank_mask2=
ddr4_bank_mask3=
ddr4_rank_mask0=
ddr4_rank_mask1=
lp3_ch_mask0=
lp3_ch_mask1=
lp3_bank_mask0=
lp3_bank_mask1=
lp3_bank_mask2=
lp3_bank_mask3=
lp3_rank_mask0=
lp3_rank_mask1=
ddr3_ch_mask0=
ddr3_ch_mask1=
ddr3_bank_mask0=
ddr3_bank_mask1=
ddr3_bank_mask2=
ddr3_bank_mask3=
ddr3_rank_mask0=
ddr3_rank_mask1=
lp2_ch_mask0=
lp2_ch_mask1=
lp2_bank_mask0=
lp2_bank_mask1=
lp2_bank_mask2=
lp2_bank_mask3=
lp2_rank_mask0=
lp2_rank_mask1=
ddr2_ch_mask0=
ddr2_ch_mask1=
ddr2_bank_mask0=
ddr2_bank_mask1=
ddr2_bank_mask2=
ddr2_bank_mask3=
ddr2_rank_mask0=
ddr2_rank_mask1=
ddr5_ch_mask0=
ddr5_ch_mask1=
ddr5_bank_mask0=
ddr5_bank_mask1=
ddr5_bank_mask2=
ddr5_bank_mask3=
ddr5_rank_mask0=
ddr5_rank_mask1=

ddr3_skew_freq_mhz=
ddr3_ca0_skew=
ddr3_ca1_skew=
ddr3_ca2_skew=
ddr3_ca3_skew=
ddr3_ca4_skew=
ddr3_ca5_skew=
ddr3_ca6_skew=
ddr3_ca7_skew=
ddr3_ca8_skew=
ddr3_ca9_skew=
ddr3_ca10_skew=
ddr3_ca11_skew=
ddr3_ca12_skew=
ddr3_ca13_skew=
ddr3_ca14_skew=
ddr3_ca15_skew=
ddr3_ras_skew=
ddr3_cas_skew=
ddr3_ba0_skew=
ddr3_ba1_skew=
ddr3_ba2_skew=
ddr3_we_skew=
ddr3_cke0_skew=
ddr3_cke1_skew=
ddr3_ckn_skew=
ddr3_ckp_skew=
ddr3_odt0_skew=
ddr3_odt1_skew=
ddr3_cs0_skew=
ddr3_cs1_skew=
ddr3_resetn_skew=

ddr4_skew_freq_mhz=
ddr4_ca0_skew=
ddr4_ca1_skew=
ddr4_ca2_skew=
ddr4_ca3_skew=
ddr4_ca4_skew=
ddr4_ca5_skew=
ddr4_ca6_skew=
ddr4_ca7_skew=
ddr4_ca8_skew=
ddr4_ca9_skew=
ddr4_ca10_skew=
ddr4_ca11_skew=
ddr4_ca12_skew=
ddr4_ca13_skew=
ddr4_ca14_skew=
ddr4_ca15_skew=
ddr4_ca16_skew=
ddr4_ca17_skew=
ddr4_ba0_skew=
ddr4_ba1_skew=
ddr4_bg0_skew=
ddr4_bg1_skew=
ddr4_cke0_skew=
ddr4_cke1_skew=
ddr4_ckn_skew=
ddr4_ckp_skew=
ddr4_odt0_skew=
ddr4_odt1_skew=
ddr4_cs0_skew=
ddr4_cs1_skew=
ddr4_resetn_skew=
ddr4_actn_skew=

lp3_skew_freq_mhz=
lp3_ca0_skew=
lp3_ca1_skew=
lp3_ca2_skew=
lp3_ca3_skew=
lp3_ca4_skew=
lp3_ca5_skew=
lp3_ca6_skew=
lp3_ca7_skew=
lp3_ca8_skew=
lp3_ca9_skew=
lp3_cke0_skew=
lp3_cke1_skew=
lp3_ckn_skew=
lp3_ckp_skew=
lp3_odt0_skew=
lp3_odt1_skew=
lp3_odt2_skew=
lp3_odt3_skew=
lp3_cs0_skew=
lp3_cs1_skew=
lp3_cs2_skew=
lp3_cs3_skew=

lp4_skew_freq_mhz=
lp4_ca0_a_skew=
lp4_ca1_a_skew=
lp4_ca2_a_skew=
lp4_ca3_a_skew=
lp4_ca4_a_skew=
lp4_ca5_a_skew=
lp4_odt0_a_skew=
lp4_odt1_a_skew=
lp4_cke0_a_skew=
lp4_cke1_a_skew=
lp4_ckn_a_skew=
lp4_ckp_a_skew=
lp4_cs0_a_skew=
lp4_cs1_a_skew=
lp4_ca0_b_skew=
lp4_ca1_b_skew=
lp4_ca2_b_skew=
lp4_ca3_b_skew=
lp4_ca4_b_skew=
lp4_ca5_b_skew=
lp4_odt0_b_skew=
lp4_odt1_b_skew=
lp4_cke0_b_skew=
lp4_cke1_b_skew=
lp4_ckn_b_skew=
lp4_ckp_b_skew=
lp4_cs0_b_skew=
lp4_cs1_b_skew=
lp4_resetn_skew=

lp5_skew_freq_mhz=
lp5_ca0_a_skew=
lp5_ca1_a_skew=
lp5_ca2_a_skew=
lp5_ca3_a_skew=
lp5_ca4_a_skew=
lp5_ca5_a_skew=
lp5_ca6_a_skew=
lp5_ckn_a_skew=
lp5_ckp_a_skew=
lp5_cs0_a_skew=
lp5_cs1_a_skew=
lp5_ca0_b_skew=
lp5_ca1_b_skew=
lp5_ca2_b_skew=
lp5_ca3_b_skew=
lp5_ca4_b_skew=
lp5_ca5_b_skew=
lp5_ca6_b_skew=
lp5_ckn_b_skew=
lp5_ckp_b_skew=
lp5_cs0_b_skew=
lp5_cs1_b_skew=
lp5_resetn_skew=

end
