from commit:
20b8d8f8d src: spinand: Support new device W25N01JWZEIG
update feature:
Support new SPI Flash
Change-Id: I458b0639a299722ffa3b69522b80248717f9f2ff
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from:
1df264c461 dram_init: rv1106: Change CFG_VERSION from V1.14 to v1.14
Update features:
60cd8a05aa dram_init: rv1106: Upadate to v1.14
a33ae16d09 drivers: ram: rv1106: Adjust SI info of BGA DDR3
cef2fb4a30 drivers: ram: rv1106: Raise vref_out when wr trn of BGA DDR3
1db2fd720d drivers: ram: rv1106: Adjust SI info of DDR4
b58f8e70ca drivers: ram: rv1106: Add fwver support
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic814c33de3a39f9c1c62ed4dc946a7cdfea4dac9
from commit:
I0043a8b1 Revert "src: spinand: Support 4KB page for new IDB"
update feature:
Revert "src: spinand: Support 4KB page for new IDB"
Change-Id: I27b89a31d60f85303bfc53bb2852d18fe78170db
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from:
f1d94e1902 configs: rv1106: Enable SPL_AB by default
Build command:
./make.sh rv1106 --spl-new --spl-fwver v1.02
Update features:
1. Support for A/B systems.
2. Print and pass the firmware version number.
3. Solve the issue that the backup image is not loaded when
the SPL load or check u-boot.dtb fails.
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Change-Id: I5d266ce9ee8209893c0eb747ae039536e91613e8
Build from:
6cf9a2f250 dram_init: rv1106: Update to v1.12
Update feature:
dd6f7dc7c6 drivers: ram: rv1106: Fast exit (DLL on) for power down on DDR3
76b28dbce9 drivers: ram: rv1106: Support modify refresh rate in loader_params
ed9d2f002f drivers: ram: rv1106: Fix calc of cs_pst
5af756bb61 drivers: ram: rv1106: Add print when distinguishing DDR2 from DDR3
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I87dd6ceb87479c5827c2957fa057e5b4b8afd359
from commit:
I6b73e5e src: spinand: Fix unnecessary QE for S35ML0xG3
update feature:
Support new spiflash.
Change-Id: Ic9a96bcf98ebe00951370fcacb28bd95eccf06ee
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from:
ec2fae0c96 rk356x: ddr: update ddr bin to v1.15
Update feature:
25f78a9a5d drivers: ram: rv1106: Initial version v1.10 20221108
1. Set reg_fb1xclk_invdelaysel_dqcmd to 0x15 except DDR2
2. Simplify print
3. Set DPLL Fvco_max of BGA to 3800MHz
4. Config sw_done to change INIT7 in set_ds_odt()
5. Use bitflip pattern to do write tain
6. Keep CLK skew = 0x80, and adjust DQS Tx skew according to wrlvl
7. Update DDR4 dram vref by A7 of MR6
8. Fix value of SCHED
9. Fix value of RANKCTL
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I6d4a71228636c7ff56d336ca138b071706363ed8
from commit:
rk_boot_all: 7eadab
update feature:
src: spinor: Support GD25LQ128
Change-Id: Ic83227375bb969a23d490a27c66830741483fd79
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from:
9e9c51a040 drivers: ram: rv1106: Initial version v1.09 20220630
(https://10.10.10.29/c/rk/ubd/+/145841/47)
Update feature:
1. Fix atag, which may affect boot
2. Skip update_dqs_rx_phase() when master DLL lock is timeout
3. Run exit code after train timeout instead of return
4. Dis auto ZQ of dram in ddr_set_rate()
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I4f36d98ea0b935710001a96cfa7cc48223bbfd73
Build from:
5dc6490a60 drivers: ram: rv1106: Initial version v1.06 20220509
(https://10.10.10.29/c/rk/ubd/+/145841/42)
Update feature:
1. Set defalut pack to QFN
2. Add 528MHz of DDR3 (Config 528MHz with ddrbin_tool)
3. Do not print warning when read eye trn flag is high, because
it is easy to happen at low freq
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I40ada0a143b7b0b561fcc88f0c24f88ec7b29b52
Build from u-boot-ddr:
drivers: ram: rv1106: Initial version v1.05 20220425
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/41)
Update feature:
1. Read OTP to get pack
2. Adjust NOC ReadLatency of DDR3 924MHz & 1056MHz
3. Delete 324MHz & 396MHz of DDR2
4. Enable PVTPLL
5. Config DDR_GRF_CON1&2 for power consumption
6. QFN gets SI info from MACRO, BGA gets SI info from
loader_params.inc
7. Set reg_train_2t_mode, and fix reg_cmd_2t_mode to 0x7fffff
8. Exit read gate if detect error flag
9. Fix set of t_xs_x32, t_xs_abort_x32 and t_xs_fast_x32
10. wait_phy_pll_lock in ddr_set_rate()
11. Decrease delay between rkclk_ddr_reset(dram, 1, 1, 1, 1) and
rkclk_ddr_reset(dram, 1, 1, 1, 0)
12. Call dram_all_config and enable_low_power in post_init
13. Add delay when detect row
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic125bf2081c01aafdd6ef473c9b2145d41337a66
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
and change baudrate to 115200
Update feature:
Change baudrate to 115200
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic18c28757ae38670e27e5a1a0f6cc94ba4271f27
Build from u-boot-ddr:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
Update feature:
c44e2c2649 drivers: ram: rv1106: Initial version v1.02 20220330
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/37)
1. Fix 328MHz to 324MHz, 664MHz to 660MHz, 784MHz to 780MHz
2. Fix ReadLatency of NOC (-50)
3. Delete DQ skew cfg of DDR2
4. Set DeviceSize of NOC
5. Fix PHY PLL set
6. Fix wrong calc of wrlvl_info.tdqss_min/max
7. Fix wrong set of tRFC
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I78755018346355647a28e5b85ee2ee390c49605d
from commit:
rk_boot_all: 209c77: src: spinand: Add SNAND tag for spinand PC tools
Update feature:
src: spinand: Add SNAND tag for spinand PC tools
Change-Id: Id03fc440a9d987c974bce0736e4494b5e0e939d5
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Build from u-boot-ddr:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
Update feature:
0cc2c5d0bd drivers: ram: rv1106: Initial version v1.01 20220325
(https://10.10.10.29/c/rk/u-boot-ddr/+/145841/33)
1. Fix wrong calc of ddrconf, which ignore col
2. Do not init UART2 when in UART download
3. Fix wrong of memcpy of NOC
4. Fix wrong of update_dq_tx_skew/update_dq_tx_skew
5. Fix wrong of Disable PVT
6. Enable 2T of PHY_REG 0x1c
7. Return error if changing freq fail
Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: I4e564b8322623834d8e117efd4dc1387f66fbffa
