mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Patch by Klaus Heydeck, 12 May 2004:
Using external watchdog for KUP4 boards in mpc8xx/cpu.c; load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c; various changes to KUP4 board specific files
This commit is contained in:
wdenk
@@ -72,8 +72,8 @@
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"contrast=55\0" \
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"silent=1\0" \
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"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
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"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
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"cp.b 200000 40040000 14000\0"
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"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 $(filesize);" \
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"cp.b 200000 40050000 14000\0"
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#define CONFIG_BOOTCOMMAND \
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"run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
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@@ -85,7 +85,7 @@
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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@@ -96,23 +96,81 @@
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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#define CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 40000
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#define CFG_I2C_SLAVE 0x7F
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/*
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* enable I2C and select the hardware/software driver
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*/
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
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#define CONFIG_KUP4K_LOGO 0x40040000 /* Address of logo bitmap */
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#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
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#define CFG_I2C_SLAVE 0xFE
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#ifdef CONFIG_SOFT_I2C
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SOFT_I2C */
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/*-----------------------------------------------------------------------
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* I2C Configuration
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*/
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#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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/* List of I2C addresses to be verified by POST */
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#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \
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CFG_I2C_RTC_ADDR, \
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}
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#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
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#define CFG_DISCOVER_PHY
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#if 0
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#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */
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#endif
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#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#if 1
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/* POST support */
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#define CONFIG_POST (CFG_POST_CPU | \
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CFG_POST_RTC | \
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CFG_POST_I2C)
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#ifdef CONFIG_POST
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#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
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#else
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#define CFG_CMD_POST_DIAG 0
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#endif
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#endif
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_IDE | \
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CFG_CMD_I2C | \
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CFG_CMD_DATE )
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CFG_CMD_DATE | \
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CFG_CMD_POST_DIAG | \
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CFG_CMD_IDE )
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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@@ -189,7 +247,7 @@
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
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#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x10000
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@@ -201,10 +259,10 @@
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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#if 0
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#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
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#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
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#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
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#if 1
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#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
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#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */
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#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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@@ -220,7 +278,7 @@
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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@@ -69,8 +69,9 @@
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
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"run addhw;diskboot 200000 0:1;bootm 200000\0" \
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"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
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"run addhw;diskboot 200000 2:1;bootm 200000\0" \
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"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
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run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
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usb stop; bootm 200000\0" \
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"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
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"panic_boot=echo No Bootdevice !!! reset\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
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@@ -85,7 +86,7 @@
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"cp.b 200000 40040000 14000\0"
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#define CONFIG_BOOTCOMMAND \
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"run slot_a_boot;run nfs_boot;run panic_boot"
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"run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
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#define CONFIG_MISC_INIT_R 1
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@@ -94,7 +95,7 @@
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#define CONFIG_WATCHDOG 1 /* watchdog enabled */
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#define CONFIG_STATUS_LED 1 /* Status LED enabled */
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@@ -105,19 +106,81 @@
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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#define CONFIG_HARD_I2C
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#define CFG_I2C_SPEED 40000
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#define CFG_I2C_SLAVE 0x7F
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/*
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* enable I2C and select the hardware/software driver
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*/
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
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#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
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#define CFG_I2C_SLAVE 0xFE
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#ifdef CONFIG_SOFT_I2C
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PB_SCL 0x00000020 /* PB 26 */
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#define PB_SDA 0x00000010 /* PB 27 */
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#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
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#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
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#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
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#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
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#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
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else immr->im_cpm.cp_pbdat &= ~PB_SDA
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#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
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else immr->im_cpm.cp_pbdat &= ~PB_SCL
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#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
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#endif /* CONFIG_SOFT_I2C */
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/*-----------------------------------------------------------------------
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* I2C Configuration
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*/
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#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
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#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
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/* List of I2C addresses to be verified by POST */
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#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \
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CFG_I2C_RTC_ADDR, \
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}
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#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
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#define CFG_DISCOVER_PHY
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#if 0
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#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
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#endif
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#undef CONFIG_KUP4K_LOGO
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/* Define to allow the user to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#if 1
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/* POST support */
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#define CONFIG_POST (CFG_POST_CPU | \
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CFG_POST_RTC | \
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CFG_POST_I2C)
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#ifdef CONFIG_POST
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#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
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#else
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#define CFG_CMD_POST_DIAG 0
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#endif
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#endif
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#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
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CFG_CMD_DHCP | \
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CFG_CMD_I2C | \
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CFG_CMD_DATE | \
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CFG_CMD_POST_DIAG | \
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CFG_CMD_IDE | \
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CFG_CMD_USB | \
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CFG_CMD_FAT)
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@@ -196,7 +259,7 @@
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
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#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x10000
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@@ -208,10 +271,10 @@
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/*-----------------------------------------------------------------------
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* Hardware Information Block
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*/
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#if 0
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#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
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#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
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#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
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#if 1
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#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
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#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */
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#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
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#endif
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/*-----------------------------------------------------------------------
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* Cache Configuration
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@@ -227,7 +290,7 @@
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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