Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc1

gpio:
- Add modepin driver

net:
- Save random mac addresses to eth variable

zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses

zynqmp clk:
- Fix clock handling for gem and usb

phy:
- Add zynqmp phy/serdes driver

serial:
- Add one missing compatible string

microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups

zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver

versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain

include/configs/microblaze-generic.h

@@ -21,9 +21,6 @@
 # define CONFIG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
 
-/* setting reset address */
-/*#define	CONFIG_SYS_RESET_ADDRESS	CONFIG_SYS_TEXT_BASE*/
-
 /* Stack location before relocation */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_TEXT_BASE - \
 					 CONFIG_SYS_MALLOC_F_LEN)
@@ -57,8 +54,6 @@
 #define	CONFIG_HOSTNAME		"microblaze-generic"
 
 /* architecture dependent code */
-#define	CONFIG_SYS_USR_EXCEP	/* user exception */
-
 #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
 #define BOOT_TARGET_DEVICES_PXE(func)	func(PXE, pxe, na)
 #else

include/dt-bindings/power/xlnx-versal-power.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
- *  Copyright (C) 2019 - 2020 Xilinx, Inc.
+ *  Copyright (C) 2019 - 2021 Xilinx, Inc.
  */
 
 #ifndef _DT_BINDINGS_VERSAL_POWER_H
@@ -26,6 +26,7 @@
 #define PM_DEV_OSPI				(0x1822402aU)
 #define PM_DEV_QSPI				(0x1822402bU)
 #define PM_DEV_GPIO_PMC				(0x1822402cU)
+#define PM_DEV_I2C_PMC				(0x1822402dU)
 #define PM_DEV_SDIO_0				(0x1822402eU)
 #define PM_DEV_SDIO_1				(0x1822402fU)
 #define PM_DEV_RTC				(0x18224034U)