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Merge tag 'u-boot-rockchip-20210812' of https://source.denx.de/u-boot/custodians/u-boot-rockchip

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- Add Rockchip SFC driver support;
- DTS sync from kernel;
- emmc hs400 support for rk3399;
- Fix for spinore bootdevice and MMC boot order;
This commit is contained in:
Tom Rini
2021-08-12 09:33:39 -04:00
parent a25277122d 60df49d22d
commit 0704305528
63 changed files with 3343 additions and 1251 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/configs/rockchip-common.h
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@@ -14,11 +14,11 @@
#ifndef CONFIG_SPL_BUILD
/* First try to boot from SD (index 0), then eMMC (index 1) */
/* First try to boot from SD (index 1), then eMMC (index 0) */
#if CONFIG_IS_ENABLED(CMD_MMC)
#define BOOT_TARGET_MMC(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1)
func(MMC, mmc, 1) \
func(MMC, mmc, 0)
#else
#define BOOT_TARGET_MMC(func)
#endif

12
include/dt-bindings/clock/rk3188-cru-common.h
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@@ -1,4 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
@@ -59,12 +59,14 @@
#define ACLK_LCDC1 196
#define ACLK_GPU 197
#define ACLK_SMC 198
#define ACLK_CIF 199
#define ACLK_CIF1 199
#define ACLK_IPP 200
#define ACLK_RGA 201
#define ACLK_CIF0 202
#define ACLK_CPU 203
#define ACLK_PERI 204
#define ACLK_VEPU 205
#define ACLK_VDPU 206
/* pclk gates */
#define PCLK_GRF 320
@@ -125,8 +127,12 @@
#define HCLK_NANDC0 467
#define HCLK_CPU 468
#define HCLK_PERI 469
#define HCLK_CIF1 470
#define HCLK_VEPU 471
#define HCLK_VDPU 472
#define HCLK_HDMI 473
#define CLK_NR_CLKS (HCLK_PERI + 1)
#define CLK_NR_CLKS (HCLK_HDMI + 1)
/* soft-reset indices */
#define SRST_MCORE 2

24
include/dt-bindings/power/rk3188-power.h Normal file
View File

@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__
#define __DT_BINDINGS_POWER_RK3188_POWER_H__
/* VD_CORE */
#define RK3188_PD_A9_0 0
#define RK3188_PD_A9_1 1
#define RK3188_PD_A9_2 2
#define RK3188_PD_A9_3 3
#define RK3188_PD_DBG 4
#define RK3188_PD_SCU 5
/* VD_LOGIC */
#define RK3188_PD_VIDEO 6
#define RK3188_PD_VIO 7
#define RK3188_PD_GPU 8
#define RK3188_PD_PERI 9
#define RK3188_PD_CPU 10
#define RK3188_PD_ALIVE 11
/* VD_PMU */
#define RK3188_PD_RTC 12
#endif