mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge tag 'qcom-for-2026.01-rc2' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
A variety of Qualcomm features/fixes for this cycle, notably with a few
new platforms gaining support:
* Initial support for SDM670 (similar to SDM845), SM6350, and SM7150
platforms is added
* USB and UART issues on MSM8916 are addressed (improving stability/
reliability)
* Firmware loading is implemented for the GENI serial engine, this is
used on some platforms to load firmware for i2c/spi/uart to work
Some additional patches like binman support for building MBN files still
need some additional work.
CI: 8ef6ac07b3/pipelines
This commit is contained in:
Tom Rini
@@ -6,6 +6,13 @@
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#ifndef _QCOM_GENI_SE
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#define _QCOM_GENI_SE
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enum geni_se_xfer_mode {
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GENI_SE_INVALID,
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GENI_SE_FIFO,
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GENI_SE_DMA,
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GENI_GPI_DMA,
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};
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/* Protocols supported by GENI Serial Engines */
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enum geni_se_protocol_type {
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GENI_SE_NONE,
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@@ -14,6 +21,7 @@ enum geni_se_protocol_type {
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GENI_SE_I2C,
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GENI_SE_I3C,
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GENI_SE_SPI_SLAVE,
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GENI_SE_INVALID_PROTO = 255,
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};
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#define QUP_HW_VER_REG 0x4
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@@ -29,6 +37,7 @@ enum geni_se_protocol_type {
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#define GENI_SER_S_CLK_CFG 0x4c
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#define GENI_IF_DISABLE_RO 0x64
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#define GENI_FW_REVISION_RO 0x68
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#define GENI_DFS_IF_CFG 0x80
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#define SE_GENI_CLK_SEL 0x7c
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#define SE_GENI_CFG_SEQ_START 0x84
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#define SE_GENI_BYTE_GRAN 0x254
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@@ -57,15 +66,24 @@ enum geni_se_protocol_type {
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#define SE_GENI_IOS 0x908
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#define SE_DMA_TX_IRQ_STAT 0xc40
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#define SE_DMA_TX_IRQ_CLR 0xc44
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#define SE_DMA_TX_IRQ_EN_SET 0xc4c
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#define SE_DMA_TX_FSM_RST 0xc58
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#define SE_DMA_RX_IRQ_STAT 0xd40
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#define SE_DMA_RX_IRQ_CLR 0xd44
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#define SE_DMA_RX_IRQ_EN_SET 0xd4c
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#define SE_DMA_RX_LEN_IN 0xd54
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#define SE_DMA_RX_FSM_RST 0xd58
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#define SE_GSI_EVENT_EN 0xe18
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#define SE_IRQ_EN 0xe1c
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#define SE_HW_PARAM_0 0xe24
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#define SE_HW_PARAM_1 0xe28
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#define SE_DMA_GENERAL_CFG 0xe30
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/* GENI_DFS_IF_CFG fields */
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#define DFS_IF_EN BIT(0)
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/* SE_DMA_RX_IRQ_EN_SET fields */
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#define RESET_DONE_EN_SET BIT(3)
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/* GENI_FORCE_DEFAULT_REG fields */
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#define FORCE_DEFAULT BIT(0)
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@@ -262,4 +280,22 @@ enum geni_se_protocol_type {
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/* QUP SE VERSION value for major number 2 and minor number 5 */
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#define QUP_SE_VERSION_2_5 0x20050000
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/* SE_DMA_GENERAL_CFG */
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#define DMA_RX_CLK_CGC_ON BIT(0)
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#define DMA_TX_CLK_CGC_ON BIT(1)
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#define DMA_AHB_SLV_CFG_ON BIT(2)
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#define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
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#define DUMMY_RX_NON_BUFFERABLE BIT(4)
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#define RX_DMA_ZERO_PADDING_EN BIT(5)
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#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
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#define RX_DMA_IRQ_DELAY_SHFT 6
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#define GENI_SE_DMA_DONE_EN BIT(0)
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#define GENI_SE_DMA_EOT_EN BIT(1)
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#define GENI_SE_DMA_AHB_ERR_EN BIT(2)
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#define GENI_SE_DMA_EOT_BUF BIT(0)
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#define GENI_DMA_MODE_EN BIT(0)
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#endif
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178
include/soc/qcom/qup-fw-load.h
Normal file
178
include/soc/qcom/qup-fw-load.h
Normal file
@@ -0,0 +1,178 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _LINUX_QCOM_QUP_FW_LOAD
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#define _LINUX_QCOM_QUP_FW_LOAD
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#include <linux/kernel.h>
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/*Magic numbers*/
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#define MAGIC_NUM_SE 0x57464553
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/* Common SE registers*/
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#define GENI_INIT_CFG_REVISION 0x0
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#define GENI_S_INIT_CFG_REVISION 0x4
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#define GENI_FORCE_DEFAULT_REG 0x20
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#define GENI_CGC_CTRL 0x28
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#define GENI_CFG_REG0 0x100
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#define QUPV3_SE_HW_PARAM_1 0xE28
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#define RX_FIFO_WIDTH_BIT 24
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#define RX_FIFO_WIDTH_MASK 0x3F
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/*Same registers as GENI_DMA_MODE_EN*/
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#define QUPV3_SE_GENI_DMA_MODE_EN 0x258
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#define GENI_M_IRQ_ENABLE 0x614
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#define GENI_S_IRQ_ENABLE 0x644
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#define GENI_RX_RFR_WATERMARK_REG 0x814
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#define DMA_TX_IRQ_EN_SET 0xC4C
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#define DMA_RX_IRQ_EN_SET 0xD4C
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#define DMA_GENERAL_CFG 0xE30
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#define SE_GENI_FW_REVISION 0x1000
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#define SE_S_FW_REVISION 0x1004
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#define SE_GENI_CFG_RAMN 0x1010
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#define SE_GENI_CLK_CTRL 0x2000
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#define SE_DMA_IF_EN 0x2004
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#define SE_FIFO_IF_DISABLE 0x2008
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#define MAX_GENI_CFG_RAMn_CNT 455
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#define MI_PBT_NON_PAGED_SEGMENT 0x0
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#define MI_PBT_HASH_SEGMENT 0x2
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#define MI_PBT_NOTUSED_SEGMENT 0x3
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#define MI_PBT_SHARED_SEGMENT 0x4
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#define MI_PBT_FLAG_PAGE_MODE_MASK 0x100000
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#define MI_PBT_FLAG_PAGE_MODE_SHIFT 0x14
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#define MI_PBT_FLAG_SEGMENT_TYPE_MASK 0x7000000
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#define MI_PBT_FLAG_SEGMENT_TYPE_SHIFT 0x18
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#define MI_PBT_FLAG_ACCESS_TYPE_MASK 0xE00000
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#define MI_PBT_FLAG_ACCESS_TYPE_SHIFT 0x15
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#define MI_PBT_PAGE_MODE_VALUE(x) \
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(((x) & MI_PBT_FLAG_PAGE_MODE_MASK) >> \
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MI_PBT_FLAG_PAGE_MODE_SHIFT)
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#define MI_PBT_SEGMENT_TYPE_VALUE(x) \
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(((x) & MI_PBT_FLAG_SEGMENT_TYPE_MASK) >> \
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MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)
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#define MI_PBT_ACCESS_TYPE_VALUE(x) \
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(((x) & MI_PBT_FLAG_ACCESS_TYPE_MASK) >> \
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MI_PBT_FLAG_ACCESS_TYPE_SHIFT)
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/* GENI_FORCE_DEFAULT_REG fields */
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#define FORCE_DEFAULT BIT(0)
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/* FW_REVISION_RO fields */
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#define FW_REV_PROTOCOL_SHFT 8
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#define FW_REV_VERSION_SHFT 0
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#define GENI_FW_REVISION_RO 0x68
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#define GENI_S_FW_REVISION_RO 0x6C
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/* SE_GENI_DMA_MODE_EN */
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#define GENI_DMA_MODE_EN BIT(0)
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/* GENI_M_IRQ_EN fields */
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#define M_CMD_DONE_EN BIT(0)
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#define M_IO_DATA_DEASSERT_EN BIT(22)
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#define M_IO_DATA_ASSERT_EN BIT(23)
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#define M_RX_FIFO_RD_ERR_EN BIT(24)
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#define M_RX_FIFO_WR_ERR_EN BIT(25)
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#define M_RX_FIFO_WATERMARK_EN BIT(26)
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#define M_RX_FIFO_LAST_EN BIT(27)
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#define M_TX_FIFO_RD_ERR_EN BIT(28)
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#define M_TX_FIFO_WR_ERR_EN BIT(29)
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#define M_TX_FIFO_WATERMARK_EN BIT(30)
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#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
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M_IO_DATA_DEASSERT_EN | \
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M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
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M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
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M_TX_FIFO_WR_ERR_EN)
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/* GENI_S_IRQ_EN fields */
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#define S_CMD_OVERRUN_EN BIT(1)
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#define S_ILLEGAL_CMD_EN BIT(2)
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#define S_CMD_CANCEL_EN BIT(4)
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#define S_CMD_ABORT_EN BIT(5)
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#define S_GP_IRQ_0_EN BIT(9)
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#define S_GP_IRQ_1_EN BIT(10)
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#define S_GP_IRQ_2_EN BIT(11)
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#define S_GP_IRQ_3_EN BIT(12)
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#define S_RX_FIFO_RD_ERR_EN BIT(24)
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#define S_RX_FIFO_WR_ERR_EN BIT(25)
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#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
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S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
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#define GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK 0x00000200
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#define GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK 0x00000100
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#define GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK 0x00000001
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#define DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008
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#define DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004
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#define DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001
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#define DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK 0x00000010
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#define DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008
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#define DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004
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#define DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001
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#define DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK 0x00000008
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#define DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK 0x00000004
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#define DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK 0x00000002
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#define DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK 0x00000001
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#define GENI_CLK_CTRL_SER_CLK_SEL_BMSK 0x00000001
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#define DMA_IF_EN_DMA_IF_EN_BMSK 0x00000001
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#define SE_GSI_EVENT_EN_BMSK 0x0000000f
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#define SE_IRQ_EN_RMSK 0x0000000f
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#define QUPV3_COMMON_CFG 0x0120
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#define FAST_SWITCH_TO_HIGH_DISABLE_BMASK 0x00000001
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#define QUPV3_SE_AHB_M_CFG 0x0118
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#define AHB_M_CLK_CGC_ON_BMASK 0x00000001
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#define QUPV3_COMMON_CGC_CTRL 0x021C
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#define COMMON_CSR_SLV_CLK_CGC_ON_BMASK 0x00000001
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/* access ports */
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#define geni_setbits32(_addr, _v) writel_relaxed(readl_relaxed(_addr) | (_v), (_addr))
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#define geni_clrbits32(_addr, _v) writel_relaxed(readl_relaxed(_addr) & ~(_v), (_addr))
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/**
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* struct elf_se_hdr - firmware configurations
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*
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* @magic: set to 'SEFW'
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* @version: A 32-bit value indicating the structure’s version number
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* @core_version: QUPV3_HW_VERSION
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* @serial_protocol: Programmed into GENI_FW_REVISION
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* @fw_version: Programmed into GENI_FW_REVISION
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* @cfg_version: Programmed into GENI_INIT_CFG_REVISION
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* @fw_size_in_items: Number of (uint32_t) GENI_FW_RAM words
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* @fw_offset: Byte offset of GENI_FW_RAM array
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* @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs
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* @cfg_idx_offset: Byte offset of GENI_FW_CFG index array
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* @cfg_val_offset: Byte offset of GENI_FW_CFG values array
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*/
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struct elf_se_hdr {
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u32 magic;
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u32 version;
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u32 core_version;
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u16 serial_protocol;
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u16 fw_version;
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u16 cfg_version;
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u16 fw_size_in_items;
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u16 fw_offset;
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u16 cfg_size_in_items;
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u16 cfg_idx_offset;
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u16 cfg_val_offset;
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};
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struct udevice;
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int qcom_geni_load_firmware(phys_addr_t qup_base, struct udevice *dev);
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#endif /* _LINUX_QCOM_QUP_FW_LOAD */
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