From daf1312b07208f231a5b27a7edecca5a7d50196b Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 10:06:29 +0800 Subject: [PATCH 01/14] riscv: global_data.h: Correct the comment for PLICSW PLIC is used for external interrupt, while PLICSW is an Andes-specific design for software interrupt. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/include/asm/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index 6fdc86dd8b1..31ba72693d7 100644 --- a/arch/riscv/include/asm/global_data.h +++ b/arch/riscv/include/asm/global_data.h @@ -22,7 +22,7 @@ struct arch_global_data { void __iomem *clint; /* clint base address */ #endif #ifdef CONFIG_ANDES_PLICSW - void __iomem *plicsw; /* plic base address */ + void __iomem *plicsw; /* andes plicsw base address */ #endif #if CONFIG_IS_ENABLED(SMP) struct ipi_data ipi[CONFIG_NR_CPUS]; From 55ca747f66742d15829f8706a633849d9013bab5 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Mon, 6 Feb 2023 16:10:44 +0800 Subject: [PATCH 02/14] riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" There is no need for RISCV_NDS_CACHE config to control cache switches. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen --- arch/riscv/cpu/ax25/Kconfig | 10 ----- arch/riscv/cpu/ax25/cache.c | 84 +------------------------------------ drivers/cache/Kconfig | 1 - 3 files changed, 2 insertions(+), 93 deletions(-) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 4a7295d30c5..eca68ea2a7c 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -12,13 +12,3 @@ config RISCV_NDS help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. - -if RISCV_NDS - -config RISCV_NDS_CACHE - bool "AndeStar V5 families specific cache support" - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - Provide Andes Technology AndeStar V5 families specific cache support. - -endif diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 35f23c748d1..1c0c3772a11 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -67,106 +67,26 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void icache_enable(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif } void icache_disable(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "fence.i\n\t" - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x1\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#endif -#endif } void dcache_enable(void) { -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "ori t0, t1, 0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_enable(); -#endif -#endif -#endif } void dcache_disable(void) { -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi t0, t1, ~0x2\n\t" - "csrw mcache_ctl, t0\n\t" - ); -#endif -#ifdef CONFIG_V5L2_CACHE - _cache_disable(); -#endif -#endif -#endif } int icache_status(void) { - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x01\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; + return 0; } int dcache_status(void) { - int ret = 0; - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) - asm volatile ( - "csrr t1, mcache_ctl\n\t" - "andi %0, t1, 0x02\n\t" - : "=r" (ret) - : - : "memory" - ); -#endif -#endif - - return ret; + return 0; } diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 40f41a817c9..6cb8c3e980c 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -25,7 +25,6 @@ config L2X0_CACHE config V5L2_CACHE bool "Andes V5L2 cache driver" select CACHE - depends on RISCV_NDS_CACHE help Support Andes V5L2 cache controller in AE350 platform. It will configure tag and data ram timing control from the From e74e21ceb3fe476e09b4068b4f986aabed2c9463 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:45 +0800 Subject: [PATCH 03/14] board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init() The L2-cache is not enabled currently, the enbale_caches() will call the v5l2_enable() callback to enable it in SPL. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index 63a966e0924..1c2288b6ce9 100644 --- a/board/AndesTech/ax25-ae350/ax25-ae350.c +++ b/board/AndesTech/ax25-ae350/ax25-ae350.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -72,6 +73,14 @@ void *board_fdt_blob_setup(int *err) return NULL; } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init() +{ + /* enable v5l2 cache */ + enable_caches(); +} +#endif + int smc_init(void) { int node = -1; @@ -96,18 +105,10 @@ int smc_init(void) return 0; } -static void v5l2_init(void) -{ - struct udevice *dev; - - uclass_get_device(UCLASS_CACHE, 0, &dev); -} - #ifdef CONFIG_BOARD_EARLY_INIT_F int board_early_init_f(void) { smc_init(); - v5l2_init(); return 0; } From 51415fa634d2ff0e2d10eeefb739cdb941d19412 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:46 +0800 Subject: [PATCH 04/14] driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform The L2C configuration register has MAP field to indicate its version is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver compatible with both memory-mapped scheme. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- drivers/cache/cache-v5l2.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index bbdb76bd574..e782430c574 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -34,6 +34,14 @@ struct l2cache { volatile u64 cctl_status; }; +/* Configuration register */ +#define MEM_MAP_OFF 20 +#define MEM_MAP_MSK BIT(MEM_MAP_OFF) +/* offset of v0 memory map (Gen1) */ +static u32 cmd_stride = 0x10; +static u32 status_stride = 0x0; +static u32 status_bit_offset = 0x4; + /* Control Register */ #define L2_ENABLE 0x1 /* prefetch */ @@ -53,14 +61,15 @@ struct l2cache { #define DRAMICTL_MSK BIT(DRAMICTL_OFF) /* CCTL Command Register */ -#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10) +#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * (cmd_stride)) #define L2_WBINVAL_ALL 0x12 /* CCTL Status Register */ -#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4)) -#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4)) -#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4)) -#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4)) +#define CCTL_STATUS_REG(base, hart) ((ulong)(base) + 0x80 + (hart) * (status_stride)) +#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * (status_bit_offset))) +#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * (status_bit_offset))) DECLARE_GLOBAL_DATA_PTR; @@ -133,12 +142,19 @@ static int v5l2_probe(struct udevice *dev) { struct v5l2_plat *plat = dev_get_plat(dev); struct l2cache *regs = plat->regs; - u32 ctl_val; + u32 cfg_val, ctl_val; + cfg_val = readl(®s->configure); ctl_val = readl(®s->control); - if (!(ctl_val & L2_ENABLE)) - ctl_val |= L2_ENABLE; + /* If true, v1 memory map (Gen2) */ + if (cfg_val & MEM_MAP_MSK) { + cmd_stride = 0x1000; + status_stride = 0x1000; + status_bit_offset = 0x0; + } + + ctl_val |= L2_ENABLE; if (plat->iprefetch != -EINVAL) { ctl_val &= ~(IPREPETCH_MSK); From d8a146d19b9a39a9b90aa40c8e61c5d0ddfa17e5 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:47 +0800 Subject: [PATCH 05/14] riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init() As the OpenSBI v1.2 does not enable the cache [0], we enable the i/d-cache in harts_early_init() and do not disable in cleanup_before_linux(). This patch also simplifies the logic and moves the CSR encoding to include/asm/arch-andes/csr.h. [0] https://github.com/riscv-software-src/opensbi/commit/bd7ef4139829da5c30fa980f7498d385124408fa Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/cpu/ax25/cpu.c | 49 ++++++------------------- arch/riscv/include/asm/arch-andes/csr.h | 31 ++++++++++++++++ 2 files changed, 43 insertions(+), 37 deletions(-) create mode 100644 arch/riscv/include/asm/arch-andes/csr.h diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index a46674f7c25..06e379bcb1f 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Andes Technology Corporation + * Copyright (C) 2023 Andes Technology Corporation * Rick Chen, Andes Technology Corporation */ @@ -10,23 +10,7 @@ #include #include #include - -#define CSR_MCACHE_CTL 0x7ca -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 - -#define V5_MCACHE_CTL_IC_EN_OFFSET 0 -#define V5_MCACHE_CTL_DC_EN_OFFSET 1 -#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 -#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) -#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) - +#include /* * cleanup_before_linux() is called just before we call linux @@ -38,38 +22,29 @@ int cleanup_before_linux(void) { disable_interrupts(); - /* turn off I/D-cache */ cache_flush(); - icache_disable(); - dcache_disable(); return 0; } void harts_early_init(void) { + /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) { - unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + + mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN | + MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN); - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) - mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; - if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN)) - mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN; csr_write(CSR_MCACHE_CTL, mcache_ctl_val); /* - * Check DC_COHEN_EN, if cannot write to mcache_ctl, - * we assume this bitmap not support L2 CM + * Check mcache_ctl.DC_COHEN, we assume this platform does + * not support CM if the bit is hard-wired to 0. */ - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); - if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) { - /* Wait for DC_COHSTA bit be set */ - while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN)) - mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) { + /* Wait for DC_COHSTA bit to be set */ + while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); } } } diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h new file mode 100644 index 00000000000..c7ed920cde5 --- /dev/null +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ + +#ifndef _ASM_ANDES_CSR_H +#define _ASM_ANDES_CSR_H + +#include +#include + +#define CSR_MCACHE_CTL 0x7ca +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 +#define CSR_MCCTLCOMMAND 0x7cc + +#define MCACHE_CTL_IC_EN_OFFSET 0 +#define MCACHE_CTL_DC_EN_OFFSET 1 +#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 +#define MCACHE_CTL_DC_COHEN_OFFSET 19 +#define MCACHE_CTL_DC_COHSTA_OFFSET 20 + +#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) +#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) +#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) +#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) +#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) + +#define CCTL_L1D_WBINVAL_ALL 6 + +#endif /* _ASM_ANDES_CSR_H */ From c1b88196807e1dd797aea6cc7ddb0dce02b4e898 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:48 +0800 Subject: [PATCH 06/14] riscv: ae350: dts: Update L2 cache compatible string Update the compatible string of L2 cache. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/dts/ae350_32.dts | 2 +- arch/riscv/dts/ae350_64.dts | 2 +- drivers/cache/cache-v5l2.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index 96ef8bd8ddb..61af6d5465e 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0xe0500000 0x40000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index cddbaec98ad..8c7db29b4f2 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -112,7 +112,7 @@ }; L2: l2-cache@e0500000 { - compatible = "v5l2cache"; + compatible = "cache"; cache-level = <2>; cache-size = <0x40000>; reg = <0x0 0xe0500000 0x0 0x40000>; diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index e782430c574..c6d3a8f8939 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -184,7 +184,7 @@ static int v5l2_probe(struct udevice *dev) } static const struct udevice_id v5l2_cache_ids[] = { - { .compatible = "v5l2cache" }, + { .compatible = "cache" }, {} }; From 600a708c0551cb31a7f4f553ec9347b0280cf21e Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:49 +0800 Subject: [PATCH 07/14] riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL This patch refines L1 cache enable/disable and v5l2-cache enable functions. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/cpu/ax25/cache.c | 96 ++++++++++++++++++++++++++----------- 1 file changed, 67 insertions(+), 29 deletions(-) diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 1c0c3772a11..40d77f671c8 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -1,57 +1,51 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Andes Technology Corporation + * Copyright (C) 2023 Andes Technology Corporation * Rick Chen, Andes Technology Corporation */ +#include +#include #include +#include #include #include -#include #include -#include -#include - -#ifdef CONFIG_RISCV_NDS_CACHE -#if CONFIG_IS_ENABLED(RISCV_MMODE) -/* mcctlcommand */ -#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc - -/* D-cache operation */ -#define CCTL_L1D_WBINVAL_ALL 6 -#endif -#endif +#include #ifdef CONFIG_V5L2_CACHE -static void _cache_enable(void) +void enable_caches(void) { - struct udevice *dev = NULL; + struct udevice *dev; + int ret; - uclass_find_first_device(UCLASS_CACHE, &dev); - - if (dev) - cache_enable(dev); + ret = uclass_get_device_by_driver(UCLASS_CACHE, + DM_DRIVER_GET(v5l2_cache), + &dev); + if (ret) { + log_debug("Cannot enable v5l2 cache\n"); + } else { + ret = cache_enable(dev); + if (ret) + log_debug("v5l2 cache enable failed\n"); + } } -static void _cache_disable(void) +static void cache_ops(int (*ops)(struct udevice *dev)) { struct udevice *dev = NULL; uclass_find_first_device(UCLASS_CACHE, &dev); if (dev) - cache_disable(dev); + ops(dev); } #endif void flush_dcache_all(void) { -#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) -#ifdef CONFIG_RISCV_NDS_CACHE #if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL); -#endif -#endif + csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); #endif } @@ -67,26 +61,70 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) void icache_enable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif } void icache_disable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x1" :: "i"(CSR_MCACHE_CTL)); +#endif } void dcache_enable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_enable); +#endif } void dcache_disable(void) { +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL)); +#endif + +#ifdef CONFIG_V5L2_CACHE + cache_ops(cache_disable); +#endif } int icache_status(void) { - return 0; + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x01\n\t" + : "=r" (ret) + : "i"(CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; } int dcache_status(void) { - return 0; + int ret = 0; + +#if CONFIG_IS_ENABLED(RISCV_MMODE) + asm volatile ( + "csrr t1, %1\n\t" + "andi %0, t1, 0x02\n\t" + : "=r" (ret) + : "i" (CSR_MCACHE_CTL) + : "memory" + ); +#endif + + return !!ret; } From 487c211ef6720b4226853755322c862be701fd36 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:50 +0800 Subject: [PATCH 08/14] configs: ae350: Enable v5l2 cache for AE350 platforms in SPL To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit: ca06444aac2c643db3a3f2eb37afc60fae15177e Turing on does not significantly increase the size of u-boot-spl.bin, so we enable it by default to improve performance. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- arch/riscv/cpu/ax25/Kconfig | 1 + configs/ae350_rv32_spl_defconfig | 2 ++ configs/ae350_rv32_spl_xip_defconfig | 2 ++ configs/ae350_rv64_spl_defconfig | 2 ++ configs/ae350_rv64_spl_xip_defconfig | 2 ++ 5 files changed, 9 insertions(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index eca68ea2a7c..82bb5a2a532 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -6,6 +6,7 @@ config RISCV_NDS imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE) imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) + imply V5L2_CACHE imply SPL_CPU imply SPL_OPENSBI imply SPL_LOAD_FIT diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index a66db656216..f5bd7a9a7e7 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 606962c0a71..014dcbedf63 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index f235db7990a..51d23d050d5 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -22,6 +22,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 4cbfd52fb19..c44df4b561d 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -23,6 +23,8 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_CACHE=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_IMLS=y From d002b2a187bac1f3da1d0374293a6db8891b7f3b Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:51 +0800 Subject: [PATCH 09/14] configs: ae350: Increase maximum retry count for AE350 platforms Loading an image via TFTP is often interrupted when retrying more than 10 times, increase the number of retries so that it does not simply stop the transfer. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/ae350_rv64_defconfig | 1 + configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 1 + configs/ae350_rv64_xip_defconfig | 1 + 8 files changed, 8 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index e5c8358e54d..a9d158dc8d9 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f5bd7a9a7e7..54587018d5e 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 014dcbedf63..b6261537230 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 069a9d3982e..628522cd4d0 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index c373b99b956..c058f767806 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 51d23d050d5..9664baf7051 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -34,6 +34,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index c44df4b561d..b7548884094 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -35,6 +35,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 4fed2ead1db..380ae096eef 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_CACHE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RETRY_COUNT=50 CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_MMC=y From f29834d150f9650c7d38dac62f601444e9a31238 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:52 +0800 Subject: [PATCH 10/14] configs: ae350: Display CPU and board info for AE350 platforms Display information about CPU and board during start up. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- configs/ae350_rv32_defconfig | 2 ++ configs/ae350_rv32_spl_defconfig | 2 ++ configs/ae350_rv32_spl_xip_defconfig | 2 ++ configs/ae350_rv32_xip_defconfig | 2 ++ configs/ae350_rv64_defconfig | 2 ++ configs/ae350_rv64_spl_defconfig | 2 ++ configs/ae350_rv64_spl_xip_defconfig | 2 ++ configs/ae350_rv64_xip_defconfig | 2 ++ 8 files changed, 16 insertions(+) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index a9d158dc8d9..fd1bf5fa4ff 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -14,6 +14,8 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 54587018d5e..4d3623a8941 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -19,6 +19,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index b6261537230..a076b778342 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -20,6 +20,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index 628522cd4d0..da1bd2b10b1 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -15,6 +15,8 @@ CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index c058f767806..959258176af 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -14,6 +14,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 9664baf7051..0217027e6df 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -19,6 +19,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index b7548884094..5a1fa8b6a15 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -20,6 +20,8 @@ CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_MAX_SIZE=0x100000 CONFIG_SPL_BSS_START_ADDR=0x4000000 diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index 380ae096eef..c3fcbf3d28d 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -15,6 +15,8 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffd70 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x4000000 From da24626d147cdd04e84f88c0196a0131fa22cee7 Mon Sep 17 00:00:00 2001 From: Yu Chien Peter Lin Date: Mon, 6 Feb 2023 16:10:53 +0800 Subject: [PATCH 11/14] driver: cache-v5l2: Fix type casting warning on RV32 This patch fixes following warning for the riscv32 toolchain. drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 122 | regs = (struct l2cache *)dev_read_addr(dev); | ^ Signed-off-by: Yu Chien Peter Lin Reviewed-by: Leo Yu-Chi Liang --- drivers/cache/cache-v5l2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c index c6d3a8f8939..eda07d3f29e 100644 --- a/drivers/cache/cache-v5l2.c +++ b/drivers/cache/cache-v5l2.c @@ -119,7 +119,7 @@ static int v5l2_of_to_plat(struct udevice *dev) struct v5l2_plat *plat = dev_get_plat(dev); struct l2cache *regs; - regs = (struct l2cache *)dev_read_addr(dev); + regs = (struct l2cache *)(uintptr_t)dev_read_addr(dev); plat->regs = regs; plat->iprefetch = -EINVAL; From 8900e2bbecd021b16eee7c344cd6ca0e1ee901f3 Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 Feb 2023 20:42:49 +0800 Subject: [PATCH 12/14] riscv: Rename Andes cpu and board names The current ae350-related defconfigs could also support newer Andes CPU IP, so modify the names of CPU from ax25 to andesv5, and board name from ax25-ae350 to ae350. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 8 ++++---- arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 0 arch/riscv/cpu/{ax25 => andesv5}/Makefile | 0 arch/riscv/cpu/{ax25 => andesv5}/cache.c | 0 arch/riscv/cpu/{ax25 => andesv5}/cpu.c | 0 arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0 arch/riscv/dts/Makefile | 2 +- board/AndesTech/{ax25-ae350 => ae350}/Kconfig | 8 ++++---- .../AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++--- board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +- .../{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 0 configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv32_spl_defconfig | 2 +- configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv32_xip_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 2 +- configs/ae350_rv64_spl_xip_defconfig | 2 +- configs/ae350_rv64_xip_defconfig | 2 +- .../AndesTech/{ax25-ae350.rst => ae350.rst} | 16 ++++++++-------- doc/board/AndesTech/index.rst | 2 +- include/configs/{ax25-ae350.h => ae350.h} | 0 22 files changed, 30 insertions(+), 30 deletions(-) rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (100%) rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%) rename arch/riscv/cpu/{ax25 => andesv5}/cache.c (100%) rename arch/riscv/cpu/{ax25 => andesv5}/cpu.c (100%) rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%) rename board/AndesTech/{ax25-ae350 => ae350}/Kconfig (88%) rename board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS (80%) rename board/AndesTech/{ax25-ae350 => ae350}/Makefile (87%) rename board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} (100%) rename doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} (98%) rename include/configs/{ax25-ae350.h => ae350.h} (100%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index ebc4bef220e..48ca4ff4c4e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -8,8 +8,8 @@ choice prompt "Target select" optional -config TARGET_AX25_AE350 - bool "Support ax25-ae350" +config TARGET_AE350 + bool "Support ae350" config TARGET_MICROCHIP_ICICLE bool "Support Microchip PolarFire-SoC Icicle Board" @@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF Do not enable data cache in SPL. # board-specific options below -source "board/AndesTech/ax25-ae350/Kconfig" +source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_icicle/Kconfig" source "board/sifive/unleashed/Kconfig" @@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig" source "board/sipeed/maix/Kconfig" # platform-specific options below -source "arch/riscv/cpu/ax25/Kconfig" +source "arch/riscv/cpu/andesv5/Kconfig" source "arch/riscv/cpu/fu540/Kconfig" source "arch/riscv/cpu/fu740/Kconfig" source "arch/riscv/cpu/generic/Kconfig" diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig similarity index 100% rename from arch/riscv/cpu/ax25/Kconfig rename to arch/riscv/cpu/andesv5/Kconfig diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile similarity index 100% rename from arch/riscv/cpu/ax25/Makefile rename to arch/riscv/cpu/andesv5/Makefile diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c similarity index 100% rename from arch/riscv/cpu/ax25/cache.c rename to arch/riscv/cpu/andesv5/cache.c diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c similarity index 100% rename from arch/riscv/cpu/ax25/cpu.c rename to arch/riscv/cpu/andesv5/cpu.c diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c similarity index 100% rename from arch/riscv/cpu/ax25/spl.c rename to arch/riscv/cpu/andesv5/spl.c diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 5c15a0f303a..c576c55767f 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb +dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ae350/Kconfig similarity index 88% rename from board/AndesTech/ax25-ae350/Kconfig rename to board/AndesTech/ae350/Kconfig index 4bb33b07936..75815bf99aa 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ae350/Kconfig @@ -1,10 +1,10 @@ -if TARGET_AX25_AE350 +if TARGET_AE350 config SYS_CPU - default "ax25" + default "andesv5" config SYS_BOARD - default "ax25-ae350" + default "ae350" config SYS_VENDOR default "AndesTech" @@ -13,7 +13,7 @@ config SYS_SOC default "ae350" config SYS_CONFIG_NAME - default "ax25-ae350" + default "ae350" config ENV_SIZE default 0x2000 if ENV_IS_IN_SPI_FLASH diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS b/board/AndesTech/ae350/MAINTAINERS similarity index 80% rename from board/AndesTech/ax25-ae350/MAINTAINERS rename to board/AndesTech/ae350/MAINTAINERS index eebee167c3b..ead8e0e2afb 100644 --- a/board/AndesTech/ax25-ae350/MAINTAINERS +++ b/board/AndesTech/ae350/MAINTAINERS @@ -1,8 +1,8 @@ -AX25-AE350 BOARD +AE350 BOARD M: Rick Chen S: Maintained -F: board/AndesTech/ax25-ae350/ -F: include/configs/ax25-ae350.h +F: board/AndesTech/ae350/ +F: include/configs/ae350.h F: configs/ae350_rv32_defconfig F: configs/ae350_rv64_defconfig F: configs/ae350_rv32_xip_defconfig diff --git a/board/AndesTech/ax25-ae350/Makefile b/board/AndesTech/ae350/Makefile similarity index 87% rename from board/AndesTech/ax25-ae350/Makefile rename to board/AndesTech/ae350/Makefile index 0e4ba8d7029..705ae43af5d 100644 --- a/board/AndesTech/ax25-ae350/Makefile +++ b/board/AndesTech/ae350/Makefile @@ -3,4 +3,4 @@ # Copyright (C) 2017 Andes Technology Corporation. # Rick Chen, Andes Technology Corporation -obj-y := ax25-ae350.o +obj-y := ae350.o diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ae350/ae350.c similarity index 100% rename from board/AndesTech/ax25-ae350/ax25-ae350.c rename to board/AndesTech/ae350/ae350.c diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index fd1bf5fa4ff..953cd0700b9 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 4d3623a8941..d61f7f5d1d6 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index a076b778342..e59ba0c38a9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index da1bd2b10b1..926632137d6 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index 959258176af..3c18562ad4c 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 0217027e6df..cb69514a7e3 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -8,7 +8,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 5a1fa8b6a15..e0773fa0aae 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -9,7 +9,7 @@ CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig index c3fcbf3d28d..0d467b9836c 100644 --- a/configs/ae350_rv64_xip_defconfig +++ b/configs/ae350_rv64_xip_defconfig @@ -6,7 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_LOAD_ADDR=0x100000 -CONFIG_TARGET_AX25_AE350=y +CONFIG_TARGET_AE350=y CONFIG_ARCH_RV64I=y CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ae350.rst similarity index 98% rename from doc/board/AndesTech/ax25-ae350.rst rename to doc/board/AndesTech/ae350.rst index b46f427f4b7..42a2b4d0b5e 100644 --- a/doc/board/AndesTech/ax25-ae350.rst +++ b/doc/board/AndesTech/ae350.rst @@ -1,20 +1,20 @@ .. SPDX-License-Identifier: GPL-2.0+ -AX25-AE350 -========== +AE350 +====== -AE350 is the mainline SoC produced by Andes Technology using AX25 CPU core -base on RISC-V architecture. +AE350 is the mainline SoC produced by Andes Technology using AndesV5 CPU core +based on RISC-V architecture. AE350 has integrated both AHB and APB bus and many periphals for application and product development. -AX25-AE350 is the SoC with AE350 hardcore CPU. +AndesV5 is Andes CPU IP family that adopts RISC-V architecture. -AX25 is Andes CPU IP to adopt RISC-V architecture. +AndesV5 family includes 25, 27, 45 series. -AX25 Features -------------- +25-Series Features +------------------ CPU Core - 5-stage in-order execution pipeline diff --git a/doc/board/AndesTech/index.rst b/doc/board/AndesTech/index.rst index d8f7d155fc2..cacc5791a91 100644 --- a/doc/board/AndesTech/index.rst +++ b/doc/board/AndesTech/index.rst @@ -7,4 +7,4 @@ Andes Tech :maxdepth: 2 adp-ag101p - ax25-ae350 + ae350 diff --git a/include/configs/ax25-ae350.h b/include/configs/ae350.h similarity index 100% rename from include/configs/ax25-ae350.h rename to include/configs/ae350.h From 68bda014812562de1d8ce0485ffe9fdea62fe9dd Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Tue, 14 Feb 2023 20:42:50 +0800 Subject: [PATCH 13/14] riscv: ae350: Adjust the memory layout of ae350 Adjust the initial stack pointer address to 0x10000000(256M) Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin Reviewed-by: Rick Chen --- configs/ae350_rv32_spl_defconfig | 6 +++--- configs/ae350_rv32_spl_xip_defconfig | 6 +++--- configs/ae350_rv64_spl_defconfig | 6 +++--- configs/ae350_rv64_spl_xip_defconfig | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index d61f7f5d1d6..61475d199d6 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " @@ -12,8 +14,6 @@ CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e59ba0c38a9..b505cec9f80 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x80000000 @@ -13,8 +15,6 @@ CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index cb69514a7e3..36a6d04ef36 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " @@ -13,8 +15,6 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index e0773fa0aae..0b70e85c189 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x01200000 +CONFIG_TEXT_BASE=0x01800000 CONFIG_SYS_MALLOC_LEN=0x80000 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x10000000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x80000000 @@ -14,8 +16,6 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 From 7574b6476afc1fd76816be6567458f6ca4f44234 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Fri, 17 Feb 2023 16:57:01 +0800 Subject: [PATCH 14/14] riscv: binman: Add help message for missing blobs Add the 'missing-msg' for more detailed output on missing system firmware. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Yu Chien Peter Lin --- arch/riscv/dts/binman.dtsi | 1 + tools/binman/missing-blob-help | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi index b8fc8f7f35e..156cb00971e 100644 --- a/arch/riscv/dts/binman.dtsi +++ b/arch/riscv/dts/binman.dtsi @@ -45,6 +45,7 @@ opensbi_blob: opensbi { filename = "fw_dynamic.bin"; + missing-msg = "opensbi"; }; }; diff --git a/tools/binman/missing-blob-help b/tools/binman/missing-blob-help index c61ca02a35e..4448ac93112 100644 --- a/tools/binman/missing-blob-help +++ b/tools/binman/missing-blob-help @@ -37,3 +37,9 @@ https://github.com/siemens/k3-rti-wdt. tee-os: See the documentation for your board. You may need to build Open Portable Trusted Execution Environment (OP-TEE) with TEE=/path/to/tee.bin + +opensbi: +See the documentation for your board. The OpenSBI git repo is at +https://github.com/riscv/opensbi.git +You may need to build fw_dynamic.bin first and re-build u-boot with +OPENSBI=/path/to/fw_dynamic.bin