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imx8mp: synchronise device tree with linux

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Synchronise device tree with linux v6.1-rc3.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
This commit is contained in:
Marcel Ziswiler
2022-11-07 22:22:39 +01:00
committed by Stefano Babic
parent cb9b70fd2f
commit 0b42fdca2d
14 changed files with 686 additions and 208 deletions
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13
include/dt-bindings/clock/imx8mp-clock.h
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@@ -117,7 +117,6 @@
#define IMX8MP_CLK_AUDIO_AHB 108
#define IMX8MP_CLK_MIPI_DSI_ESC_RX 109
#define IMX8MP_CLK_IPG_ROOT 110
#define IMX8MP_CLK_IPG_AUDIO_ROOT 111
#define IMX8MP_CLK_DRAM_ALT 112
#define IMX8MP_CLK_DRAM_APB 113
#define IMX8MP_CLK_VPU_G1 114
@@ -125,7 +124,6 @@
#define IMX8MP_CLK_CAN1 116
#define IMX8MP_CLK_CAN2 117
#define IMX8MP_CLK_MEMREPAIR 118
#define IMX8MP_CLK_PCIE_PHY 119
#define IMX8MP_CLK_PCIE_AUX 120
#define IMX8MP_CLK_I2C5 121
#define IMX8MP_CLK_I2C6 122
@@ -182,8 +180,6 @@
#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
#define IMX8MP_CLK_MEDIA_LDB 174
#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
#define IMX8MP_CLK_PCIE2_CTRL 176
#define IMX8MP_CLK_PCIE2_PHY 177
#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
#define IMX8MP_CLK_ECSPI3 179
#define IMX8MP_CLK_PDM 180
@@ -321,8 +317,15 @@
#define IMX8MP_CLK_AUDIO_AXI 310
#define IMX8MP_CLK_HSIO_AXI 311
#define IMX8MP_CLK_MEDIA_ISP 312
#define IMX8MP_CLK_MEDIA_DISP2_PIX 313
#define IMX8MP_CLK_CLKOUT1_SEL 314
#define IMX8MP_CLK_CLKOUT1_DIV 315
#define IMX8MP_CLK_CLKOUT1 316
#define IMX8MP_CLK_CLKOUT2_SEL 317
#define IMX8MP_CLK_CLKOUT2_DIV 318
#define IMX8MP_CLK_CLKOUT2 319
#define IMX8MP_CLK_END 313
#define IMX8MP_CLK_END 320
#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0
#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1

59
include/dt-bindings/interconnect/fsl,imx8mp.h Normal file
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@@ -0,0 +1,59 @@
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
/*
* Interconnect framework driver for i.MX SoC
*
* Copyright 2022 NXP
* Peng Fan <peng.fan@nxp.com>
*/
#ifndef __DT_BINDINGS_INTERCONNECT_IMX8MP_H
#define __DT_BINDINGS_INTERCONNECT_IMX8MP_H
#define IMX8MP_ICN_NOC 0
#define IMX8MP_ICN_MAIN 1
#define IMX8MP_ICS_DRAM 2
#define IMX8MP_ICS_OCRAM 3
#define IMX8MP_ICM_A53 4
#define IMX8MP_ICM_SUPERMIX 5
#define IMX8MP_ICM_GIC 6
#define IMX8MP_ICM_MLMIX 7
#define IMX8MP_ICN_AUDIO 8
#define IMX8MP_ICM_DSP 9
#define IMX8MP_ICM_SDMA2PER 10
#define IMX8MP_ICM_SDMA2BURST 11
#define IMX8MP_ICM_SDMA3PER 12
#define IMX8MP_ICM_SDMA3BURST 13
#define IMX8MP_ICM_EDMA 14
#define IMX8MP_ICN_GPU 15
#define IMX8MP_ICM_GPU2D 16
#define IMX8MP_ICM_GPU3D 17
#define IMX8MP_ICN_HDMI 18
#define IMX8MP_ICM_HRV 19
#define IMX8MP_ICM_LCDIF_HDMI 20
#define IMX8MP_ICM_HDCP 21
#define IMX8MP_ICN_HSIO 22
#define IMX8MP_ICM_NOC_PCIE 23
#define IMX8MP_ICM_USB1 24
#define IMX8MP_ICM_USB2 25
#define IMX8MP_ICM_PCIE 26
#define IMX8MP_ICN_MEDIA 27
#define IMX8MP_ICM_LCDIF_RD 28
#define IMX8MP_ICM_LCDIF_WR 29
#define IMX8MP_ICM_ISI0 30
#define IMX8MP_ICM_ISI1 31
#define IMX8MP_ICM_ISI2 32
#define IMX8MP_ICM_ISP0 33
#define IMX8MP_ICM_ISP1 34
#define IMX8MP_ICM_DWE 35
#define IMX8MP_ICN_VIDEO 36
#define IMX8MP_ICM_VPU_G1 37
#define IMX8MP_ICM_VPU_G2 38
#define IMX8MP_ICM_VPU_H1 39
#endif /* __DT_BINDINGS_INTERCONNECT_IMX8MP_H */

21
include/dt-bindings/power/imx8mp-power.h
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@@ -38,9 +38,22 @@
#define IMX8MP_MEDIABLK_PD_ISI 3
#define IMX8MP_MEDIABLK_PD_MIPI_CSI2_2 4
#define IMX8MP_MEDIABLK_PD_LCDIF_2 5
#define IMX8MP_MEDIABLK_PD_ISP2 6
#define IMX8MP_MEDIABLK_PD_ISP1 7
#define IMX8MP_MEDIABLK_PD_DWE 8
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 9
#define IMX8MP_MEDIABLK_PD_ISP 6
#define IMX8MP_MEDIABLK_PD_DWE 7
#define IMX8MP_MEDIABLK_PD_MIPI_DSI_2 8
#define IMX8MP_HDMIBLK_PD_IRQSTEER 0
#define IMX8MP_HDMIBLK_PD_LCDIF 1
#define IMX8MP_HDMIBLK_PD_PAI 2
#define IMX8MP_HDMIBLK_PD_PVI 3
#define IMX8MP_HDMIBLK_PD_TRNG 4
#define IMX8MP_HDMIBLK_PD_HDMI_TX 5
#define IMX8MP_HDMIBLK_PD_HDMI_TX_PHY 6
#define IMX8MP_HDMIBLK_PD_HDCP 7
#define IMX8MP_HDMIBLK_PD_HRV 8
#define IMX8MP_VPUBLK_PD_G1 0
#define IMX8MP_VPUBLK_PD_G2 1
#define IMX8MP_VPUBLK_PD_VC8000E 2
#endif

50
include/dt-bindings/reset/imx8mp-reset.h Normal file
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@@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright 2020 NXP
*/
#ifndef DT_BINDING_RESET_IMX8MP_H
#define DT_BINDING_RESET_IMX8MP_H
#define IMX8MP_RESET_A53_CORE_POR_RESET0 0
#define IMX8MP_RESET_A53_CORE_POR_RESET1 1
#define IMX8MP_RESET_A53_CORE_POR_RESET2 2
#define IMX8MP_RESET_A53_CORE_POR_RESET3 3
#define IMX8MP_RESET_A53_CORE_RESET0 4
#define IMX8MP_RESET_A53_CORE_RESET1 5
#define IMX8MP_RESET_A53_CORE_RESET2 6
#define IMX8MP_RESET_A53_CORE_RESET3 7
#define IMX8MP_RESET_A53_DBG_RESET0 8
#define IMX8MP_RESET_A53_DBG_RESET1 9
#define IMX8MP_RESET_A53_DBG_RESET2 10
#define IMX8MP_RESET_A53_DBG_RESET3 11
#define IMX8MP_RESET_A53_ETM_RESET0 12
#define IMX8MP_RESET_A53_ETM_RESET1 13
#define IMX8MP_RESET_A53_ETM_RESET2 14
#define IMX8MP_RESET_A53_ETM_RESET3 15
#define IMX8MP_RESET_A53_SOC_DBG_RESET 16
#define IMX8MP_RESET_A53_L2RESET 17
#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18
#define IMX8MP_RESET_OTG1_PHY_RESET 19
#define IMX8MP_RESET_OTG2_PHY_RESET 20
#define IMX8MP_RESET_SUPERMIX_RESET 21
#define IMX8MP_RESET_AUDIOMIX_RESET 22
#define IMX8MP_RESET_MLMIX_RESET 23
#define IMX8MP_RESET_PCIEPHY 24
#define IMX8MP_RESET_PCIEPHY_PERST 25
#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26
#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27
#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28
#define IMX8MP_RESET_MEDIA_RESET 29
#define IMX8MP_RESET_GPU2D_RESET 30
#define IMX8MP_RESET_GPU3D_RESET 31
#define IMX8MP_RESET_GPU_RESET 32
#define IMX8MP_RESET_VPU_RESET 33
#define IMX8MP_RESET_VPU_G1_RESET 34
#define IMX8MP_RESET_VPU_G2_RESET 35
#define IMX8MP_RESET_VPUVC8KE_RESET 36
#define IMX8MP_RESET_NOC_RESET 37
#define IMX8MP_RESET_NUM 38
#endif