Merge branch '2019-10-11-master-imports'

- Assorted cleanups
- FAT bugfixes
- mediatek platform updates

include/dt-bindings/reset/mt7623-reset.h

@@ -6,11 +6,9 @@
 #ifndef _DT_BINDINGS_MTK_RESET_H_
 #define _DT_BINDINGS_MTK_RESET_H_
 
-/* ETHSYS */
+/* ETHSYS resets */
 #define ETHSYS_PPE_RST			31
-#define ETHSYS_EPHY_RST			24
 #define ETHSYS_GMAC_RST			23
-#define ETHSYS_ESW_RST			16
 #define ETHSYS_FE_RST			6
 #define ETHSYS_MCM_RST			2
 #define ETHSYS_SYS_RST			0

include/dt-bindings/reset/mt7629-reset.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MTK_RESET_H_
+#define _DT_BINDINGS_MTK_RESET_H_
+
+/* PCIe Subsystem resets */
+#define PCIE1_CORE_RST			19
+#define PCIE1_MMIO_RST			20
+#define PCIE1_HRST			21
+#define PCIE1_USER_RST			22
+#define PCIE1_PIPE_RST			23
+#define PCIE0_CORE_RST			27
+#define PCIE0_MMIO_RST			28
+#define PCIE0_HRST			29
+#define PCIE0_USER_RST			30
+#define PCIE0_PIPE_RST			31
+
+/* SSUSB Subsystem resets */
+#define SSUSB_PHY_PWR_RST		3
+#define SSUSB_MAC_PWR_RST		4
+
+/* ETH Subsystem resets */
+#define ETHSYS_SYS_RST			0
+#define ETHSYS_MCM_RST			2
+#define ETHSYS_HSDMA_RST		5
+#define ETHSYS_FE_RST			6
+#define ETHSYS_ESW_RST			16
+#define ETHSYS_GMAC_RST			23
+#define ETHSYS_EPHY_RST			24
+#define ETHSYS_CRYPTO_RST		29
+#define ETHSYS_PPE_RST			31
+
+#endif /* _DT_BINDINGS_MTK_RESET_H_ */

include/wait_bit.h

@@ -72,10 +72,12 @@ static inline int wait_for_bit_##sfx(const void *reg,			\
 
 BUILD_WAIT_FOR_BIT(8, u8, readb)
 BUILD_WAIT_FOR_BIT(le16, u16, readw)
+BUILD_WAIT_FOR_BIT(16, u16, readw)
 #ifdef readw_be
 BUILD_WAIT_FOR_BIT(be16, u16, readw_be)
 #endif
 BUILD_WAIT_FOR_BIT(le32, u32, readl)
+BUILD_WAIT_FOR_BIT(32, u32, readl)
 #ifdef readl_be
 BUILD_WAIT_FOR_BIT(be32, u32, readl_be)
 #endif