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Merge branch 'master' of git://git.denx.de/u-boot-sunxi

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This commit is contained in:
Tom Rini
2018-08-04 19:41:30 -04:00
parent d64caaf77d 89a897fc4d
commit 0cba6e906a
46 changed files with 2560 additions and 61 deletions
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2
include/configs/sun4i.h
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@@ -15,8 +15,6 @@
#define CONFIG_USB_EHCI_SUNXI
#endif
#define CONFIG_SUNXI_USB_PHYS 3
/*
* Include common sunxi configuration where most the settings are
*/

7
include/configs/sun50i.h
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@@ -15,10 +15,13 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
#define CONFIG_SUNXI_USB_PHYS 1
#ifndef CONFIG_MACH_SUN50I_H6
#define GICD_BASE 0x1c81000
#define GICC_BASE 0x1c82000
#else
#define GICD_BASE 0x3021000
#define GICC_BASE 0x3022000
#endif
/*
* Include common sunxi configuration where most the settings are

2
include/configs/sun5i.h
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@@ -15,8 +15,6 @@
#define CONFIG_USB_EHCI_SUNXI
#endif
#define CONFIG_SUNXI_USB_PHYS 2
/*
* Include common sunxi configuration where most the settings are
*/

2
include/configs/sun6i.h
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@@ -18,8 +18,6 @@
#define CONFIG_USB_EHCI_SUNXI
#endif
#define CONFIG_SUNXI_USB_PHYS 3
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */

2
include/configs/sun7i.h
View File

@@ -16,8 +16,6 @@
#define CONFIG_USB_EHCI_SUNXI
#endif
#define CONFIG_SUNXI_USB_PHYS 3
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */

10
include/configs/sun8i.h
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@@ -16,16 +16,6 @@
#define CONFIG_USB_EHCI_SUNXI
#endif
#ifdef CONFIG_MACH_SUN8I_H3
#define CONFIG_SUNXI_USB_PHYS 4
#elif defined CONFIG_MACH_SUN8I_A83T
#define CONFIG_SUNXI_USB_PHYS 3
#elif defined CONFIG_MACH_SUN8I_V3S
#define CONFIG_SUNXI_USB_PHYS 1
#else
#define CONFIG_SUNXI_USB_PHYS 2
#endif
/*
* Include common sunxi configuration where most the settings are
*/

24
include/configs/sunxi-common.h
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@@ -82,20 +82,19 @@
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
#ifdef CONFIG_SUNXI_HIGH_SRAM
/*
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
* slightly bigger. Note that it is possible to map the first 32 KiB of the
* A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the
* undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
* A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register
* is known yet.
* H6 has SRAM A1 at 0x00020000.
*/
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
#else
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#endif
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS
/* FIXME: this may be larger on some SoCs */
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
@@ -184,7 +183,11 @@
#define CONFIG_SPL_BOARD_LOAD_IMAGE
#endif
#ifdef CONFIG_SUNXI_HIGH_SRAM
/*
* We cannot use expressions here, because expressions won't be evaluated in
* autoconf.mk.
*/
#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000
#define CONFIG_SPL_TEXT_BASE 0x10060 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
#ifdef CONFIG_ARM64
@@ -193,6 +196,11 @@
#else
#define LOW_LEVEL_SRAM_STACK 0x00018000
#endif /* !CONFIG_ARM64 */
#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000
#define CONFIG_SPL_TEXT_BASE 0x20060 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */
/* end of SRAM A2 on H6 for now */
#define LOW_LEVEL_SRAM_STACK 0x00118000
#else
#define CONFIG_SPL_TEXT_BASE 0x60 /* sram start+header */
#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */

125
include/dt-bindings/clock/sun50i-h6-ccu.h Normal file
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@@ -0,0 +1,125 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_H_
#define CLK_PLL_PERIPH0 3
#define CLK_CPUX 21
#define CLK_APB1 26
#define CLK_DE 29
#define CLK_BUS_DE 30
#define CLK_DEINTERLACE 31
#define CLK_BUS_DEINTERLACE 32
#define CLK_GPU 33
#define CLK_BUS_GPU 34
#define CLK_CE 35
#define CLK_BUS_CE 36
#define CLK_VE 37
#define CLK_BUS_VE 38
#define CLK_EMCE 39
#define CLK_BUS_EMCE 40
#define CLK_VP9 41
#define CLK_BUS_VP9 42
#define CLK_BUS_DMA 43
#define CLK_BUS_MSGBOX 44
#define CLK_BUS_SPINLOCK 45
#define CLK_BUS_HSTIMER 46
#define CLK_AVS 47
#define CLK_BUS_DBG 48
#define CLK_BUS_PSI 49
#define CLK_BUS_PWM 50
#define CLK_BUS_IOMMU 51
#define CLK_MBUS_DMA 53
#define CLK_MBUS_VE 54
#define CLK_MBUS_CE 55
#define CLK_MBUS_TS 56
#define CLK_MBUS_NAND 57
#define CLK_MBUS_CSI 58
#define CLK_MBUS_DEINTERLACE 59
#define CLK_NAND0 61
#define CLK_NAND1 62
#define CLK_BUS_NAND 63
#define CLK_MMC0 64
#define CLK_MMC1 65
#define CLK_MMC2 66
#define CLK_BUS_MMC0 67
#define CLK_BUS_MMC1 68
#define CLK_BUS_MMC2 69
#define CLK_BUS_UART0 70
#define CLK_BUS_UART1 71
#define CLK_BUS_UART2 72
#define CLK_BUS_UART3 73
#define CLK_BUS_I2C0 74
#define CLK_BUS_I2C1 75
#define CLK_BUS_I2C2 76
#define CLK_BUS_I2C3 77
#define CLK_BUS_SCR0 78
#define CLK_BUS_SCR1 79
#define CLK_SPI0 80
#define CLK_SPI1 81
#define CLK_BUS_SPI0 82
#define CLK_BUS_SPI1 83
#define CLK_BUS_EMAC 84
#define CLK_TS 85
#define CLK_BUS_TS 86
#define CLK_IR_TX 87
#define CLK_BUS_IR_TX 88
#define CLK_BUS_THS 89
#define CLK_I2S3 90
#define CLK_I2S0 91
#define CLK_I2S1 92
#define CLK_I2S2 93
#define CLK_BUS_I2S0 94
#define CLK_BUS_I2S1 95
#define CLK_BUS_I2S2 96
#define CLK_BUS_I2S3 97
#define CLK_SPDIF 98
#define CLK_BUS_SPDIF 99
#define CLK_DMIC 100
#define CLK_BUS_DMIC 101
#define CLK_AUDIO_HUB 102
#define CLK_BUS_AUDIO_HUB 103
#define CLK_USB_OHCI0 104
#define CLK_USB_PHY0 105
#define CLK_USB_PHY1 106
#define CLK_USB_OHCI3 107
#define CLK_USB_PHY3 108
#define CLK_USB_HSIC_12M 109
#define CLK_USB_HSIC 110
#define CLK_BUS_OHCI0 111
#define CLK_BUS_OHCI3 112
#define CLK_BUS_EHCI0 113
#define CLK_BUS_XHCI 114
#define CLK_BUS_EHCI3 115
#define CLK_BUS_OTG 116
#define CLK_PCIE_REF_100M 117
#define CLK_PCIE_REF 118
#define CLK_PCIE_REF_OUT 119
#define CLK_PCIE_MAXI 120
#define CLK_PCIE_AUX 121
#define CLK_BUS_PCIE 122
#define CLK_HDMI 123
#define CLK_HDMI_SLOW 124
#define CLK_HDMI_CEC 125
#define CLK_BUS_HDMI 126
#define CLK_BUS_TCON_TOP 127
#define CLK_TCON_LCD0 128
#define CLK_BUS_TCON_LCD0 129
#define CLK_TCON_TV0 130
#define CLK_BUS_TCON_TV0 131
#define CLK_CSI_CCI 132
#define CLK_CSI_TOP 133
#define CLK_CSI_MCLK 134
#define CLK_BUS_CSI 135
#define CLK_HDCP 136
#define CLK_BUS_HDCP 137
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */

24
include/dt-bindings/clock/sun50i-h6-r-ccu.h Normal file
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@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
#define CLK_AR100 0
#define CLK_R_APB1 2
#define CLK_R_APB1_TIMER 4
#define CLK_R_APB1_TWD 5
#define CLK_R_APB1_PWM 6
#define CLK_R_APB2_UART 7
#define CLK_R_APB2_I2C 8
#define CLK_R_APB1_IR 9
#define CLK_R_APB1_W1 10
#define CLK_IR 11
#define CLK_W1 12
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */

73
include/dt-bindings/reset/sun50i-h6-ccu.h Normal file
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@@ -0,0 +1,73 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
#define _DT_BINDINGS_RESET_SUN50I_H6_H_
#define RST_MBUS 0
#define RST_BUS_DE 1
#define RST_BUS_DEINTERLACE 2
#define RST_BUS_GPU 3
#define RST_BUS_CE 4
#define RST_BUS_VE 5
#define RST_BUS_EMCE 6
#define RST_BUS_VP9 7
#define RST_BUS_DMA 8
#define RST_BUS_MSGBOX 9
#define RST_BUS_SPINLOCK 10
#define RST_BUS_HSTIMER 11
#define RST_BUS_DBG 12
#define RST_BUS_PSI 13
#define RST_BUS_PWM 14
#define RST_BUS_IOMMU 15
#define RST_BUS_DRAM 16
#define RST_BUS_NAND 17
#define RST_BUS_MMC0 18
#define RST_BUS_MMC1 19
#define RST_BUS_MMC2 20
#define RST_BUS_UART0 21
#define RST_BUS_UART1 22
#define RST_BUS_UART2 23
#define RST_BUS_UART3 24
#define RST_BUS_I2C0 25
#define RST_BUS_I2C1 26
#define RST_BUS_I2C2 27
#define RST_BUS_I2C3 28
#define RST_BUS_SCR0 29
#define RST_BUS_SCR1 30
#define RST_BUS_SPI0 31
#define RST_BUS_SPI1 32
#define RST_BUS_EMAC 33
#define RST_BUS_TS 34
#define RST_BUS_IR_TX 35
#define RST_BUS_THS 36
#define RST_BUS_I2S0 37
#define RST_BUS_I2S1 38
#define RST_BUS_I2S2 39
#define RST_BUS_I2S3 40
#define RST_BUS_SPDIF 41
#define RST_BUS_DMIC 42
#define RST_BUS_AUDIO_HUB 43
#define RST_USB_PHY0 44
#define RST_USB_PHY1 45
#define RST_USB_PHY3 46
#define RST_USB_HSIC 47
#define RST_BUS_OHCI0 48
#define RST_BUS_OHCI3 49
#define RST_BUS_EHCI0 50
#define RST_BUS_XHCI 51
#define RST_BUS_EHCI3 52
#define RST_BUS_OTG 53
#define RST_BUS_PCIE 54
#define RST_PCIE_POWERUP 55
#define RST_BUS_HDMI 56
#define RST_BUS_HDMI_SUB 57
#define RST_BUS_TCON_TOP 58
#define RST_BUS_TCON_LCD0 59
#define RST_BUS_TCON_TV0 60
#define RST_BUS_CSI 61
#define RST_BUS_HDCP 62
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */

17
include/dt-bindings/reset/sun50i-h6-r-ccu.h Normal file
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@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
/*
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
*/
#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
#define RST_R_APB1_TIMER 0
#define RST_R_APB1_TWD 1
#define RST_R_APB1_PWM 2
#define RST_R_APB2_UART 3
#define RST_R_APB2_I2C 4
#define RST_R_APB1_IR 5
#define RST_R_APB1_W1 6
#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */