imx95_evk: add i.MX95 19x19 EVK board basic support

This patch adds i.MX95 19x19 EVK board basic support.

Messaging unit for EdgeLock Secure Enclave, messaging unit for System
Manager, uSDHC for SD Card, gpio, lpuart are supported now.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Ye Li
2025-04-28 18:37:43 +08:00
committed by Fabio Estevam
parent fe8ab3b0c0
commit 0cbd26bee4
15 changed files with 799 additions and 0 deletions

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@@ -0,0 +1,62 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
*/
#include "imx95-u-boot.dtsi"
&lpuart1 {
bootph-pre-ram;
};
&reg_usdhc2_vmmc {
bootph-pre-ram;
};
&usdhc1 {
bootph-pre-ram;
};
&usdhc2 {
bootph-pre-ram;
};
&wdog3 {
status = "disabled";
};
&pinctrl_uart1 {
bootph-pre-ram;
};
&pinctrl_usdhc1 {
bootph-pre-ram;
};
&pinctrl_usdhc1_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc1_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2 {
bootph-pre-ram;
};
&pinctrl_usdhc2_100mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_200mhz {
bootph-pre-ram;
};
&pinctrl_usdhc2_gpio {
bootph-pre-ram;
};
&pinctrl_reg_usdhc2_vmmc {
bootph-pre-ram;
};

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@@ -0,0 +1,188 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2025 NXP
*/
/ {
binman {
multiple-images;
m33-oei-ddrfw {
pad-byte = <0x00>;
align-size = <0x8>;
filename = "m33-oei-ddrfw.bin";
oei-m33-ddr {
align-size = <0x4>;
filename = "oei-m33-ddr.bin";
type = "blob-ext";
};
imx-lpddr {
type = "nxp-header-ddrfw";
imx-lpddr-imem {
filename = "lpddr5_imem_v202311.bin";
type = "blob-ext";
};
imx-lpddr-dmem {
filename = "lpddr5_dmem_v202311.bin";
type = "blob-ext";
};
};
imx-lpddr-qb {
type = "nxp-header-ddrfw";
imx-lpddr-imem-qb {
filename = "lpddr5_imem_qb_v202311.bin";
type = "blob-ext";
};
imx-lpddr-dmem-qb {
filename = "lpddr5_dmem_qb_v202311.bin";
type = "blob-ext";
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
align = <0x400>;
align-size = <0x400>;
type = "mkimage";
args = "-n spl/u-boot-spl.cfgout -T imx8image";
};
u-boot {
type = "mkimage";
args = "-n u-boot-container.cfgout -T imx8image";
};
};
};
};
&A55_0 {
clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&A55_1 {
clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&A55_2 {
clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&A55_3 {
clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&A55_4 {
clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&A55_5 {
clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
/delete-property/ power-domains;
};
&aips1 {
bootph-all;
};
&aips2 {
bootph-all;
};
&aips3 {
bootph-pre-ram;
};
&clk_ext1 {
bootph-all;
};
&elemu1 {
bootph-all;
status = "okay";
};
&elemu3 {
bootph-all;
status = "okay";
};
&{/firmware} {
bootph-all;
};
&{/firmware/scmi} {
bootph-all;
};
&{/firmware/scmi/protocol@11} {
bootph-all;
};
&{/firmware/scmi/protocol@13} {
bootph-all;
};
&{/firmware/scmi/protocol@14} {
bootph-all;
};
&{/firmware/scmi/protocol@19} {
bootph-all;
};
&gpio2 {
bootph-pre-ram;
};
&gpio3 {
bootph-pre-ram;
};
&gpio4 {
bootph-pre-ram;
};
&gpio5 {
bootph-pre-ram;
};
&mu2 {
bootph-all;
};
&osc_24m {
bootph-all;
};
&{/soc} {
bootph-all;
};
&sram0 {
bootph-all;
};
&scmi_buf0 {
reg = <0x0 0x400>;
bootph-all;
};
&scmi_buf1 {
bootph-all;
};

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@@ -76,6 +76,13 @@ config TARGET_PHYCORE_IMX93
select OF_BOARD_FIXUP
select OF_BOARD_SETUP
config TARGET_IMX95_19X19_EVK
bool "imx95_19x19_evk"
select IMX95
imply BOOTSTD_BOOTCOMMAND
imply BOOTSTD_FULL
imply OF_UPSTREAM
endchoice
source "board/freescale/imx91_evk/Kconfig"
@@ -83,6 +90,7 @@ source "board/freescale/imx93_evk/Kconfig"
source "board/freescale/imx93_qsb/Kconfig"
source "board/phytec/phycore_imx93/Kconfig"
source "board/variscite/imx93_var_som/Kconfig"
source "board/freescale/imx95_evk/Kconfig"
endif

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@@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2025 NXP
*/
BOOT_FROM SD
SOC_TYPE IMX9
CONTAINER
IMAGE A55 bl31.bin 0x8a200000
IMAGE A55 u-boot.bin CONFIG_TEXT_BASE

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@@ -0,0 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2025 NXP
*/
BOOT_FROM SD
SOC_TYPE IMX9
APPEND mx95a0-ahab-container.img
CONTAINER
IMAGE OEI m33-oei-ddrfw.bin 0x1ffc0000
HOLD 0x10000
IMAGE OEI oei-m33-tcm.bin 0x1ffc0000
IMAGE M33 m33_image.bin 0x1ffc0000
IMAGE A55 spl/u-boot-spl.bin 0x20480000
DUMMY_V2X 0x8b000000