From 6ddffa89cb8396bf043adcc5090e8b1a9b1d0246 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 23:49:27 +0100 Subject: [PATCH 1/7] mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHz The prior stage bootloader might have left the SDnCKCR register in completely arbitrary state before passing control to U-Boot, which includes the register being populated with incorrect values. Currently the SDHI driver will attempt to use clock framework to configure SDn clock, which may fail in case SDnCKCR contains invalid values for the SDnH clock, because the clock framework would not be able to determine SDnH clock rate and would get -EINVAL instead, which in turn would not allow the clock framework to determine the correct SDn clock divider ratio. This failure occurs specifically in case SDnCKCR reads back 0x209 . Correct the problem by first setting default SDnH clock rate to 800 MHz, thus assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn clock rate to default 200 MHz. Note that the SDHI driver may reconfigure SDnH clock later based on IOS settings obtained from the attached card, the 800 MHz set up here is only the default value. Signed-off-by: Marek Vasut --- drivers/mmc/renesas-sdhi.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 4a1accebfcb..2473261f3c4 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -977,8 +977,16 @@ static int renesas_sdhi_probe(struct udevice *dev) /* optional SDnH clock */ ret = clk_get_by_name(dev, "clkh", &priv->clkh); - if (ret < 0) + if (ret < 0) { dev_dbg(dev, "failed to get clkh\n"); + } else { + ret = clk_set_rate(&priv->clkh, 800000000); + if (ret < 0) { + dev_err(dev, "failed to set rate for SDnH clock\n"); + clk_free(&priv->clk); + return ret; + } + } /* set to max rate */ ret = clk_set_rate(&priv->clk, 200000000); From f20a61af4209785721bdee96131785d9dc24698d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 27 Feb 2023 23:49:28 +0100 Subject: [PATCH 2/7] mmc: renesas-sdhi: Add proper probe error fail path In case one of the calls in probe fail, trigger a fail path and undo all the steps done in probe until the point of failure. The current implementation failed to stop controller clock and free claimed clock, so fix that. Furthermore, print return code in error prints for easier debugging. Signed-off-by: Marek Vasut --- drivers/mmc/renesas-sdhi.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 2473261f3c4..34119f949aa 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -982,37 +982,45 @@ static int renesas_sdhi_probe(struct udevice *dev) } else { ret = clk_set_rate(&priv->clkh, 800000000); if (ret < 0) { - dev_err(dev, "failed to set rate for SDnH clock\n"); - clk_free(&priv->clk); - return ret; + dev_err(dev, "failed to set rate for SDnH clock (%d)\n", ret); + goto err_clk; } } /* set to max rate */ ret = clk_set_rate(&priv->clk, 200000000); if (ret < 0) { - dev_err(dev, "failed to set rate for host clock\n"); - clk_free(&priv->clk); - return ret; + dev_err(dev, "failed to set rate for SDn clock (%d)\n", ret); + goto err_clkh; } ret = clk_enable(&priv->clk); if (ret) { - dev_err(dev, "failed to enable host clock\n"); - return ret; + dev_err(dev, "failed to enable SDn clock (%d)\n", ret); + goto err_clkh; } priv->quirks = quirks; ret = tmio_sd_probe(dev, quirks); + if (ret) + goto err_tmio_probe; renesas_sdhi_filter_caps(dev); #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) - if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS)) + if (priv->caps & TMIO_SD_CAP_RCAR_UHS) renesas_sdhi_reset_tuning(priv); #endif + return 0; + +err_tmio_probe: + clk_disable(&priv->clk); +err_clkh: + clk_free(&priv->clkh); +err_clk: + clk_free(&priv->clk); return ret; } From 3efdf01fa49a24cc2f1139d67f2e1e5cd43cf882 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Feb 2023 22:16:02 +0100 Subject: [PATCH 3/7] clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3. The former depends on the clock framework, which is always enabled in this context of clock framework driver, while the later depends on reset framework which may not always be enabled. Ensure the reset framework is also always enabled to prevent inobvious early boot time bind failure of the CPG driver, which leads to system showing no activity and is difficult to debug. Note that one possible approach to debug this is to use CONFIG_DEBUG_UART and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c . Signed-off-by: Marek Vasut --- drivers/clk/renesas/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 1686410d6d3..d58e897ca1b 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -49,6 +49,7 @@ config CLK_RCAR_GEN3 def_bool y if RCAR_GEN3 depends on CLK_RENESAS select CLK_RCAR_CPG_LIB + select DM_RESET help Enable this to support the clocks on Renesas RCar Gen3 SoC. From ce4681721570494574beff5f47df3d35d5e9aa10 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Feb 2023 07:25:53 +0100 Subject: [PATCH 4/7] pinctrl: renesas: Drop non-existent PFC info table entries Remove PFC info table entries which are never instantiated, since there are no drivers for those. No functional change. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/sh_pfc.h | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index 59d447ead5c..0ab743e80d5 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -309,21 +309,6 @@ extern const struct sh_pfc_soc_info r8a77980_pinmux_info; extern const struct sh_pfc_soc_info r8a77990_pinmux_info; extern const struct sh_pfc_soc_info r8a77995_pinmux_info; extern const struct sh_pfc_soc_info r8a779a0_pinmux_info; -extern const struct sh_pfc_soc_info r8a779f0_pinmux_info; -extern const struct sh_pfc_soc_info r8a779g0_pinmux_info; -extern const struct sh_pfc_soc_info sh7203_pinmux_info; -extern const struct sh_pfc_soc_info sh7264_pinmux_info; -extern const struct sh_pfc_soc_info sh7269_pinmux_info; -extern const struct sh_pfc_soc_info sh73a0_pinmux_info; -extern const struct sh_pfc_soc_info sh7720_pinmux_info; -extern const struct sh_pfc_soc_info sh7722_pinmux_info; -extern const struct sh_pfc_soc_info sh7723_pinmux_info; -extern const struct sh_pfc_soc_info sh7724_pinmux_info; -extern const struct sh_pfc_soc_info sh7734_pinmux_info; -extern const struct sh_pfc_soc_info sh7757_pinmux_info; -extern const struct sh_pfc_soc_info sh7785_pinmux_info; -extern const struct sh_pfc_soc_info sh7786_pinmux_info; -extern const struct sh_pfc_soc_info shx3_pinmux_info; /* ----------------------------------------------------------------------------- * Helper macros to create pin and port lists From b791b9cf5500b589df5f8b227a6320bf34ba081c Mon Sep 17 00:00:00 2001 From: Tam Nguyen Date: Mon, 27 Feb 2023 23:58:46 +0100 Subject: [PATCH 5/7] sysinfo: rcar3: Fix Draak and Eagle board code Correct the board code ID based on the hardware documentation Reviewed-by: Marek Vasut Signed-off-by: Tam Nguyen Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- drivers/sysinfo/rcar3.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index c2f4ddfbbe3..c0afc92f675 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -16,12 +16,12 @@ #define BOARD_SALVATOR_X 0x0 #define BOARD_KRIEK 0x1 #define BOARD_STARTER_KIT 0x2 +#define BOARD_EAGLE 0x3 #define BOARD_SALVATOR_XS 0x4 +#define BOARD_DRAAK 0x7 #define BOARD_EBISU 0x8 #define BOARD_STARTER_KIT_PRE 0xB #define BOARD_EBISU_4D 0xD -#define BOARD_DRAAK 0xE -#define BOARD_EAGLE 0xF /** * struct sysinfo_rcar_priv - sysinfo private data From c8eaebb426fed1bbb7020566486b4a8f4eb0f159 Mon Sep 17 00:00:00 2001 From: Tam Nguyen Date: Mon, 27 Feb 2023 23:58:47 +0100 Subject: [PATCH 6/7] ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-I Add new sysinfo IDs for R-Car V3H Condor/Condor-I . Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut Signed-off-by: Tam Nguyen Signed-off-by: Hai Pham Signed-off-by: Marek Vasut [Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Update the commit message, note the new sysinfo IDs. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.] --- arch/arm/dts/r8a77980-condor-u-boot.dts | 17 +++++++++++++++++ configs/r8a77980_condor_defconfig | 5 +++++ drivers/sysinfo/rcar3.c | 15 +++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/arch/arm/dts/r8a77980-condor-u-boot.dts b/arch/arm/dts/r8a77980-condor-u-boot.dts index 576a74e6030..530abdb72bc 100644 --- a/arch/arm/dts/r8a77980-condor-u-boot.dts +++ b/arch/arm/dts/r8a77980-condor-u-boot.dts @@ -12,6 +12,23 @@ aliases { spi0 = &rpc; }; + + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + u-boot,dm-pre-reloc; + }; }; &rpc { diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 0c3493cdf8d..e1b3dc5d38a 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -64,6 +65,9 @@ CONFIG_DFU_SF=y CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y @@ -84,6 +88,7 @@ CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_RENESAS_RPC_SPI=y +CONFIG_SYSINFO=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_USB=y diff --git a/drivers/sysinfo/rcar3.c b/drivers/sysinfo/rcar3.c index c0afc92f675..7b127986da7 100644 --- a/drivers/sysinfo/rcar3.c +++ b/drivers/sysinfo/rcar3.c @@ -18,10 +18,12 @@ #define BOARD_STARTER_KIT 0x2 #define BOARD_EAGLE 0x3 #define BOARD_SALVATOR_XS 0x4 +#define BOARD_CONDOR 0x6 #define BOARD_DRAAK 0x7 #define BOARD_EBISU 0x8 #define BOARD_STARTER_KIT_PRE 0xB #define BOARD_EBISU_4D 0xD +#define BOARD_CONDOR_I 0x10 /** * struct sysinfo_rcar_priv - sysinfo private data @@ -65,6 +67,7 @@ static void sysinfo_rcar_parse(struct sysinfo_rcar_priv *priv) const u8 board_rev = priv->val & BOARD_REV_MASK; bool salvator_xs = false; bool ebisu_4d = false; + bool condor_i = false; char rev_major = '?'; char rev_minor = '?'; @@ -138,6 +141,18 @@ static void sysinfo_rcar_parse(struct sysinfo_rcar_priv *priv) "Renesas Kriek board rev %c.%c", rev_major, rev_minor); return; + case BOARD_CONDOR_I: + condor_i = true; + fallthrough; + case BOARD_CONDOR: + if (!board_rev) { /* Only rev 0 is valid */ + rev_major = '1'; + rev_minor = '0'; + } + snprintf(priv->boardmodel, sizeof(priv->boardmodel), + "Renesas Condor%s board rev %c.%c", + condor_i ? "-I" : "", rev_major, rev_minor); + return; default: snprintf(priv->boardmodel, sizeof(priv->boardmodel), "Renesas -Unknown- board rev ?.?"); From ae08097faac226a951f4258c481e3e62d6ed8ac2 Mon Sep 17 00:00:00 2001 From: Tam Nguyen Date: Mon, 27 Feb 2023 23:58:48 +0100 Subject: [PATCH 7/7] ARM: dts: renesas: Enable sysinfo on R-Car D3 Draak Enable support for sysinfo on R-Car D3 Draak board. The sysinfo is used e.g. to access and decode board-specific information and then in turn used by board-info to print those information. Reviewed-by: Marek Vasut Signed-off-by: Tam Nguyen Signed-off-by: Hai Pham Signed-off-by: Marek Vasut [Marek: Drop compatible from I2C node, this is in r8a77995.dtsi already. Drop status = "okay" from EEPROM node. Add dts: tag. Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.] --- arch/arm/dts/r8a77995-draak-u-boot.dts | 19 +++++++++++++++++++ configs/r8a77995_draak_defconfig | 5 +++++ 2 files changed, 24 insertions(+) diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dts index 0ea2570c1dc..260bc5da19f 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dts +++ b/arch/arm/dts/r8a77995-draak-u-boot.dts @@ -8,6 +8,25 @@ #include "r8a77995-draak.dts" #include "r8a77995-u-boot.dtsi" +/ { + sysinfo { + compatible = "renesas,rcar-sysinfo"; + i2c-eeprom = <&sysinfo_eeprom>; + u-boot,dm-pre-reloc; + }; +}; + +&i2c0 { + u-boot,dm-pre-reloc; + + sysinfo_eeprom: eeprom@50 { + compatible = "rohm,br24t01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + u-boot,dm-pre-reloc; + }; +}; + &rpc { reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; status = "disabled"; diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 4ddb66aef9c..a09b33e7740 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_BOOTZ=y +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -65,6 +66,9 @@ CONFIG_DFU_SF=y CONFIG_RCAR_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y @@ -94,6 +98,7 @@ CONFIG_SCIF_CONSOLE=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_RENESAS_RPC_SPI=y +CONFIG_SYSINFO=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_USB=y