From 40b43c94d29e91a023d6690eaa4fb9720a0ed1a1 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:05 +0530 Subject: [PATCH 01/20] clk: stub: Sort compatible strings alphabetically Reorder compatible strings in stub_clk_ids to maintain alphabetical order for easier maintenance. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-1-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/clk-stub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index 117266ac778..ddcaaa00d91 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -50,10 +50,10 @@ static struct clk_ops stub_clk_ops = { static const struct udevice_id stub_clk_ids[] = { { .compatible = "qcom,rpmcc" }, - { .compatible = "qcom,sdm670-rpmh-clk" }, - { .compatible = "qcom,sdm845-rpmh-clk" }, { .compatible = "qcom,sc7180-rpmh-clk" }, { .compatible = "qcom,sc7280-rpmh-clk" }, + { .compatible = "qcom,sdm670-rpmh-clk" }, + { .compatible = "qcom,sdm845-rpmh-clk" }, { .compatible = "qcom,sm6350-rpmh-clk" }, { .compatible = "qcom,sm8150-rpmh-clk" }, { .compatible = "qcom,sm8250-rpmh-clk" }, From be1dc88b4a15b10df5a446f7219da58b3795d70d Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:06 +0530 Subject: [PATCH 02/20] clk: qcom: clk-stub: Add compatibles for QCS615/SA8775P Add RPMH clock compatible strings for QCS615 and SA8775P SoCs to enable clock framework support on these platforms. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-2-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/clk-stub.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-stub.c b/drivers/clk/clk-stub.c index ddcaaa00d91..4a6c71016da 100644 --- a/drivers/clk/clk-stub.c +++ b/drivers/clk/clk-stub.c @@ -49,7 +49,9 @@ static struct clk_ops stub_clk_ops = { }; static const struct udevice_id stub_clk_ids[] = { + { .compatible = "qcom,qcs615-rpmh-clk" }, { .compatible = "qcom,rpmcc" }, + { .compatible = "qcom,sa8775p-rpmh-clk" }, { .compatible = "qcom,sc7180-rpmh-clk" }, { .compatible = "qcom,sc7280-rpmh-clk" }, { .compatible = "qcom,sdm670-rpmh-clk" }, From 4b1580e060847ce63b38a1f87bd482b60ec6523f Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:07 +0530 Subject: [PATCH 03/20] clk: qcom: sa8775p: Add UFS clock support Add UFS clock support for SA8775P including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg Signed-off-by: Balaji Selvanathan Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-3-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-sa8775p.c | 63 ++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c index 4957abf6f58..7eec4aeae48 100644 --- a/drivers/clk/qcom/clock-sa8775p.c +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -19,6 +19,11 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0x1b028 #define USB3_PRIM_PHY_AUX_CMD_RCGR 0x1b06c +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x8302c +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x83074 +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x830a8 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x8308c + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -44,9 +49,35 @@ #define GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT BIT(25) +/* UFS AXI clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS ICE CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS UNIPRO CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + static ulong sa8775p_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, @@ -63,6 +94,24 @@ static ulong sa8775p_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return 19200000; default: return 0; } @@ -106,6 +155,20 @@ static const struct gate_clk sa8775p_clks[] = { /* QUP Wrapper 3 clocks */ GATE_CLK(GCC_QUPV3_WRAP3_S0_CLK, 0x4b000, GCC_QUPV3_WRAP3_S0_CLK_ENA_BIT), + + /* UFS PHY clocks */ + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x83018, 1), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x830d4, 1), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x83020, 1), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x83064, 1), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x83024, 1), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x83028, 1), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x830c0, 1), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x830a4, 1), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x8306c, 1), + + /* EDP reference clock (used by UFS PHY) */ + GATE_CLK(GCC_EDP_REF_CLKREF_EN, 0x97448, 1), }; static int sa8775p_enable(struct clk *clk) From 213edfd64501fca1c9e62640b4b1b362a2fd486a Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:08 +0530 Subject: [PATCH 04/20] clk: qcom: qcs615: Add UFS clock support Add UFS clock support for qcs615 including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg Signed-off-by: Balaji Selvanathan Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-4-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcs615.c | 63 ++++++++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c index 2087fc38f63..7b3fe49de9c 100644 --- a/drivers/clk/qcom/clock-qcs615.c +++ b/drivers/clk/qcom/clock-qcs615.c @@ -19,6 +19,11 @@ #define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf01c #define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf060 +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77020 +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x77048 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77060 +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x7707c + #define GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT BIT(10) #define GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT BIT(11) #define GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT BIT(12) @@ -33,9 +38,37 @@ #define GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT BIT(26) #define GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT BIT(27) +/* UFS PHY AXI clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(200000000, CFG_CLK_SRC_GPLL0, 3, 0, 0), + F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0), + { } +}; + +/* UFS PHY ICE CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0, 2, 0, 0), + { } +}; + +/* UFS PHY UNIPRO CORE clock frequency table */ +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(37500000, CFG_CLK_SRC_GPLL0_EVEN, 8, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0, 8, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0, 4, 0, 0), + { } +}; + static ulong qcs615_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; if (clk->id < priv->data->num_clks) debug("%s: %s, requested rate=%ld\n", __func__, @@ -52,6 +85,24 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate) 5, 0, 0, CFG_CLK_SRC_GPLL0, 8); clk_rcg_set_rate(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR, 0, 0); return rate; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + clk_rcg_set_rate(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO); + return 19200000; default: return 0; } @@ -81,7 +132,17 @@ static const struct gate_clk qcs615_clks[] = { GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT), GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT), GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)), - GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)) + GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)), + /* UFS clocks */ + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), }; static int qcs615_enable(struct clk *clk) From 7e670b7d6e10e5e072dfe05f425e635acec2524c Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:09 +0530 Subject: [PATCH 05/20] clk: qcom: sc7280: Add UFS clock support Add UFS clock support for sc7280 including register definitions, rate configuration, and gate clocks. Reviewed-by: Sumit Garg Signed-off-by: Balaji Selvanathan Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-5-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-sc7280.c | 52 +++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c index 01c8587ac39..91e3fcc27cb 100644 --- a/drivers/clk/qcom/clock-sc7280.c +++ b/drivers/clk/qcom/clock-sc7280.c @@ -23,6 +23,10 @@ #define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058 #define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c #define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054 +#define UFS_PHY_AXI_CLK_CMD_RCGR 0x77024 +#define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c +#define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0 +#define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0), @@ -54,6 +58,33 @@ static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0), + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_phy_aux_clk_src[] = { + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = { + F(75000000, CFG_CLK_SRC_GPLL0_EVEN, 4, 0, 0), + F(150000000, CFG_CLK_SRC_GPLL0_EVEN, 2, 0, 0), + F(300000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 0, 0), + { } +}; + static ulong sc7280_set_rate(struct clk *clk, ulong rate) { struct msm_clk_priv *priv = dev_get_priv(clk->dev); @@ -103,6 +134,26 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate) case GCC_PCIE1_PHY_RCHNG_CLK: clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN); return 100000000; + case GCC_UFS_PHY_AXI_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_axi_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_AXI_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_ICE_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_ice_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_ICE_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_PHY_AUX_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_phy_aux_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_PHY_AUX_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; + case GCC_UFS_PHY_UNIPRO_CORE_CLK: + freq = qcom_find_freq(ftbl_gcc_ufs_phy_unipro_core_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 8); + return freq->freq; default: return rate; } @@ -148,6 +199,7 @@ static const struct gate_clk sc7280_clks[] = { GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)), GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)), GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)), GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)), GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)), GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)), From 83edbe9426a4f4b22d118c9b11d82dfb3cb472ee Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:10 +0530 Subject: [PATCH 06/20] drivers: ufs: qcom: Initialize and enable clocks before hardware access Move UFS clock initialization and enabling before hardware setup to ensure clocks are running when accessing UFS registers. Previously, U-Boot depended on earlier bootloader stages to initialize UFS clocks. When these bootloaders failed to do so, UFS registers became inaccessible, causing initialization to fail. This change makes U-Boot initialize and enable UFS clocks early in the init sequence, removing the dependency on previous bootloaders. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-6-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/ufs/ufs-qcom.c | 53 ++++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c index dc40ee62daf..ae33f62fbee 100644 --- a/drivers/ufs/ufs-qcom.c +++ b/drivers/ufs/ufs-qcom.c @@ -30,6 +30,7 @@ #define UFS_CPU_MAX_BANDWIDTH 819200 static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable); +static u32 ufs_qcom_get_core_clk_unipro_max_freq(struct ufs_hba *hba); static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) { @@ -47,17 +48,6 @@ static int ufs_qcom_enable_clks(struct ufs_qcom_priv *priv) return 0; } -static int ufs_qcom_init_clks(struct ufs_qcom_priv *priv) -{ - int err; - struct udevice *dev = priv->hba->dev; - - err = clk_get_bulk(dev, &priv->clks); - if (err) - return err; - - return 0; -} static int ufs_qcom_check_hibern8(struct ufs_hba *hba) { @@ -557,10 +547,45 @@ static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_hba *hba, bool enable) static int ufs_qcom_init(struct ufs_hba *hba) { struct ufs_qcom_priv *priv = dev_get_priv(hba->dev); + struct udevice *dev = hba->dev; + struct clk clk; + u32 max_freq; + long rate; int err; priv->hba = hba; + /* Get maximum frequency for core_clk_unipro from device tree */ + max_freq = ufs_qcom_get_core_clk_unipro_max_freq(hba); + + /* Get and configure core_clk_unipro */ + err = clk_get_by_name(dev, "core_clk_unipro", &clk); + if (err) { + dev_err(dev, "Failed to get core_clk_unipro: %d\n", err); + return err; + } + + rate = clk_set_rate(&clk, max_freq); + if (rate < 0) { + dev_err(dev, "Failed to set core_clk_unipro rate to %u Hz: %ld\n", + max_freq, rate); + } + + /* Get all clocks */ + err = clk_get_bulk(dev, &priv->clks); + if (err) { + dev_err(dev, "clk_get_bulk failed: %d\n", err); + return err; + } + + /* Enable clocks */ + err = ufs_qcom_enable_clks(priv); + if (err) { + dev_err(dev, "failed to enable clocks: %d\n", err); + clk_release_bulk(&priv->clks); + return err; + } + /* setup clocks */ ufs_qcom_setup_clocks(hba, true, PRE_CHANGE); @@ -579,12 +604,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) priv->hw_ver.minor, priv->hw_ver.step); - err = ufs_qcom_init_clks(priv); - if (err) { - dev_err(hba->dev, "failed to initialize clocks, err:%d\n", err); - return err; - } - ufs_qcom_advertise_quirks(hba); ufs_qcom_setup_clocks(hba, true, POST_CHANGE); From 6d2bcb6398cf3b7caa9e80add7c49e28a1e9a6c6 Mon Sep 17 00:00:00 2001 From: Balaji Selvanathan Date: Mon, 27 Apr 2026 14:56:11 +0530 Subject: [PATCH 07/20] ufs: qcom: Remove redundant POST_CHANGE clock setup call The ufs_qcom_init() function was calling ufs_qcom_setup_clocks() with POST_CHANGE twice. The first call after setting PA_TXHSADAPTTYPE correctly enables the device reference clock. The second call after ufs_qcom_advertise_quirks() is redundant as the clock is already enabled. Signed-off-by: Balaji Selvanathan Reviewed-by: Sumit Garg Reviewed-by: Neha Malcom Francis Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260427-ufs_clk-v2-7-36e10a7c0ef6@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/ufs/ufs-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/ufs/ufs-qcom.c b/drivers/ufs/ufs-qcom.c index ae33f62fbee..f5f5a6eb110 100644 --- a/drivers/ufs/ufs-qcom.c +++ b/drivers/ufs/ufs-qcom.c @@ -605,7 +605,6 @@ static int ufs_qcom_init(struct ufs_hba *hba) priv->hw_ver.step); ufs_qcom_advertise_quirks(hba); - ufs_qcom_setup_clocks(hba, true, POST_CHANGE); return 0; } From c9eb2d64e2c6c1e1f1ebd3ea734afe2b0bac963b Mon Sep 17 00:00:00 2001 From: Aswin Murugan Date: Fri, 24 Apr 2026 16:12:37 +0530 Subject: [PATCH 08/20] dts: lemans-evk-u-boot: add override dtsi Add initial support for the lemans EVK platform based on lemans SoC. Define memory layout statically. Signed-off-by: Aswin Murugan Signed-off-by: Sumit Garg Link: https://patch.msgid.link/20260424104237.968195-1-sumit.garg@kernel.org Signed-off-by: Casey Connolly --- arch/arm/dts/lemans-evk-u-boot.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 arch/arm/dts/lemans-evk-u-boot.dtsi diff --git a/arch/arm/dts/lemans-evk-u-boot.dtsi b/arch/arm/dts/lemans-evk-u-boot.dtsi new file mode 100644 index 00000000000..cdd3d32f61a --- /dev/null +++ b/arch/arm/dts/lemans-evk-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2026, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/ { + /* Will be removed when bootloader updates later */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x3ee00000>, + <0x0 0xc0000000 0x0 0x0fd00000>, + <0xD 0x00000000 0x2 0x54100000>, + <0xA 0x80000000 0x1 0x80000000>, + <0x9 0x00000000 0x1 0x80000000>, + <0x1 0x00000000 0x3 0x00000000>, + <0x0 0xd0000000 0x0 0x01900000>, + <0x0 0xd3500000 0x0 0x2cb00000>; + }; +}; From 8fce24a418bdd498ae478fa381023db2f8565f44 Mon Sep 17 00:00:00 2001 From: Timple Raj M Date: Tue, 21 Apr 2026 10:15:55 +0530 Subject: [PATCH 09/20] serial: msm-geni: configure RX watermark register The SE_GENI_RX_WATERMARK_REG was not being programmed in the RX setup paths. Set it to DEF_RX_WM (2) in qcom_geni_serial_start_rx(), msm_geni_serial_setup_rx() and _debug_uart_init() to align with the Linux kernel driver behaviour. Without this, the RX FIFO watermark interrupt threshold is left at its hardware reset value, which may differ from the expected value and can cause RX data loss or missed watermark interrupts. Link: https://lore.kernel.org/all/20200227132223.864425794@linuxfoundation.org/ Signed-off-by: Timple Raj M Signed-off-by: Gurumoorthy Santhakumar Reviewed-by: Simon Glass Reviewed-by: Sumit Garg Reviewed-by: Csey Connolly Link: https://patch.msgid.link/20260421044555.368486-1-gurumoorthy.santhakumar@oss.qualcomm.com Signed-off-by: Casey Connolly --- drivers/serial/serial_msm_geni.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c index 3dca581f68f..ae4015e0fdc 100644 --- a/drivers/serial/serial_msm_geni.c +++ b/drivers/serial/serial_msm_geni.c @@ -55,6 +55,7 @@ #define SE_UART_RX_PARITY_CFG 0x2a8 #define DEF_TX_WM 2 +#define DEF_RX_WM 2 /* GENI_FORCE_DEFAULT_REG fields */ #define UART_START_READ 0x1 @@ -345,6 +346,7 @@ static void qcom_geni_serial_start_rx(struct udevice *dev) geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG); setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); } @@ -373,6 +375,7 @@ static void msm_geni_serial_setup_rx(struct udevice *dev) geni_se_setup_s_cmd(priv->base, UART_START_READ, 0); + writel(DEF_RX_WM, priv->base + SE_GENI_RX_WATERMARK_REG); setbits_le32(priv->base + SE_GENI_S_IRQ_EN, S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); setbits_le32(priv->base + SE_GENI_M_IRQ_EN, M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); } @@ -616,6 +619,7 @@ static inline void _debug_uart_init(void) phys_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); geni_serial_init(&init_dev); + writel(DEF_RX_WM, base + SE_GENI_RX_WATERMARK_REG); geni_serial_baud(base, CLK_DIV, CONFIG_BAUDRATE); qcom_geni_serial_start_tx(base); } From 53e6ccc0c10ac8b7b8808ffafaa3f3104902fe8a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 5 May 2026 11:14:31 +0200 Subject: [PATCH 10/20] cmd: ufetch: show net feature when NET_LWIP is selected We've had a new lwIP networking stack for a couple of years already, so let's show there is a "net" feature if it's selected. Since NET_LEGACY || NET_LWIP is the same as NET, let's check on NET. Reported-by: Simon Glass Closes: https://lore.kernel.org/u-boot/CAFLszTgZC1FGy8965pHiG-u=FhrguftRv41ghQ_Qb_RRXx6tyg@mail.gmail.com/ Reviewed-by: Simon Glass Reviewed-by: Casey Connolly Signed-off-by: Quentin Schulz Link: https://patch.msgid.link/20260505-ufetch-net-v3-1-eee5eb9ca5ce@cherry.de Signed-off-by: Casey Connolly --- cmd/ufetch.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cmd/ufetch.c b/cmd/ufetch.c index f8dc904bdd0..bc5db08eee1 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -159,7 +159,7 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, break; case FEATURES: printf("Features:" RESET " "); - if (IS_ENABLED(CONFIG_NET_LEGACY)) + if (IS_ENABLED(CONFIG_NET)) printf("Net"); if (IS_ENABLED(CONFIG_EFI_LOADER)) printf(", EFI"); From 218cbc4b12615e01c034bc6da925653903c0bb2a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Tue, 5 May 2026 11:14:32 +0200 Subject: [PATCH 11/20] cmd: ufetch: only show comma separator if there was a previous feature Currently, if NET is disabled, the next feature to be printed will start with a comma and a space which is not pretty. Add the comma and whitespace only when a previous feature has already been shown. Signed-off-by: Quentin Schulz Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260505-ufetch-net-v3-2-eee5eb9ca5ce@cherry.de Signed-off-by: Casey Connolly --- cmd/ufetch.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/cmd/ufetch.c b/cmd/ufetch.c index bc5db08eee1..e7b5d773f5e 100644 --- a/cmd/ufetch.c +++ b/cmd/ufetch.c @@ -157,26 +157,37 @@ static int do_ufetch(struct cmd_tbl *cmdtp, int flag, int argc, printf(" (%d baud)", gd->baudrate); putc('\n'); break; - case FEATURES: + case FEATURES: { + const char *sep = ""; + printf("Features:" RESET " "); - if (IS_ENABLED(CONFIG_NET)) - printf("Net"); - if (IS_ENABLED(CONFIG_EFI_LOADER)) - printf(", EFI"); - if (IS_ENABLED(CONFIG_CMD_CAT)) - printf(", cat :3"); + if (IS_ENABLED(CONFIG_NET)) { + printf("%sNet", sep); + sep = ", "; + } + if (IS_ENABLED(CONFIG_EFI_LOADER)) { + printf("%sEFI", sep); + sep = ", "; + } + if (IS_ENABLED(CONFIG_CMD_CAT)) { + printf("%scat :3", sep); + sep = ", "; + } #ifdef CONFIG_ARM64 switch (current_el()) { case 2: - printf(", VMs"); + printf("%sVMs", sep); + sep = ", "; break; case 3: - printf(", full control!"); + printf("%sfull control!", sep); + sep = ", "; break; } #endif printf("\n"); break; + } case RELOCATION: if (gd->flags & GD_FLG_SKIP_RELOC) printf("Relocated:" RESET " no\n"); From 140f248556f48e595480e207af13aa48629566a3 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Wed, 4 Feb 2026 16:10:52 +0000 Subject: [PATCH 12/20] clk/qcom: Add SM6125 clock driver Add clock driver for the GCC block found in the SM6125 SoC. Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly soc98: input: 1 [x] mmc@4784000.cd-gpios soc98: input: 0 [x] mmc@4784000.cd-gpios Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-1-9cf4c556557a@gmail.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sm6125.c | 260 ++++++++++++++++++++++++++++++++ 3 files changed, 269 insertions(+) create mode 100644 drivers/clk/qcom/clock-sm6125.c diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 0a2ce55aaa2..9ad233c83ac 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -111,6 +111,14 @@ config CLK_QCOM_SM6115 on the Snapdragon SM6115 SoC. This driver supports the clocks and resets exposed by the GCC hardware block. +config CLK_QCOM_SM6125 + bool "Qualcomm SM6125 GCC" + select CLK_QCOM + help + Say Y here to enable support for the Global Clock Controller + on the Snapdragon SM6125 SoC. This driver supports the clocks + and resets exposed by the GCC hardware block. + config CLK_QCOM_SM6350 bool "Qualcomm SM6350 GCC" select CLK_QCOM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index b96d61b603e..c0d95a6300e 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CLK_QCOM_QCS615) += clock-qcs615.o obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o obj-$(CONFIG_CLK_QCOM_SC7280) += clock-sc7280.o obj-$(CONFIG_CLK_QCOM_SM6115) += clock-sm6115.o +obj-$(CONFIG_CLK_QCOM_SM6125) += clock-sm6125.o obj-$(CONFIG_CLK_QCOM_SM6350) += clock-sm6350.o obj-$(CONFIG_CLK_QCOM_SM7150) += clock-sm7150.o obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o diff --git a/drivers/clk/qcom/clock-sm6125.c b/drivers/clk/qcom/clock-sm6125.c new file mode 100644 index 00000000000..1fd72d55e88 --- /dev/null +++ b/drivers/clk/qcom/clock-sm6125.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Clock drivers for Qualcomm sm6125 + * + * (C) Copyright 2026 Biswapriyo Nath + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "clock-qcom.h" + +#define GCC_BASE 0x01400000 + +#define QUPV3_WRAP0_S4_CMD_RCGR 0x1f608 +#define SDCC1_APPS_CLK_CMD_RCGR 0x38028 +#define SDCC2_APPS_CLK_CMD_RCGR 0x1e00c + +#define GCC_GPLL0_MODE 0x0 +#define GCC_GPLL3_MODE 0x3000 +#define GCC_GPLL4_MODE 0x4000 +#define GCC_GPLL5_MODE 0x5000 +#define GCC_GPLL6_MODE 0x6000 +#define GCC_GPLL7_MODE 0x7000 +#define GCC_GPLL8_MODE 0x8000 +#define GCC_GPLL9_MODE 0x9000 + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + F(7372800, CFG_CLK_SRC_GPLL0_AUX2, 1, 384, 15625), + F(14745600, CFG_CLK_SRC_GPLL0_AUX2, 1, 768, 15625), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(29491200, CFG_CLK_SRC_GPLL0_AUX2, 1, 1536, 15625), + F(32000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 75), + F(48000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 25), + F(64000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 16, 75), + F(75000000, CFG_CLK_SRC_GPLL0_AUX2, 4, 0, 0), + F(80000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 4, 15), + F(96000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 8, 25), + F(100000000, CFG_CLK_SRC_GPLL0, 6, 0, 0), + F(102400000, CFG_CLK_SRC_GPLL0_AUX2, 1, 128, 375), + F(112000000, CFG_CLK_SRC_GPLL0_AUX2, 1, 28, 75), + F(117964800, CFG_CLK_SRC_GPLL0_AUX2, 1, 6144, 15625), + F(120000000, CFG_CLK_SRC_GPLL0_AUX2, 2.5, 0, 0), + F(128000000, CFG_CLK_SRC_GPLL6, 3, 0, 0), + {} +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + F(400000, CFG_CLK_SRC_CXO, 12, 1, 4), + F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0), + F(25000000, CFG_CLK_SRC_GPLL0_AUX2, 12, 0, 0), + F(50000000, CFG_CLK_SRC_GPLL0_AUX2, 6, 0, 0), + F(100000000, CFG_CLK_SRC_GPLL0_AUX2, 3, 0, 0), + {} +}; + +static const struct pll_vote_clk gpll0_clk = { + .status = 0, + .status_bit = BIT(31), + .ena_vote = 0x79000, + .vote_bit = BIT(0), +}; + +static const struct gate_clk sm6125_clks[] = { + GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1a084, BIT(0)), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_2X_CLK, 0x7900c, BIT(9)), + GATE_CLK(GCC_QUPV3_WRAP0_CORE_CLK, 0x7900c, BIT(8)), + GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x7900c, BIT(10)), + GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x7900c, BIT(11)), + GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x7900c, BIT(12)), + GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x7900c, BIT(13)), + GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x7900c, BIT(14)), + GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x7900c, BIT(15)), + GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x7900c, BIT(6)), + GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x7900c, BIT(7)), + GATE_CLK(GCC_SDCC1_AHB_CLK, 0x38008, BIT(0)), + GATE_CLK(GCC_SDCC1_APPS_CLK, 0x38004, BIT(0)), + GATE_CLK(GCC_SDCC1_ICE_CORE_CLK, 0x3800c, BIT(0)), + GATE_CLK(GCC_SDCC2_AHB_CLK, 0x1e008, BIT(0)), + GATE_CLK(GCC_SDCC2_APPS_CLK, 0x1e004, BIT(0)), + GATE_CLK(GCC_SYS_NOC_CPUSS_AHB_CLK, 0x79004, BIT(0)), + GATE_CLK(GCC_SYS_NOC_UFS_PHY_AXI_CLK, 0x45098, BIT(0)), + GATE_CLK(GCC_SYS_NOC_USB3_PRIM_AXI_CLK, 0x1a080, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x45014, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x45010, BIT(0)), + GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x45044, BIT(0)), + GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x45078, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x4501c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x45018, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x45040, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1a010, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1a018, BIT(0)), + GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1a014, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x80278, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1a054, BIT(0)), + GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x1a058, BIT(0)), + GATE_CLK(GCC_AHB2PHY_USB_CLK, 0x1d008, BIT(0)), + GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)), +}; + +static ulong sm6125_set_rate(struct clk *clk, ulong rate) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + const struct freq_tbl *freq; + + debug("%s: clk %s rate %lu\n", __func__, sm6125_clks[clk->id].name, + rate); + + switch (clk->id) { + case GCC_QUPV3_WRAP0_S4_CLK: + freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate); + clk_rcg_set_rate_mnd(priv->base, QUPV3_WRAP0_S4_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 16); + return 0; + case GCC_SDCC2_APPS_CLK: + clk_enable_gpll0(priv->base, &gpll0_clk); + freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate); + WARN(freq->src != CFG_CLK_SRC_GPLL0, + "SDCC2_APPS_CLK_SRC not set to GPLL0, requested rate %lu\n", + rate); + clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, + 8); + return freq->freq; + case GCC_SDCC1_APPS_CLK: + /* The firmware turns this on for us and always sets it to this rate */ + return 384000000; + default: + return rate; + } +} + +static int sm6125_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + if (priv->data->num_clks < clk->id) { + debug("%s: unknown clk id %lu\n", __func__, clk->id); + return 0; + } + + debug("%s: clk %s\n", __func__, sm6125_clks[clk->id].name); + + switch (clk->id) { + case GCC_USB30_PRIM_MASTER_CLK: + qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK); + qcom_gate_clk_en(priv, GCC_USB3_PRIM_CLKREF_CLK); + break; + } + + return qcom_gate_clk_en(priv, clk->id); +} + +static const struct qcom_reset_map sm6125_gcc_resets[] = { + [GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 }, + [GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 }, + [GCC_UFS_PHY_BCR] = { 0x45000 }, + [GCC_USB30_PRIM_BCR] = { 0x1a000 }, + [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 }, + [GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 }, + [GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 }, + [GCC_CAMSS_MICRO_BCR] = { 0x560ac }, +}; + +static const struct qcom_power_map sm6125_gdscs[] = { + [USB30_PRIM_GDSC] = { 0x1a004 }, + [UFS_PHY_GDSC] = { 0x45004 }, + [CAMSS_VFE0_GDSC] = { 0x54004 }, + [CAMSS_VFE1_GDSC] = { 0x5403c }, + [CAMSS_TOP_GDSC] = { 0x5607c }, + [CAM_CPP_GDSC] = { 0x560bc }, + [HLOS1_VOTE_TURING_MMU_TBU1_GDSC] = { 0x7d060 }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC] = { 0x80074 }, + [HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC] = { 0x80084 }, + [HLOS1_VOTE_TURING_MMU_TBU0_GDSC] = { 0x80094 }, +}; + +static const phys_addr_t sm6125_gpll_addrs[] = { + GCC_BASE + GCC_GPLL0_MODE, GCC_BASE + GCC_GPLL3_MODE, + GCC_BASE + GCC_GPLL4_MODE, GCC_BASE + GCC_GPLL5_MODE, + GCC_BASE + GCC_GPLL6_MODE, GCC_BASE + GCC_GPLL7_MODE, + GCC_BASE + GCC_GPLL8_MODE, GCC_BASE + GCC_GPLL9_MODE, +}; + +static const phys_addr_t sm6125_rcg_addrs[] = { + 0x0141a01c, // GCC_USB30_PRIM_MASTER_CMD_RCGR + 0x0141a034, // GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR + 0x0141a060, // GCC_USB3_PRIM_PHY_AUX_CMD_RCGR + 0x01438028, // GCC_SDCC1_APPS_CMD_RCGR + 0x0141e00c, // GCC_SDCC2_APPS_CMD_RCGR + 0x0141f148, // GCC_QUPV3_WRAP0_S0_CMD_RCGR + 0x0141f278, // GCC_QUPV3_WRAP0_S1_CMD_RCGR + 0x0141f3a8, // GCC_QUPV3_WRAP0_S2_CMD_RCGR + 0x0141f4d8, // GCC_QUPV3_WRAP0_S3_CMD_RCGR + 0x0141f608, // GCC_QUPV3_WRAP0_S4_CMD_RCGR + 0x0141f738, // GCC_QUPV3_WRAP0_S5_CMD_RCGR + 0x01445020, // GCC_UFS_PHY_AXI_CMD_RCGR + 0x01445048, // GCC_UFS_PHY_ICE_CORE_CMD_RCGR + 0x01445060, // GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR + 0x0144507c, // GCC_UFS_PHY_PHY_AUX_CMD_RCGR +}; + +static const char *const sm6125_rcg_names[] = { + "GCC_USB30_PRIM_MASTER_CMD_RCGR", + "GCC_USB30_PRIM_MOCK_UTMI_CMD_RCGR", + "GCC_USB3_PRIM_PHY_AUX_CMD_RCGR", + "GCC_SDCC1_APPS_CMD_RCGR", + "GCC_SDCC2_APPS_CMD_RCGR", + "GCC_QUPV3_WRAP0_S0_CMD_RCGR", + "GCC_QUPV3_WRAP0_S1_CMD_RCGR", + "GCC_QUPV3_WRAP0_S2_CMD_RCGR", + "GCC_QUPV3_WRAP0_S3_CMD_RCGR", + "GCC_QUPV3_WRAP0_S4_CMD_RCGR", + "GCC_QUPV3_WRAP0_S5_CMD_RCGR", + "GCC_UFS_PHY_AXI_CMD_RCGR", + "GCC_UFS_PHY_ICE_CORE_CMD_RCGR", + "GCC_UFS_PHY_UNIPRO_CORE_CMD_RCGR", + "GCC_UFS_PHY_PHY_AUX_CMD_RCGR", +}; + +static struct msm_clk_data sm6125_gcc_data = { + .resets = sm6125_gcc_resets, + .num_resets = ARRAY_SIZE(sm6125_gcc_resets), + .clks = sm6125_clks, + .num_clks = ARRAY_SIZE(sm6125_clks), + .power_domains = sm6125_gdscs, + .num_power_domains = ARRAY_SIZE(sm6125_gdscs), + + .enable = sm6125_enable, + .set_rate = sm6125_set_rate, + + .dbg_pll_addrs = sm6125_gpll_addrs, + .num_plls = ARRAY_SIZE(sm6125_gpll_addrs), + .dbg_rcg_addrs = sm6125_rcg_addrs, + .num_rcgs = ARRAY_SIZE(sm6125_rcg_addrs), + .dbg_rcg_names = sm6125_rcg_names, +}; + +static const struct udevice_id gcc_sm6125_of_match[] = { + { + .compatible = "qcom,gcc-sm6125", + .data = (ulong)&sm6125_gcc_data, + }, + {} +}; + +U_BOOT_DRIVER(gcc_sm6125) = { + .name = "gcc_sm6125", + .id = UCLASS_NOP, + .of_match = gcc_sm6125_of_match, + .bind = qcom_cc_bind, + .flags = DM_FLAG_PRE_RELOC, +}; From b6470f662a4413794770b349f914c6e6a1eb8504 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Wed, 4 Feb 2026 16:10:53 +0000 Subject: [PATCH 13/20] qcom_defconfig: Enable SM6125 clock driver Enable the driver so that SM6125 devices can boot with qcom_defconfig. Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly soc98: input: 1 [x] mmc@4784000.cd-gpios soc98: input: 0 [x] mmc@4784000.cd-gpios Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-2-9cf4c556557a@gmail.com Signed-off-by: Casey Connolly --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index d0d54ec5a70..facc9785d05 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -65,6 +65,7 @@ CONFIG_CLK_QCOM_QCS8300=y CONFIG_CLK_QCOM_SA8775P=y CONFIG_CLK_QCOM_SDM845=y CONFIG_CLK_QCOM_SM6115=y +CONFIG_CLK_QCOM_SM6125=y CONFIG_CLK_QCOM_SM6350=y CONFIG_CLK_QCOM_SM7150=y CONFIG_CLK_QCOM_SM8150=y From 60bc1eb8c2f17ee53b566b27da1d11c5cdc25e76 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Wed, 4 Feb 2026 16:10:54 +0000 Subject: [PATCH 14/20] drivers: pinctrl: Add Qualcomm SM6125 TLMM driver Add support for TLMM pin controller block (Top Level Mode Multiplexer) on SM6125 SoC, with support for special pins. Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly soc98: input: 1 [x] mmc@4784000.cd-gpios soc98: input: 0 [x] mmc@4784000.cd-gpios Link: https://patch.msgid.link/20260204-sm6125-clk-pinctrl-v1-3-9cf4c556557a@gmail.com Signed-off-by: Casey Connolly --- drivers/pinctrl/qcom/Kconfig | 8 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6125.c | 147 ++++++++++++++++++++++++++ 3 files changed, 156 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6125.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 11e6763b5f3..43100d5d981 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -133,6 +133,14 @@ config PINCTRL_QCOM_SM6115 Say Y here to enable support for pinctrl on the Snapdragon SM6115 SoC, as well as the associated GPIO driver. +config PINCTRL_QCOM_SM6125 + bool "Qualcomm SM6125 Pinctrl" + default y if PINCTRL_QCOM_GENERIC + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon SM6125 SoC, + as well as the associated GPIO driver. + config PINCTRL_QCOM_SM6350 bool "Qualcomm SM6350 Pinctrl" default y if PINCTRL_QCOM_GENERIC diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 4096c1aa491..87cb128c4d4 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_QCOM_SDM670) += pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_QCOM_SM6115) += pinctrl-sm6115.o +obj-$(CONFIG_PINCTRL_QCOM_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_QCOM_SM6350) += pinctrl-sm6350.o obj-$(CONFIG_PINCTRL_QCOM_SM7150) += pinctrl-sm7150.o obj-$(CONFIG_PINCTRL_QCOM_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c new file mode 100644 index 00000000000..82f8972ff5b --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Pinctrl driver for Qualcomm SM6125 + * + * (C) Copyright 2026 Biswapriyo Nath + * + * Based on Linux Kernel driver + */ + +#include + +#include "pinctrl-qcom.h" + +#define TLMM_BASE 0x00500000 +#define WEST (0x00500000 - TLMM_BASE) /* 0x0 */ +#define SOUTH (0x00900000 - TLMM_BASE) /* 0x400000 */ +#define EAST (0x00d00000 - TLMM_BASE) /* 0x800000 */ + +#define MAX_PIN_NAME_LEN 32 +static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); + +static const struct pinctrl_function msm_pinctrl_functions[] = { + { "qup04", 1 }, + { "gpio", 0 }, +}; + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = pg_name, \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = pg_name, \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + } + +static const struct msm_special_pin_data msm_special_pins_data[] = { + [0] = UFS_RESET("ufs_reset", 0x190000), + [1] = SDC_QDSD_PINGROUP("sdc1_rclk", WEST + 0x18d000, 15, 0), + [2] = SDC_QDSD_PINGROUP("sdc1_clk", WEST + 0x18d000, 13, 6), + [3] = SDC_QDSD_PINGROUP("sdc1_cmd", WEST + 0x18d000, 11, 3), + [4] = SDC_QDSD_PINGROUP("sdc1_data", WEST + 0x18d000, 9, 0), + [5] = SDC_QDSD_PINGROUP("sdc2_clk", SOUTH + 0x58b000, 14, 6), + [6] = SDC_QDSD_PINGROUP("sdc2_cmd", SOUTH + 0x58b000, 11, 3), + [7] = SDC_QDSD_PINGROUP("sdc2_data", SOUTH + 0x58b000, 9, 0), +}; + +static const unsigned int sm6125_pin_offsets[] = { + [0] = WEST, [1] = WEST, [2] = WEST, [3] = WEST, + [4] = WEST, [5] = WEST, [6] = WEST, [7] = WEST, + [8] = WEST, [9] = WEST, [10] = EAST, [11] = EAST, + [12] = EAST, [13] = EAST, [14] = WEST, [15] = WEST, + [16] = WEST, [17] = WEST, [18] = EAST, [19] = EAST, + [20] = EAST, [21] = EAST, [22] = WEST, [23] = WEST, + [24] = WEST, [25] = WEST, [26] = WEST, [27] = WEST, + [28] = WEST, [29] = WEST, [30] = WEST, [31] = WEST, + [32] = WEST, [33] = WEST, [34] = SOUTH, [35] = SOUTH, + [36] = SOUTH, [37] = SOUTH, [38] = EAST, [39] = EAST, + [40] = EAST, [41] = EAST, [42] = EAST, [43] = EAST, + [44] = SOUTH, [45] = SOUTH, [46] = SOUTH, [47] = SOUTH, + [48] = SOUTH, [49] = SOUTH, [50] = SOUTH, [51] = SOUTH, + [52] = SOUTH, [53] = SOUTH, [54] = SOUTH, [55] = SOUTH, + [56] = SOUTH, [57] = SOUTH, [58] = SOUTH, [59] = SOUTH, + [60] = SOUTH, [61] = SOUTH, [62] = SOUTH, [63] = SOUTH, + [64] = SOUTH, [65] = SOUTH, [66] = SOUTH, [67] = SOUTH, + [68] = SOUTH, [69] = SOUTH, [70] = SOUTH, [71] = SOUTH, + [72] = SOUTH, [73] = SOUTH, [74] = SOUTH, [75] = SOUTH, + [76] = SOUTH, [77] = SOUTH, [78] = SOUTH, [79] = SOUTH, + [80] = SOUTH, [81] = SOUTH, [82] = SOUTH, [83] = SOUTH, + [84] = SOUTH, [85] = SOUTH, [86] = SOUTH, [87] = WEST, + [88] = WEST, [89] = WEST, [90] = WEST, [91] = WEST, + [92] = WEST, [93] = WEST, [94] = SOUTH, [95] = SOUTH, + [96] = SOUTH, [97] = SOUTH, [98] = SOUTH, [99] = SOUTH, + [100] = SOUTH, [101] = SOUTH, [102] = SOUTH, [103] = SOUTH, + [104] = EAST, [105] = EAST, [106] = EAST, [107] = EAST, + [108] = EAST, [109] = EAST, [110] = EAST, [111] = EAST, + [112] = EAST, [113] = EAST, [114] = EAST, [115] = EAST, + [116] = EAST, [117] = SOUTH, [118] = SOUTH, [119] = SOUTH, + [120] = SOUTH, [121] = EAST, [122] = EAST, [123] = EAST, + [124] = EAST, [125] = EAST, [126] = EAST, [127] = EAST, + [128] = EAST, [129] = SOUTH, [130] = SOUTH, [131] = SOUTH, + [132] = SOUTH, +}; + +static const char *sm6125_get_function_name(struct udevice *dev, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].name; +} + +static const char *sm6125_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + if (selector >= 133 && selector <= 140) + snprintf(pin_name, MAX_PIN_NAME_LEN, + msm_special_pins_data[selector - 133].name); + else + snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector); + + return pin_name; +} + +static int sm6125_get_function_mux(__maybe_unused unsigned int pin, + unsigned int selector) +{ + return msm_pinctrl_functions[selector].val; +} + +static struct msm_pinctrl_data sm6125_data = { + .pin_data = { + .pin_offsets = sm6125_pin_offsets, + .pin_count = 141, + .special_pins_start = 133, + .special_pins_data = msm_special_pins_data, + }, + .functions_count = ARRAY_SIZE(msm_pinctrl_functions), + .get_function_name = sm6125_get_function_name, + .get_function_mux = sm6125_get_function_mux, + .get_pin_name = sm6125_get_pin_name, +}; + +static const struct udevice_id msm_pinctrl_ids[] = { + { .compatible = "qcom,sm6125-tlmm", .data = (ulong)&sm6125_data }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(pinctrl_sm6125) = { + .name = "pinctrl_sm6125", + .id = UCLASS_NOP, + .of_match = msm_pinctrl_ids, + .ops = &msm_pinctrl_ops, + .bind = msm_pinctrl_bind, +}; From 246b0f185ac08cca335a983235eb8978d6b74113 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:05:31 +0200 Subject: [PATCH 15/20] gpio: qcom_pmic: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260507220549.209113-1-marek.vasut+renesas@mailbox.org Signed-off-by: Casey Connolly --- drivers/gpio/qcom_pmic_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 4458c55cd3d..3cabb7df88c 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -410,7 +410,7 @@ static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigne return 0; } -struct pinctrl_ops qcom_pmic_pinctrl_ops = { +static const struct pinctrl_ops qcom_pmic_pinctrl_ops = { .get_pins_count = qcom_pmic_pinctrl_get_pins_count, .get_pin_name = qcom_pmic_pinctrl_get_pin_name, .set_state = pinctrl_generic_set_state, From bc2811928806bf74d1cd2e24da34d9d6d169e1fd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:05:32 +0200 Subject: [PATCH 16/20] gpio: qcom: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260507220549.209113-2-marek.vasut+renesas@mailbox.org Signed-off-by: Casey Connolly --- drivers/gpio/qcom_spmi_gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpio/qcom_spmi_gpio.c b/drivers/gpio/qcom_spmi_gpio.c index 77a69140213..ae75a4e151d 100644 --- a/drivers/gpio/qcom_spmi_gpio.c +++ b/drivers/gpio/qcom_spmi_gpio.c @@ -1020,7 +1020,7 @@ static int qcom_spmi_pmic_pinctrl_pinmux_set_mux(struct udevice *dev, unsigned i return spmi_pmic_gpio_write(plat, pad, PMIC_GPIO_REG_EN_CTL, val); } -struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { +static const struct pinctrl_ops qcom_spmi_pmic_pinctrl_ops = { .get_pins_count = qcom_spmi_pmic_pinctrl_get_pins_count, .get_pin_name = qcom_spmi_pmic_pinctrl_get_pin_name, .set_state = pinctrl_generic_set_state, From 5a995c2fe0b17dbff46fd7b3ed26a8338fd55404 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 14:21:37 +0200 Subject: [PATCH 17/20] pci: pcie_dw_qcom: Staticize and constify driver ops Set the ops structure as static const. The structure is not accessible from outside of this driver and is not going to be modified at runtime. Signed-off-by: Marek Vasut Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260508122144.512818-1-marek.vasut+renesas@mailbox.org Signed-off-by: Casey Connolly --- drivers/pci/pcie_dw_qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c index 10c45aaba20..ce6b4d97d1d 100644 --- a/drivers/pci/pcie_dw_qcom.c +++ b/drivers/pci/pcie_dw_qcom.c @@ -22,7 +22,7 @@ struct qcom_pcie; -struct qcom_pcie_ops { +static const struct qcom_pcie_ops { int (*config_sid)(struct qcom_pcie *priv); }; From d54d2ec651e2a98a0fe84f3f176005205fa4bdf6 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Fri, 15 May 2026 18:10:02 +0000 Subject: [PATCH 18/20] phy: qcom: Add SM6115 and SM6125 to QMP UFS PHY driver The UFS on SM6125 can reuse SM6115 configuration, just like Linux. Reviewed-by: Neil Armstrong Signed-off-by: Biswapriyo Nath Reviewed-by: Casey Connolly Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-1-0a35d083d2da@gmail.com Signed-off-by: Casey Connolly --- drivers/phy/qcom/phy-qcom-qmp-ufs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 80eba734a63..3df88189a90 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -1741,6 +1741,8 @@ static const struct udevice_id qmp_ufs_ids[] = { { .compatible = "qcom,milos-qmp-ufs-phy", .data = (ulong)&milos_ufsphy_cfg, }, { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, + { .compatible = "qcom,sm6115-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, + { .compatible = "qcom,sm6125-qmp-ufs-phy", .data = (ulong)&sm6115_ufsphy_cfg, }, { .compatible = "qcom,sm6350-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, { .compatible = "qcom,sm7150-qmp-ufs-phy", .data = (ulong)&sm7150_ufsphy_cfg }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, From bf6de8136737c4362a442d810deeadadab3d7948 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Fri, 15 May 2026 18:10:03 +0000 Subject: [PATCH 19/20] clk/qcom: qcm2290: Fix vote_bit of gpll6 clock This changes the vote_bit same as enable_mask in Linux clock driver. Fixes: 3ddc67573fab ("clk/qcom: qcm2290: Add SDCC1 apps clock frequency table") Signed-off-by: Biswapriyo Nath Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-2-0a35d083d2da@gmail.com Signed-off-by: Casey Connolly --- drivers/clk/qcom/clock-qcm2290.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/clock-qcm2290.c b/drivers/clk/qcom/clock-qcm2290.c index 5a599085b50..c38ff1a1e4a 100644 --- a/drivers/clk/qcom/clock-qcm2290.c +++ b/drivers/clk/qcom/clock-qcm2290.c @@ -73,7 +73,7 @@ static const struct pll_vote_clk gpll6_clk = { .status = 0x6000, .status_bit = BIT(31), .ena_vote = 0x79000, - .vote_bit = BIT(7), + .vote_bit = BIT(6), }; static const struct gate_clk qcm2290_clks[] = { From 0d131b3b06023c3fe0d1a98588e17a7894e318f0 Mon Sep 17 00:00:00 2001 From: Biswapriyo Nath Date: Fri, 15 May 2026 18:10:04 +0000 Subject: [PATCH 20/20] board/qualcomm: qcom-phone: Add poweroff command This command helps to shutdown the device directly from serial command line. Or, the phone has to be booted into recovery mode to power off. Signed-off-by: Biswapriyo Nath Link: https://patch.msgid.link/20260515-ufs-sm61x5-v2-3-0a35d083d2da@gmail.com Signed-off-by: Casey Connolly --- board/qualcomm/qcom-phone.env | 1 + configs/qcom_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env index e91ae3ecdfb..f9911340295 100644 --- a/board/qualcomm/qcom-phone.env +++ b/board/qualcomm/qcom-phone.env @@ -40,6 +40,7 @@ bootmenu_6=Dump clocks=clk dump; pause bootmenu_7=Dump environment=printenv; pause bootmenu_8=Board info=bdinfo; pause bootmenu_9=Dump bootargs=fdt print /chosen bootargs; pause +bootmenu_10=Power off=poweroff # Allow holding the volume down button while U-Boot loads to enter # the boot menu diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index facc9785d05..ecd77388763 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -38,6 +38,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_UFS=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y