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armv7: ls102xa: Add workaround for DDR erratum A-008850

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Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Alison Wang
2019-03-06 14:49:14 +08:00
committed by Prabhakar Kushwaha
parent ba7eadd8e1
commit 158097052a
10 changed files with 58 additions and 37 deletions
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2
include/configs/ls1021aiot.h
View File

@@ -85,6 +85,8 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
/*
* Serial Port
*/

2
include/configs/ls1021atwr.h
View File

@@ -104,6 +104,8 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
!defined(CONFIG_QSPI_BOOT)
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR