From a89fea7fd101212cbd0583ba7fa152009afb7a52 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Tue, 8 Feb 2022 22:00:09 +0100 Subject: [PATCH 01/10] arm: apple: Add M1 Pro/Max support Choose the memory map based on the compatible property from the device tree passed to us by m1n1. Since DRAM on the M1 Pro/Max starts at a different address avoid hardcoding the top of usable memory. Also make sure that the addresses entered into the memory map are page aligned such that we don't crash in dcache_enable(). Signed-off-by: Mark Kettenis Tested on: Macbook M1 Max Tested-by: Janne Grunau --- arch/arm/mach-apple/board.c | 217 ++++++++++++++++++++++++++++-------- 1 file changed, 173 insertions(+), 44 deletions(-) diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index b7e8d212f1a..f9f8a2f2780 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -14,12 +14,22 @@ DECLARE_GLOBAL_DATA_PTR; -static struct mm_region apple_mem_map[] = { +/* Apple M1 */ + +static struct mm_region t8103_mem_map[] = { { /* I/O */ .virt = 0x200000000, .phys = 0x200000000, - .size = 8UL * SZ_1G, + .size = 2UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -27,7 +37,7 @@ static struct mm_region apple_mem_map[] = { /* I/O */ .virt = 0x500000000, .phys = 0x500000000, - .size = 2UL * SZ_1G, + .size = SZ_1G, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -63,15 +73,110 @@ static struct mm_region apple_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - /* Empty entry for framebuffer */ - 0, + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { /* List terminator */ 0, } }; -struct mm_region *mem_map = apple_mem_map; +/* Apple M1 Pro/Max */ + +static struct mm_region t6000_mem_map[] = { + { + /* I/O */ + .virt = 0x280000000, + .phys = 0x280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xf00000000, + .phys = 0xf00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x1300000000, + .phys = 0x1300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 16UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map; int board_init(void) { @@ -80,38 +185,7 @@ int board_init(void) int dram_init(void) { - ofnode node; - int index, ret; - fdt_addr_t base; - fdt_size_t size; - - ret = fdtdec_setup_mem_size_base(); - if (ret) - return ret; - - /* Update RAM mapping */ - index = ARRAY_SIZE(apple_mem_map) - 3; - apple_mem_map[index].virt = gd->ram_base; - apple_mem_map[index].phys = gd->ram_base; - apple_mem_map[index].size = gd->ram_size; - - node = ofnode_path("/chosen/framebuffer"); - if (!ofnode_valid(node)) - return 0; - - base = ofnode_get_addr_size(node, "reg", &size); - if (base == FDT_ADDR_T_NONE) - return 0; - - /* Add framebuffer mapping */ - index = ARRAY_SIZE(apple_mem_map) - 2; - apple_mem_map[index].virt = base; - apple_mem_map[index].phys = base; - apple_mem_map[index].size = size; - apple_mem_map[index].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; - - return 0; + return fdtdec_setup_mem_size_base(); } int dram_init_banksize(void) @@ -128,11 +202,66 @@ void *board_fdt_blob_setup(int *err) return (void *)fw_dtb_pointer; } -ulong board_get_usable_ram_top(ulong total_size) +void build_mem_map(void) { - /* - * Top part of RAM is used by firmware for things like the - * framebuffer. This gives us plenty of room to play with. - */ - return 0x980000000; + ofnode node; + fdt_addr_t base; + fdt_size_t size; + int i; + + if (of_machine_is_compatible("apple,t8103")) + mem_map = t8103_mem_map; + else if (of_machine_is_compatible("apple,t6000")) + mem_map = t6000_mem_map; + else if (of_machine_is_compatible("apple,t6001")) + mem_map = t6000_mem_map; + else + panic("Unsupported SoC\n"); + + /* Find list terminator. */ + for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) + ; + + /* Align RAM mapping to page boundaries */ + base = gd->bd->bi_dram[0].start; + size = gd->bd->bi_dram[0].size; + size += (base - ALIGN_DOWN(base, SZ_4K)); + base = ALIGN_DOWN(base, SZ_4K); + size = ALIGN(size, SZ_4K); + + /* Update RAM mapping */ + mem_map[i - 2].virt = base; + mem_map[i - 2].phys = base; + mem_map[i - 2].size = size; + + node = ofnode_path("/chosen/framebuffer"); + if (!ofnode_valid(node)) + return; + + base = ofnode_get_addr_size(node, "reg", &size); + if (base == FDT_ADDR_T_NONE) + return; + + /* Align framebuffer mapping to page boundaries */ + size += (base - ALIGN_DOWN(base, SZ_4K)); + base = ALIGN_DOWN(base, SZ_4K); + size = ALIGN(size, SZ_4K); + + /* Add framebuffer mapping */ + mem_map[i - 1].virt = base; + mem_map[i - 1].phys = base; + mem_map[i - 1].size = size; +} + +void enable_caches(void) +{ + build_mem_map(); + + icache_enable(); + dcache_enable(); +} + +u64 get_page_table_size(void) +{ + return SZ_256K; } From 5a0973f013095b87959eb68ec223bc10fc6b38ce Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Mon, 14 Feb 2022 22:09:25 +0100 Subject: [PATCH 02/10] arm: apple: Disable debug UART The address of the debug UART varies differs between the M1 and the M1 Pro/Max SoCs. So we have to disable it to make a single U-Boot binary that works on all SoC generations. Leave the settings for the base address and clock rate of the M1 in place to make it easier to re-enable the debug UART when needed. Signed-off-by: Mark Kettenis --- configs/apple_m1_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 760bd81c629..9254e246995 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -3,7 +3,6 @@ CONFIG_ARCH_APPLE=y CONFIG_DEFAULT_DEVICE_TREE="t8103-j274" CONFIG_DEBUG_UART_BASE=0x235200000 CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART=y CONFIG_SYS_LOAD_ADDR=0x880000000 CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set From 0ae3c79b7c126b1e91c5851ed2549e01e8c37238 Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Mon, 14 Feb 2022 22:09:26 +0100 Subject: [PATCH 03/10] doc: board: apple: Update Apple M1 documentation U-Boot now supports NVMe storage and on the laptop models, the SPI keyboard. Since we now disable the debug console by default provide instructions on how the enable the debug console including a table listing the appropriate UART base address for each of the supported SoCs. Signed-off-by: Mark Kettenis --- doc/board/apple/m1.rst | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/doc/board/apple/m1.rst b/doc/board/apple/m1.rst index 9fa21767c92..083bfb0a1a6 100644 --- a/doc/board/apple/m1.rst +++ b/doc/board/apple/m1.rst @@ -7,18 +7,21 @@ Allows Apple Silicon Macs to boot U-Boot via the m1n1 bootloader developed by the Asahi Linux project. At this point the machines with the following SoCs work: - - Apple M1 SoC + - Apple M1 SoC (t8103) + - Apple M1 Pro SoC (t6000) + - Apple M1 Max SoC (t6001) On these SoCs the following hardware is supported: - S5L serial port + - SPI keyboard (on laptops) - Framebuffer + - NVMe storage - USB 3.1 Type-C ports -Device trees are currently provided for the M1 Mac mini (2020, J274) -and M1 MacBook Pro 13" (2020, J293). The M1 MacBook Air (2020) is -expected to work with the J293 device tree. The M1 iMac (2021) may -work with the J274 device tree. +Device trees are currently provided for the M1 Mac mini (2020, J274), +M1 MacBook Pro 13" (2020, J293), M1 MacBook Air (2020, J313) and M1 +iMac (2021, J456/J457). Building U-Boot --------------- @@ -57,3 +60,23 @@ Instructions on how to install U-Boot on your Mac can be found at: https://github.com/AsahiLinux/docs/wiki/Developer-Quickstart Just replace ``m1n1.macho`` with ``u-boot.macho`` in the instructions. + +Debug UART +---------- + +Since the base address of the UART is SoC-dependent, the debug UART is +not enabled by default. To enable the debug UART the base address +needs to be adjusted and the CONFIG_DEBUG_UART option needs to be +enabled. The table below gives the correct base address for the +supported SoCs. + +.. list-table:: + :widths: 32 16 + :header-rows: 1 + + * - SoC + - Base Address + * - M1 (t8103) + - 0x235200000 + * - M1 Pro/Max (t6000/t6001) + - 0x39b200000 From d15e1926ff0d71a57e0d607bc05d8c37358802ca Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Tue, 8 Feb 2022 22:27:49 +0100 Subject: [PATCH 04/10] iommu: Add M1 Pro/Max support to Apple DART driver For the purpose of this driver (activating bypass mode) t6000-dart and t8103-dart are fully compatible. Signed-off-by: Janne Grunau Reviewed-by: Mark Kettenis --- drivers/iommu/apple_dart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index ff8c5fa62c2..f2e17009607 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -48,6 +48,7 @@ static int apple_dart_probe(struct udevice *dev) static const struct udevice_id apple_dart_ids[] = { { .compatible = "apple,t8103-dart" }, + { .compatible = "apple,t6000-dart" }, { /* sentinel */ } }; From da6a8d9c28d0dd08b892bf6fa9f8596d1b8f7497 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Thu, 10 Feb 2022 09:25:58 +0530 Subject: [PATCH 05/10] arm: dts: k3-j721e-r5-common-proc-board: tps659413: Correct the min/max voltages of VDD_CPU Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU minimum voltage is .6V & maximum voltage is .9V. Correct the same. While at it fix the comment to reflect VDD_CPU instead of VDD_MPU. Data Sheet Link: https://www.ti.com/lit/gpn/dra829v Signed-off-by: Keerthy --- arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 54f8353d769..a14b148e11f 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -259,10 +259,10 @@ regulators: regulators { u-boot,dm-spl; buck12_reg: buck12 { - /*VDD_MPU*/ + /*VDD_CPU*/ regulator-name = "buck12"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1250000>; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <900000>; regulator-always-on; regulator-boot-on; u-boot,dm-spl; From 1c6ea4da24c7481720b8eaee32532a7881863dc9 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 12 Feb 2022 06:12:40 -0600 Subject: [PATCH 06/10] arm: omap3: Cleanup sys_info to fit OMAP3 booting with LTO With LTO enabled, some functions appear to be optimized in a way that causes hanging on some OMAP3 boards after some unrelated patches were applied. The solution appears to make several functions __used. There also appears be to be some dead code, so remove it while cleaning this up. This has been tested on a general purpose OMAP3530, DM3730, and AM3517. Signed-off-by: Adam Ford --- arch/arm/include/asm/arch-omap3/sys_proto.h | 4 --- arch/arm/mach-omap2/omap3/sys_info.c | 39 +++------------------ 2 files changed, 5 insertions(+), 38 deletions(-) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index a6e9ff84aa0..e7078a32dbe 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -45,16 +45,12 @@ void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, u32 size); void set_gpmc_cs0(int flash_type); - void watchdog_init(void); void set_muxconf_regs(void); - u32 get_cpu_family(void); u32 get_cpu_rev(void); -u32 get_sku_id(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); -u32 get_gpmc0_width(void); u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); diff --git a/arch/arm/mach-omap2/omap3/sys_info.c b/arch/arm/mach-omap2/omap3/sys_info.c index ac72633c20f..5f535e27827 100644 --- a/arch/arm/mach-omap2/omap3/sys_info.c +++ b/arch/arm/mach-omap2/omap3/sys_info.c @@ -55,7 +55,7 @@ void omap_die_id(unsigned int *die_id) /****************************************** * get_cpu_type(void) - extract cpu info ******************************************/ -u32 get_cpu_type(void) +static u32 get_cpu_type(void) { return readl(&ctrl_base->ctrl_omap_stat); } @@ -64,7 +64,7 @@ u32 get_cpu_type(void) * get_cpu_id(void) - extract cpu id * returns 0 for ES1.0, cpuid otherwise ******************************************/ -u32 get_cpu_id(void) +static u32 get_cpu_id(void) { struct ctrl_id *id_base; u32 cpuid = 0; @@ -89,7 +89,7 @@ u32 get_cpu_id(void) /****************************************** * get_cpu_family(void) - extract cpu info ******************************************/ -u32 get_cpu_family(void) +__used u32 get_cpu_family(void) { u16 hawkeye; u32 cpu_family; @@ -119,7 +119,7 @@ u32 get_cpu_family(void) /****************************************** * get_cpu_rev(void) - extract version info ******************************************/ -u32 get_cpu_rev(void) +__used u32 get_cpu_rev(void) { u32 cpuid = get_cpu_id(); @@ -132,41 +132,12 @@ u32 get_cpu_rev(void) /***************************************************************** * get_sku_id(void) - read sku_id to get info on max clock rate *****************************************************************/ -u32 get_sku_id(void) +static u32 get_sku_id(void) { struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE; return readl(&id_base->sku_id) & SKUID_CLK_MASK; } -/*************************************************************************** - * get_gpmc0_base() - Return current address hardware will be - * fetching from. The below effectively gives what is correct, its a bit - * mis-leading compared to the TRM. For the most general case the mask - * needs to be also taken into account this does work in practice. - * - for u-boot we currently map: - * -- 0 to nothing, - * -- 4 to flash - * -- 8 to enent - * -- c to wifi - ****************************************************************************/ -u32 get_gpmc0_base(void) -{ - u32 b; - - b = readl(&gpmc_cfg->cs[0].config7); - b &= 0x1F; /* keep base [5:0] */ - b = b << 24; /* ret 0x0b000000 */ - return b; -} - -/******************************************************************* - * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand) - *******************************************************************/ -u32 get_gpmc0_width(void) -{ - return WIDTH_16BIT; -} - /************************************************************************* * get_board_rev() - setup to pass kernel board revision information * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) From 68a51cc8ec4692f4d7104afde8e0db7596fce545 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 12 Feb 2022 06:12:41 -0600 Subject: [PATCH 07/10] arm: omap3: Make some memory functions static and clean headers There are a few memory functions for both the emif4 (AM3517) and sdrc (OMAP35/DM37) code that can be defined as static, because those functions are not used externally. Make them static and clean up some of the corresponding headers. Signed-off-by: Adam Ford --- arch/arm/include/asm/arch-omap3/mem.h | 1 - arch/arm/include/asm/arch-omap3/sys_proto.h | 5 --- arch/arm/mach-omap2/omap3/emif4.c | 2 +- arch/arm/mach-omap2/omap3/sdrc.c | 35 ++++++++++----------- 4 files changed, 18 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 7adc134a752..569779c55e4 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -480,7 +480,6 @@ void mem_init(void); u32 is_mem_sdr(void); u32 mem_ok(u32 cs); -u32 get_sdr_cs_size(u32); u32 get_sdr_cs_offset(u32); #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index e7078a32dbe..3e6335c5fa1 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -33,11 +33,8 @@ struct board_sdrc_timings { void prcm_init(void); void per_clocks_enable(void); void ehci_clocks_enable(void); - void memif_init(void); void sdrc_init(void); -void do_sdrc_init(u32, u32); - void get_board_mem_timings(struct board_sdrc_timings *timings); int identify_nand_chip(int *mfr, int *id); void emif4_init(void); @@ -60,12 +57,10 @@ void invalidate_dcache(u32); u32 wait_on_value(u32, u32, void *, u32); void cancel_out(u32 *num, u32 *den, u32 den_limit); void sdelay(unsigned long); -void make_cs1_contiguous(void); int omap_nand_switch_ecc(uint32_t, uint32_t); void power_init_r(void); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); void omap3_set_aux_cr_secure(u32 acr); u32 warm_reset(void); - void save_omap_boot_params(void); #endif diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index df6e9ce1d6c..d7d779819bf 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -35,7 +35,7 @@ u32 is_mem_sdr(void) * get_sdr_cs_size - * - Get size of chip select 0/1 */ -u32 get_sdr_cs_size(u32 cs) +static u32 get_sdr_cs_size(u32 cs) { u32 size = 0; diff --git a/arch/arm/mach-omap2/omap3/sdrc.c b/arch/arm/mach-omap2/omap3/sdrc.c index 4d85b1dee99..07f534a60b2 100644 --- a/arch/arm/mach-omap2/omap3/sdrc.c +++ b/arch/arm/mach-omap2/omap3/sdrc.c @@ -44,13 +44,28 @@ u32 is_mem_sdr(void) return 0; } +/* + * get_sdr_cs_size - + * - Get size of chip select 0/1 + */ +static u32 get_sdr_cs_size(u32 cs) +{ + u32 size; + + /* get ram size field */ + size = readl(&sdrc_base->cs[cs].mcfg) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size <<= 21; /* multiply by 2 MiB to find size in MB */ + return size; +} + /* * make_cs1_contiguous - * - When we have CS1 populated we want to have it mapped after cs0 to allow * command line mem=xyz use all memory with out discontinuous support * compiled in. We could do it in the ATAG, but there really is two banks... */ -void make_cs1_contiguous(void) +static void make_cs1_contiguous(void) { u32 size, a_add_low, a_add_high; @@ -62,22 +77,6 @@ void make_cs1_contiguous(void) } - -/* - * get_sdr_cs_size - - * - Get size of chip select 0/1 - */ -u32 get_sdr_cs_size(u32 cs) -{ - u32 size; - - /* get ram size field */ - size = readl(&sdrc_base->cs[cs].mcfg) >> 8; - size &= 0x3FF; /* remove unwanted bits */ - size <<= 21; /* multiply by 2 MiB to find size in MB */ - return size; -} - /* * get_sdr_cs_offset - * - Get offset of cs from cs0 start @@ -128,7 +127,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, * true and a possible 2nd time depending on memory configuration from * stack+global context. */ -void do_sdrc_init(u32 cs, u32 early) +static void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; struct board_sdrc_timings timings; From 5d90836cb51de553cf3a83143f99cd60cae26578 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Sun, 13 Feb 2022 12:48:48 -0600 Subject: [PATCH 08/10] arm: dts: k3-j7200: Fix up MAIN R5FSS cluster mode back to Split-mode The default U-Boot environment variables and design are all set up for the MAIN R5FSS cluster to be in Split-mode. This is the setting used when the dts nodes were originally added in v2021.01 U-Boot and the dt nodes are synched with the kernel binding property names in commit 468ec2f3ef8f ("remoteproc: k3_r5: Sync to upstreamed kernel DT property names") merged in v2021.04-rc2. The modes for the MAIN R5FSS cluster got switched back to LockStep mode by mistake in commit fa09b12dc5f6 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") in v2022.01-rc1. This throws the following warning messages when early-booting the cores using default env variables, k3_r5f_rproc r5f@5d00000: Invalid op: Trying to start secondary core 7 in lockstep mode Load Remote Processor 3 with data@addr=0x82000000 83148 bytes: Failed! Fix this by switching back both the clusters to the expected Split-mode. Make this mode change in the u-boot specific dtsi file to avoid such sync overrides in the future until the kernel dts is also switched to Split-mode by default. Fixes: fa09b12dc5f6 ("arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14") Signed-off-by: Suman Anna --- arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index 1544c2e51bd..ce52ffcf96a 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -192,3 +192,7 @@ &serdes0 { u-boot,dm-spl; }; + +&main_r5fss0 { + ti,cluster-mode = <0>; +}; From 829b41171b181e083fc984b72bb8acb31c1fb952 Mon Sep 17 00:00:00 2001 From: Neal Liu Date: Tue, 15 Feb 2022 18:14:40 +0800 Subject: [PATCH 09/10] crypto: aspeed: fix polling RSA status wrong issue Check interrupt status to see if RSA engine is completed. After completion of the task, write-clear the status to finish operation. Add missing register base for completion. Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY support") Signed-off-by: Neal Liu Reviewed-by: Chia-Wei Wang --- drivers/crypto/aspeed/aspeed_acry.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/crypto/aspeed/aspeed_acry.c b/drivers/crypto/aspeed/aspeed_acry.c index c28cdf374b6..47a007f633a 100644 --- a/drivers/crypto/aspeed/aspeed_acry.c +++ b/drivers/crypto/aspeed/aspeed_acry.c @@ -103,7 +103,7 @@ static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, uint32_t while (1) { reg = readl(acry->base + ACRY_RSA_INT_STS); if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_CMPLT)) { - writel(reg, ACRY_RSA_INT_STS); + writel(reg, acry->base + ACRY_RSA_INT_STS); break; } udelay(20); From a064e0c75fdf63c546a5a0885fa0c58bb1643dac Mon Sep 17 00:00:00 2001 From: Nikita Yushchenko Date: Tue, 15 Feb 2022 21:10:09 +0300 Subject: [PATCH 10/10] ti: i2c: fix probe_chip() return value Per documentation, dm_i2c_ops.probe_chip() shall return -EREMOTEIO if probe fails. Currently, omap_i2c_probe_chip() returns 1 instead. Fix that. Signed-off-by: Nikita Yushchenko Reviewed-by: Heiko Schocher --- drivers/i2c/omap24xx_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a767dee9866..c656cf8b7a1 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -1015,7 +1015,7 @@ static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, struct omap_i2c *priv = dev_get_priv(bus); return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay, - chip_addr); + chip_addr) ? -EREMOTEIO : 0; } static int omap_i2c_probe(struct udevice *bus)