Support AT91CAP9 revC CPUs

The AT91CAP9 revC CPU has a few differences over the previous,
revB CPU which was distributed in small quantities only (revA was
an internal Atmel product only).

The revC silicon needs a special initialisation sequence to
switch from the internal (imprecise) RC oscillator to the
external 32k clock.

Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Stelian Pop
2008-05-08 14:52:34 +02:00
committed by Jean-Christophe PLAGNIOL-VILLARD
parent 098b7b4b44
commit 19883aede2
3 changed files with 46 additions and 1 deletions

View File

@@ -96,4 +96,9 @@
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
#endif

View File

@@ -101,12 +101,24 @@
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
* SCKCR flags
*/
#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
/*
* Internal Memory.
*/