mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts: drivers/serial/serial.c The conflict above was a trivial case of adding one init function in each branch, and manually resolved in merge.
This commit is contained in:
Albert ARIBAUD
67
arch/arm/include/asm/arch-mx6/hab.h
Normal file
67
arch/arm/include/asm/arch-mx6/hab.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __SECURE_MX6Q_H__
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#define __SECURE_MX6Q_H__
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#include <linux/types.h>
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/* -------- start of HAB API updates ------------*/
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/* The following are taken from HAB4 SIS */
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/* Status definitions */
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enum hab_status {
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HAB_STS_ANY = 0x00,
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HAB_FAILURE = 0x33,
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HAB_WARNING = 0x69,
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HAB_SUCCESS = 0xf0
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};
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/* Security Configuration definitions */
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enum hab_config {
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HAB_CFG_RETURN = 0x33, /**< Field Return IC */
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HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
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HAB_CFG_CLOSED = 0xcc /**< Secure IC */
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};
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/* State definitions */
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enum hab_state {
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HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
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HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
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HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
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HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
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HAB_STATE_SECURE = 0xaa, /**< Secure state */
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HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
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HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
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HAB_STATE_NONE = 0xf0, /**< No security state machine */
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HAB_STATE_MAX
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};
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/*Function prototype description*/
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typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
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uint8_t* , size_t*);
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typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
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enum hab_state *);
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typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
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typedef enum hab_status hab_rvt_entry_t(void);
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typedef enum hab_status hab_rvt_exit_t(void);
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typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
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void **, size_t *, hab_loader_callback_f_t);
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typedef void hapi_clock_init_t(void);
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#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
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#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
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#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
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#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
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#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
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#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
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#define HAB_CID_ROM 0 /**< ROM Caller ID */
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#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
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/* ----------- end of HAB API updates ------------*/
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#endif
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@@ -456,7 +456,13 @@ struct fuse_bank0_regs {
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u32 uid_low;
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u32 rsvd1[3];
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u32 uid_high;
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u32 rsvd2[0x17];
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u32 rsvd2[3];
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u32 rsvd3[4];
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u32 rsvd4[4];
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u32 rsvd5[4];
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u32 cfg5;
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u32 rsvd6[3];
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u32 rsvd7[4];
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};
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struct fuse_bank4_regs {
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@@ -629,29 +635,12 @@ struct anatop_regs {
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u32 digprog_sololite; /* 0x280 */
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};
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#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
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#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
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#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
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#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
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#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
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#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
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#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
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#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
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#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
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#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
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#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
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#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
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#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
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#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
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#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
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#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
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#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
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#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
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#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
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#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
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#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
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#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
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#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
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#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
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#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
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#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
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#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
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#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
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#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
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struct iomuxc_base_regs {
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u32 gpr[14]; /* 0x000 */
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@@ -19,6 +19,13 @@
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||||
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||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
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u32 get_cpu_rev(void);
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/* returns MXC_CPU_ value */
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#define cpu_type(rev) (((rev) >> 12)&0xff)
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/* use with MXC_CPU_ constants */
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#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
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const char *get_imx_type(u32 imxtype);
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unsigned imx_ddr_size(void);
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220
arch/arm/include/asm/arch-mxs/regs-uartapp.h
Normal file
220
arch/arm/include/asm/arch-mxs/regs-uartapp.h
Normal file
@@ -0,0 +1,220 @@
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/*
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* Freescale MXS UARTAPP Register Definitions
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*
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* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
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*
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* Based on code from LTIB:
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||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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||||
*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ARCH_ARM___MXS_UARTAPP_H
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#define __ARCH_ARM___MXS_UARTAPP_H
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#include <asm/imx-common/regs-common.h>
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#ifndef __ASSEMBLY__
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struct mxs_uartapp_regs {
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mxs_reg_32(hw_uartapp_ctrl0)
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mxs_reg_32(hw_uartapp_ctrl1)
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mxs_reg_32(hw_uartapp_ctrl2)
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mxs_reg_32(hw_uartapp_linectrl)
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mxs_reg_32(hw_uartapp_linectrl2)
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mxs_reg_32(hw_uartapp_intr)
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mxs_reg_32(hw_uartapp_data)
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mxs_reg_32(hw_uartapp_stat)
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mxs_reg_32(hw_uartapp_debug)
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mxs_reg_32(hw_uartapp_version)
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mxs_reg_32(hw_uartapp_autobaud)
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};
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#endif
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#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
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#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
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#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
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#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
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||||
#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
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||||
#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
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#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
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||||
#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
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#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
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#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
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||||
#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
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||||
#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
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||||
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||||
#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
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||||
#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
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||||
#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
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||||
#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
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||||
#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
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||||
#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
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#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
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||||
#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
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#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
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#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
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#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
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||||
#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
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||||
#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
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||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
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||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
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||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
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#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
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||||
#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
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||||
#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
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#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
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||||
#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
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||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
|
||||
#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
|
||||
#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
|
||||
#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
|
||||
#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
|
||||
#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
|
||||
#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
|
||||
#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
|
||||
#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
|
||||
#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
|
||||
#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
|
||||
|
||||
#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
|
||||
#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
|
||||
#define UARTAPP_CTRL2_UARTEN_MASK 0x01
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
|
||||
#define UARTAPP_LINECTRL_BRK_MASK 1
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
|
||||
|
||||
#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
|
||||
#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
|
||||
#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
|
||||
#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
|
||||
#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
|
||||
#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
|
||||
#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
|
||||
#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
|
||||
#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
|
||||
#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
|
||||
#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
|
||||
#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
|
||||
|
||||
#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
|
||||
#define UARTAPP_INTR_OEIS_MASK (1 << 10)
|
||||
#define UARTAPP_INTR_BEIS_MASK (1 << 9)
|
||||
#define UARTAPP_INTR_PEIS_MASK (1 << 8)
|
||||
#define UARTAPP_INTR_FEIS_MASK (1 << 7)
|
||||
#define UARTAPP_INTR_RTIS_MASK (1 << 6)
|
||||
#define UARTAPP_INTR_TXIS_MASK (1 << 5)
|
||||
#define UARTAPP_INTR_RXIS_MASK (1 << 4)
|
||||
#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
|
||||
#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
|
||||
#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
|
||||
#define UARTAPP_INTR_RIMIS_MASK 0x1
|
||||
|
||||
#define UARTAPP_DATA_DATA_OFFSET 0
|
||||
#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
|
||||
#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
|
||||
|
||||
#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
|
||||
|
||||
#define UARTAPP_STAT_BUSY_MASK (1 << 29)
|
||||
#define UARTAPP_STAT_CTS_MASK (1 << 28)
|
||||
#define UARTAPP_STAT_TXFE_MASK (1 << 27)
|
||||
#define UARTAPP_STAT_RXFF_MASK (1 << 26)
|
||||
#define UARTAPP_STAT_TXFF_MASK (1 << 25)
|
||||
#define UARTAPP_STAT_RXFE_MASK (1 << 24)
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
|
||||
|
||||
#define UARTAPP_STAT_OERR_MASK (1 << 19)
|
||||
#define UARTAPP_STAT_BERR_MASK (1 << 18)
|
||||
#define UARTAPP_STAT_PERR_MASK (1 << 17)
|
||||
#define UARTAPP_STAT_FERR_MASK (1 << 16)
|
||||
#define UARTAPP_STAT_RXCOUNT_OFFSET 0
|
||||
#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
|
||||
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
|
||||
|
||||
#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
|
||||
#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
|
||||
#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
|
||||
#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
|
||||
#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
|
||||
#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
|
||||
|
||||
#define UARTAPP_VERSION_MAJOR_OFFSET 24
|
||||
#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_VERSION_MINOR_OFFSET 16
|
||||
#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_VERSION_STEP_OFFSET 0
|
||||
#define UARTAPP_VERSION_STEP_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
|
||||
#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
|
||||
#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
|
||||
#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
|
||||
#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
|
||||
#endif /* __ARCH_ARM___UARTAPP_H */
|
||||
Reference in New Issue
Block a user