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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Stefano Babic
2014-03-05 12:51:26 +01:00
parent 335143c766 cc07294bc7
commit 1ad6364eeb
987 changed files with 36620 additions and 82901 deletions
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1
include/.gitignore vendored
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@@ -1,5 +1,4 @@
/autoconf.mk*
/asm
/bmp_logo.h
/bmp_logo_data.h
/config.h

26
include/asm-generic/sections.h
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@@ -63,28 +63,16 @@ extern char __image_copy_end[];
extern void _start(void);
/*
* ARM needs to use offsets for symbols, since the values of some symbols
* are not resolved prior to relocation (and are just 0). Maybe this can be
* resolved, or maybe other architectures are similar, iwc this should be
* promoted to an architecture option.
* ARM defines its symbols as char[]. Other arches define them as ulongs.
*/
#ifdef CONFIG_ARM
#define CONFIG_SYS_SYM_OFFSETS
#endif
#ifdef CONFIG_SYS_SYM_OFFSETS
/* Start/end of the relocation entries, as an offset from _start */
extern ulong _rel_dyn_start_ofs;
extern ulong _rel_dyn_end_ofs;
/* End of the region to be relocated, as an offset form _start */
extern ulong _image_copy_end_ofs;
extern ulong _bss_start_ofs; /* BSS start relative to _start */
extern ulong _bss_end_ofs; /* BSS end relative to _start */
extern ulong _end_ofs; /* end of image relative to _start */
extern ulong _TEXT_BASE; /* code start */
extern char __bss_start[];
extern char __bss_end[];
extern char __image_copy_start[];
extern char __image_copy_end[];
extern char __rel_dyn_start[];
extern char __rel_dyn_end[];
#else /* don't use offsets: */

58
include/bitfield.h Normal file
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@@ -0,0 +1,58 @@
/*
* Copyright 2013 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Bitfield operations
*
* These are generic bitfield operations which allow manipulation of variable
* width bitfields within a word. One use of this would be to use data tables
* to determine how to reprogram fields within R/W hardware registers.
*
* Example:
*
* old_reg_val
* +--------+----+---+--+-----+----------+
* | | | | | old | |
* +--------+----+---+--+-----+----------+
*
* new_reg_val
* +--------+----+---+--+-----+----------+
* | | | | | new | |
* +--------+----+---+--+-----+----------+
*
* mask = bitfield_mask(10, 5);
* old = bitfield_extract(old_reg_val, 10, 5);
* new_reg_val = bitfield_replace(old_reg_val, 10, 5, new);
*
* The numbers 10 and 5 could for example come from data
* tables which describe all bitfields in all registers.
*/
#include <linux/types.h>
/* Produces a mask of set bits covering a range of a uint value */
static inline uint bitfield_mask(uint shift, uint width)
{
return ((1 << width) - 1) << shift;
}
/* Extract the value of a bitfield found within a given register value */
static inline uint bitfield_extract(uint reg_val, uint shift, uint width)
{
return (reg_val & bitfield_mask(shift, width)) >> shift;
}
/*
* Replace the value of a bitfield found within a given register value
* Returns the newly modified uint value with the replaced field.
*/
static inline uint bitfield_replace(uint reg_val, uint shift, uint width,
uint bitfield_val)
{
uint mask = bitfield_mask(shift, width);
return (reg_val & ~mask) | (bitfield_val << shift);
}

6
include/clk.h Normal file
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@@ -0,0 +1,6 @@
#ifndef _CLK_H_
#define _CLK_H_
int soc_clk_dump(void);
#endif /* _CLK_H_ */

29
include/common.h
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@@ -302,9 +302,16 @@ int checkdram (void);
int last_stage_init(void);
extern ulong monitor_flash_len;
int mac_read_from_eeprom(void);
extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
int set_cpu_clk_info(void);
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void);
#else
static inline int print_cpuinfo(void)
{
return 0;
}
#endif
int update_flash_size(int flash_size);
/**
@@ -408,6 +415,9 @@ static inline int setenv_addr(const char *varname, const void *addr)
#ifdef CONFIG_MIPS
# include <asm/u-boot-mips.h>
#endif /* CONFIG_MIPS */
#ifdef CONFIG_ARC
# include <asm/u-boot-arc.h>
#endif /* CONFIG_ARC */
#ifdef CONFIG_AUTO_COMPLETE
int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf);
@@ -451,6 +461,7 @@ void api_init (void);
/* common/memsize.c */
long get_ram_size (long *, long);
phys_size_t get_effective_memsize(void);
/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
@@ -961,6 +972,22 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
/*
* Divide positive or negative dividend by positive divisor and round
* to closest integer. Result is undefined for negative divisors and
* for negative dividends if the divisor variable type is unsigned.
*/
#define DIV_ROUND_CLOSEST(x, divisor)( \
{ \
typeof(x) __x = x; \
typeof(divisor) __d = divisor; \
(((typeof(x))-1) > 0 || \
((typeof(divisor))-1) > 0 || (__x) > 0) ? \
(((__x) + ((__d) / 2)) / (__d)) : \
(((__x) - ((__d) / 2)) / (__d)); \
} \
)
#define ALIGN(x,a) __ALIGN_MASK((x),(typeof(x))(a)-1)
#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask))

2
include/config_cmd_all.h
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@@ -23,6 +23,7 @@
#define CONFIG_CMD_BSP /* Board Specific functions */
#define CONFIG_CMD_CACHE /* icache, dcache */
#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */
#define CONFIG_CMD_CLK /* Clock support */
#define CONFIG_CMD_CONSOLE /* coninfo */
#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
#define CONFIG_CMD_DHCP /* DHCP Support */
@@ -37,7 +38,6 @@
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_FAT /* FAT support */
#define CONFIG_CMD_FDC /* Floppy Disk Support */
#define CONFIG_CMD_FDOS /* Floppy DOS support */
#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_CMD_FPGA /* FPGA configuration Support */
#define CONFIG_CMD_FUSE /* Device fuse support */

56
include/config_distro_defaults.h Normal file
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@@ -0,0 +1,56 @@
/*
* Copyright 2013-2014 Red Hat, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_CMD_DISTRO_DEFAULTS_H
#define _CONFIG_CMD_DISTRO_DEFAULTS_H
/*
* List of all commands and options that when defined enables support for
* features required by distros to support boards in a standardised and
* consitant manner.
*/
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_PXE
#define CONFIG_BOOTP_SUBNETMASK
#if defined(__arm__)
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
#if defined(__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__)
#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7"
#else
#define CONFIG_BOOTP_VCI_STRING "U-boot.arm"
#endif
#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_PXE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#define CONFIG_BOOTDELAY 2
#define CONFIG_SYS_LONGHELP
#define CONFIG_MENU
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_SUPPORT_RAW_INITRD
#define CONFIG_SYS_HUSH_PARSER
#endif /* _CONFIG_CMD_DISTRO_DEFAULTS_H */

5
include/configs/M54418TWR.h
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@@ -77,7 +77,6 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
#define CONFIG_SYS_NAND_SELECT_DEVICE
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/* Network configuration */
@@ -268,10 +267,8 @@
/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
#define CONFIG_SYS_INIT_RAM_CTRL 0x221
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 256
#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_GBL_DATA_SIZE) - 32)
GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)

3
include/configs/MERGERBOX.h
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@@ -121,9 +121,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE -\
CONFIG_SYS_GBL_DATA_SIZE)
GENERATED_GBL_DATA_SIZE)
/*
* Local Bus Configuration & Clock Setup

12
include/configs/MPC8536DS.h
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@@ -24,7 +24,7 @@
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif
@@ -42,7 +42,7 @@
#endif
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff80000
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#ifndef CONFIG_RESET_VECTOR_ADDRESS
@@ -326,7 +326,7 @@
/* NAND boot: 4K NAND loader config */
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
#define CONFIG_SYS_NAND_U_BOOT_START \
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
@@ -626,7 +626,7 @@
#if defined(CONFIG_RAMBOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
@@ -649,11 +649,7 @@
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif

2
include/configs/MPC8569MDS.h
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@@ -56,7 +56,7 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif
#endif

2
include/configs/MPC8572DS.h
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@@ -24,7 +24,7 @@
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif

156
include/configs/P1010RDB.h
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@@ -21,19 +21,75 @@
#define CONFIG_NAND_FSL_IFC
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#define CONFIG_SPL
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_MMC_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif
#ifdef CONFIG_SPIFLASH
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#else
#define CONFIG_SPL
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_FLASH_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_COMMON_INIT_DDR
#endif
#endif
#endif
#ifdef CONFIG_NAND
#define CONFIG_SPL
#ifdef CONFIG_SECURE_BOOT
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
@@ -51,8 +107,48 @@
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#else
#define CONFIG_TPL
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NAND_INIT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_COMMON_INIT_DDR
#define CONFIG_SPL_MAX_SIZE (128 << 10)
#define CONFIG_SPL_TEXT_BASE 0xD0001000
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
#elif defined(CONFIG_SPL_BUILD)
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TEXT_BASE 0xff800000
#define CONFIG_SPL_MAX_SIZE 8192
#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
#endif
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_TPL_PAD_TO 0x20000
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
#endif
#endif
#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
#define CONFIG_RAMBOOT_NAND
@@ -473,6 +569,43 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
/*
* Config the L2 Cache as L2 SRAM
*/
#if defined(CONFIG_SPL_BUILD)
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
#else
#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
#endif
#endif
#endif
/* Serial Port */
#define CONFIG_CONS_INDEX 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
@@ -480,7 +613,7 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
@@ -637,12 +770,12 @@ extern unsigned long get_sdram_size(void);
/*
* Environment
*/
#if defined(CONFIG_RAMBOOT_SDCARD)
#if defined(CONFIG_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#elif defined(CONFIG_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
@@ -653,6 +786,10 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_ENV_SIZE 0x2000
#elif defined(CONFIG_NAND)
#define CONFIG_ENV_IS_IN_NAND
#ifdef CONFIG_TPL_BUILD
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#else
#if defined(CONFIG_P1010RDB_PA)
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
@@ -660,7 +797,8 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
#endif
#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#endif
#define CONFIG_ENV_OFFSET (1024 * 1024)
#elif defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)

18
include/configs/P1022DS.h
View File

@@ -30,12 +30,12 @@
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
@@ -60,12 +60,12 @@
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
@@ -365,10 +365,10 @@
#define CONFIG_SYS_L2_SIZE (256 << 10)
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD

5
include/configs/P1023RDS.h
View File

@@ -26,7 +26,7 @@
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#endif /* CONFIG_NAND_SPL */
#endif
@@ -194,9 +194,8 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */

2
include/configs/P1_P2_RDB.h
View File

@@ -38,7 +38,7 @@
#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
#else
#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
#define CONFIG_SYS_TEXT_BASE 0xf8f82000
#endif /* CONFIG_NAND_SPL */
#endif

6
include/configs/T1040QDS.h
View File

@@ -611,9 +611,8 @@ unsigned long get_board_ddr_clk(void);
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
@@ -670,7 +669,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data

25
include/configs/T1040RDB.h
View File

@@ -79,10 +79,6 @@
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
@@ -202,6 +198,7 @@
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
@@ -386,6 +383,10 @@
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
/*
* General PCI
@@ -543,13 +544,12 @@
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1"
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
@@ -596,7 +596,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
@@ -627,9 +626,9 @@
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \

21
include/configs/T1042RDB_PI.h
View File

@@ -79,10 +79,6 @@
#if defined(CONFIG_SPIFLASH)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
@@ -202,6 +198,7 @@
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
#define CONFIG_SYS_CSPR2_EXT (0xf)
#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
| CSPR_PORT_SIZE_8 \
| CSPR_MSEL_GPCM \
@@ -394,6 +391,10 @@
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
/*
* General PCI
@@ -551,8 +552,11 @@
#endif
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
#define CONFIG_MII /* MII PHY management */
#define CONFIG_ETHPRIME "FM1@DTSEC1"
#define CONFIG_ETHPRIME "FM1@DTSEC4"
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
@@ -600,7 +604,6 @@
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
@@ -631,9 +634,9 @@
#define __USB_PHY_TYPE utmi
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \

30
include/configs/T2080QDS.h → include/configs/T208xQDS.h
View File

@@ -5,21 +5,25 @@
*/
/*
* T2080 QDS board configuration file
* T2080/T2081 QDS board configuration file
*/
#ifndef __T2080QDS_H
#define __T2080QDS_H
#ifndef __T208xQDS_H
#define __T208xQDS_H
#define CONFIG_T2080QDS
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#define CONFIG_MMC
#define CONFIG_SPI_FLASH
#define CONFIG_USB_EHCI
#if defined(CONFIG_PPC_T2080)
#define CONFIG_T2080QDS
#define CONFIG_FSL_SATA_V2
#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
#define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */
#elif defined(CONFIG_PPC_T2081)
#define CONFIG_T2081QDS
#endif
/* High Level Configuration Options */
#define CONFIG_PHYS_64BIT
@@ -44,8 +48,12 @@
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t2080qds/t2080_pbi.cfg
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t2080qds/t2080_rcw.cfg
#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
#if defined(CONFIG_PPC_T2080)
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
#elif defined(CONFIG_PPC_T2081)
#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
#endif
#endif
#define CONFIG_SRIO_PCIE_BOOT_MASTER
@@ -447,7 +455,12 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO
#if defined(CONFIG_T2080QDS)
#define CONFIG_SPI_FLASH_SPANSION
#elif defined(CONFIG_T2081QDS)
#define CONFIG_SPI_FLASH_EON
#endif
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -505,7 +518,7 @@ unsigned long get_board_ddr_clk(void);
#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
#define CONFIG_NET_MULTI
#define CONFIG_E1000
#define CONFIG_PCI_PNP /* do pci plug-and-play */
@@ -680,7 +693,6 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
/*
* For booting Linux, the board info and command line data
@@ -801,4 +813,4 @@ unsigned long get_board_ddr_clk(void);
#undef CONFIG_CMD_USB
#endif
#endif /* __T2080QDS_H */
#endif /* __T208xQDS_H */

3
include/configs/ac14xx.h
View File

@@ -289,9 +289,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
#define CONFIG_SYS_GBL_DATA_SIZE 0x100
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
CONFIG_SYS_GBL_DATA_SIZE)
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE

226
include/configs/actux1.h
View File

@@ -1,226 +0,0 @@
/*
* (C) Copyright 2007
* Michael Schwingen, michael@schwingen.org
*
* Configuration settings for the AcTux-1 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_IXP425 1
#define CONFIG_ACTUX1 1
#define CONFIG_MACH_TYPE 1479
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_LDSCRIPT "board/actux1/u-boot.lds"
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Command line configuration. */
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_PNP
#define CONFIG_IXP_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI_ENUM
#endif
#define CONFIG_BOOTCOMMAND "run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE 230400
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113842
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#ifdef CONFIG_RAM_32MB
# define CONFIG_SYS_SDR_CONFIG 0x18
# define PHYS_SDRAM_1_SIZE 0x02000000
# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
# define CONFIG_SYS_DRAM_SIZE 0x02000000
#else /* 16MB SDRAM */
# define CONFIG_SYS_SDR_CONFIG 0x3A
# define PHYS_SDRAM_1_SIZE 0x01000000
# define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
# define CONFIG_SYS_SDR_MODE_CONFIG 0x1
# define CONFIG_SYS_DRAM_SIZE 0x01000000
#endif
/* FLASH organization */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#ifdef CONFIG_FLASH2X2
# define CONFIG_SYS_MAX_FLASH_BANKS 2
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT 40
# define PHYS_FLASH_1 0x50000000
# define PHYS_FLASH_2 0x50200000
# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#endif
#ifdef CONFIG_FLASH1X8
# define CONFIG_SYS_MAX_FLASH_BANKS 1
/* max number of sectors on one chip */
# define CONFIG_SYS_MAX_FLASH_SECT 140
# define PHYS_FLASH_1 0x50000000
# define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#endif
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_BOARD_SIZE_LIMIT 262144
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Ethernet */
/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE 1
/* NPE0 PHY address */
#define CONFIG_PHY_ADDR 0
/* NPE1 PHY address (HW Release E only) */
#define CONFIG_PHY1_ADDR 1
/* MII PHY management */
#define CONFIG_MII 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_RESET_PHY_R 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* environment organization:
* one flash sector, embedded in uboot area (bottom bootblock flash)
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
#define CONFIG_SYS_USE_PPCENV 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"npe_ucode=50040000\0" \
"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
"kerneladdr=50050000\0" \
"kernelfile=actux1/uImage\0" \
"rootfile=actux1/rootfs\0" \
"rootaddr=50170000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} actux1/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 50003fff;" \
" protect off 50006000 5003ffff;" \
" erase 50000000 50003fff;" \
" erase 50006000 5003ffff\0" \
"writeboot=cp.b 10000 50000000 4000;" \
" cp.b 16000 50006000 3a000\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
"updatekern=tftp ${loadaddr} ${kernelfile};" \
" era ${kerneladdr} +${filesize};" \
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
"boot_net=run netargs addtty addeth;" \
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

206
include/configs/actux2.h
View File

@@ -1,206 +0,0 @@
/*
* (C) Copyright 2007
* Michael Schwingen, michael@schwingen.org
*
* Configuration settings for the AcTux-2 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_IXP425 1
#define CONFIG_ACTUX2 1
#define CONFIG_MACH_TYPE 1480
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_LDSCRIPT "board/actux2/u-boot.lds"
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Command line configuration. */
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#undef CONFIG_CMD_PCI
#undef CONFIG_PCI
#define CONFIG_BOOTCOMMAND "run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE 230400
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113042
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* 16MB SDRAM */
#define CONFIG_SYS_SDR_CONFIG 0x3A
#define PHYS_SDRAM_1_SIZE 0x01000000
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
#define CONFIG_SYS_DRAM_SIZE 0x01000000
/* FLASH organization */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 140
#define PHYS_FLASH_1 0x50000000
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_BOARD_SIZE_LIMIT 262144
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Ethernet */
/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE 1
/* NPE0 PHY address */
#define CONFIG_PHY_ADDR 0x00
/* MII PHY management */
#define CONFIG_MII 1
/* fixed-speed switch without standard PHY registers on MII */
#define CONFIG_MII_NPE0_FIXEDLINK 1
#define CONFIG_MII_NPE0_SPEED 100
#define CONFIG_MII_NPE0_FULLDUPLEX 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_RESET_PHY_R 1
/* ethernet switch connected to MII port */
#define CONFIG_MII_ETHSWITCH 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* environment organization:
* one flash sector, embedded in uboot area (bottom bootblock flash)
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
#define CONFIG_SYS_USE_PPCENV 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"npe_ucode=50040000\0" \
"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
"kerneladdr=50050000\0" \
"kernelfile=actux2/uImage\0" \
"rootfile=actux2/rootfs\0" \
"rootaddr=50170000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} actux2/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 50003fff;" \
" protect off 50006000 5003ffff;" \
" erase 50000000 50003fff;" \
" erase 50006000 5003ffff\0" \
"writeboot=cp.b 10000 50000000 4000;" \
" cp.b 16000 50006000 3a000\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
"updatekern=tftp ${loadaddr} ${kernelfile};" \
" era ${kerneladdr} +${filesize};" \
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
"boot_net=run netargs addtty addeth;" \
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

205
include/configs/actux3.h
View File

@@ -1,205 +0,0 @@
/*
* (C) Copyright 2007
* Michael Schwingen, michael@schwingen.org
*
* Configuration settings for the AcTux-3 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_IXP425 1
#define CONFIG_ACTUX3 1
#define CONFIG_MACH_TYPE 1481
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_LDSCRIPT "board/actux3/u-boot.lds"
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Command line configuration. */
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_BOOTCOMMAND "run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#define CONFIG_REVISION_TAG 1
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE 230400
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113442
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* 16MB SDRAM */
#define CONFIG_SYS_SDR_CONFIG 0x3A
#define PHYS_SDRAM_1_SIZE 0x01000000
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
#define CONFIG_SYS_DRAM_SIZE 0x01000000
/* FLASH organization */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 140
#define PHYS_FLASH_1 0x50000000
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_BOARD_SIZE_LIMIT 262144
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Ethernet */
/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE 1
/* NPE0 PHY address */
#define CONFIG_PHY_ADDR 0x10
/* MII PHY management */
#define CONFIG_MII 1
/* fixed-speed switch without standard PHY registers on MII */
#define CONFIG_MII_NPE0_FIXEDLINK 1
#define CONFIG_MII_NPE0_SPEED 100
#define CONFIG_MII_NPE0_FULLDUPLEX 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_RESET_PHY_R 1
/* ethernet switch connected to MII port */
#define CONFIG_MII_ETHSWITCH 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* environment organization:
* one flash sector, embedded in uboot area (bottom bootblock flash)
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
#define CONFIG_SYS_USE_PPCENV 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"npe_ucode=50040000\0" \
"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \
"kerneladdr=50050000\0" \
"kernelfile=actux3/uImage\0" \
"rootfile=actux3/rootfs\0" \
"rootaddr=50170000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} actux3/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 50003fff;" \
" protect off 50006000 5003ffff;" \
" erase 50000000 50003fff;" \
" erase 50006000 5003ffff\0" \
"writeboot=cp.b 10000 50000000 4000;" \
" cp.b 16000 50006000 3a000\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
"updatekern=tftp ${loadaddr} ${kernelfile};" \
" era ${kerneladdr} +${filesize};" \
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
"boot_net=run netargs addtty addeth;" \
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

204
include/configs/actux4.h
View File

@@ -1,204 +0,0 @@
/*
* (C) Copyright 2007
* Michael Schwingen, michael@schwingen.org
*
* Configuration settings for the AcTux-4 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_IXP425 1
#define CONFIG_ACTUX4 1
#define CONFIG_MACH_TYPE 1532
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOARD_EARLY_INIT_F 1
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Command line configuration */
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_PCI
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_PNP
#define CONFIG_IXP_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI_ENUM
#endif
#define CONFIG_BOOTCOMMAND "run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE 230400
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x00400000
#define CONFIG_SYS_MEMTEST_END 0x00800000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66000000
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113003
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* 32MB SDRAM */
#define CONFIG_SYS_SDR_CONFIG 0x18
#define PHYS_SDRAM_1_SIZE 0x02000000
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
#define CONFIG_SYS_DRAM_SIZE 0x02000000
/* FLASH organization */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_MAX_FLASH_BANKS 2
/* max # of sectors per chip */
#define CONFIG_SYS_MAX_FLASH_SECT 70
#define PHYS_FLASH_1 0x50000000
#define PHYS_FLASH_2 0x51000000
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN (252 << 10)
#define CONFIG_BOARD_SIZE_LIMIT 258048
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* board provides its own flash_init code */
#define CONFIG_FLASH_CFI_LEGACY 1
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* SST 39VF020 etc. support */
#define CONFIG_SYS_FLASH_LEGACY_256Kx8 1
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Ethernet */
/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE 1
/* NPE0 PHY address */
#define CONFIG_PHY_ADDR 0x1C
/* MII PHY management */
#define CONFIG_MII 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32
/* environment organization: one complete 4k flash sector */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000)
#define CONFIG_EXTRA_ENV_SETTINGS \
"npe_ucode=51000000\0" \
"mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \
"IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \
"kerneladdr=51020000\0" \
"kernelfile=actux4/uImage\0" \
"rootfile=actux4/rootfs\0" \
"rootaddr=51160000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} actux4/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 5003efff;" \
" erase 50000000 +${filesize}\0" \
"writeboot=cp.b 10000 50000000 ${filesize}\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
"updatekern=tftp ${loadaddr} ${kernelfile};" \
" era ${kerneladdr} +${filesize};" \
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
"boot_net=run netargs addtty addeth;" \
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

5
include/configs/adp-ag101.h
View File

@@ -138,11 +138,6 @@
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* size in bytes reserved for initial data
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* AHB Controller configuration
*/

5
include/configs/adp-ag101p.h
View File

@@ -138,11 +138,6 @@
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
/*
* size in bytes reserved for initial data
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* AHB Controller configuration
*/

5
include/configs/adp-ag102.h
View File

@@ -203,11 +203,6 @@
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
/*
* size in bytes reserved for initial data
*/
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* AHB Controller configuration
*/

14
include/configs/am335x_evm.h
View File

@@ -20,6 +20,7 @@
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_BOARD_LATE_INIT
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
@@ -31,6 +32,12 @@
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#ifdef CONFIG_NAND
#define NANDARGS \
"mtdids=" MTDIDS_DEFAULT "\0" \
@@ -64,6 +71,9 @@
"bootfile=zImage\0" \
"fdtfile=undefined\0" \
"console=ttyO0,115200n8\0" \
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
@@ -295,6 +305,9 @@
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* disable EFI partitions and partition UUID support */
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
/*
* Disable CPSW SPL support so we fit within the 101KiB limit.
*/
@@ -385,7 +398,6 @@
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
/* NAND support */

1
include/configs/am335x_igep0033.h
View File

@@ -181,7 +181,6 @@
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
/* NAND support */

55
include/configs/am43xx_evm.h
View File

@@ -84,6 +84,32 @@
#define CONFIG_OMAP_USB_PHY
#define CONFIG_AM437X_USB2PHY2_HOST
/* SPI */
#undef CONFIG_OMAP3_SPI
#define CONFIG_TI_QSPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_MACRONIX
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
#define CONFIG_TI_SPI_MMAP
#define CONFIG_QSPI_SEL_GPIO 48
#define CONFIG_SF_DEFAULT_SPEED 48000000
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
/* SPI SPL */
#define CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SPL_SPI_LOAD
#define CONFIG_SPL_SPI_FLASH_SUPPORT
#define CONFIG_SPL_SPI_BUS 0
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
@@ -95,6 +121,9 @@
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"console=ttyO0,115200n8\0" \
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
@@ -176,4 +205,30 @@
"run usbboot;"
#endif
/* CPSW Ethernet */
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII
#define CONFIG_DRIVER_TI_CPSW
#define CONFIG_MII
#define CONFIG_BOOTP_DEFAULT
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM43xx U-Boot SPL"
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SYS_RX_ETH_BUFFER 64
#endif /* __CONFIG_AM43XX_EVM_H */

2
include/configs/ap_sh4a_4a.h
View File

@@ -134,8 +134,6 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */

5
include/configs/apf27.h
View File

@@ -355,11 +355,6 @@
#define CONFIG_SYS_RTC_BUS_NUM 0
#endif /* CONFIG_CMD_DATE */
/*
* Clocks
*/
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
/*
* PLL
*

92
include/configs/arcangel4-be.h Normal file
View File

@@ -0,0 +1,92 @@
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_ARCANGEL4_H_
#define _CONFIG_ARCANGEL4_H_
/*
* CPU configuration
*/
#define CONFIG_SYS_BIG_ENDIAN
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_CLK_FREQ 70000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
#define CONFIG_ARCH_EARLY_INIT_R
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_SYS_NO_FLASH
/*
* UART configuration
*
*/
#define CONFIG_ARC_SERIAL
#define CONFIG_ARC_UART_BASE 0xC0FC1000
#define CONFIG_BAUDRATE 115200
/*
* Command line configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_OF_LIBFDT
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 16
/*
* Environment settings
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
#define CONFIG_ENV_OFFSET 0
/*
* Environment configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "arcangel4# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#endif /* _CONFIG_ARCANGEL4_H_ */

91
include/configs/arcangel4.h Normal file
View File

@@ -0,0 +1,91 @@
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_ARCANGEL4_H_
#define _CONFIG_ARCANGEL4_H_
/*
* CPU configuration
*/
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_CLK_FREQ 70000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
#define CONFIG_ARCH_EARLY_INIT_R
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_SYS_NO_FLASH
/*
* UART configuration
*
*/
#define CONFIG_ARC_SERIAL
#define CONFIG_ARC_UART_BASE 0xC0FC1000
#define CONFIG_BAUDRATE 115200
/*
* Command line configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_OF_LIBFDT
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 16
/*
* Environment settings
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
#define CONFIG_ENV_OFFSET 0
/*
* Environment configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyARC0,115200n8"
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "arcangel4# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#endif /* _CONFIG_ARCANGEL4_H_ */

1
include/configs/armadillo-800eva.h
View File

@@ -94,7 +94,6 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_TEXT_BASE 0xE80C0000

2
include/configs/arndale.h
View File

@@ -22,8 +22,6 @@
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
/* Enable fdt support for Exynos5250 */
#define CONFIG_ARCH_DEVICE_TREE exynos5250
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE

181
include/configs/axs101.h Normal file
View File

@@ -0,0 +1,181 @@
/*
* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_AXS101_H_
#define _CONFIG_AXS101_H_
/*
* CPU configuration
*/
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER 3
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_CLK_FREQ 750000000
#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
/* dwgmac doesn't work with D$ enabled now */
#define CONFIG_SYS_DCACHE_OFF
/*
* Board configuration
*/
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
#define CONFIG_ARCH_EARLY_INIT_R
#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
#define ARC_APB_PERIPHERAL_BASE 0xF0000000
#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0x81000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
#define CONFIG_SYS_LOAD_ADDR 0x82000000
/*
* NAND Flash configuration
*/
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
/*
* UART configuration
*
* CONFIG_CONS_INDEX = 1 - Debug UART
* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
*/
#define CONFIG_CONS_INDEX 4
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE -4
#if (CONFIG_CONS_INDEX == 1)
/* Debug UART */
# define CONFIG_SYS_NS16550_CLK 33333000
#else
/* FPGA UARTs use different clock */
# define CONFIG_SYS_NS16550_CLK 33333333
#endif
#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_BAUDRATE 115200
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_ENV_EEPROM_BUS 2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_I2C_SLAVE 0
#define CONFIG_SYS_I2C_BASE 0xE001D000
#define CONFIG_SYS_I2C_BASE1 0xE001E000
#define CONFIG_SYS_I2C_BASE2 0xE001F000
#define CONFIG_SYS_I2C_BUS_MAX 3
#define IC_CLK 50
/*
* EEPROM configuration
*/
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32
/*
* SD/MMC configuration
*/
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_DOS_PARTITION
/*
* Ethernet PHY configuration
*/
#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE
/*
* Ethernet configuration
*/
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_AUTONEG
#define CONFIG_DW_SEARCH_PHY
#define CONFIG_NET_MULTI
/*
* Command line configuration
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_RARP
#define CONFIG_OF_LIBFDT
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 16
/*
* Environment settings
*/
#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
#define CONFIG_ENV_OFFSET 0
/*
* Environment configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
/*
* Console configuration
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "AXS# "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/*
* Misc utility configuration
*/
#define CONFIG_BOUNCE_BUFFER
#endif /* _CONFIG_AXS101_H_ */

1
include/configs/balloon3.h
View File

@@ -84,7 +84,6 @@
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
/*

140
include/configs/bcm28155_ap.h Normal file
View File

@@ -0,0 +1,140 @@
/*
* Copyright 2013 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __BCM28155_AP_H
#define __BCM28155_AP_H
#include <asm/sizes.h>
#include <asm/arch/sysmap.h>
/* Architecture, CPU, chip, mach, etc */
#define CONFIG_ARMV7
#define CONFIG_KONA
#define CONFIG_SKIP_LOWLEVEL_INIT
/*
* Memory configuration
*/
#define CONFIG_SYS_TEXT_BASE 0xae000000
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_SDRAM_SIZE 0x80000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */
#define CONFIG_STACKSIZE SZ_256K
/* GPIO Driver */
#define CONFIG_KONA_GPIO
/* MMC/SD Driver */
#define CONFIG_SDHCI
#define CONFIG_MMC_SDMA
#define CONFIG_KONA_SDHCI
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
#define CONFIG_SYS_SDIO0 "sdio1"
#define CONFIG_SYS_SDIO1 "sdio2"
#define CONFIG_SYS_SDIO2 "sdio3"
#define CONFIG_SYS_SDIO3 "sdio4"
/* I2C Driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_KONA
#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */
#define CONFIG_SYS_MAX_I2C_BUS 4
#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR
#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR
#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR
#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR
/* Timer Driver */
#define CONFIG_SYS_TIMER_RATE 32000
#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */
/* Init functions */
#define CONFIG_MISC_INIT_R /* board's misc_init_r function */
/* Some commands use this as the default load address */
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
/* No mtest functions as recommended */
#undef CONFIG_CMD_MEMORY
/*
* This is the initial SP which is used only briefly for relocating the u-boot
* image to the top of SDRAM. After relocation u-boot moves the stack to the
* proper place.
*/
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
/* Serial Info */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* Post pad 3 bytes after each reg addr */
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 13000000
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 0x3e000000
#define CONFIG_BAUDRATE 115200
#define CONFIG_ENV_SIZE 0x10000
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_SYS_NO_FLASH /* Not using NAND/NOR unmanaged flash */
/* console configuration */
#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16) /* Printbuffer size */
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* One partition type must be defined for part.c
* This is necessary for the fatls command to work on an SD card
* for example.
*/
#define CONFIG_DOS_PARTITION
/* version string, parser, etc */
#define CONFIG_VERSION_VARIABLE
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC
/* Initial upstream - boot to cmd prompt only */
#define CONFIG_BOOTCOMMAND ""
/* Commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_BOOTZ
#define CONFIG_FAT_WRITE
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#endif /* __BCM28155_AP_H */

3
include/configs/bf609-ezkit.h
View File

@@ -72,12 +72,13 @@
#define CONFIG_NET_MULTI
#define CONFIG_HOSTNAME "bf609-ezkit"
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_PHY_ADDR 1
#define CONFIG_DW_PORTS 1
#define CONFIG_DW_AUTONEG
#define CONFIG_DW_ALTDESCRIPTOR
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_PHYLIB
/* i2c Settings */
#define CONFIG_BFIN_TWI_I2C

196
include/configs/bur_am335x_common.h Normal file
View File

@@ -0,0 +1,196 @@
/*
* bur_am335x_common.h
*
* common parts used by B&R AM335x based boards
*
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __BUR_AM335X_COMMON_H__
#define __BUR_AM335X_COMMON_H__
/* ------------------------------------------------------------------------- */
#define CONFIG_AM33XX
#define CONFIG_OMAP
#define CONFIG_OMAP_COMMON
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
/* Timer information */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_POWER_TPS65217
#define CONFIG_SYS_NO_FLASH /* have no NOR-flash */
#include <asm/arch/omap.h>
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CONFIG_BAUDRATE 115200
/* Network defines */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_NET_RETRY_COUNT 4
#define CONFIG_CMD_PING
#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_PHYLIB
#define CONFIG_PHY_NATSEMI
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
/*
* SPL related defines. The Public RAM memory map the ROM defines the
* area between 0x402F0400 and 0x4030B800 as a download area and
* 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
* supports X-MODEM loading via UART, and we leverage this and then use
* Y-MODEM to load u-boot.img, when booted over UART.
*/
#define CONFIG_SPL_TEXT_BASE 0x402F0400
#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE)
/*
* Since SPL did pll and ddr initialization for us,
* we don't need to do it twice.
*/
#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif /* !CONFIG_SPL_BUILD, ... */
/*
* Our DDR memory always starts at 0x80000000 and U-Boot shall have
* relocated itself to higher in memory by the time this value is used.
*/
#define CONFIG_SYS_LOAD_ADDR 0x80000000
/*
* ----------------------------------------------------------------------------
* DDR information. We say (for simplicity) that we have 1 bank,
* always, even when we have more. We always start at 0x80000000,
* and we place the initial stack pointer in our SRAM.
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
GENERATED_GBL_DATA_SIZE)
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_SYS_I2C_OMAP24XX
/* GPIO */
#define CONFIG_OMAP_GPIO
#define CONFIG_CMD_GPIO
/*
* ----------------------------------------------------------------------------
* The following are general good-enough settings for U-Boot. We set a
* large malloc pool as we generally have a lot of DDR, and we opt for
* function over binary size in the main portion of U-Boot as this is
* generally easily constrained later if needed. We enable the config
* options that give us information in the environment about what board
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot (BuR V2.0)# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */
/* As stated above, the following choices are optional. */
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_VERSION_VARIABLE
/* We set the max number of command args high to avoid HUSH bugs. */
#define CONFIG_SYS_MAXARGS 64
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 512
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For commands to use, we take the default list and add a few other
* useful commands. Note that we must have set CONFIG_SYS_NO_FLASH
* prior to this include, in order to skip a few commands. When we do
* have flash, if we expect these commands they must be enabled in that
* config. If desired, a specific list of desired commands can be used
* instead.
*/
#include <config_cmd_default.h>
/* undefine commands, which we do not need */
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_CRC32
/* define command we need always */
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SOURCE
/*
* Our platforms make use of SPL to initalize the hardware (primarily
* memory) enough for full U-Boot to be loaded. We also support Falcon
* Mode so that the Linux kernel can be booted directly from SPL
* instead, if desired. We make use of the general SPL framework found
* under common/spl/. Given our generally common memory map, we set a
* number of related defaults and sizes here.
*/
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
/*
* Place the image at the start of the ROM defined image space.
* We limit our size to the ROM-defined downloaded image area, and use the
* rest of the space for stack. We load U-Boot itself into memory at
* 0x80800000 for legacy reasons (to not conflict with older SPLs). We
* have our BSS be placed 1MiB after this, to allow for the default
* Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
* We have the SPL malloc pool at the end of the BSS area.
*
* ----------------------------------------------------------------------------
*/
#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
#undef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
/* General parts of the framework, required. */
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#endif /* ! __BUR_AM335X_COMMON_H__ */

4
include/configs/cardhu.h
View File

@@ -30,6 +30,10 @@
#define V_PROMPT "Tegra30 (Cardhu) # "
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
#define BOARD_EXTRA_ENV_SETTINGS \
"board_name=cardhu-a04\0" \
"fdtfile=tegra30-cardhu-a04.dtb\0"
/* Board-specific serial config */
#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA

1
include/configs/cm_t335.h
View File

@@ -114,7 +114,6 @@
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_ATHEROS
/* NAND support */

7
include/configs/cm_t35.h
View File

@@ -45,13 +45,6 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
/*
* The early kernel mapping on ARM currently only maps from the base of DRAM
* to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000.
* The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000,
* so that leaves DRAM base to DRAM base + 0x4000 available.
*/
#define CONFIG_SYS_BOOTMAPSZ 0x4000
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS

1
include/configs/corvus.h
View File

@@ -33,7 +33,6 @@
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
#define CONFIG_SYS_HZ 1000
#define CONFIG_AT91FAMILY

1
include/configs/devkit3250.h
View File

@@ -29,7 +29,6 @@
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_MALLOC_LEN SZ_1M
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
#define CONFIG_SYS_SDRAM_SIZE SZ_64M
#define CONFIG_SYS_TEXT_BASE 0x83FA0000

3
include/configs/dlvision-10g.h
View File

@@ -217,9 +217,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*

14
include/configs/dra7xx_evm.h
View File

@@ -34,8 +34,19 @@
#define CONFIG_SYS_OMAP_ABE_SYSCK
/* Define the default GPT table for eMMC */
#define PARTS_DEFAULT \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
#include <configs/ti_omap5_common.h>
/* Enhance our eMMC support / experience. */
#define CONFIG_CMD_GPT
#define CONFIG_EFI_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
/* CPSW Ethernet */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
@@ -51,7 +62,6 @@
#define CONFIG_MII /* Required in net/eth.c */
#define CONFIG_PHY_GIGE /* per-board part of CPSW */
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 2
/* SPI */
#undef CONFIG_OMAP3_SPI
@@ -73,6 +83,8 @@
#define CONFIG_SPL_SPI_CS 0
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
#define CONFIG_SUPPORT_EMMC_BOOT
/* USB xHCI HOST */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST

222
include/configs/dvlhost.h
View File

@@ -1,222 +0,0 @@
/*
* (C) Copyright 2009
* Michael Schwingen, michael@schwingen.org
*
* Configuration settings for the
* dLAN200 AV Wireless G ("dvlhost") board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_IXP425 1
#define CONFIG_DVLHOST 1
#define CONFIG_MACH_TYPE 1343
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_IXP_SERIAL
#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_SYS_LDSCRIPT "board/dvlhost/u-boot.lds"
/***************************************************************
* U-boot generic defines start here.
***************************************************************/
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/* Command line configuration. */
#include <config_cmd_default.h>
#define CONFIG_CMD_ELF
#define CONFIG_PCI
#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_PCI_PNP
#define CONFIG_IXP_PCI
#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_CMD_PCI_ENUM
#endif
#define CONFIG_BOOTCOMMAND "run boot_flash"
/* enable passing of ATAGs */
#define CONFIG_CMDLINE_TAG 1
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG 1
#if defined(CONFIG_CMD_KGDB)
# define CONFIG_KGDB_BAUDRATE 230400
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP
/* Console I/O Buffer Size */
#define CONFIG_SYS_CBSIZE 256
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* max number of command args */
#define CONFIG_SYS_MAXARGS 16
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x00000000
#define CONFIG_SYS_MEMTEST_END 0x01D80000
/* timer clock - 2* OSC_IN system clock */
#define CONFIG_IXP425_TIMER_CLK 66666666
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x00010000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200, 230400 }
#define CONFIG_SERIAL_RTS_ACTIVE 1
/* Expansion bus settings */
#define CONFIG_SYS_EXP_CS0 0xbd113442
/* SDRAM settings */
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 0x00000000
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* 32MB SDRAM: 2* 8Mx16, CL3 */
#define CONFIG_SYS_SDR_CONFIG 0x18
#define PHYS_SDRAM_1_SIZE 0x02000000
#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x800
#define CONFIG_SYS_SDR_MODE_CONFIG 0x1
#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
/* FLASH organization: one Spansion S29AL032D-04 Flash */
#define CONFIG_SYS_TEXT_BASE 0x50000000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 140
#define PHYS_FLASH_1 0x50000000
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
#define CONFIG_SYS_MONITOR_LEN (256 << 10)
#define CONFIG_BOARD_SIZE_LIMIT 262144
/* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
/* no byte writes on IXP4xx */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Ethernet */
/* include IXP4xx NPE support */
#define CONFIG_IXP4XX_NPE 1
/* NPE0 PHY: MII dLAN200 AVmodule, 100BaseT-FDX fixed */
#define CONFIG_PHY_ADDR 0x18
/* NPE1 PHY: MII IP175 switch, port 5 is host port */
#define CONFIG_PHY1_ADDR 0x05
/* MII PHY management */
#define CONFIG_MII 1
/* fixed-speed powerline modem without standard PHY registers on MII */
#define CONFIG_MII_NPE0_FIXEDLINK 1
#define CONFIG_MII_NPE0_SPEED 100
#define CONFIG_MII_NPE0_FULLDUPLEX 1
/* fixed-speed switch without standard PHY registers on MII */
#define CONFIG_MII_NPE1_FIXEDLINK 1
#define CONFIG_MII_NPE1_SPEED 100
#define CONFIG_MII_NPE1_FULLDUPLEX 1
/* Number of ethernet rx buffers & descriptors */
#define CONFIG_SYS_RX_ETH_BUFFER 16
#define CONFIG_RESET_PHY_R 1
/* ethernet switch connected to MII port */
#define CONFIG_MII_ETHSWITCH 1
#define CONFIG_HAS_ETH1 1
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#undef CONFIG_CMD_NFS
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE 32
/*
* environment organization:
* one flash sector, embedded in uboot area (bottom bootblock flash)
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x4000)
#define CONFIG_SYS_USE_PPCENV 1
#define CONFIG_EXTRA_ENV_SETTINGS \
"npe_ucode=50040000\0" \
"ethprime=NPE1\0" \
"ethrotate=no\0" \
"mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root),\0" \
"kerneladdr=50050000\0" \
"kernelfile=dvlhost/uImage\0" \
"rootfile=dvlhost/rootfs\0" \
"rootaddr=50170000\0" \
"loadaddr=10000\0" \
"updateboot_ser=mw.b 10000 ff 40000;" \
" loady ${loadaddr};" \
" run eraseboot writeboot\0" \
"updateboot_net=mw.b 10000 ff 40000;" \
" tftp ${loadaddr} dvlhost/u-boot.bin;" \
" run eraseboot writeboot\0" \
"eraseboot=protect off 50000000 50003fff;" \
" protect off 50006000 5003ffff;" \
" erase 50000000 50003fff;" \
" erase 50006000 5003ffff\0" \
"writeboot=cp.b 10000 50000000 4000;" \
" cp.b 16000 50006000 3a000\0" \
"updateucode=loady;" \
" era ${npe_ucode} +${filesize};" \
" cp.b ${loadaddr} ${npe_ucode} ${filesize}\0" \
"updateroot=tftp ${loadaddr} ${rootfile};" \
" era ${rootaddr} +${filesize};" \
" cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \
"updatekern=tftp ${loadaddr} ${kernelfile};" \
" era ${kerneladdr} +${filesize};" \
" cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \
"flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \
" rootfstype=squashfs,jffs2 init=/etc/preinit\0" \
"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
"addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \
"boot_flash=run flashargs addtty addeth;" \
" bootm ${kerneladdr}\0" \
"boot_net=run netargs addtty addeth;" \
" tftpboot ${loadaddr} ${kernelfile};" \
" bootm\0"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
#endif /* __CONFIG_H */

2
include/configs/dxr2.h
View File

@@ -26,6 +26,7 @@
#define BOARD_DFU_BUTTON_GPIO 27
#define BOARD_DFU_BUTTON_LED 64
#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */
#undef CONFIG_DOS_PARTITION
#undef CONFIG_CMD_FAT
@@ -49,7 +50,6 @@
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#define CONFIG_FACTORYSET

2
include/configs/ecovec.h
View File

@@ -158,8 +158,6 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */

1
include/configs/hummingboard.h
View File

@@ -190,7 +190,6 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
#define CONFIG_CMDLINE_EDITING

3
include/configs/io.h
View File

@@ -198,9 +198,8 @@
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*

3
include/configs/iocon.h
View File

@@ -238,9 +238,8 @@ int fpga_gpio_get(unsigned int bus, int pin);
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size/bytes res'd for init data*/
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
(CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*

19
include/configs/km/keymile-common.h
View File

@@ -99,11 +99,16 @@
#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */
#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS
#define CONFIG_KM_UBI_PART_BOOT_OPTS ""
#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */
#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP
/* one flash chip only called boot */
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
# define CONFIG_KM_UBI_LINUX_MTD \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \
CONFIG_KM_UBI_PART_BOOT_OPTS
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
"ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0"
#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */
@@ -111,7 +116,8 @@
/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */
/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */
# define CONFIG_KM_UBI_LINUX_MTD \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \
CONFIG_KM_UBI_PART_BOOT_OPTS " " \
"ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP
# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \
"ubiattach=if test ${boot_bank} -eq 0; then; " \
@@ -135,8 +141,8 @@
* - 'release': for a standalone system kernel/rootfs from flash
*/
#define CONFIG_KM_DEF_ENV_BOOTTARGETS \
"subbootcmds=ubiattach ubicopy cramfsloadfdt cramfsloadkernel " \
"flashargs add_default addpanic boot\0" \
"subbootcmds=ubiattach ubicopy cramfsloadfdt set_fdthigh " \
"cramfsloadkernel flashargs add_default addpanic boot\0"\
"develop=" \
"tftp 200000 scripts/develop-${arch}.txt && " \
"env import -t 200000 ${filesize} && " \
@@ -220,6 +226,7 @@
CONFIG_KM_DEF_ENV_FLASH_BOOT \
CONFIG_KM_DEF_ENV_CONSTANTS \
"altbootcmd=run bootcmd\0" \
"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
"bootcmd=km_checkbidhwk && " \
"setenv bootcmd \'if km_checktestboot; then; " \
"setenv boot_bank ${test_bank}; else; " \
@@ -229,6 +236,10 @@
"run ${subbootcmds}; reset\' && " \
"saveenv && saveenv && boot\0" \
"bootlimit=3\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
"fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \
"init=/sbin/init-overlay.sh\0" \
"load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
"load=tftpboot ${load_addr_r} ${u-boot}\0" \

6
include/configs/km/km-powerpc.h
View File

@@ -70,11 +70,6 @@
#define CONFIG_KM_DEF_BOOT_ARGS_CPU ""
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
"fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=" \
"protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
@@ -82,6 +77,7 @@
"cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \
" ${filesize} && " \
"protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\
"set_fdthigh=true\0" \
""
#endif /* __CONFIG_KEYMILE_POWERPC_H */

1
include/configs/km/km83xx-common.h
View File

@@ -84,7 +84,6 @@
#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)

14
include/configs/km/km_arm.h
View File

@@ -70,7 +70,8 @@
#define CONFIG_KM_PHRAM 0x17F000
#define CONFIG_KM_CRAMFS_ADDR 0x2400000
#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 3098KBytes */
#define CONFIG_KM_FDT_ADDR 0x23E0000 /* 128KBytes */
/* architecture specific default bootargs */
#define CONFIG_KM_DEF_BOOT_ARGS_CPU \
@@ -78,15 +79,17 @@
" boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}"
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
"u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_UPDATE_UBOOT \
"set_fdthigh=setenv fdt_high ${kernelmem}\0" \
""
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_MISC_INIT_R
/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT
/*
* NS16550 Configuration
*/
@@ -289,10 +292,15 @@ int get_scl(void);
" ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif
#ifndef CONFIG_KM_BOARD_EXTRA_ENV
#define CONFIG_KM_BOARD_EXTRA_ENV ""
#endif
/*
* Default environment variables
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_BOARD_EXTRA_ENV \
CONFIG_KM_DEF_ENV \
CONFIG_KM_NEW_ENV \
"arch=arm\0" \

22
include/configs/km/kmp204x-common.h
View File

@@ -15,6 +15,10 @@
#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"
/* an additionnal option is required for UBI as subpage access is
* supported in u-boot */
#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
#define CONFIG_NAND_ECC_BCH
/* common KM defines */
@@ -148,8 +152,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */
#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */
#define CONFIG_BOOTCOUNT_LIMIT
/*
* Local Bus Definitions
*/
@@ -206,8 +208,13 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
/* bootcounter in QRIO */
#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
#define CONFIG_MISC_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT
@@ -263,7 +270,10 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */
#define CONFIG_SYS_NUM_I2C_BUSES 3
#define CONFIG_SYS_I2C_MAX_HOPS 1
#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */
@@ -276,6 +286,12 @@ unsigned long get_board_sys_clk(unsigned long dummy);
{0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
{0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
}
#ifndef __ASSEMBLY__
void set_sda(int state);
void set_scl(int state);
int get_sda(void);
int get_scl(void);
#endif
#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/
@@ -286,6 +302,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_BAR /* 4 byte-addressing */
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_CMD_SF
#define CONFIG_SF_DEFAULT_SPEED 20000000
#define CONFIG_SF_DEFAULT_MODE 0
@@ -420,6 +437,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);
"update=" \
"sf probe 0;sf erase 0 +${filesize};" \
"sf write ${load_addr_r} 0 ${filesize};\0" \
"set_fdthigh=true\0" \
""
#define CONFIG_HW_ENV_SETTINGS \

15
include/configs/km_kirkwood.h
View File

@@ -45,11 +45,19 @@
#define CONFIG_KM_DISABLE_PCIE
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
/* KM_NUSA */
#elif defined(CONFIG_KM_NUSA)
/* KM_NUSA / KM_SUGP1 */
#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
# if defined(CONFIG_KM_NUSA)
#define CONFIG_IDENT_STRING "\nKeymile NUSA"
#define CONFIG_HOSTNAME kmnusa
# elif defined(CONFIG_KM_SUGP1)
#define CONFIG_IDENT_STRING "\nKeymile SUGP1"
#define CONFIG_HOSTNAME kmsugp1
#define KM_PCIE_RESET_MPP7
#endif
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
@@ -97,6 +105,9 @@
#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
#define CONFIG_IDENT_STRING "\nKeymile SUV31"
#define CONFIG_HOSTNAME kmsuv31
#undef CONFIG_SYS_KWD_CONFIG
#define CONFIG_SYS_KWD_CONFIG \
$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
#define CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_FPGA_CONFIG

7
include/configs/kmp204x.h
View File

@@ -13,6 +13,11 @@
#define CONFIG_HOSTNAME kmlion1
#define CONFIG_KM_BOARD_NAME "kmlion1"
/* KMCOGE4 */
#elif defined(CONFIG_KMCOGE4)
#define CONFIG_HOSTNAME kmcoge4
#define CONFIG_KM_BOARD_NAME "kmcoge4"
#else
#error ("Board not supported")
#endif
@@ -42,6 +47,7 @@
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM
/* Local bus app1 Options */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM
#endif
/* App2 Local bus */
#define CONFIG_SYS_LBAPP2_BASE 0xE0000000
@@ -63,6 +69,5 @@
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
/* Local bus app2 Options */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
#endif
#endif /* __CONFIG_H */

2
include/configs/koelsch.h
View File

@@ -106,7 +106,6 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
@@ -171,7 +170,6 @@
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ 14745600
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
/* i2c */
#define CONFIG_CMD_I2C

128
include/configs/kwb.h Normal file
View File

@@ -0,0 +1,128 @@
/*
* kwb.h
*
* specific parts for B&R KWB Motherboard
*
* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at> -
* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_KWB_H__
#define __CONFIG_KWB_H__
#include <configs/bur_am335x_common.h>
/* ------------------------------------------------------------------------- */
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_POWER_TPS65217
#define CONFIG_MACH_TYPE 3589
/* I2C IP block */
#define CONFIG_SYS_OMAP24_I2C_SPEED_PSOC 20000
/* GPIO */
#define CONFIG_SPL_GPIO_SUPPORT
/* MMC/SD IP block */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_OMAP_HSMMC
#define CONFIG_CMD_MMC
#define CONFIG_SUPPORT_EMMC_BOOT
/* RAW SD card / eMMC locations. */
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /*addr. 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
#define CONFIG_SPL_MMC_SUPPORT
#undef CONFIG_SPL_OS_BOOT
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000
/* RAW SD card / eMMC */
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */
#endif /* CONFIG_SPL_OS_BOOT */
/* Always 128 KiB env size */
#define CONFIG_ENV_SIZE (128 << 10)
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=0\0" \
"loadaddr=0x80100000\0" \
"bootfile=arimg\0" \
"usbboot=echo Booting from USB-Stick ...; " \
"usb start; " \
"fatload usb 0 ${loadaddr} ${bootfile}; " \
"usb stop; " \
"go ${loadaddr};\0" \
"netboot=echo Booting from network ...; " \
"setenv autoload 0; " \
"dhcp; " \
"tftp ${loadaddr} arimg; " \
"go ${loadaddr}\0" \
"usbupdate=echo Updating UBOOT from USB-Stick ...; " \
"usb start; " \
"fatload usb 0 0x80000000 updateubootusb.img; " \
"source;\0" \
"netupdate=echo Updating UBOOT from Network (TFTP) ...; " \
"setenv autoload 0; " \
"dhcp;" \
"tftp 0x80000000 updateUBOOT.img;" \
"source;\0"
#endif /* !CONFIG_SPL_BUILD*/
#define CONFIG_BOOTCOMMAND \
"run usbupdate;"
#define CONFIG_BOOTDELAY 1 /* TODO: für release auf 0 setzen */
/* undefine command which we not need here */
#undef CONFIG_BOOTM_LINUX
#undef CONFIG_BOOTM_NETBSD
#undef CONFIG_BOOTM_PLAN9
#undef CONFIG_BOOTM_RTEMS
#undef CONFIG_GZIP
#undef CONFIG_ZLIB
#undef CONFIG_CMD_CRC32
/* USB configuration */
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
/* attention! not only for gadget, enables also highspeed in hostmode */
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_HOST
#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif /* CONFIG_MUSB_HOST */
#undef CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
/*
* Common filesystems support. When we have removable storage we
* enabled a number of useful commands and support.
*/
#if defined(CONFIG_MMC) || defined(CONFIG_USB_STORAGE)
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_FAT
#define CONFIG_FAT_WRITE
#define CONFIG_CMD_FS_GENERIC
#endif /* CONFIG_MMC, ... */
#endif /* ! __CONFIG_TSERIES_H__ */

1
include/configs/kzm9g.h
View File

@@ -88,7 +88,6 @@
#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_TEXT_BASE 0x00000000

2
include/configs/lager.h
View File

@@ -109,7 +109,6 @@
#define CONFIG_SYS_MONITOR_BASE 0x00000000
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#if defined(CONFIG_SYS_USE_BOOT_NORFLASH)
@@ -196,6 +195,5 @@
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4
#define CONFIG_SYS_HZ 1000
#endif /* __LAGER_H */

9
include/configs/mcx.h
View File

@@ -98,6 +98,7 @@
/* EHCI */
#define CONFIG_USB_STORAGE
#define CONFIG_OMAP3_GPIO_2
#define CONFIG_OMAP3_GPIO_5
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_OMAP
@@ -263,10 +264,9 @@
"${mtdparts} " \
"vram=6M omapfb.vram=1:2M,2:2M,3:2M " \
"omapdss.def_disp=lcd;" \
"bootm 0x82000000 0x84000000\0"
#define CONFIG_BOOTCOMMAND \
"run nandboot"
"bootm 0x82000000 0x84000000\0" \
"bootcmd=mmc rescan;if fatload mmc 0 82000000 loadbootscr.scr;" \
"then source 82000000;else run nandboot;fi\0"
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
@@ -395,6 +395,7 @@
#define CONFIG_SYS_NAND_ECCSIZE 256
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE

63
include/configs/microblaze-generic.h
View File

@@ -200,7 +200,8 @@
# define CONFIG_SYS_MAX_FLASH_SECT 512
/* hardware flash protection */
# define CONFIG_SYS_FLASH_PROTECTION
/* use buffered writes (20x faster) */
# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
# ifdef RAMENV
# define CONFIG_ENV_IS_NOWHERE 1
# define CONFIG_ENV_SIZE 0x1000
@@ -446,4 +447,64 @@
# undef CONFIG_PHYLIB
#endif
/* SPL part */
#define CONFIG_SPL
#define CONFIG_CMD_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT "arch/microblaze/cpu/u-boot-spl.lds"
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_NOR_SUPPORT
/* for booting directly linux */
#define CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + \
0x60000)
#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
0x40000)
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \
0x1000000)
/* SP location before relocation, must use scratch RAM */
/* BRAM start */
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
/* BRAM size - will be generated */
#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
/* Stack pointer prior relocation, must situated at on-chip RAM */
#define CONFIG_SYS_SPL_MALLOC_END (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100
/*
* The main reason to do it in this way is that MALLOC_START
* can't be defined - common/spl/spl.c
*/
#if (CONFIG_SYS_SPL_MALLOC_SIZE != 0)
# define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_SPL_MALLOC_END - \
CONFIG_SYS_SPL_MALLOC_SIZE)
# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_START
#else
# define CONFIG_SPL_STACK_ADDR CONFIG_SYS_SPL_MALLOC_END
#endif
/* Just for sure that there is a space for stack */
#define CONFIG_SPL_STACK_SIZE 0x100
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \
CONFIG_SYS_INIT_RAM_ADDR - \
GENERATED_GBL_DATA_SIZE - \
CONFIG_SYS_SPL_MALLOC_SIZE - \
CONFIG_SPL_STACK_SIZE)
#endif /* __CONFIG_H */

170
include/configs/mini2440.h
View File

@@ -1,170 +0,0 @@
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
* Gary Jennejohn <gj@denx.de>
* David Mueller <d.mueller@elsoft.ch>
*
* (C) Copyright 2009-2010
* Michel Pollet <buserror@gmail.com>
*
* (C) Copyright 2012
* Gabriel Huau <contact@huau-gabriel.fr>
*
* Configuation settings for the MINI2440 board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_TEXT_BASE 0x0
#define CONFIG_S3C2440_GPIO
/*
* High Level Configuration Options
*/
#define CONFIG_ARM920T /* This is an ARM920T Core */
#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24X0 SoC */
#define CONFIG_S3C2440 /* in a SAMSUNG S3C2440 SoC */
#define CONFIG_MINI2440 /* on a MIN2440 Board */
#define MACH_TYPE_MINI2440 1999
#define CONFIG_MACH_TYPE MACH_TYPE_MINI2440
/*
* We don't use lowlevel_init
*/
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F
/*
* input clock of PLL
*/
/* MINI2440 has 12.0000MHz input clock */
#define CONFIG_SYS_CLK_FREQ 12000000
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048*1024)
/*
* Hardware drivers
*/
#define CONFIG_DRIVER_DM9000
#define CONFIG_DRIVER_DM9000_NO_EEPROM
#define CONFIG_DM9000_BASE 0x20000300
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE+4)
/*
* select serial console configuration
*/
#define CONFIG_S3C24X0_SERIAL
#define CONFIG_SERIAL1
/*
* allow to overwrite serial and ethaddr
*/
#define CONFIG_ENV_OVERWRITE
/*
* Command definition
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PORTIO
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVES
/*
* Miscellaneous configurable options
*/
#define CONFIG_LONGHELP
#define CONFIG_SYS_PROMPT "MINI2440 => "
#define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 32
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x30000000
#define CONFIG_SYS_MEMTEST_END 0x34000000 /* 64MB in DRAM */
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x32000000
/* boot parameters address */
#define CONFIG_BOOT_PARAM_ADDR 0x30000100
/*
* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need
* it to wrap 100 times (total 1562500) to get 1 sec.
*/
#define CONFIG_SYS_HZ 1562500
/*
* valid baudrates
*/
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BAUDRATE 115200
/*
* Stack sizes
* The stack sizes are set up in start.S using the settings below
*/
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
#ifdef CONFIG_USE_IRQ
#define CONFIG_STACKSIZE_IRQ (8*1024) /* IRQ stack */
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
#endif
/*
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_SIZE (64*1024*1024) /* 64MB of DRAM */
#define CONFIG_SYS_SDRAM_BASE 0x30000000
#define CONFIG_SYS_FLASH_BASE 0x0
/*
* Stack should be on the SRAM because
* DRAM is not init
*/
#define CONFIG_SYS_INIT_SP_ADDR (0x40001000 - GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH organization
* Now uses the standard CFI interface
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_MONITOR_BASE 0x0
/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
/* 512 * 4096 sectors, or 32 * 64k blocks */
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_FLASH_SHOW_PROGRESS 1
/*
* Config for NOR flash
*/
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_MY_ENV_OFFSET 0x40000
/* addr of environment */
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_MY_ENV_OFFSET)
/* 16k Total Size of Environment Sector */
#define CONFIG_ENV_SIZE 0x4000
/* ATAG configuration */
#define CONFIG_INITRD_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE
#endif /* __CONFIG_H */

1
include/configs/mxs.h
View File

@@ -59,7 +59,6 @@
/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */

2
include/configs/nitrogen6x.h
View File

@@ -31,7 +31,7 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_MXC_GPIO
#define CONFIG_MV_UDC
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER

4
include/configs/o2dnt-common.h
View File

@@ -275,10 +275,8 @@
#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
CONFIG_SYS_GBL_DATA_SIZE)
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE

1
include/configs/omap5_uevm.h
View File

@@ -37,6 +37,7 @@
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#define CONFIG_HSMMC2_8BIT
#define CONFIG_SUPPORT_EMMC_BOOT
/* Required support for the TCA642X GPIO we have on the uEVM */
#define CONFIG_TCA642X

24
include/configs/p1_p2_rdb_pc.h
View File

@@ -159,12 +159,12 @@
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_MMC_BOOT
@@ -189,12 +189,12 @@
#define CONFIG_FSL_LAW /* Use common FSL init code */
#define CONFIG_SYS_TEXT_BASE 0x11001000
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_PAD_TO 0x18000
#define CONFIG_SPL_MAX_SIZE (96 * 1024)
#define CONFIG_SPL_PAD_TO 0x20000
#define CONFIG_SPL_MAX_SIZE (128 * 1024)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
#define CONFIG_SYS_MPC85XX_NO_RESETVEC
#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
#define CONFIG_SPL_SPI_BOOT
@@ -579,11 +579,15 @@
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
#if defined(CONFIG_P2020RDB)
#define CONFIG_SPL_RELOC_MALLOC_SIZE (364 << 10)
#else
#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
#endif
#elif defined(CONFIG_NAND)
#ifdef CONFIG_TPL_BUILD
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000

3
include/configs/p1_twr.h
View File

@@ -238,9 +238,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS
#define CONFIG_SYS_64BIT_VSPRINTF
#define CONFIG_SYS_64BIT_STRTOUL
/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */

1
include/configs/palmld.h
View File

@@ -115,7 +115,6 @@
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */
/*

1
include/configs/palmtc.h
View File

@@ -117,7 +117,6 @@
* Clock Configuration
*/
#undef CONFIG_SYS_CLKS_IN_HZ
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */
/*

1
include/configs/pcm051.h
View File

@@ -297,7 +297,6 @@
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_SMSC
#endif /* ! __CONFIG_PCM051_H */

207
include/configs/pengwyn.h Normal file
View File

@@ -0,0 +1,207 @@
/*
* pengwyn.h
*
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
*
* based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_PENGWYN_H
#define __CONFIG_PENGWYN_H
#define CONFIG_NAND
#define CONFIG_SERIAL1
#define CONFIG_CONS_INDEX 1
#include <configs/ti_am335x_common.h>
/* Clock Defines */
#define V_OSCK 24000000
#define V_SCLK V_OSCK
/* set env size */
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"fdtfile=am335x-pengwyn.dtb\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
"mmcrootfstype=ext4 rootwait\0" \
"rootpath=/export/rootfs\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
"::off\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"netargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=/dev/nfs " \
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
"ip=dhcp\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcloados=run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr};\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run loadimage; then " \
"run loadfdt;" \
"run mmcloados;" \
"fi;" \
"fi;\0" \
"netboot=echo Booting from network ...; " \
"setenv autoload no; " \
"dhcp; " \
"tftp ${loadaddr} ${bootfile}; " \
"tftp ${fdtaddr} ${fdtfile}; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${fdtaddr} u-boot-spl-os; " \
"nand read ${loadaddr} kernel; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
#endif
#define CONFIG_BOOTCOMMAND \
"run mmcboot;" \
"run nandboot;"
/* NS16550 Configuration: primary UART via FDTI */
#define CONFIG_SYS_NS16550_COM1 0x44e09000
#define CONFIG_BAUDRATE 115200
/* I2C Configuration */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_CMD_EEPROM
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS
/* SPL */
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_YMODEM_SUPPORT
/* General network SPL */
#define CONFIG_SPL_NET_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
/* NAND support */
#define CONFIG_CMD_NAND
#define CONFIG_NAND_OMAP_GPMC
#define CONFIG_NAND_OMAP_ELM
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
"128k(SPL.backup1)," \
"128k(SPL.backup2)," \
"128k(SPL.backup3),1792k(u-boot)," \
"128k(u-boot-spl-os)," \
"128k(u-boot-env),5m(kernel),-(rootfs)"
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/*
* USB configuration. We enable MUSB support, both for host and for
* gadget. We set USB0 as peripheral and USB1 as host, based on the
* board schematic and physical port wired to each. Then for host we
* add mass storage support.
*/
#define CONFIG_USB_MUSB_DSPS
#define CONFIG_ARCH_MISC_INIT
#define CONFIG_MUSB_GADGET
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#if defined(CONFIG_MUSB_HOST)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#endif
#if defined(CONFIG_SPL_BUILD)
/* disable host part of MUSB in SPL */
#undef CONFIG_MUSB_HOST
/* Disable CPSW SPL support so we fit within the 101KiB limit. */
#undef CONFIG_SPL_ETH_SUPPORT
#endif
/* Network */
#define CONFIG_CMD_MII
#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET 1
#define CONFIG_PHY_NATSEMI
/* CPSW support */
#define CONFIG_SPL_ETH_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#endif /* ! __CONFIG_PENGWYN_H */

1
include/configs/pxm2.h
View File

@@ -44,7 +44,6 @@
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
#define CONFIG_PHY_ADDR 0
#define CONFIG_PHY_ATHEROS
#define CONFIG_FACTORYSET

2
include/configs/r0p7734.h
View File

@@ -140,8 +140,6 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE (256)
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* ENV setting */

120
include/configs/rpi_b.h
View File

@@ -95,12 +95,25 @@
#define CONFIG_SYS_LOAD_ADDR 0x1000000
#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_PREBOOT \
"if load mmc 0:1 ${loadaddr} /uEnv.txt; then " \
"env import -t ${loadaddr} ${filesize}; " \
"fi"
#define ENV_DEVICE_SETTINGS \
"stdin=serial,lcd\0" \
"stdout=serial,lcd\0" \
"stderr=serial,lcd\0"
/*
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it low in memory to avoid conflicts.
*
* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
* something else. Put it low in memory to avoid conflicts.
*
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -116,67 +129,112 @@
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"stdin=serial\0" \
"stderr=serial,lcd\0" \
"stdout=serial,lcd\0" \
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
"kernel_addr_r=0x01000000\0" \
"fdt_addr_r=0x02000000\0" \
"fdtfile=bcm2835-rpi-b.dtb\0" \
"ramdisk_addr_r=0x02100000\0" \
"boot_targets=mmc0\0" \
\
"script_boot=" \
"if fatload ${devtype} ${devnum}:1 " \
"${scriptaddr} boot.scr.uimg; then " \
"source ${scriptaddr}; " \
"fi;\0" \
\
#define BOOTCMDS_MMC \
"mmc_boot=" \
"setenv devtype mmc; " \
"if mmc dev ${devnum}; then " \
"run script_boot; " \
"run scan_boot; " \
"fi\0" \
"bootcmd_mmc0=setenv devnum 0; run mmc_boot;\0"
#define BOOT_TARGETS_MMC "mmc0"
#define BOOTCMDS_COMMON \
"rootpart=1\0" \
\
"bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \
"do_script_boot=" \
"load ${devtype} ${devnum}:${rootpart} " \
"${scriptaddr} ${prefix}${script}; " \
"source ${scriptaddr}\0" \
\
"script_boot=" \
"for script in ${boot_scripts}; do " \
"if test -e ${devtype} ${devnum}:${rootpart} " \
"${prefix}${script}; then " \
"echo Found ${prefix}${script}; " \
"run do_script_boot; " \
"echo SCRIPT FAILED: continuing...; " \
"fi; " \
"done\0" \
\
"do_sysboot_boot=" \
"sysboot ${devtype} ${devnum}:${rootpart} any " \
"${scriptaddr} ${prefix}extlinux/extlinux.conf\0" \
\
"sysboot_boot=" \
"if test -e ${devtype} ${devnum}:${rootpart} " \
"${prefix}extlinux/extlinux.conf; then " \
"echo Found ${prefix}extlinux/extlinux.conf; " \
"run do_sysboot_boot; " \
"echo SCRIPT FAILED: continuing...; " \
"fi\0" \
\
"scan_boot=" \
"echo Scanning ${devtype} ${devnum}...; " \
"for prefix in ${boot_prefixes}; do " \
"run sysboot_boot; " \
"run script_boot; " \
"done\0" \
\
"boot_targets=" \
BOOT_TARGETS_MMC " " \
"\0" \
\
"boot_prefixes=/\0" \
\
"boot_scripts=boot.scr.uimg\0" \
\
BOOTCMDS_MMC
#define CONFIG_BOOTCOMMAND \
"for target in ${boot_targets}; do run bootcmd_${target}; done"
#define CONFIG_BOOTDELAY 2
#define CONFIG_BOOTCOMMAND \
"for target in ${boot_targets}; do run bootcmd_${target}; done"
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_DEVICE_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
BOOTCMDS_COMMON
#define CONFIG_BOOTDELAY 2
/* Shell */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_MAXARGS 8
#define CONFIG_SYS_PROMPT "U-Boot> "
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE
/* Commands */
#include <config_cmd_default.h>
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MMC
#define CONFIG_DOS_PARTITION
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT
/* Some things don't make sense on this HW or yet */
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SAVEENV
/* Device tree support for bootm/bootz */
#define CONFIG_OF_LIBFDT
/* Device tree support */
#define CONFIG_OF_BOARD_SETUP
/* ATAGs support for bootm/bootz */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG
#include <config_distro_defaults.h>
/* Some things don't make sense on this HW or yet */
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_MII
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_PING
#endif

1
include/configs/rut.h
View File

@@ -41,7 +41,6 @@
#undef CONFIG_SPL_NET_VCI_STRING
#undef CONFIG_SPL_ETH_SUPPORT
#define CONFIG_PHY_ADDR 1
#define CONFIG_PHY_NATSEMI
#define CONFIG_FACTORYSET

10
include/configs/s5p_goni.h
View File

@@ -34,6 +34,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_INITRD_TAG
#define CONFIG_CMDLINE_EDITING
@@ -113,8 +114,13 @@
#define CONFIG_UBIFS_OPTION "rootflags=bulk_read,no_chk_data_crc"
#define CONFIG_MISC_COMMON
#define CONFIG_MISC_INIT_R
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_UPDATEB \
"updatek=" \
@@ -208,8 +214,8 @@
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3)
#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0)
#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3)
#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */

46
include/configs/s5pc210_universal.h
View File

@@ -124,6 +124,9 @@
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
#define CONFIG_EXTRA_ENV_SETTINGS \
"updateb=" \
"onenand erase 0x0 0x100000;" \
@@ -229,8 +232,8 @@
/*
* I2C Settings
*/
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6)
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
@@ -253,10 +256,10 @@
*/
#define CONFIG_SOFT_SPI
#define CONFIG_SOFT_SPI_MODE SPI_MODE_3
#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1)
#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3)
#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0)
#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3)
#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1)
#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3)
#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0)
#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3)
#define SPI_DELAY udelay(1)
#undef SPI_INIT
@@ -269,16 +272,43 @@ void universal_spi_sda(int bit);
int universal_spi_read(void);
#endif
/* Common misc for Samsung */
#define CONFIG_MISC_COMMON
#define CONFIG_MISC_INIT_R
/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
#define CONFIG_LCD_MENU_BOARD
/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
#include <power/max8998_pmic.h>
#define KEY_PWR_PMIC_NAME "MAX8998_PMIC"
#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1
#define KEY_PWR_STATUS_MASK (1 << 7)
#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1
#define KEY_PWR_INTERRUPT_MASK (1 << 7)
#define KEY_VOL_UP_GPIO exynos4_gpio_get(2, x2, 0)
#define KEY_VOL_DOWN_GPIO exynos4_gpio_get(2, x2, 1)
#endif /* __ASSEMBLY__ */
/* LCD console */
#define LCD_BPP LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK
/*
* LCD Settings
*/
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_32BPP
#define CONFIG_BMP_16BPP
#define CONFIG_LD9040
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((520 * 120 * 4) + (1 << 12))
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
#endif /* __CONFIG_H */

1
include/configs/sandbox.h
View File

@@ -42,6 +42,7 @@
#define CONFIG_CMD_PART
#define CONFIG_DOS_PARTITION
#define CONFIG_HOST_MAX_DEVICES 4
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_SYS_VSNPRINTF

2
include/configs/sansa_fuze_plus.h
View File

@@ -56,7 +56,7 @@
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */
#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER

1
include/configs/scb9328.h
View File

@@ -69,7 +69,6 @@
#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
#define CONFIG_SYS_MEMTEST_END 0x08F00000
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
#define CONFIG_BAUDRATE 115200

1
include/configs/shmin.h
View File

@@ -62,7 +62,6 @@
#define CONFIG_SYS_MONITOR_BASE (SHMIN_FLASH_BASE_1 + CONFIG_ENV_SECT_SIZE)
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
#define CONFIG_SYS_GBL_DATA_SIZE 256
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */

2
include/configs/smdk5420.h
View File

@@ -17,8 +17,6 @@
#undef CONFIG_DEFAULT_DEVICE_TREE
#define CONFIG_DEFAULT_DEVICE_TREE exynos5420-smdk5420
#define CONFIG_ARCH_DEVICE_TREE exynos5420
#define CONFIG_VAR_SIZE_SPL
#define CONFIG_SYS_SDRAM_BASE 0x20000000

2
include/configs/snowball.h
View File

@@ -41,8 +41,6 @@
#define CONFIG_ENV_SIZE (8*1024)
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256*1024)
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_CMD_ENV
#define CONFIG_CMD_SAVEENV

13
include/configs/spear-common.h
View File

@@ -17,11 +17,9 @@
/* Ethernet driver configuration */
#define CONFIG_MII
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_SEARCH_PHY
#define CONFIG_DW0_PHY 1
#define CONFIG_NET_MULTI
#define CONFIG_PHYLIB
#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
/* USBD driver configuration */
@@ -41,6 +39,15 @@
/* I2C driver configuration */
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
#if defined(CONFIG_SPEAR600)
#define CONFIG_SYS_I2C_BASE 0xD0200000
#elif defined(CONFIG_SPEAR300)
#define CONFIG_SYS_I2C_BASE 0xD0180000
#elif defined(CONFIG_SPEAR310)
#define CONFIG_SYS_I2C_BASE 0xD0180000
#elif defined(CONFIG_SPEAR320)
#define CONFIG_SYS_I2C_BASE 0xD0180000
#endif
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_SYS_I2C_SLAVE 0x02

3
include/configs/spear6xx_evb.h
View File

@@ -37,6 +37,9 @@
#define CONFIG_SYS_FSMC_NAND_8BIT
#define CONFIG_SYS_NAND_BASE 0xD2000000
/* Ethernet PHY configuration */
#define CONFIG_PHY_NATSEMI
/* Environment Settings */
#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY

7
include/configs/tao3530.h
View File

@@ -83,6 +83,13 @@
#define CONFIG_OMAP_HSMMC
#define CONFIG_DOS_PARTITION
/* GPIO banks */
#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
/* commands to include */
#include <config_cmd_default.h>

1
include/configs/taurus.h
View File

@@ -37,7 +37,6 @@
/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
#define CONFIG_SYS_HZ 1000
/* Misc CPU related */
#define CONFIG_ARCH_CPU_INIT

8
include/configs/tegra-common-post.h
View File

@@ -99,6 +99,7 @@
BOOTCMDS_DHCP
#define CONFIG_BOOTCOMMAND \
"set usb_need_init; " \
"for target in ${boot_targets}; do run bootcmd_${target}; done"
#endif
@@ -129,10 +130,15 @@
"stderr=serial" STDOUT_LCD "\0" \
""
#ifndef BOARD_EXTRA_ENV_SETTINGS
#define BOARD_EXTRA_ENV_SETTINGS
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
TEGRA_DEVICE_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
BOOTCMDS_COMMON
BOOTCMDS_COMMON \
BOARD_EXTRA_ENV_SETTINGS
#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI)
#define CONFIG_FDT_SPI

83
include/configs/tegra124-common.h Normal file
View File

@@ -0,0 +1,83 @@
/*
* (C) Copyright 2013
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _TEGRA124_COMMON_H_
#define _TEGRA124_COMMON_H_
#include "tegra-common.h"
/* Cortex-A15 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
/*
* High Level Configuration Options
*/
#define CONFIG_TEGRA124 /* is an NVIDIA Tegra124 core */
/* Environment information, boards can override if required */
#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_SYS_TEXT_BASE 0x8010E000
/*
* Memory layout for where various images get loaded by boot scripts:
*
* scriptaddr can be pretty much anywhere that doesn't conflict with something
* else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
* something else. Put it above BOOTMAPSZ to eliminate conflicts.
*
* kernel_addr_r must be within the first 128M of RAM in order for the
* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
* should not overlap that area, or the kernel will have to copy itself
* somewhere else before decompression. Similarly, the address of any other
* data passed to the kernel shouldn't overlap the start of RAM. Pushing
* this up to 16M allows for a sizable kernel to be decompressed below the
* compressed load address.
*
* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
* the compressed kernel to be up to 16M too.
*
* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
* for the FDT/DTB to be up to 1M, which is hopefully plenty.
*/
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=0x90000000\0" \
"pxefile_addr_r=0x90100000\0" \
"kernel_addr_r=0x81000000\0" \
"fdt_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x82100000\0"
/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE 0x80108000
#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
#define CONFIG_SPL_STACK 0x800ffffc
/* Total I2C ports on Tegra124 */
#define TEGRA_I2C_NUM_CONTROLLERS 5
/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
#endif /* _TEGRA124_COMMON_H_ */

1
include/configs/ti814x_evm.h
View File

@@ -233,7 +233,6 @@
#define CONFIG_NET_MULTI
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_ADDR 1
#define CONFIG_PHY_ET1011C
#define CONFIG_PHY_ET1011C_TX_CLK_FIX

2
include/configs/ti_am335x_common.h
View File

@@ -13,7 +13,6 @@
#define __CONFIG_TI_AM335X_COMMON_H__
#define CONFIG_AM33XX
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
@@ -31,6 +30,7 @@
/* Network defines. */
#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME

6
include/configs/ti_omap4_common.h
View File

@@ -163,4 +163,10 @@
#define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
#endif
#ifdef CONFIG_SPL_BUILD
/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */
#undef CONFIG_SYS_I2C
#undef CONFIG_SYS_I2C_OMAP24XX
#endif
#endif /* __CONFIG_TI_OMAP4_COMMON_H */

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