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board: phytec: phycore_imx8mp: Change debug UART

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With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Teresa Remmet
2021-07-07 12:57:59 +00:00
committed by Stefano Babic
parent 3240d9c63a
commit 1feac813fe
4 changed files with 13 additions and 13 deletions
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6
board/phytec/phycore_imx8mp/spl.c
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@@ -80,8 +80,8 @@ int board_fit_config_name_match(const char *name)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static iomux_v3_cfg_t const uart_pads[] = {
MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX8MP_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
@@ -107,7 +107,7 @@ void board_init_f(ulong dummy)
arch_cpu_init();
init_uart_clk(1);
init_uart_clk(0);
board_early_init_f();