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Merge git://git.denx.de/u-boot-rockchip

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This commit is contained in:
Tom Rini
2016-09-22 16:51:19 -04:00
parent 82f5279b0c 4f0b8efa50
commit 201c9d884d
26 changed files with 1390 additions and 25 deletions
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1
include/configs/rk3288_common.h
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@@ -9,6 +9,7 @@
#include <asm/arch/hardware.h>
#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#define CONFIG_SYS_NO_FLASH
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_ENV_SIZE 0x2000

12
include/configs/rk3399_common.h
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@@ -83,4 +83,16 @@
#endif
/* enable usb config for usb ether */
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_ASIX88179
#define CONFIG_USB_ETHER_MCS7830
#define CONFIG_USB_ETHER_SMSC95XX
#define CONFIG_USB_ETHER_RTL8152
/* rockchip xhci host driver */
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif

14
include/linux/usb/dwc3.h
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@@ -180,7 +180,21 @@ struct dwc3 { /* offset: 0xC100 */
/* Global USB2 PHY Configuration Register */
#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS (1 << 30)
#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
#define DWC3_GUSB2PHYCFG_PHYIF (1 << 3)
/* Global USB2 PHY Configuration Mask */
#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK (0xf << 10)
/* Global USB2 PHY Configuration Offset */
#define DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET 10
#define DWC3_GUSB2PHYCFG_USBTRDTIM_16BIT (0x5 << \
DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
#define DWC3_GUSB2PHYCFG_USBTRDTIM_8BIT (0x9 << \
DWC3_GUSB2PHYCFG_USBTRDTIM_OFFSET)
/* Global USB3 PIPE Control Register */
#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)