spi: zynqmp_gqspi: Add parallel memories support in GQSPI driver

Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands are exclueded by using zynqmp_qspi_update_stripe().

Also update copyright info for this file.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
This commit is contained in:
Venkatesh Yadav Abbarapu
2024-09-26 10:25:06 +05:30
committed by Tom Rini
parent 34da258bb0
commit 217b0a28b6
2 changed files with 129 additions and 16 deletions

View File

@@ -38,6 +38,9 @@
#define SPI_DEFAULT_WORDLEN 8
#define SPI_3BYTE_MODE 0x0
#define SPI_4BYTE_MODE 0x1
/* SPI transfer flags */
#define SPI_XFER_STRIPE (1 << 6)
#define SPI_XFER_MASK (3 << 8)
@@ -172,6 +175,7 @@ struct spi_slave {
* at once.
*/
bool multi_cs_cap;
u32 bytemode;
};
/**