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Merge tag 'v2024.07-rc4' into next

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Prepare v2024.070-rc4
This commit is contained in:
Tom Rini
2024-06-03 18:42:11 -06:00
parent 15d0dcc0ec c0ea27bccf
commit 227be29df3
106 changed files with 884 additions and 8067 deletions
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15
include/configs/nova-rk3588s.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2022 Collabora Ltd.
*/
#ifndef __NOVA_RK3588S_H
#define __NOVA_RK3588S_H
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#include <configs/rk3588_common.h>
#endif /* __NOVA_RK3588S_H */

12
include/configs/powkiddy-x55-rk3566.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __POWKIDDY_X55_RK3566_H
#define __POWKIDDY_X55_RK3566_H
#include <configs/rk3568_common.h>
#define ROCKCHIP_DEVICE_SETTINGS \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
#endif

337
include/dt-bindings/clock/exynos850.h
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@@ -1,337 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2021 Linaro Ltd.
* Author: Sam Protsenko <semen.protsenko@linaro.org>
*
* Device Tree binding constants for Exynos850 clock controller.
*/
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H
#define _DT_BINDINGS_CLOCK_EXYNOS_850_H
/* CMU_TOP */
#define CLK_FOUT_SHARED0_PLL 1
#define CLK_FOUT_SHARED1_PLL 2
#define CLK_FOUT_MMC_PLL 3
#define CLK_MOUT_SHARED0_PLL 4
#define CLK_MOUT_SHARED1_PLL 5
#define CLK_MOUT_MMC_PLL 6
#define CLK_MOUT_CORE_BUS 7
#define CLK_MOUT_CORE_CCI 8
#define CLK_MOUT_CORE_MMC_EMBD 9
#define CLK_MOUT_CORE_SSS 10
#define CLK_MOUT_DPU 11
#define CLK_MOUT_HSI_BUS 12
#define CLK_MOUT_HSI_MMC_CARD 13
#define CLK_MOUT_HSI_USB20DRD 14
#define CLK_MOUT_PERI_BUS 15
#define CLK_MOUT_PERI_UART 16
#define CLK_MOUT_PERI_IP 17
#define CLK_DOUT_SHARED0_DIV3 18
#define CLK_DOUT_SHARED0_DIV2 19
#define CLK_DOUT_SHARED1_DIV3 20
#define CLK_DOUT_SHARED1_DIV2 21
#define CLK_DOUT_SHARED0_DIV4 22
#define CLK_DOUT_SHARED1_DIV4 23
#define CLK_DOUT_CORE_BUS 24
#define CLK_DOUT_CORE_CCI 25
#define CLK_DOUT_CORE_MMC_EMBD 26
#define CLK_DOUT_CORE_SSS 27
#define CLK_DOUT_DPU 28
#define CLK_DOUT_HSI_BUS 29
#define CLK_DOUT_HSI_MMC_CARD 30
#define CLK_DOUT_HSI_USB20DRD 31
#define CLK_DOUT_PERI_BUS 32
#define CLK_DOUT_PERI_UART 33
#define CLK_DOUT_PERI_IP 34
#define CLK_GOUT_CORE_BUS 35
#define CLK_GOUT_CORE_CCI 36
#define CLK_GOUT_CORE_MMC_EMBD 37
#define CLK_GOUT_CORE_SSS 38
#define CLK_GOUT_DPU 39
#define CLK_GOUT_HSI_BUS 40
#define CLK_GOUT_HSI_MMC_CARD 41
#define CLK_GOUT_HSI_USB20DRD 42
#define CLK_GOUT_PERI_BUS 43
#define CLK_GOUT_PERI_UART 44
#define CLK_GOUT_PERI_IP 45
#define CLK_MOUT_CLKCMU_APM_BUS 46
#define CLK_DOUT_CLKCMU_APM_BUS 47
#define CLK_GOUT_CLKCMU_APM_BUS 48
#define CLK_MOUT_AUD 49
#define CLK_GOUT_AUD 50
#define CLK_DOUT_AUD 51
#define CLK_MOUT_IS_BUS 52
#define CLK_MOUT_IS_ITP 53
#define CLK_MOUT_IS_VRA 54
#define CLK_MOUT_IS_GDC 55
#define CLK_GOUT_IS_BUS 56
#define CLK_GOUT_IS_ITP 57
#define CLK_GOUT_IS_VRA 58
#define CLK_GOUT_IS_GDC 59
#define CLK_DOUT_IS_BUS 60
#define CLK_DOUT_IS_ITP 61
#define CLK_DOUT_IS_VRA 62
#define CLK_DOUT_IS_GDC 63
#define CLK_MOUT_MFCMSCL_MFC 64
#define CLK_MOUT_MFCMSCL_M2M 65
#define CLK_MOUT_MFCMSCL_MCSC 66
#define CLK_MOUT_MFCMSCL_JPEG 67
#define CLK_GOUT_MFCMSCL_MFC 68
#define CLK_GOUT_MFCMSCL_M2M 69
#define CLK_GOUT_MFCMSCL_MCSC 70
#define CLK_GOUT_MFCMSCL_JPEG 71
#define CLK_DOUT_MFCMSCL_MFC 72
#define CLK_DOUT_MFCMSCL_M2M 73
#define CLK_DOUT_MFCMSCL_MCSC 74
#define CLK_DOUT_MFCMSCL_JPEG 75
#define CLK_MOUT_G3D_SWITCH 76
#define CLK_GOUT_G3D_SWITCH 77
#define CLK_DOUT_G3D_SWITCH 78
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
#define OSCCLK_RCO_APM 2
#define CLK_RCO_APM__ALV 3
#define CLK_DLL_DCO 4
#define CLK_MOUT_APM_BUS_USER 5
#define CLK_MOUT_RCO_APM_I3C_USER 6
#define CLK_MOUT_RCO_APM_USER 7
#define CLK_MOUT_DLL_USER 8
#define CLK_MOUT_CLKCMU_CHUB_BUS 9
#define CLK_MOUT_APM_BUS 10
#define CLK_MOUT_APM_I3C 11
#define CLK_DOUT_CLKCMU_CHUB_BUS 12
#define CLK_DOUT_APM_BUS 13
#define CLK_DOUT_APM_I3C 14
#define CLK_GOUT_CLKCMU_CMGP_BUS 15
#define CLK_GOUT_CLKCMU_CHUB_BUS 16
#define CLK_GOUT_RTC_PCLK 17
#define CLK_GOUT_TOP_RTC_PCLK 18
#define CLK_GOUT_I3C_PCLK 19
#define CLK_GOUT_I3C_SCLK 20
#define CLK_GOUT_SPEEDY_PCLK 21
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
#define CLK_GOUT_PMU_ALIVE_PCLK 23
#define CLK_GOUT_SYSREG_APM_PCLK 24
/* CMU_AUD */
#define CLK_DOUT_AUD_AUDIF 1
#define CLK_DOUT_AUD_BUSD 2
#define CLK_DOUT_AUD_BUSP 3
#define CLK_DOUT_AUD_CNT 4
#define CLK_DOUT_AUD_CPU 5
#define CLK_DOUT_AUD_CPU_ACLK 6
#define CLK_DOUT_AUD_CPU_PCLKDBG 7
#define CLK_DOUT_AUD_FM 8
#define CLK_DOUT_AUD_FM_SPDY 9
#define CLK_DOUT_AUD_MCLK 10
#define CLK_DOUT_AUD_UAIF0 11
#define CLK_DOUT_AUD_UAIF1 12
#define CLK_DOUT_AUD_UAIF2 13
#define CLK_DOUT_AUD_UAIF3 14
#define CLK_DOUT_AUD_UAIF4 15
#define CLK_DOUT_AUD_UAIF5 16
#define CLK_DOUT_AUD_UAIF6 17
#define CLK_FOUT_AUD_PLL 18
#define CLK_GOUT_AUD_ABOX_ACLK 19
#define CLK_GOUT_AUD_ASB_CCLK 20
#define CLK_GOUT_AUD_CA32_CCLK 21
#define CLK_GOUT_AUD_CNT_BCLK 22
#define CLK_GOUT_AUD_CODEC_MCLK 23
#define CLK_GOUT_AUD_DAP_CCLK 24
#define CLK_GOUT_AUD_GPIO_PCLK 25
#define CLK_GOUT_AUD_PPMU_ACLK 26
#define CLK_GOUT_AUD_PPMU_PCLK 27
#define CLK_GOUT_AUD_SPDY_BCLK 28
#define CLK_GOUT_AUD_SYSMMU_CLK 29
#define CLK_GOUT_AUD_SYSREG_PCLK 30
#define CLK_GOUT_AUD_TZPC_PCLK 31
#define CLK_GOUT_AUD_UAIF0_BCLK 32
#define CLK_GOUT_AUD_UAIF1_BCLK 33
#define CLK_GOUT_AUD_UAIF2_BCLK 34
#define CLK_GOUT_AUD_UAIF3_BCLK 35
#define CLK_GOUT_AUD_UAIF4_BCLK 36
#define CLK_GOUT_AUD_UAIF5_BCLK 37
#define CLK_GOUT_AUD_UAIF6_BCLK 38
#define CLK_GOUT_AUD_WDT_PCLK 39
#define CLK_MOUT_AUD_CPU 40
#define CLK_MOUT_AUD_CPU_HCH 41
#define CLK_MOUT_AUD_CPU_USER 42
#define CLK_MOUT_AUD_FM 43
#define CLK_MOUT_AUD_PLL 44
#define CLK_MOUT_AUD_TICK_USB_USER 45
#define CLK_MOUT_AUD_UAIF0 46
#define CLK_MOUT_AUD_UAIF1 47
#define CLK_MOUT_AUD_UAIF2 48
#define CLK_MOUT_AUD_UAIF3 49
#define CLK_MOUT_AUD_UAIF4 50
#define CLK_MOUT_AUD_UAIF5 51
#define CLK_MOUT_AUD_UAIF6 52
#define IOCLK_AUDIOCDCLK0 53
#define IOCLK_AUDIOCDCLK1 54
#define IOCLK_AUDIOCDCLK2 55
#define IOCLK_AUDIOCDCLK3 56
#define IOCLK_AUDIOCDCLK4 57
#define IOCLK_AUDIOCDCLK5 58
#define IOCLK_AUDIOCDCLK6 59
#define TICK_USB 60
#define CLK_GOUT_AUD_CMU_AUD_PCLK 61
/* CMU_CMGP */
#define CLK_RCO_CMGP 1
#define CLK_MOUT_CMGP_ADC 2
#define CLK_MOUT_CMGP_USI0 3
#define CLK_MOUT_CMGP_USI1 4
#define CLK_DOUT_CMGP_ADC 5
#define CLK_DOUT_CMGP_USI0 6
#define CLK_DOUT_CMGP_USI1 7
#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
#define CLK_GOUT_CMGP_GPIO_PCLK 10
#define CLK_GOUT_CMGP_USI0_IPCLK 11
#define CLK_GOUT_CMGP_USI0_PCLK 12
#define CLK_GOUT_CMGP_USI1_IPCLK 13
#define CLK_GOUT_CMGP_USI1_PCLK 14
#define CLK_GOUT_SYSREG_CMGP_PCLK 15
/* CMU_G3D */
#define CLK_FOUT_G3D_PLL 1
#define CLK_MOUT_G3D_PLL 2
#define CLK_MOUT_G3D_SWITCH_USER 3
#define CLK_MOUT_G3D_BUSD 4
#define CLK_DOUT_G3D_BUSP 5
#define CLK_GOUT_G3D_CMU_G3D_PCLK 6
#define CLK_GOUT_G3D_GPU_CLK 7
#define CLK_GOUT_G3D_TZPC_PCLK 8
#define CLK_GOUT_G3D_GRAY2BIN_CLK 9
#define CLK_GOUT_G3D_BUSD_CLK 10
#define CLK_GOUT_G3D_BUSP_CLK 11
#define CLK_GOUT_G3D_SYSREG_PCLK 12
/* CMU_HSI */
#define CLK_MOUT_HSI_BUS_USER 1
#define CLK_MOUT_HSI_MMC_CARD_USER 2
#define CLK_MOUT_HSI_USB20DRD_USER 3
#define CLK_MOUT_HSI_RTC 4
#define CLK_GOUT_USB_RTC_CLK 5
#define CLK_GOUT_USB_REF_CLK 6
#define CLK_GOUT_USB_PHY_REF_CLK 7
#define CLK_GOUT_USB_PHY_ACLK 8
#define CLK_GOUT_USB_BUS_EARLY_CLK 9
#define CLK_GOUT_GPIO_HSI_PCLK 10
#define CLK_GOUT_MMC_CARD_ACLK 11
#define CLK_GOUT_MMC_CARD_SDCLKIN 12
#define CLK_GOUT_SYSREG_HSI_PCLK 13
#define CLK_GOUT_HSI_PPMU_ACLK 14
#define CLK_GOUT_HSI_PPMU_PCLK 15
#define CLK_GOUT_HSI_CMU_HSI_PCLK 16
/* CMU_IS */
#define CLK_MOUT_IS_BUS_USER 1
#define CLK_MOUT_IS_ITP_USER 2
#define CLK_MOUT_IS_VRA_USER 3
#define CLK_MOUT_IS_GDC_USER 4
#define CLK_DOUT_IS_BUSP 5
#define CLK_GOUT_IS_CMU_IS_PCLK 6
#define CLK_GOUT_IS_CSIS0_ACLK 7
#define CLK_GOUT_IS_CSIS1_ACLK 8
#define CLK_GOUT_IS_CSIS2_ACLK 9
#define CLK_GOUT_IS_TZPC_PCLK 10
#define CLK_GOUT_IS_CSIS_DMA_CLK 11
#define CLK_GOUT_IS_GDC_CLK 12
#define CLK_GOUT_IS_IPP_CLK 13
#define CLK_GOUT_IS_ITP_CLK 14
#define CLK_GOUT_IS_MCSC_CLK 15
#define CLK_GOUT_IS_VRA_CLK 16
#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
#define CLK_GOUT_IS_SYSREG_PCLK 23
/* CMU_MFCMSCL */
#define CLK_MOUT_MFCMSCL_MFC_USER 1
#define CLK_MOUT_MFCMSCL_M2M_USER 2
#define CLK_MOUT_MFCMSCL_MCSC_USER 3
#define CLK_MOUT_MFCMSCL_JPEG_USER 4
#define CLK_DOUT_MFCMSCL_BUSP 5
#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
#define CLK_MOUT_PERI_UART_USER 2
#define CLK_MOUT_PERI_HSI2C_USER 3
#define CLK_MOUT_PERI_SPI_USER 4
#define CLK_DOUT_PERI_HSI2C0 5
#define CLK_DOUT_PERI_HSI2C1 6
#define CLK_DOUT_PERI_HSI2C2 7
#define CLK_DOUT_PERI_SPI0 8
#define CLK_GOUT_PERI_HSI2C0 9
#define CLK_GOUT_PERI_HSI2C1 10
#define CLK_GOUT_PERI_HSI2C2 11
#define CLK_GOUT_GPIO_PERI_PCLK 12
#define CLK_GOUT_HSI2C0_IPCLK 13
#define CLK_GOUT_HSI2C0_PCLK 14
#define CLK_GOUT_HSI2C1_IPCLK 15
#define CLK_GOUT_HSI2C1_PCLK 16
#define CLK_GOUT_HSI2C2_IPCLK 17
#define CLK_GOUT_HSI2C2_PCLK 18
#define CLK_GOUT_I2C0_PCLK 19
#define CLK_GOUT_I2C1_PCLK 20
#define CLK_GOUT_I2C2_PCLK 21
#define CLK_GOUT_I2C3_PCLK 22
#define CLK_GOUT_I2C4_PCLK 23
#define CLK_GOUT_I2C5_PCLK 24
#define CLK_GOUT_I2C6_PCLK 25
#define CLK_GOUT_MCT_PCLK 26
#define CLK_GOUT_PWM_MOTOR_PCLK 27
#define CLK_GOUT_SPI0_IPCLK 28
#define CLK_GOUT_SPI0_PCLK 29
#define CLK_GOUT_SYSREG_PERI_PCLK 30
#define CLK_GOUT_UART_IPCLK 31
#define CLK_GOUT_UART_PCLK 32
#define CLK_GOUT_WDT0_PCLK 33
#define CLK_GOUT_WDT1_PCLK 34
/* CMU_CORE */
#define CLK_MOUT_CORE_BUS_USER 1
#define CLK_MOUT_CORE_CCI_USER 2
#define CLK_MOUT_CORE_MMC_EMBD_USER 3
#define CLK_MOUT_CORE_SSS_USER 4
#define CLK_MOUT_CORE_GIC 5
#define CLK_DOUT_CORE_BUSP 6
#define CLK_GOUT_CCI_ACLK 7
#define CLK_GOUT_GIC_CLK 8
#define CLK_GOUT_MMC_EMBD_ACLK 9
#define CLK_GOUT_MMC_EMBD_SDCLKIN 10
#define CLK_GOUT_SSS_ACLK 11
#define CLK_GOUT_SSS_PCLK 12
#define CLK_GOUT_GPIO_CORE_PCLK 13
#define CLK_GOUT_SYSREG_CORE_PCLK 14
/* CMU_DPU */
#define CLK_MOUT_DPU_USER 1
#define CLK_DOUT_DPU_BUSP 2
#define CLK_GOUT_DPU_CMU_DPU_PCLK 3
#define CLK_GOUT_DPU_DECON0_ACLK 4
#define CLK_GOUT_DPU_DMA_ACLK 5
#define CLK_GOUT_DPU_DPP_ACLK 6
#define CLK_GOUT_DPU_PPMU_ACLK 7
#define CLK_GOUT_DPU_PPMU_PCLK 8
#define CLK_GOUT_DPU_SMMU_CLK 9
#define CLK_GOUT_DPU_SYSREG_PCLK 10
#define DPU_NR_CLK 11
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */

632
include/dt-bindings/clock/rockchip,rv1126-cru.h
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@@ -1,632 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
* Copyright (c) 2019 Rockchip Electronics Co. Ltd.
* Author: Finley Xiao <finley.xiao@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
/* pmucru-clocks indices */
/* pll clocks */
#define PLL_GPLL 1
/* sclk (special clocks) */
#define CLK_OSC0_DIV32K 2
#define CLK_RTC32K 3
#define CLK_WIFI_DIV 4
#define CLK_WIFI_OSC0 5
#define CLK_WIFI 6
#define CLK_PMU 7
#define SCLK_UART1_DIV 8
#define SCLK_UART1_FRACDIV 9
#define SCLK_UART1_MUX 10
#define SCLK_UART1 11
#define CLK_I2C0 12
#define CLK_I2C2 13
#define CLK_CAPTURE_PWM0 14
#define CLK_PWM0 15
#define CLK_CAPTURE_PWM1 16
#define CLK_PWM1 17
#define CLK_SPI0 18
#define DBCLK_GPIO0 19
#define CLK_PMUPVTM 20
#define CLK_CORE_PMUPVTM 21
#define CLK_REF12M 22
#define CLK_USBPHY_OTG_REF 23
#define CLK_USBPHY_HOST_REF 24
#define CLK_REF24M 25
#define CLK_MIPIDSIPHY_REF 26
/* pclk */
#define PCLK_PDPMU 30
#define PCLK_PMU 31
#define PCLK_UART1 32
#define PCLK_I2C0 33
#define PCLK_I2C2 34
#define PCLK_PWM0 35
#define PCLK_PWM1 36
#define PCLK_SPI0 37
#define PCLK_GPIO0 38
#define PCLK_PMUSGRF 39
#define PCLK_PMUGRF 40
#define PCLK_PMUCRU 41
#define PCLK_CHIPVEROTP 42
#define PCLK_PDPMU_NIU 43
#define PCLK_PMUPVTM 44
#define PCLK_SCRKEYGEN 45
#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
/* cru-clocks indices */
/* pll clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
#define PLL_CPLL 3
#define PLL_HPLL 4
/* sclk (special clocks) */
#define ARMCLK 5
#define USB480M 6
#define CLK_CORE_CPUPVTM 7
#define CLK_CPUPVTM 8
#define CLK_SCR1 9
#define CLK_SCR1_CORE 10
#define CLK_SCR1_RTC 11
#define CLK_SCR1_JTAG 12
#define SCLK_UART0_DIV 13
#define SCLK_UART0_FRAC 14
#define SCLK_UART0_MUX 15
#define SCLK_UART0 16
#define SCLK_UART2_DIV 17
#define SCLK_UART2_FRAC 18
#define SCLK_UART2_MUX 19
#define SCLK_UART2 20
#define SCLK_UART3_DIV 21
#define SCLK_UART3_FRAC 22
#define SCLK_UART3_MUX 23
#define SCLK_UART3 24
#define SCLK_UART4_DIV 25
#define SCLK_UART4_FRAC 26
#define SCLK_UART4_MUX 27
#define SCLK_UART4 28
#define SCLK_UART5_DIV 29
#define SCLK_UART5_FRAC 30
#define SCLK_UART5_MUX 31
#define SCLK_UART5 32
#define CLK_I2C1 33
#define CLK_I2C3 34
#define CLK_I2C4 35
#define CLK_I2C5 36
#define CLK_SPI1 37
#define CLK_CAPTURE_PWM2 38
#define CLK_PWM2 39
#define DBCLK_GPIO1 40
#define DBCLK_GPIO2 41
#define DBCLK_GPIO3 42
#define DBCLK_GPIO4 43
#define CLK_SARADC 44
#define CLK_TIMER0 45
#define CLK_TIMER1 46
#define CLK_TIMER2 47
#define CLK_TIMER3 48
#define CLK_TIMER4 49
#define CLK_TIMER5 50
#define CLK_CAN 51
#define CLK_NPU_TSADC 52
#define CLK_NPU_TSADCPHY 53
#define CLK_CPU_TSADC 54
#define CLK_CPU_TSADCPHY 55
#define CLK_CRYPTO_CORE 56
#define CLK_CRYPTO_PKA 57
#define MCLK_I2S0_TX_DIV 58
#define MCLK_I2S0_TX_FRACDIV 59
#define MCLK_I2S0_TX_MUX 60
#define MCLK_I2S0_TX 61
#define MCLK_I2S0_RX_DIV 62
#define MCLK_I2S0_RX_FRACDIV 63
#define MCLK_I2S0_RX_MUX 64
#define MCLK_I2S0_RX 65
#define MCLK_I2S0_TX_OUT2IO 66
#define MCLK_I2S0_RX_OUT2IO 67
#define MCLK_I2S1_DIV 68
#define MCLK_I2S1_FRACDIV 69
#define MCLK_I2S1_MUX 70
#define MCLK_I2S1 71
#define MCLK_I2S1_OUT2IO 72
#define MCLK_I2S2_DIV 73
#define MCLK_I2S2_FRACDIV 74
#define MCLK_I2S2_MUX 75
#define MCLK_I2S2 76
#define MCLK_I2S2_OUT2IO 77
#define MCLK_PDM 78
#define SCLK_ADUPWM_DIV 79
#define SCLK_AUDPWM_FRACDIV 80
#define SCLK_AUDPWM_MUX 81
#define SCLK_AUDPWM 82
#define CLK_ACDCDIG_ADC 83
#define CLK_ACDCDIG_DAC 84
#define CLK_ACDCDIG_I2C 85
#define CLK_VENC_CORE 86
#define CLK_VDEC_CORE 87
#define CLK_VDEC_CA 88
#define CLK_VDEC_HEVC_CA 89
#define CLK_RGA_CORE 90
#define CLK_IEP_CORE 91
#define CLK_ISP_DIV 92
#define CLK_ISP_NP5 93
#define CLK_ISP_NUX 94
#define CLK_ISP 95
#define CLK_CIF_OUT_DIV 96
#define CLK_CIF_OUT_FRACDIV 97
#define CLK_CIF_OUT_MUX 98
#define CLK_CIF_OUT 99
#define CLK_MIPICSI_OUT_DIV 100
#define CLK_MIPICSI_OUT_FRACDIV 101
#define CLK_MIPICSI_OUT_MUX 102
#define CLK_MIPICSI_OUT 103
#define CLK_ISPP_DIV 104
#define CLK_ISPP_NP5 105
#define CLK_ISPP_NUX 106
#define CLK_ISPP 107
#define CLK_SDMMC 108
#define SCLK_SDMMC_DRV 109
#define SCLK_SDMMC_SAMPLE 110
#define CLK_SDIO 111
#define SCLK_SDIO_DRV 112
#define SCLK_SDIO_SAMPLE 113
#define CLK_EMMC 114
#define SCLK_EMMC_DRV 115
#define SCLK_EMMC_SAMPLE 116
#define CLK_NANDC 117
#define SCLK_SFC 118
#define CLK_USBHOST_UTMI_OHCI 119
#define CLK_USBOTG_REF 120
#define CLK_GMAC_DIV 121
#define CLK_GMAC_RGMII_M0 122
#define CLK_GMAC_SRC_M0 123
#define CLK_GMAC_RGMII_M1 124
#define CLK_GMAC_SRC_M1 125
#define CLK_GMAC_SRC 126
#define CLK_GMAC_REF 127
#define CLK_GMAC_TX_SRC 128
#define CLK_GMAC_TX_DIV5 129
#define CLK_GMAC_TX_DIV50 130
#define RGMII_MODE_CLK 131
#define CLK_GMAC_RX_SRC 132
#define CLK_GMAC_RX_DIV2 133
#define CLK_GMAC_RX_DIV20 134
#define RMII_MODE_CLK 135
#define CLK_GMAC_TX_RX 136
#define CLK_GMAC_PTPREF 137
#define CLK_GMAC_ETHERNET_OUT 138
#define CLK_DDRPHY 139
#define CLK_DDR_MON 140
#define TMCLK_DDR_MON 141
#define CLK_NPU_DIV 142
#define CLK_NPU_NP5 143
#define CLK_CORE_NPU 144
#define CLK_CORE_NPUPVTM 145
#define CLK_NPUPVTM 146
#define SCLK_DDRCLK 147
#define CLK_OTP 148
/* dclk */
#define DCLK_DECOM 150
#define DCLK_VOP_DIV 151
#define DCLK_VOP_FRACDIV 152
#define DCLK_VOP_MUX 153
#define DCLK_VOP 154
#define DCLK_CIF 155
#define DCLK_CIFLITE 156
/* aclk */
#define ACLK_PDBUS 160
#define ACLK_DMAC 161
#define ACLK_DCF 162
#define ACLK_SPINLOCK 163
#define ACLK_DECOM 164
#define ACLK_PDCRYPTO 165
#define ACLK_CRYPTO 166
#define ACLK_PDVEPU 167
#define ACLK_VENC 168
#define ACLK_PDVDEC 169
#define ACLK_PDJPEG 170
#define ACLK_VDEC 171
#define ACLK_JPEG 172
#define ACLK_PDVO 173
#define ACLK_RGA 174
#define ACLK_VOP 175
#define ACLK_IEP 176
#define ACLK_PDVI_DIV 177
#define ACLK_PDVI_NP5 178
#define ACLK_PDVI 179
#define ACLK_ISP 180
#define ACLK_CIF 181
#define ACLK_CIFLITE 182
#define ACLK_PDISPP_DIV 183
#define ACLK_PDISPP_NP5 184
#define ACLK_PDISPP 185
#define ACLK_ISPP 186
#define ACLK_PDPHP 187
#define ACLK_PDUSB 188
#define ACLK_USBOTG 189
#define ACLK_PDGMAC 190
#define ACLK_GMAC 191
#define ACLK_PDNPU_DIV 192
#define ACLK_PDNPU_NP5 193
#define ACLK_PDNPU 194
#define ACLK_NPU 195
/* hclk */
#define HCLK_PDCORE_NIU 200
#define HCLK_PDUSB 201
#define HCLK_PDCRYPTO 202
#define HCLK_CRYPTO 203
#define HCLK_PDAUDIO 204
#define HCLK_I2S0 205
#define HCLK_I2S1 206
#define HCLK_I2S2 207
#define HCLK_PDM 208
#define HCLK_AUDPWM 209
#define HCLK_PDVEPU 210
#define HCLK_VENC 211
#define HCLK_PDVDEC 212
#define HCLK_PDJPEG 213
#define HCLK_VDEC 214
#define HCLK_JPEG 215
#define HCLK_PDVO 216
#define HCLK_RGA 217
#define HCLK_VOP 218
#define HCLK_IEP 219
#define HCLK_PDVI 220
#define HCLK_ISP 221
#define HCLK_CIF 222
#define HCLK_CIFLITE 223
#define HCLK_PDISPP 224
#define HCLK_ISPP 225
#define HCLK_PDPHP 226
#define HCLK_PDSDMMC 227
#define HCLK_SDMMC 228
#define HCLK_PDSDIO 229
#define HCLK_SDIO 230
#define HCLK_PDNVM 231
#define HCLK_EMMC 232
#define HCLK_NANDC 233
#define HCLK_SFC 234
#define HCLK_SFCXIP 235
#define HCLK_PDBUS 236
#define HCLK_USBHOST 237
#define HCLK_USBHOST_ARB 238
#define HCLK_PDNPU 239
#define HCLK_NPU 240
/* pclk */
#define PCLK_CPUPVTM 245
#define PCLK_PDBUS 246
#define PCLK_DCF 247
#define PCLK_WDT 248
#define PCLK_MAILBOX 249
#define PCLK_UART0 250
#define PCLK_UART2 251
#define PCLK_UART3 252
#define PCLK_UART4 253
#define PCLK_UART5 254
#define PCLK_I2C1 255
#define PCLK_I2C3 256
#define PCLK_I2C4 257
#define PCLK_I2C5 258
#define PCLK_SPI1 259
#define PCLK_PWM2 261
#define PCLK_GPIO1 262
#define PCLK_GPIO2 263
#define PCLK_GPIO3 264
#define PCLK_GPIO4 265
#define PCLK_SARADC 266
#define PCLK_TIMER 267
#define PCLK_DECOM 268
#define PCLK_CAN 269
#define PCLK_NPU_TSADC 270
#define PCLK_CPU_TSADC 271
#define PCLK_ACDCDIG 272
#define PCLK_PDVO 273
#define PCLK_DSIHOST 274
#define PCLK_PDVI 275
#define PCLK_CSIHOST 276
#define PCLK_PDGMAC 277
#define PCLK_GMAC 278
#define PCLK_PDDDR 279
#define PCLK_DDR_MON 280
#define PCLK_PDNPU 281
#define PCLK_NPUPVTM 282
#define PCLK_PDTOP 283
#define PCLK_TOPCRU 284
#define PCLK_TOPGRF 285
#define PCLK_CPUEMADET 286
#define PCLK_DDRPHY 287
#define PCLK_DSIPHY 289
#define PCLK_CSIPHY0 290
#define PCLK_CSIPHY1 291
#define PCLK_USBPHY_HOST 292
#define PCLK_USBPHY_OTG 293
#define PCLK_OTP 294
#define CLK_NR_CLKS (PCLK_OTP + 1)
/* pmu soft-reset indices */
/* pmu_cru_softrst_con0 */
#define SRST_PDPMU_NIU_P 0
#define SRST_PMU_SGRF_P 1
#define SRST_PMU_SGRF_REMAP_P 2
#define SRST_I2C0_P 3
#define SRST_I2C0 4
#define SRST_I2C2_P 7
#define SRST_I2C2 8
#define SRST_UART1_P 9
#define SRST_UART1 10
#define SRST_PWM0_P 11
#define SRST_PWM0 12
#define SRST_PWM1_P 13
#define SRST_PWM1 14
#define SRST_DDR_FAIL_SAFE 15
/* pmu_cru_softrst_con1 */
#define SRST_GPIO0_P 17
#define SRST_GPIO0_DB 18
#define SRST_SPI0_P 19
#define SRST_SPI0 20
#define SRST_PMUGRF_P 21
#define SRST_CHIPVEROTP_P 22
#define SRST_PMUPVTM 24
#define SRST_PMUPVTM_P 25
#define SRST_PMUCRU_P 30
/* soft-reset indices */
/* cru_softrst_con0 */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1
#define SRST_CORE2_PO 2
#define SRST_CORE3_PO 3
#define SRST_CORE0 4
#define SRST_CORE1 5
#define SRST_CORE2 6
#define SRST_CORE3 7
#define SRST_CORE0_DBG 8
#define SRST_CORE1_DBG 9
#define SRST_CORE2_DBG 10
#define SRST_CORE3_DBG 11
#define SRST_NL2 12
#define SRST_CORE_NIU_A 13
#define SRST_DBG_DAPLITE_P 14
#define SRST_DAPLITE_P 15
/* cru_softrst_con1 */
#define SRST_PDBUS_NIU1_A 16
#define SRST_PDBUS_NIU1_H 17
#define SRST_PDBUS_NIU1_P 18
#define SRST_PDBUS_NIU2_A 19
#define SRST_PDBUS_NIU2_H 20
#define SRST_PDBUS_NIU3_A 21
#define SRST_PDBUS_NIU3_H 22
#define SRST_PDBUS_HOLD_NIU1_A 23
#define SRST_DBG_NIU_P 24
#define SRST_PDCORE_NIIU_H 25
#define SRST_MUC_NIU 26
#define SRST_DCF_A 29
#define SRST_DCF_P 30
#define SRST_SYSTEM_SRAM_A 31
/* cru_softrst_con2 */
#define SRST_I2C1_P 32
#define SRST_I2C1 33
#define SRST_I2C3_P 34
#define SRST_I2C3 35
#define SRST_I2C4_P 36
#define SRST_I2C4 37
#define SRST_I2C5_P 38
#define SRST_I2C5 39
#define SRST_SPI1_P 40
#define SRST_SPI1 41
#define SRST_MCU_CORE 42
#define SRST_PWM2_P 44
#define SRST_PWM2 45
#define SRST_SPINLOCK_A 46
/* cru_softrst_con3 */
#define SRST_UART0_P 48
#define SRST_UART0 49
#define SRST_UART2_P 50
#define SRST_UART2 51
#define SRST_UART3_P 52
#define SRST_UART3 53
#define SRST_UART4_P 54
#define SRST_UART4 55
#define SRST_UART5_P 56
#define SRST_UART5 57
#define SRST_WDT_P 58
#define SRST_SARADC_P 59
#define SRST_GRF_P 61
#define SRST_TIMER_P 62
#define SRST_MAILBOX_P 63
/* cru_softrst_con4 */
#define SRST_TIMER0 64
#define SRST_TIMER1 65
#define SRST_TIMER2 66
#define SRST_TIMER3 67
#define SRST_TIMER4 68
#define SRST_TIMER5 69
#define SRST_INTMUX_P 70
#define SRST_GPIO1_P 72
#define SRST_GPIO1_DB 73
#define SRST_GPIO2_P 74
#define SRST_GPIO2_DB 75
#define SRST_GPIO3_P 76
#define SRST_GPIO3_DB 77
#define SRST_GPIO4_P 78
#define SRST_GPIO4_DB 79
/* cru_softrst_con5 */
#define SRST_CAN_P 80
#define SRST_CAN 81
#define SRST_DECOM_A 85
#define SRST_DECOM_P 86
#define SRST_DECOM_D 87
#define SRST_PDCRYPTO_NIU_A 88
#define SRST_PDCRYPTO_NIU_H 89
#define SRST_CRYPTO_A 90
#define SRST_CRYPTO_H 91
#define SRST_CRYPTO_CORE 92
#define SRST_CRYPTO_PKA 93
#define SRST_SGRF_P 95
/* cru_softrst_con6 */
#define SRST_PDAUDIO_NIU_H 96
#define SRST_PDAUDIO_NIU_P 97
#define SRST_I2S0_H 98
#define SRST_I2S0_TX_M 99
#define SRST_I2S0_RX_M 100
#define SRST_I2S1_H 101
#define SRST_I2S1_M 102
#define SRST_I2S2_H 103
#define SRST_I2S2_M 104
#define SRST_PDM_H 105
#define SRST_PDM_M 106
#define SRST_AUDPWM_H 107
#define SRST_AUDPWM 108
#define SRST_ACDCDIG_P 109
#define SRST_ACDCDIG 110
/* cru_softrst_con7 */
#define SRST_PDVEPU_NIU_A 112
#define SRST_PDVEPU_NIU_H 113
#define SRST_VENC_A 114
#define SRST_VENC_H 115
#define SRST_VENC_CORE 116
#define SRST_PDVDEC_NIU_A 117
#define SRST_PDVDEC_NIU_H 118
#define SRST_VDEC_A 119
#define SRST_VDEC_H 120
#define SRST_VDEC_CORE 121
#define SRST_VDEC_CA 122
#define SRST_VDEC_HEVC_CA 123
#define SRST_PDJPEG_NIU_A 124
#define SRST_PDJPEG_NIU_H 125
#define SRST_JPEG_A 126
#define SRST_JPEG_H 127
/* cru_softrst_con8 */
#define SRST_PDVO_NIU_A 128
#define SRST_PDVO_NIU_H 129
#define SRST_PDVO_NIU_P 130
#define SRST_RGA_A 131
#define SRST_RGA_H 132
#define SRST_RGA_CORE 133
#define SRST_VOP_A 134
#define SRST_VOP_H 135
#define SRST_VOP_D 136
#define SRST_TXBYTEHS_DSIHOST 137
#define SRST_DSIHOST_P 138
#define SRST_IEP_A 139
#define SRST_IEP_H 140
#define SRST_IEP_CORE 141
#define SRST_ISP_RX_P 142
/* cru_softrst_con9 */
#define SRST_PDVI_NIU_A 144
#define SRST_PDVI_NIU_H 145
#define SRST_PDVI_NIU_P 146
#define SRST_ISP 147
#define SRST_CIF_A 148
#define SRST_CIF_H 149
#define SRST_CIF_D 150
#define SRST_CIF_P 151
#define SRST_CIF_I 152
#define SRST_CIF_RX_P 153
#define SRST_PDISPP_NIU_A 154
#define SRST_PDISPP_NIU_H 155
#define SRST_ISPP_A 156
#define SRST_ISPP_H 157
#define SRST_ISPP 158
#define SRST_CSIHOST_P 159
/* cru_softrst_con10 */
#define SRST_PDPHPMID_NIU_A 160
#define SRST_PDPHPMID_NIU_H 161
#define SRST_PDNVM_NIU_H 163
#define SRST_SDMMC_H 164
#define SRST_SDIO_H 165
#define SRST_EMMC_H 166
#define SRST_SFC_H 167
#define SRST_SFCXIP_H 168
#define SRST_SFC 169
#define SRST_NANDC_H 170
#define SRST_NANDC 171
#define SRST_PDSDMMC_H 173
#define SRST_PDSDIO_H 174
/* cru_softrst_con11 */
#define SRST_PDUSB_NIU_A 176
#define SRST_PDUSB_NIU_H 177
#define SRST_USBHOST_H 178
#define SRST_USBHOST_ARB_H 179
#define SRST_USBHOST_UTMI 180
#define SRST_USBOTG_A 181
#define SRST_USBPHY_OTG_P 182
#define SRST_USBPHY_HOST_P 183
#define SRST_USBPHYPOR_OTG 184
#define SRST_USBPHYPOR_HOST 185
#define SRST_PDGMAC_NIU_A 188
#define SRST_PDGMAC_NIU_P 189
#define SRST_GMAC_A 190
/* cru_softrst_con12 */
#define SRST_DDR_DFICTL_P 193
#define SRST_DDR_MON_P 194
#define SRST_DDR_STANDBY_P 195
#define SRST_DDR_GRF_P 196
#define SRST_DDR_MSCH_P 197
#define SRST_DDR_SPLIT_A 198
#define SRST_DDR_MSCH 199
#define SRST_DDR_DFICTL 202
#define SRST_DDR_STANDBY 203
#define SRST_NPUMCU_NIU 205
#define SRST_DDRPHY_P 206
#define SRST_DDRPHY 207
/* cru_softrst_con13 */
#define SRST_PDNPU_NIU_A 208
#define SRST_PDNPU_NIU_H 209
#define SRST_PDNPU_NIU_P 210
#define SRST_NPU_A 211
#define SRST_NPU_H 212
#define SRST_NPU 213
#define SRST_NPUPVTM_P 214
#define SRST_NPUPVTM 215
#define SRST_NPU_TSADC_P 216
#define SRST_NPU_TSADC 217
#define SRST_NPU_TSADCPHY 218
#define SRST_CIFLITE_A 220
#define SRST_CIFLITE_H 221
#define SRST_CIFLITE_D 222
#define SRST_CIFLITE_RX_P 223
/* cru_softrst_con14 */
#define SRST_TOPNIU_P 224
#define SRST_TOPCRU_P 225
#define SRST_TOPGRF_P 226
#define SRST_CPUEMADET_P 227
#define SRST_CSIPHY0_P 228
#define SRST_CSIPHY1_P 229
#define SRST_DSIPHY_P 230
#define SRST_CPU_TSADC_P 232
#define SRST_CPU_TSADC 233
#define SRST_CPU_TSADCPHY 234
#define SRST_CPUPVTM_P 235
#define SRST_CPUPVTM 236
#endif

356
include/dt-bindings/clock/rv1108-cru.h
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@@ -1,356 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2017 Rockchip Electronics Co. Ltd.
* Author: Shawn Lin <shawn.lin@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
/* pll id */
#define PLL_APLL 0
#define PLL_DPLL 1
#define PLL_GPLL 2
#define ARMCLK 3
/* sclk gates (special clocks) */
#define SCLK_SPI0 65
#define SCLK_NANDC 67
#define SCLK_SDMMC 68
#define SCLK_SDIO 69
#define SCLK_EMMC 71
#define SCLK_UART0 72
#define SCLK_UART1 73
#define SCLK_UART2 74
#define SCLK_I2S0 75
#define SCLK_I2S1 76
#define SCLK_I2S2 77
#define SCLK_TIMER0 78
#define SCLK_TIMER1 79
#define SCLK_SFC 80
#define SCLK_SDMMC_DRV 81
#define SCLK_SDIO_DRV 82
#define SCLK_EMMC_DRV 83
#define SCLK_SDMMC_SAMPLE 84
#define SCLK_SDIO_SAMPLE 85
#define SCLK_EMMC_SAMPLE 86
#define SCLK_VENC_CORE 87
#define SCLK_HEVC_CORE 88
#define SCLK_HEVC_CABAC 89
#define SCLK_PWM0_PMU 90
#define SCLK_I2C0_PMU 91
#define SCLK_WIFI 92
#define SCLK_CIFOUT 93
#define SCLK_MIPI_CSI_OUT 94
#define SCLK_CIF0 95
#define SCLK_CIF1 96
#define SCLK_CIF2 97
#define SCLK_CIF3 98
#define SCLK_DSP 99
#define SCLK_DSP_IOP 100
#define SCLK_DSP_EPP 101
#define SCLK_DSP_EDP 102
#define SCLK_DSP_EDAP 103
#define SCLK_CVBS_HOST 104
#define SCLK_HDMI_SFR 105
#define SCLK_HDMI_CEC 106
#define SCLK_CRYPTO 107
#define SCLK_SPI 108
#define SCLK_SARADC 109
#define SCLK_TSADC 110
#define SCLK_MAC_PRE 111
#define SCLK_MAC 112
#define SCLK_MAC_RX 113
#define SCLK_MAC_REF 114
#define SCLK_MAC_REFOUT 115
#define SCLK_DSP_PFM 116
#define SCLK_RGA 117
#define SCLK_I2C1 118
#define SCLK_I2C2 119
#define SCLK_I2C3 120
#define SCLK_PWM 121
#define SCLK_ISP 122
#define SCLK_USBPHY 123
#define SCLK_I2S0_SRC 124
#define SCLK_I2S1_SRC 125
#define SCLK_I2S2_SRC 126
#define SCLK_UART0_SRC 127
#define SCLK_UART1_SRC 128
#define SCLK_UART2_SRC 129
#define SCLK_MAC_TX 130
#define SCLK_MACREF 131
#define SCLK_MACREF_OUT 132
#define DCLK_VOP_SRC 185
#define DCLK_HDMIPHY 186
#define DCLK_VOP 187
/* aclk gates */
#define ACLK_DMAC 192
#define ACLK_PRE 193
#define ACLK_CORE 194
#define ACLK_ENMCORE 195
#define ACLK_RKVENC 196
#define ACLK_RKVDEC 197
#define ACLK_VPU 198
#define ACLK_CIF0 199
#define ACLK_VIO0 200
#define ACLK_VIO1 201
#define ACLK_VOP 202
#define ACLK_IEP 203
#define ACLK_RGA 204
#define ACLK_ISP 205
#define ACLK_CIF1 206
#define ACLK_CIF2 207
#define ACLK_CIF3 208
#define ACLK_PERI 209
#define ACLK_GMAC 210
/* pclk gates */
#define PCLK_GPIO1 256
#define PCLK_GPIO2 257
#define PCLK_GPIO3 258
#define PCLK_GRF 259
#define PCLK_I2C1 260
#define PCLK_I2C2 261
#define PCLK_I2C3 262
#define PCLK_SPI 263
#define PCLK_SFC 264
#define PCLK_UART0 265
#define PCLK_UART1 266
#define PCLK_UART2 267
#define PCLK_TSADC 268
#define PCLK_PWM 269
#define PCLK_TIMER 270
#define PCLK_PERI 271
#define PCLK_GPIO0_PMU 272
#define PCLK_I2C0_PMU 273
#define PCLK_PWM0_PMU 274
#define PCLK_ISP 275
#define PCLK_VIO 276
#define PCLK_MIPI_DSI 277
#define PCLK_HDMI_CTRL 278
#define PCLK_SARADC 279
#define PCLK_DSP_CFG 280
#define PCLK_BUS 281
#define PCLK_EFUSE0 282
#define PCLK_EFUSE1 283
#define PCLK_WDT 284
#define PCLK_GMAC 285
/* hclk gates */
#define HCLK_I2S0_8CH 320
#define HCLK_I2S1_2CH 321
#define HCLK_I2S2_2CH 322
#define HCLK_NANDC 323
#define HCLK_SDMMC 324
#define HCLK_SDIO 325
#define HCLK_EMMC 326
#define HCLK_PERI 327
#define HCLK_SFC 328
#define HCLK_RKVENC 329
#define HCLK_RKVDEC 330
#define HCLK_CIF0 331
#define HCLK_VIO 332
#define HCLK_VOP 333
#define HCLK_IEP 334
#define HCLK_RGA 335
#define HCLK_ISP 336
#define HCLK_CRYPTO_MST 337
#define HCLK_CRYPTO_SLV 338
#define HCLK_HOST0 339
#define HCLK_OTG 340
#define HCLK_CIF1 341
#define HCLK_CIF2 342
#define HCLK_CIF3 343
#define HCLK_BUS 344
#define HCLK_VPU 345
#define CLK_NR_CLKS (HCLK_VPU + 1)
/* reset id */
#define SRST_CORE_PO_AD 0
#define SRST_CORE_AD 1
#define SRST_L2_AD 2
#define SRST_CPU_NIU_AD 3
#define SRST_CORE_PO 4
#define SRST_CORE 5
#define SRST_L2 6
#define SRST_CORE_DBG 8
#define PRST_DBG 9
#define RST_DAP 10
#define PRST_DBG_NIU 11
#define ARST_STRC_SYS_AD 15
#define SRST_DDRPHY_CLKDIV 16
#define SRST_DDRPHY 17
#define PRST_DDRPHY 18
#define PRST_HDMIPHY 19
#define PRST_VDACPHY 20
#define PRST_VADCPHY 21
#define PRST_MIPI_CSI_PHY 22
#define PRST_MIPI_DSI_PHY 23
#define PRST_ACODEC 24
#define ARST_BUS_NIU 25
#define PRST_TOP_NIU 26
#define ARST_INTMEM 27
#define HRST_ROM 28
#define ARST_DMAC 29
#define SRST_MSCH_NIU 30
#define PRST_MSCH_NIU 31
#define PRST_DDRUPCTL 32
#define NRST_DDRUPCTL 33
#define PRST_DDRMON 34
#define HRST_I2S0_8CH 35
#define MRST_I2S0_8CH 36
#define HRST_I2S1_2CH 37
#define MRST_IS21_2CH 38
#define HRST_I2S2_2CH 39
#define MRST_I2S2_2CH 40
#define HRST_CRYPTO 41
#define SRST_CRYPTO 42
#define PRST_SPI 43
#define SRST_SPI 44
#define PRST_UART0 45
#define PRST_UART1 46
#define PRST_UART2 47
#define SRST_UART0 48
#define SRST_UART1 49
#define SRST_UART2 50
#define PRST_I2C1 51
#define PRST_I2C2 52
#define PRST_I2C3 53
#define SRST_I2C1 54
#define SRST_I2C2 55
#define SRST_I2C3 56
#define PRST_PWM1 58
#define SRST_PWM1 60
#define PRST_WDT 61
#define PRST_GPIO1 62
#define PRST_GPIO2 63
#define PRST_GPIO3 64
#define PRST_GRF 65
#define PRST_EFUSE 66
#define PRST_EFUSE512 67
#define PRST_TIMER0 68
#define SRST_TIMER0 69
#define SRST_TIMER1 70
#define PRST_TSADC 71
#define SRST_TSADC 72
#define PRST_SARADC 73
#define SRST_SARADC 74
#define HRST_SYSBUS 75
#define PRST_USBGRF 76
#define ARST_PERIPH_NIU 80
#define HRST_PERIPH_NIU 81
#define PRST_PERIPH_NIU 82
#define HRST_PERIPH 83
#define HRST_SDMMC 84
#define HRST_SDIO 85
#define HRST_EMMC 86
#define HRST_NANDC 87
#define NRST_NANDC 88
#define HRST_SFC 89
#define SRST_SFC 90
#define ARST_GMAC 91
#define HRST_OTG 92
#define SRST_OTG 93
#define SRST_OTG_ADP 94
#define HRST_HOST0 95
#define HRST_HOST0_AUX 96
#define HRST_HOST0_ARB 97
#define SRST_HOST0_EHCIPHY 98
#define SRST_HOST0_UTMI 99
#define SRST_USBPOR 100
#define SRST_UTMI0 101
#define SRST_UTMI1 102
#define ARST_VIO0_NIU 102
#define ARST_VIO1_NIU 103
#define HRST_VIO_NIU 104
#define PRST_VIO_NIU 105
#define ARST_VOP 106
#define HRST_VOP 107
#define DRST_VOP 108
#define ARST_IEP 109
#define HRST_IEP 110
#define ARST_RGA 111
#define HRST_RGA 112
#define SRST_RGA 113
#define PRST_CVBS 114
#define PRST_HDMI 115
#define SRST_HDMI 116
#define PRST_MIPI_DSI 117
#define ARST_ISP_NIU 118
#define HRST_ISP_NIU 119
#define HRST_ISP 120
#define SRST_ISP 121
#define ARST_VIP0 122
#define HRST_VIP0 123
#define PRST_VIP0 124
#define ARST_VIP1 125
#define HRST_VIP1 126
#define PRST_VIP1 127
#define ARST_VIP2 128
#define HRST_VIP2 129
#define PRST_VIP2 120
#define ARST_VIP3 121
#define HRST_VIP3 122
#define PRST_VIP4 123
#define PRST_CIF1TO4 124
#define SRST_CVBS_CLK 125
#define HRST_CVBS 126
#define ARST_VPU_NIU 140
#define HRST_VPU_NIU 141
#define ARST_VPU 142
#define HRST_VPU 143
#define ARST_RKVDEC_NIU 144
#define HRST_RKVDEC_NIU 145
#define ARST_RKVDEC 146
#define HRST_RKVDEC 147
#define SRST_RKVDEC_CABAC 148
#define SRST_RKVDEC_CORE 149
#define ARST_RKVENC_NIU 150
#define HRST_RKVENC_NIU 151
#define ARST_RKVENC 152
#define HRST_RKVENC 153
#define SRST_RKVENC_CORE 154
#define SRST_DSP_CORE 156
#define SRST_DSP_SYS 157
#define SRST_DSP_GLOBAL 158
#define SRST_DSP_OECM 159
#define PRST_DSP_IOP_NIU 160
#define ARST_DSP_EPP_NIU 161
#define ARST_DSP_EDP_NIU 162
#define PRST_DSP_DBG_NIU 163
#define PRST_DSP_CFG_NIU 164
#define PRST_DSP_GRF 165
#define PRST_DSP_MAILBOX 166
#define PRST_DSP_INTC 167
#define PRST_DSP_PFM_MON 169
#define SRST_DSP_PFM_MON 170
#define ARST_DSP_EDAP_NIU 171
#define SRST_PMU 172
#define SRST_PMU_I2C0 173
#define PRST_PMU_I2C0 174
#define PRST_PMU_GPIO0 175
#define PRST_PMU_INTMEM 176
#define PRST_PMU_PWM0 177
#define SRST_PMU_PWM0 178
#define PRST_PMU_GRF 179
#define SRST_PMU_NIU 180
#define SRST_PMU_PVTM 181
#define ARST_DSP_EDP_PERF 184
#define ARST_DSP_EPP_PERF 185
#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */

35
include/dt-bindings/power/rockchip,rv1126-power.h
View File

@@ -1,35 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__
#define __DT_BINDINGS_POWER_RV1126_POWER_H__
/* VD_CORE */
#define RV1126_PD_CPU_0 0
#define RV1126_PD_CPU_1 1
#define RV1126_PD_CPU_2 2
#define RV1126_PD_CPU_3 3
#define RV1126_PD_CORE_ALIVE 4
/* VD_PMU */
#define RV1126_PD_PMU 5
#define RV1126_PD_PMU_ALIVE 6
/* VD_NPU */
#define RV1126_PD_NPU 7
/* VD_VEPU */
#define RV1126_PD_VEPU 8
/* VD_LOGIC */
#define RV1126_PD_VI 9
#define RV1126_PD_VO 10
#define RV1126_PD_ISPP 11
#define RV1126_PD_VDPU 12
#define RV1126_PD_CRYPTO 13
#define RV1126_PD_DDR 14
#define RV1126_PD_NVM 15
#define RV1126_PD_SDIO 16
#define RV1126_PD_USB 17
#define RV1126_PD_LOGIC_ALIVE 18
#endif

17
include/dt-bindings/soc/samsung,exynos-usi.h
View File

@@ -1,17 +0,0 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2021 Linaro Ltd.
* Author: Sam Protsenko <semen.protsenko@linaro.org>
*
* Device Tree bindings for Samsung Exynos USI (Universal Serial Interface).
*/
#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H
#define USI_V2_NONE 0
#define USI_V2_UART 1
#define USI_V2_SPI 2
#define USI_V2_I2C 3
#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */

77
include/tpm-v2.h
View File

@@ -386,7 +386,54 @@ enum tpm2_algorithms {
TPM2_ALG_SM3_256 = 0x12,
};
extern const enum tpm2_algorithms tpm2_supported_algorithms[4];
/**
* struct digest_info - details of supported digests
*
* @hash_name: hash name
* @hash_alg: hash algorithm id
* @hash_mask: hash registry mask
* @hash_len: hash digest length
*/
struct digest_info {
const char *hash_name;
u16 hash_alg;
u32 hash_mask;
u16 hash_len;
};
/* Algorithm Registry */
#define TCG2_BOOT_HASH_ALG_SHA1 0x00000001
#define TCG2_BOOT_HASH_ALG_SHA256 0x00000002
#define TCG2_BOOT_HASH_ALG_SHA384 0x00000004
#define TCG2_BOOT_HASH_ALG_SHA512 0x00000008
#define TCG2_BOOT_HASH_ALG_SM3_256 0x00000010
static const struct digest_info hash_algo_list[] = {
{
"sha1",
TPM2_ALG_SHA1,
TCG2_BOOT_HASH_ALG_SHA1,
TPM2_SHA1_DIGEST_SIZE,
},
{
"sha256",
TPM2_ALG_SHA256,
TCG2_BOOT_HASH_ALG_SHA256,
TPM2_SHA256_DIGEST_SIZE,
},
{
"sha384",
TPM2_ALG_SHA384,
TCG2_BOOT_HASH_ALG_SHA384,
TPM2_SHA384_DIGEST_SIZE,
},
{
"sha512",
TPM2_ALG_SHA512,
TCG2_BOOT_HASH_ALG_SHA512,
TPM2_SHA512_DIGEST_SIZE,
},
};
static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a)
{
@@ -404,8 +451,6 @@ static inline u16 tpm2_algorithm_to_len(enum tpm2_algorithms a)
}
}
#define tpm2_algorithm_to_mask(a) (1 << (a))
/* NV index attributes */
enum tpm_index_attrs {
TPMA_NV_PPWRITE = 1UL << 0,
@@ -965,4 +1010,30 @@ u32 tpm2_enable_nvcommits(struct udevice *dev, uint vendor_cmd,
*/
u32 tpm2_auto_start(struct udevice *dev);
/**
* tpm2_name_to_algorithm() - Return an algorithm id given a supported
* algorithm name
*
* @name: algorithm name
* Return: enum tpm2_algorithms or -EINVAL
*/
enum tpm2_algorithms tpm2_name_to_algorithm(const char *name);
/**
* tpm2_algorithm_name() - Return an algorithm name string for a
* supported algorithm id
*
* @algorithm_id: algorithm defined in enum tpm2_algorithms
* Return: algorithm name string or ""
*/
const char *tpm2_algorithm_name(enum tpm2_algorithms);
/**
* tpm2_algorithm_to_mask() - Get a TCG hash mask for algorithm
*
* @hash_alg: TCG defined algorithm
* Return: TCG hashing algorithm bitmaps (or 0 if algo not supported)
*/
u32 tpm2_algorithm_to_mask(enum tpm2_algorithms);
#endif /* __TPM_V2_H */