From ebe2e0c309470249ffb09480d39c2dea9e64871c Mon Sep 17 00:00:00 2001
From: Patrick Wildt <patrick@blueri.se>
Date: Mon, 6 Feb 2023 00:48:26 +0100
Subject: [PATCH 01/24] board: mntre: imx8mq: Add MNT Reform 2 board support

The MNT Reform 2 is a modular DIY laptop.  In its initial version it
is based on the BoundaryDevices i.MX8MQ SoM.  Some parts have been
lifted from BoundaryDevices official U-Boot downstream project.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi   |   11 +
 arch/arm/mach-imx/imx8m/Kconfig               |    7 +
 board/mntre/imx8mq_reform2/Kconfig            |   15 +
 board/mntre/imx8mq_reform2/MAINTAINERS        |    7 +
 board/mntre/imx8mq_reform2/Makefile           |   12 +
 board/mntre/imx8mq_reform2/imx8mq_reform2.c   |  171 +++
 board/mntre/imx8mq_reform2/lpddr4_timing.c    | 1014 +++++++++++++++++
 .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h  |   95 ++
 board/mntre/imx8mq_reform2/spl.c              |  260 +++++
 configs/imx8mq_reform2_defconfig              |  107 ++
 include/configs/imx8mq_reform2.h              |   67 ++
 11 files changed, 1766 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
 create mode 100644 board/mntre/imx8mq_reform2/Kconfig
 create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS
 create mode 100644 board/mntre/imx8mq_reform2/Makefile
 create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c
 create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
 create mode 100644 board/mntre/imx8mq_reform2/spl.c
 create mode 100644 configs/imx8mq_reform2_defconfig
 create mode 100644 include/configs/imx8mq_reform2.h

diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
new file mode 100644
index 00000000000..46a4dfe4e8a
--- /dev/null
+++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include "imx8mq-u-boot.dtsi"
+
+&pinctrl_uart1 {
+	bootph-pre-ram;
+};
+
+&uart1 { /* console */
+	bootph-pre-ram;
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index dc51f971d45..7639439bdc9 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -60,6 +60,12 @@ config TARGET_IMX8MQ_PHANBELL
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MQ_REFORM2
+	bool "imx8mq_reform2"
+	select BINMAN
+	select IMX8MQ
+	select IMX8M_LPDDR4
+
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
 	bool "Data Modul eDM SBC i.MX8M Mini"
 	select BINMAN
@@ -362,6 +368,7 @@ source "board/kontron/pitx_imx8m/Kconfig"
 source "board/kontron/sl-mx8mm/Kconfig"
 source "board/menlo/mx8menlo/Kconfig"
 source "board/msc/sm2s_imx8mp/Kconfig"
+source "board/mntre/imx8mq_reform2/Kconfig"
 source "board/phytec/phycore_imx8mm/Kconfig"
 source "board/phytec/phycore_imx8mp/Kconfig"
 source "board/purism/librem5/Kconfig"
diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig
new file mode 100644
index 00000000000..f9260cb7f53
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8MQ_REFORM2
+
+config SYS_BOARD
+	default "imx8mq_reform2"
+
+config SYS_VENDOR
+	default "mntre"
+
+config SYS_CONFIG_NAME
+	default "imx8mq_reform2"
+
+config IMX_CONFIG
+	default "arch/arm/mach-imx/imx8m/imximage.cfg"
+
+endif
diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS
new file mode 100644
index 00000000000..946f287ecf8
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/MAINTAINERS
@@ -0,0 +1,7 @@
+REFORM2 IMX8MQ BOARD
+M:	Lukas F. Hartmann <lukas@mntre.com>
+M:	Patrick Wildt <patrick@blueri.se>
+S:	Maintained
+F:	board/mntre/imx8mq_reform2/
+F:	include/configs/imx8mq_reform2.h
+F:	configs/imx8mq_reform2_defconfig
diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile
new file mode 100644
index 00000000000..2efd56bb4ad
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mq_reform2.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
new file mode 100644
index 00000000000..be5c5060a2a
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright (C) 2018, Boundary Devices <info@boundarydevices.com>
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+	set_wdog_reset(wdog);
+
+	return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+
+#define PHY_RESET	IMX_GPIO_NR(1, 9)
+#define PHY_RX_CTL	IMX_GPIO_NR(1, 24)
+#define PHY_RXC		IMX_GPIO_NR(1, 25)
+#define PHY_RD0		IMX_GPIO_NR(1, 26)
+#define PHY_RD1		IMX_GPIO_NR(1, 27)
+#define PHY_RD2		IMX_GPIO_NR(1, 28)
+#define PHY_RD3		IMX_GPIO_NR(1, 29)
+
+#define STRAP_AR8035	(0x28) // 0010 1000
+
+static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6),
+	IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1),
+	IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91),
+	/* 1.8V(1)/1.5V select(0) */
+	IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1),
+};
+
+static const iomux_v3_cfg_t enet_ar8035_pads[] = {
+	IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91),
+	IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91),
+};
+
+static void setup_fec(void)
+{
+	struct iomuxc_gpr_base_regs *gpr =
+		(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+	/* Pull PHY into reset */
+	gpio_request(PHY_RESET, "fec_rst");
+	gpio_direction_output(PHY_RESET, 0);
+
+	/* Configure ethernet pins value as GPIOs */
+	gpio_request(PHY_RD0, "fec_rd0");
+	gpio_direction_output(PHY_RD0, 0);
+	gpio_request(PHY_RD1, "fec_rd1");
+	gpio_direction_output(PHY_RD1, 0);
+	gpio_request(PHY_RD2, "fec_rd2");
+	gpio_direction_output(PHY_RD2, 0);
+	gpio_request(PHY_RD3, "fec_rd3");
+	gpio_direction_output(PHY_RD3, 1);
+	gpio_request(PHY_RX_CTL, "fec_rx_ctl");
+	gpio_direction_output(PHY_RX_CTL, 0);
+	gpio_request(PHY_RXC, "fec_rxc");
+	gpio_direction_output(PHY_RXC, 1);
+
+	/* Set ethernet pins to GPIO to bootstrap PHY */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads,
+	    ARRAY_SIZE(enet_ar8035_gpio_pads));
+
+	/* Use 125M anatop REF_CLK1 for ENET1, not from external */
+	clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+	/* Enable RGMII TX clk output */
+	setbits_le32(&gpr->gpr[1], BIT(22));
+	set_clk_enet(ENET_125MHZ);
+
+	/* 1 ms minimum reset pulse for ar8035 */
+	mdelay(1);
+
+	/* Release PHY from reset */
+	gpio_set_value(PHY_RESET, 1);
+
+	/* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */
+	udelay(12);
+
+	/* Change ethernet pins back to normal function */
+	imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads,
+	    ARRAY_SIZE(enet_ar8035_pads));
+}
+#endif
+
+#define USB1_HUB_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define USB1_HUB_RESET		IMX_GPIO_NR(1, 14)
+
+static void setup_usb(void)
+{
+	imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 |
+	    MUX_PAD_CTRL(USB1_HUB_PAD_CTRL));
+	gpio_request(USB1_HUB_RESET, "usb1_rst");
+	gpio_direction_output(USB1_HUB_RESET, 0);
+	mdelay(10);
+	gpio_set_value(USB1_HUB_RESET, 1);
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
+	setup_usb();
+
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_DWC3)
+	init_usb_clk();
+#endif
+
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "Reform2");
+	env_set("board_rev", "iMX8MQ");
+#endif
+
+	return 0;
+}
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c
new file mode 100644
index 00000000000..e5303db0f80
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c
@@ -0,0 +1,1014 @@
+/*
+ * Copyright 2019 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot version:
+ * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga
+ */
+#include "lpddr4_timing_ch2.h"
+
+static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/** Initialize DDRC registers **/
+	{ DDRC_DBG1(0), 1 },
+	/* selfref_en=1, SDRAM enter self-refresh state */
+	{ DDRC_PWRCTL(0), 1 },
+	{ DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) },
+	{ DDRC_MSTR2(0), 0 },
+	{ DDRC_DERATEEN(0), 0x0203 },
+	{ DDRC_DERATEINT(0), 0x0003e800 },
+	{ DDRC_RFSHTMG(0), 0x006100e0 },
+	{ DDRC_INIT0(0), 0xc003061c },
+	{ DDRC_INIT1(0), 0x009e0000 },
+	{ DDRC_INIT3(0), 0x00d4002d },
+	{ DDRC_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0016004a },
+	{ DDRC_DRAMTMG0(0), 0x1a201b22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00c0c000 },
+	{ DDRC_DRAMTMG4(0), 0x0f04080f },
+	{ DDRC_DRAMTMG5(0), 0x02040c0c },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x0401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0c100002 },
+	{ DDRC_DRAMTMG14(0), 0xe6 },
+	{ DDRC_DRAMTMG17(0), 0x00a00050 },
+	{ DDRC_ZQCTL0(0), 0xc3200018 },
+	{ DDRC_ZQCTL1(0), 0x028061a8 },
+	{ DDRC_ZQCTL2(0), 0 },
+	{ DDRC_DFITMG0(0), 0x0497820a },
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xe0400018 },
+	{ DDRC_DFIUPD1(0), 0x00df00e4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x11 },
+	{ DDRC_DFITMG2(0), 0x170a },
+	{ DDRC_DBICTL(0), 1 },
+	{ DDRC_DFIPHYMSTR(0), 1 },
+	{ DDRC_RANKCTL(0), 0x0639 },
+	{ DDRC_DRAMTMG2(0), 0x070e1617 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 },
+	{ DDRC_ADDRMAP3(0), 0 },
+	/* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */
+	{ DDRC_ADDRMAP4(0), 0x1f1f },
+	/* bank interleave */
+	/* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	/* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	/* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */
+	{ DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 },
+	{ DDRC_ADDRMAP7(0), 0x0f0f },
+	{ DDRC_FREQ1_DERATEEN(0), 1 },
+	{ DDRC_FREQ1_DERATEINT(0), 0xd0c0 },
+	{ DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x0014002f },
+	{ DDRC_FREQ1_INIT3(0), 0x00940009 },
+	{ DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0016004a },
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x0003040b },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x04040204 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x02030303 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0301 },
+	{ DDRC_FREQ1_DRAMTMG12(0), 0x00020300 },
+	{ DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x31 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x00220011 },
+	{ DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03858202 },
+	{ DDRC_FREQ1_DFITMG1(0), 0x00080303 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x0502 },
+	{ DDRC_ODTMAP(0), 0 },
+	{ DDRC_SCHED(0), 0x29001505 },
+	{ DDRC_SCHED1(0), 0x2c },
+	{ DDRC_PERFHPR1(0), 0x5900575b },
+	{ DDRC_PERFLPR1(0), 0x90000096 },
+	{ DDRC_PERFWR1(0), 0x1000012c },
+	{ DDRC_DBG0(0), 0x16 },
+	{ DDRC_DBG1(0), 0 },
+	{ DDRC_DBGCMD(0), 0 },
+	{ DDRC_SWCTL(0), 1 },
+	{ DDRC_POISONCFG(0), 0x11 },
+	{ DDRC_PCCFG(0), 0x0111 },
+	{ DDRC_PCFGR_0(0), 0x10f3 },
+	{ DDRC_PCFGW_0(0), 0x72ff },
+	{ DDRC_PCTRL_0(0), 1 },
+	{ DDRC_PCFGQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGQOS1_0(0), 0x0062ffff },
+	{ DDRC_PCFGWQOS0_0(0), 0x0e00 },
+	{ DDRC_PCFGWQOS1_0(0), 0xffff },
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x100a0, 0 },
+	{ 0x100a1, 1 },
+	{ 0x100a2, 2 },
+	{ 0x100a3, 3 },
+	{ 0x100a4, 4 },
+	{ 0x100a5, 5 },
+	{ 0x100a6, 6 },
+	{ 0x100a7, 7 },
+	{ 0x110a0, 0 },
+	{ 0x110a1, 1 },
+	{ 0x110a2, 2 },
+	{ 0x110a3, 3 },
+	{ 0x110a4, 4 },
+	{ 0x110a5, 5 },
+	{ 0x110a6, 6 },
+	{ 0x110a7, 7 },
+	{ 0x120a0, 0 },
+	{ 0x120a1, 1 },
+	{ 0x120a2, 2 },
+	{ 0x120a3, 3 },
+	{ 0x120a4, 4 },
+	{ 0x120a5, 5 },
+	{ 0x120a6, 6 },
+	{ 0x120a7, 7 },
+	{ 0x130a0, 0 },
+	{ 0x130a1, 1 },
+	{ 0x130a2, 2 },
+	{ 0x130a3, 3 },
+	{ 0x130a4, 4 },
+	{ 0x130a5, 5 },
+	{ 0x130a6, 6 },
+	{ 0x130a7, 7 },
+	{ 0x1005f, 0x01ff },
+	{ 0x1015f, 0x01ff },
+	{ 0x1105f, 0x01ff },
+	{ 0x1115f, 0x01ff },
+	{ 0x1205f, 0x01ff },
+	{ 0x1215f, 0x01ff },
+	{ 0x1305f, 0x01ff },
+	{ 0x1315f, 0x01ff },
+	{ 0x11005f, 0x01ff },
+	{ 0x11015f, 0x01ff },
+	{ 0x11105f, 0x01ff },
+	{ 0x11115f, 0x01ff },
+	{ 0x11205f, 0x01ff },
+	{ 0x11215f, 0x01ff },
+	{ 0x11305f, 0x01ff },
+	{ 0x11315f, 0x01ff },
+	{ 0x0055, 0x01ff },
+	{ 0x1055, 0x01ff },
+	{ 0x2055, 0x01ff },
+	{ 0x3055, 0x01ff },
+	{ 0x4055, 0x01ff },
+	{ 0x5055, 0x01ff },
+	{ 0x6055, 0x01ff },
+	{ 0x7055, 0x01ff },
+	{ 0x8055, 0x01ff },
+	{ 0x9055, 0x01ff },
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 7 },
+	{ 0x2002e, 2 },
+	{ 0x12002e, 1 },
+	{ 0x90204, 0 },
+	{ 0x190204, 0 },
+	{ 0x20024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x120024, 0x01ab },
+	{ 0x2003a, 0 },
+	{ 0x20056, 3 },
+	{ 0x120056, 3 },
+	{ 0x1004d, 0x0e00 },
+	{ 0x1014d, 0x0e00 },
+	{ 0x1104d, 0x0e00 },
+	{ 0x1114d, 0x0e00 },
+	{ 0x1204d, 0x0e00 },
+	{ 0x1214d, 0x0e00 },
+	{ 0x1304d, 0x0e00 },
+	{ 0x1314d, 0x0e00 },
+	{ 0x11004d, 0x0e00 },
+	{ 0x11014d, 0x0e00 },
+	{ 0x11104d, 0x0e00 },
+	{ 0x11114d, 0x0e00 },
+	{ 0x11204d, 0x0e00 },
+	{ 0x11214d, 0x0e00 },
+	{ 0x11304d, 0x0e00 },
+	{ 0x11314d, 0x0e00 },
+	{ 0x10049, 0x0eba },
+	{ 0x10149, 0x0eba },
+	{ 0x11049, 0x0eba },
+	{ 0x11149, 0x0eba },
+	{ 0x12049, 0x0eba },
+	{ 0x12149, 0x0eba },
+	{ 0x13049, 0x0eba },
+	{ 0x13149, 0x0eba },
+	{ 0x110049, 0x0eba },
+	{ 0x110149, 0x0eba },
+	{ 0x111049, 0x0eba },
+	{ 0x111149, 0x0eba },
+	{ 0x112049, 0x0eba },
+	{ 0x112149, 0x0eba },
+	{ 0x113049, 0x0eba },
+	{ 0x113149, 0x0eba },
+	{ 0x0043, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+	{ 0x20018, 3 },
+	{ 0x20075, 4 },
+	{ 0x20050, 0 },
+	{ 0x20008, 0x0320 },
+	{ 0x120008, 0xa7 },
+	{ 0x20088, 9 },
+	{ 0x200b2, 0xdc },
+	{ 0x10043, 0x05a1 },
+	{ 0x10143, 0x05a1 },
+	{ 0x11043, 0x05a1 },
+	{ 0x11143, 0x05a1 },
+	{ 0x12043, 0x05a1 },
+	{ 0x12143, 0x05a1 },
+	{ 0x13043, 0x05a1 },
+	{ 0x13143, 0x05a1 },
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x05a1 },
+	{ 0x110143, 0x05a1 },
+	{ 0x111043, 0x05a1 },
+	{ 0x111143, 0x05a1 },
+	{ 0x112043, 0x05a1 },
+	{ 0x112143, 0x05a1 },
+	{ 0x113043, 0x05a1 },
+	{ 0x113143, 0x05a1 },
+	{ 0x200fa, 1 },
+	{ 0x1200fa, 1 },
+	{ 0x20019, 1 },
+	{ 0x120019, 1 },
+	{ 0x200f0, 0 },
+	{ 0x200f1, 0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5555 },
+	{ 0x200f5, 0 },
+	{ 0x200f6, 0 },
+	{ 0x200f7, 0xf000 },
+	{ 0x20025, 0 },
+	{ 0x2002d, 0 },
+	{ 0x12002d, 0 },
+	{ 0x200c7, 0x80 },
+	{ 0x1200c7, 0x80 },
+	{ 0x200ca, 0x0106 },
+	{ 0x1200ca, 0x0106 },
+	{ 0x20110, 2 },
+	{ 0x20111, 3 },
+	{ 0x20112, 4 },
+	{ 0x20113, 5 },
+	{ 0x20114, 0 },
+	{ 0x20115, 1 },
+};
+
+/* P0 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x131f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P1 message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54002, 1 },
+	{ 0x54003, 0x029c },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x121f },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x0994 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x0994 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0x9400 },
+	{ 0x54033, 0x3109 },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0x9400 },
+	{ 0x54039, 0x3109 },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+
+/* P0 2D message block parameter for training firmware */
+static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0 },
+	{ 0x54003, 0x0c80 },
+	{ 0x54004, 2 },
+	{ 0x54005, 0x2228 },
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54008, 0x61 },
+	{ 0x54009, LPDDR4_HDT_CTL_3200_1D },
+	{ 0x5400b, 2 },
+	{ 0x5400d, 0x0100 },
+	{ 0x5400f, 0x0100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, 0x31 },
+	{ 0x5401b, 0x4a66 },
+	{ 0x5401c, 0x4a08 },
+	{ 0x5401e, 0x16 },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, 0x31 },
+	{ 0x54021, 0x4a66 },
+	{ 0x54022, 0x4a08 },
+	{ 0x54024, 0x16 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, CH2_LPDDR4_CS },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, 0x312d },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x084a },
+	{ 0x54036, 0x4a },
+	{ 0x54037, 0x1600 },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, 0x312d },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x084a },
+	{ 0x5403c, 0x4a },
+	{ 0x5403d, 0x1600 },
+	{ 0xd0000, 1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x0400 },
+	{ 0x90002, 0x010e },
+	{ 0x90003, 0 },
+	{ 0x90004, 0 },
+	{ 0x90005, 8 },
+	{ 0x90029, 0x0b },
+	{ 0x9002a, 0x0480 },
+	{ 0x9002b, 0x0109 },
+	{ 0x9002c, 8 },
+	{ 0x9002d, 0x0448 },
+	{ 0x9002e, 0x0139 },
+	{ 0x9002f, 8 },
+	{ 0x90030, 0x0478 },
+	{ 0x90031, 0x0109 },
+	{ 0x90032, 0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x0109 },
+	{ 0x90035, 2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x0139 },
+	{ 0x90038, 0x0f },
+	{ 0x90039, 0x07c0 },
+	{ 0x9003a, 0x0139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x0630 },
+	{ 0x9003d, 0x0159 },
+	{ 0x9003e, 0x014f },
+	{ 0x9003f, 0x0630 },
+	{ 0x90040, 0x0159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x0630 },
+	{ 0x90043, 0x0149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x0630 },
+	{ 0x90046, 0x0179 },
+	{ 0x90047, 8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x0109 },
+	{ 0x9004a, 0 },
+	{ 0x9004b, 0x07c8 },
+	{ 0x9004c, 0x0109 },
+	{ 0x9004d, 0 },
+	{ 0x9004e, 1 },
+	{ 0x9004f, 8 },
+	{ 0x90050, 0 },
+	{ 0x90051, 0x045a },
+	{ 0x90052, 9 },
+	{ 0x90053, 0 },
+	{ 0x90054, 0x0448 },
+	{ 0x90055, 0x0109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x0630 },
+	{ 0x90058, 0x0179 },
+	{ 0x90059, 1 },
+	{ 0x9005a, 0x0618 },
+	{ 0x9005b, 0x0109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x0630 },
+	{ 0x9005e, 0x0149 },
+	{ 0x9005f, 8 },
+	{ 0x90060, 4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x0630 },
+	{ 0x90064, 0x0149 },
+	{ 0x90065, 0 },
+	{ 0x90066, 4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x0630 },
+	{ 0x9006a, 0x0149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0 },
+	{ 0x9006f, 4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x0549 },
+	{ 0x90072, 0x0630 },
+	{ 0x90073, 0x0159 },
+	{ 0x90074, 0x0d49 },
+	{ 0x90075, 0x0630 },
+	{ 0x90076, 0x0159 },
+	{ 0x90077, 0x094a },
+	{ 0x90078, 0x0630 },
+	{ 0x90079, 0x0159 },
+	{ 0x9007a, 0x0441 },
+	{ 0x9007b, 0x0630 },
+	{ 0x9007c, 0x0149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x0630 },
+	{ 0x9007f, 0x0149 },
+	{ 0x90080, 1 },
+	{ 0x90081, 0x0630 },
+	{ 0x90082, 0x0149 },
+	{ 0x90083, 0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x0109 },
+	{ 0x90086, 0x0a },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x0109 },
+	{ 0x90089, 9 },
+	{ 0x9008a, 0x03c0 },
+	{ 0x9008b, 0x0149 },
+	{ 0x9008c, 9 },
+	{ 0x9008d, 0x03c0 },
+	{ 0x9008e, 0x0159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x0109 },
+	{ 0x90092, 0 },
+	{ 0x90093, 0x03c0 },
+	{ 0x90094, 0x0109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0x0a },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x0109 },
+	{ 0x9009e, 2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x0109 },
+	{ 0x900a1, 5 },
+	{ 0x900a2, 0x07c0 },
+	{ 0x900a3, 0x0109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x0109 },
+	{ 0x40000, 0x0811 },
+	{ 0x40020, 0x0880 },
+	{ 0x40040, 0 },
+	{ 0x40060, 0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0 },
+	{ 0x40003, 0x0811 },
+	{ 0x40023, 0x0880 },
+	{ 0x40043, 0 },
+	{ 0x40063, 0 },
+	{ 0x40004, 0x0720 },
+	{ 0x40024, 0x0f },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0 },
+	{ 0x40006, 0x0716 },
+	{ 0x40026, 0x0f },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0 },
+	{ 0x40007, 0x0716 },
+	{ 0x40027, 0x0f },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0 },
+	{ 0x40008, 0x0716 },
+	{ 0x40028, 0x0f },
+	{ 0x40048, 0x0f00 },
+	{ 0x40068, 0 },
+	{ 0x40009, 0x0720 },
+	{ 0x40029, 0x0f },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0 },
+	{ 0x4000a, 0x0e08 },
+	{ 0x4002a, 0x0c15 },
+	{ 0x4004a, 0 },
+	{ 0x4006a, 0 },
+	{ 0x4000b, 0x0623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0 },
+	{ 0x4006b, 0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0 },
+	{ 0x4006c, 0 },
+	{ 0x4000d, 0x0e08 },
+	{ 0x4002d, 0x0c1a },
+	{ 0x4004d, 0 },
+	{ 0x4006d, 0 },
+	{ 0x4000e, 0x0623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0 },
+	{ 0x4006e, 0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0 },
+	{ 0x4006f, 0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0 },
+	{ 0x40070, 0 },
+	{ 0x40011, 0x0708 },
+	{ 0x40031, 5 },
+	{ 0x40051, 0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0 },
+	{ 0x40072, 0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0 },
+	{ 0x40073, 0 },
+	{ 0x40014, 0x0708 },
+	{ 0x40034, 0x0a },
+	{ 0x40054, 0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0 },
+	{ 0x40075, 0 },
+	{ 0x40016, 0x060a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0 },
+	{ 0x40017, 0x061a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0 },
+	{ 0x40018, 0x060a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0 },
+	{ 0x40019, 0x0642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x0880 },
+	{ 0x4005a, 0 },
+	{ 0x4007a, 0 },
+	{ 0x900a7, 0 },
+	{ 0x900a8, 0x0790 },
+	{ 0x900a9, 0x011a },
+	{ 0x900aa, 8 },
+	{ 0x900ab, 0x07aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x07b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0 },
+	{ 0x900b1, 0x07c8 },
+	{ 0x900b2, 0x0109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x02a8 },
+	{ 0x900b5, 0x0129 },
+	{ 0x900b6, 8 },
+	{ 0x900b7, 0x0370 },
+	{ 0x900b8, 0x0129 },
+	{ 0x900b9, 0x0a },
+	{ 0x900ba, 0x03c8 },
+	{ 0x900bb, 0x01a9 },
+	{ 0x900bc, 0x0c },
+	{ 0x900bd, 0x0408 },
+	{ 0x900be, 0x0199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x0790 },
+	{ 0x900c1, 0x011a },
+	{ 0x900c2, 8 },
+	{ 0x900c3, 4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0x0e },
+	{ 0x900c6, 0x0408 },
+	{ 0x900c7, 0x0199 },
+	{ 0x900c8, 8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x0108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x0790 },
+	{ 0x900cd, 0x016a },
+	{ 0x900ce, 8 },
+	{ 0x900cf, 0x01d8 },
+	{ 0x900d0, 0x0169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x0168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x0788 },
+	{ 0x900d6, 0x016a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x01e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x0798 },
+	{ 0x900dc, 0x016a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x07a0 },
+	{ 0x900df, 0x016a },
+	{ 0x900e0, 8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x0168 },
+	{ 0x900e3, 8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x0168 },
+	{ 0x900e6, 0x0a },
+	{ 0x900e7, 0x0408 },
+	{ 0x900e8, 0x0169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0 },
+	{ 0x900ed, 0x0408 },
+	{ 0x900ee, 0x0169 },
+	{ 0x900ef, 0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x0168 },
+	{ 0x900f2, 0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x0168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x01e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x0798 },
+	{ 0x900fa, 0x016a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x07a0 },
+	{ 0x900fd, 0x016a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x0790 },
+	{ 0x90100, 0x016a },
+	{ 0x90101, 8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x0168 },
+	{ 0x90104, 8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x0168 },
+	{ 0x90107, 0x0a },
+	{ 0x90108, 0x0408 },
+	{ 0x90109, 0x0169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0 },
+	{ 0x9010e, 0x0408 },
+	{ 0x9010f, 0x0169 },
+	{ 0x90110, 0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x0168 },
+	{ 0x90113, 0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x0168 },
+	{ 0x90116, 0 },
+	{ 0x90117, 0x01d8 },
+	{ 0x90118, 0x0169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x0790 },
+	{ 0x9011b, 0x016a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x07aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0x0a },
+	{ 0x90120, 0 },
+	{ 0x90121, 0x01e9 },
+	{ 0x90122, 8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x0108 },
+	{ 0x90125, 0x0f },
+	{ 0x90126, 0x0408 },
+	{ 0x90127, 0x0169 },
+	{ 0x90128, 0x0c },
+	{ 0x90129, 0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 9 },
+	{ 0x9012c, 0 },
+	{ 0x9012d, 0x01a9 },
+	{ 0x9012e, 0 },
+	{ 0x9012f, 0x0408 },
+	{ 0x90130, 0x0169 },
+	{ 0x90131, 0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x0108 },
+	{ 0x90134, 8 },
+	{ 0x90135, 0x07aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x0108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x0790 },
+	{ 0x9013c, 0x016a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x0168 },
+	{ 0x90143, 0x0f },
+	{ 0x90144, 0x0408 },
+	{ 0x90145, 0x0169 },
+	{ 0x90146, 0x0c },
+	{ 0x90147, 0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0 },
+	{ 0x9014a, 0x0408 },
+	{ 0x9014b, 0x0169 },
+	{ 0x9014c, 0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x0168 },
+	{ 0x9014f, 8 },
+	{ 0x90150, 0x03c8 },
+	{ 0x90151, 0x01a9 },
+	{ 0x90152, 3 },
+	{ 0x90153, 0x0370 },
+	{ 0x90154, 0x0129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x02aa },
+	{ 0x90157, 9 },
+	{ 0x90158, 0 },
+	{ 0x90159, 0x0400 },
+	{ 0x9015a, 0x010e },
+	{ 0x9015b, 8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x0109 },
+	{ 0x9015e, 0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x010c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x010c },
+	{ 0x90164, 8 },
+	{ 0x90165, 0x07c8 },
+	{ 0x90166, 0x0101 },
+	{ 0x90167, 8 },
+	{ 0x90168, 0 },
+	{ 0x90169, 8 },
+	{ 0x9016a, 8 },
+	{ 0x9016b, 0x0448 },
+	{ 0x9016c, 0x0109 },
+	{ 0x9016d, 0x0f },
+	{ 0x9016e, 0x07c0 },
+	{ 0x9016f, 0x0109 },
+	{ 0x90170, 0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x0109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x0630 },
+	{ 0x90175, 0x0109 },
+	{ 0x90176, 8 },
+	{ 0x90177, 0x0618 },
+	{ 0x90178, 0x0109 },
+	{ 0x90179, 8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x0109 },
+	{ 0x9017c, 0 },
+	{ 0x9017d, 0x07c8 },
+	{ 0x9017e, 0x0109 },
+	{ 0x9017f, 8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x010c },
+	{ 0x90182, 0 },
+	{ 0x90183, 1 },
+	{ 0x90184, 8 },
+	{ 0x90185, 8 },
+	{ 0x90186, 4 },
+	{ 0x90187, 8 },
+	{ 0x90188, 8 },
+	{ 0x90189, 0x07c8 },
+	{ 0x9018a, 0x0101 },
+	{ 0x90006, 0 },
+	{ 0x90007, 0 },
+	{ 0x90008, 8 },
+	{ 0x90009, 0 },
+	{ 0x9000a, 0 },
+	{ 0x9000b, 0 },
+	{ 0xd00e7, 0x0400 },
+	{ 0x90017, 0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0 },
+	{ 0x400d1, 0x0101 },
+	{ 0x400d2, 0x0105 },
+	{ 0x400d3, 0x0107 },
+	{ 0x400d4, 0x010f },
+	{ 0x400d5, 0x0202 },
+	{ 0x400d6, 0x020a },
+	{ 0x400d7, 0x020b },
+	{ 0x2003a, 2 },
+	{ 0x2000b, 0x64 },
+	{ 0x2000c, 0xc8 },
+	{ 0x2000d, 0x07d0 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0x14 },
+	{ 0x12000c, 0x29 },
+	{ 0x12000d, 0x01a1 },
+	{ 0x12000e, 0x10 },
+	{ 0x9000c, 0 },
+	{ 0x9000d, 0x0173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x400fd, 0x0f },
+	{ 0x10011, 1 },
+	{ 0x10012, 1 },
+	{ 0x10013, 0x0180 },
+	{ 0x10018, 1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 1 },
+	{ 0x101b4, 1 },
+	{ 0x102b4, 1 },
+	{ 0x103b4, 1 },
+	{ 0x104b4, 1 },
+	{ 0x105b4, 1 },
+	{ 0x106b4, 1 },
+	{ 0x107b4, 1 },
+	{ 0x108b4, 1 },
+	{ 0x11011, 1 },
+	{ 0x11012, 1 },
+	{ 0x11013, 0x0180 },
+	{ 0x11018, 1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 1 },
+	{ 0x111b4, 1 },
+	{ 0x112b4, 1 },
+	{ 0x113b4, 1 },
+	{ 0x114b4, 1 },
+	{ 0x115b4, 1 },
+	{ 0x116b4, 1 },
+	{ 0x117b4, 1 },
+	{ 0x118b4, 1 },
+	{ 0x12011, 1 },
+	{ 0x12012, 1 },
+	{ 0x12013, 0x0180 },
+	{ 0x12018, 1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 1 },
+	{ 0x121b4, 1 },
+	{ 0x122b4, 1 },
+	{ 0x123b4, 1 },
+	{ 0x124b4, 1 },
+	{ 0x125b4, 1 },
+	{ 0x126b4, 1 },
+	{ 0x127b4, 1 },
+	{ 0x128b4, 1 },
+	{ 0x13011, 1 },
+	{ 0x13012, 1 },
+	{ 0x13013, 0x0180 },
+	{ 0x13018, 1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 1 },
+	{ 0x131b4, 1 },
+	{ 0x132b4, 1 },
+	{ 0x133b4, 1 },
+	{ 0x134b4, 1 },
+	{ 0x135b4, 1 },
+	{ 0x136b4, 1 },
+	{ 0x137b4, 1 },
+	{ 0x138b4, 1 },
+	{ 0x2003a, 2 },
+	{ 0xc0080, 2 },
+	{ 0xd0000, 1 }
+};
+
+static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3200mts 1D */
+		.drate = 3200,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P1 667mts 1D */
+		.drate = 667,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P0 3200mts 2D */
+		.drate = 3200,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing_ch2 = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+	.fsp_table = { 3200, 667, },
+};
diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
new file mode 100644
index 00000000000..a55086bb5e2
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright Boundary Devices
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <config.h>
+#include <linux/kernel.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+/* MNT Reform2 */
+#define CFG_DDR_MB 4096
+#define CFG_DDR_RANK_BITS 1
+#define CFG_DDR_CHANNEL_CNT 2
+
+#ifdef WR_POST_EXT_3200
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 0x00020008)
+#else
+#define CH2_VAL_INIT4	((LPDDR4_MR3 << 16) | 8)
+#endif
+
+#if CFG_DDR_MB == 1024
+	/* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x0F070707
+
+#elif CFG_DDR_MB == 2048
+	/* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R0	0x0000001F
+#define CH2_VAL_DDRC_ADDRMAP6_R0	0x07070707
+	/* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000016
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x0F070707
+
+#elif CFG_DDR_MB == 3072
+	/* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000015
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x48080707
+
+#elif CFG_DDR_MB == 4096
+	/* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */
+#define CH2_VAL_DDRC_ADDRMAP0_R1	0x00000017
+#define CH2_VAL_DDRC_ADDRMAP6_R1	0x07070707
+#else
+#error unsupported memory size
+#endif
+
+#define LPDDR4_CS_R0	0x1	/* 0 rank bits, 1 chip select */
+#define LPDDR4_CS_R1	0x3	/* 1 rank bit, 2 chip selects */
+
+#if (CFG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_LPDDR4_CS			LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R0
+#else
+#error unsupported memory rank/size
+#endif
+/*
+ * rank0 will succeed, even if really rank 1, so we need
+ * to probe memory if rank0 succeeds
+ */
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R1
+#endif
+
+#elif (CFG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#ifdef CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_LPDDR4_CS			LPDDR4_CS_R1
+#define CH2_VAL_DDRC_ADDRMAP0		CH2_VAL_DDRC_ADDRMAP0_R1
+#define CH2_VAL_DDRC_ADDRMAP6		CH2_VAL_DDRC_ADDRMAP6_R1
+#else
+#error unsupported memory rank/size
+#endif
+
+#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#define CH2_LPDDR4_CS_NEW		LPDDR4_CS_R0
+#define CH2_VAL_DDRC_ADDRMAP0_NEW	CH2_VAL_DDRC_ADDRMAP0_R0
+#define CH2_VAL_DDRC_ADDRMAP6_NEW	CH2_VAL_DDRC_ADDRMAP6_R0
+#endif
+
+#else
+#error unsupported rank bits
+#endif
+
+#if (CFG_DDR_CHANNEL_CNT == 2)
+#if (CFG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0)
+#error unsupported options
+#endif
+#if (CFG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1)
+#error unsupported options
+#endif
+#endif
diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c
new file mode 100644
index 00000000000..21fad4972ab
--- /dev/null
+++ b/board/mntre/imx8mq_reform2/spl.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <mmc.h>
+#include <linux/delay.h>
+#include <power/pmic.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern struct dram_timing_info dram_timing_ch2;
+
+static void spl_dram_init(void)
+{
+	ddr_init(&dram_timing_ch2);
+}
+
+#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
+		.gp = IMX_GPIO_NR(5, 14),
+	},
+	.sda = {
+		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
+		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
+		.gp = IMX_GPIO_NR(5, 15),
+	},
+};
+
+#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		return ret;
+	}
+
+	return 1;
+}
+
+#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			 PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
+	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
+	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+							 ARRAY_SIZE(usdhc1_pads));
+			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+			gpio_direction_output(USDHC1_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC1_PWR_GPIO, 1);
+			break;
+		case 1:
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
+			gpio_direction_output(USDHC2_VSEL, 0);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
+#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
+#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
+#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)
+
+#define I2C_MUX_ADDR		0x70
+#define I2C_FAN53555_ADDR	0x60
+
+static iomux_v3_cfg_t const power_pads[] = {
+	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
+};
+
+int power_init_board(void)
+{
+	uint8_t val;
+
+	imx_iomux_v3_setup_multiple_pads(power_pads,
+					 ARRAY_SIZE(usdhc2_pads));
+
+	/* Release I2C multiplexer reset */
+	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
+	gpio_direction_output(I2C1_PCA9546_RESET, 1);
+
+	/* Select VSEL0 on voltage regulators */
+	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
+	gpio_direction_output(ARM_DRAM_VSEL, 0);
+	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
+	gpio_direction_output(DRAM_1P1_VSEL, 0);
+	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
+	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
+
+	/* Set mux to target ARM/DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
+	/* .6 + .40 = 1.00 */
+	val = 0x80 + 40;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target DRAM regulator */
+	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
+	/* .6 + .50 = 1.10 */
+	val = 0x80 + 50;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target SoC/GPU/VPU regulator */
+	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
+	/*  .6 + .30 = .90 */
+	val = 0x80 + 30;
+	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
+	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
+
+	/* Set mux to target peripherals */
+	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
+
+	return 0;
+}
+
+void spl_board_init(void)
+{
+	puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(0);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+	power_init_board();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig
new file mode 100644
index 00000000000..9b14a1bca10
--- /dev/null
+++ b/configs/imx8mq_reform2_defconfig
@@ -0,0 +1,107 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_TEXT_BASE=0x40200000
+CONFIG_SYS_MALLOC_LEN=0x600000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2"
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_REFORM2=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_SYS_LOAD_ADDR=0x40480000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_REMAKE_ELF=y
+CONFIG_SYS_MONITOR_LEN=524288
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_USE_PREBOOT=y
+CONFIG_DEFAULT_FDT_FILE="freescale/imx8mq-mnt-reform2.dtb"
+CONFIG_CONSOLE_MUX=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x180000
+CONFIG_SPL_BSS_MAX_SIZE=0x2000
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0x187ff0
+CONFIG_SYS_SPL_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000
+CONFIG_SYS_SPL_MALLOC_SIZE=0x80000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
+CONFIG_SPL_I2C=y
+CONFIG_SPL_POWER=y
+CONFIG_SPL_WATCHDOG=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_PBSIZE=1050
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_MDIO is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="FEC"
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PHY=y
+CONFIG_PHY_IMX8MQ_USB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_SPL_POWER_LEGACY=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_POWER_I2C=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_KEYBOARD=y
diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h
new file mode 100644
index 00000000000..3148e8622e1
--- /dev/null
+++ b/include/configs/imx8mq_reform2.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_REFORM2_H
+#define __IMX8M_REFORM2_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CFG_MALLOC_F_ADDR		0x182000
+/* For RAW image gives a error info not panic */
+#endif
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CFG_FEC_MXC_PHYADDR		4
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 1) \
+	func(MMC, mmc, 0) \
+	func(USB, usb, 0) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#define CFG_EXTRA_ENV_SETTINGS		\
+	BOOTENV \
+	"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"image=Image\0" \
+	"console=ttymxc0,115200\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"ramdisk_addr_r=0x44000000\0" \
+	"boot_fdt=try\0" \
+	"fdtfile=imx8mq-mnt-reform2.dtb\0" \
+	"initrd_addr=0x43800000\0" \
+	"bootm_size=0x10000000\0" \
+	"mmcpart=1\0" \
+	"mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+	"stdin=serial,usbkbd\0"
+
+/* Link Definitions */
+
+#define CFG_SYS_INIT_RAM_ADDR		0x40000000
+#define CFG_SYS_INIT_RAM_SIZE		0x80000
+
+
+#define CFG_SYS_SDRAM_BASE		0x40000000
+#define PHYS_SDRAM			0x40000000
+#define PHYS_SDRAM_SIZE			0x100000000	/* 4 GiB DDR */
+
+#define CFG_MXC_UART_BASE		UART_BASE_ADDR(1)
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+
+#endif

From b016fcf723c976ff50c4d4b0848c89cb06158c57 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@denx.de>
Date: Sun, 16 Apr 2023 14:55:04 -0300
Subject: [PATCH 02/24] pico-imx6ul: Convert to CONFIG_DM_SERIAL

The conversion to CONFIG_DM_SERIAL is mandatory, so select
this option.

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/pico-imx6ul_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index dcee179fcff..4e60159a462 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -76,6 +76,7 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_PFUZE100=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
 CONFIG_MXC_UART=y
 CONFIG_USB=y
 CONFIG_USB_MAX_CONTROLLER_COUNT=2

From 76ce66408dfccb491114d721260717ae76795b4d Mon Sep 17 00:00:00 2001
From: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Date: Tue, 18 Apr 2023 01:37:21 +0200
Subject: [PATCH 03/24] imx8mn: buffer overflow in low_drive_gpu_freq()

Avoid a buffer overflow if assigned-clock-rates has less than two elements.

Fixes: 98bcdf16356c ("imx8mn: Add low drive mode support for DDR4/LPDDR4 EVK")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index df865e997d3..20672ded961 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -914,6 +914,8 @@ static int low_drive_gpu_freq(void *blob)
 
 	if (cnt != 7)
 		printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[0], cnt);
+	if (cnt < 2)
+		return -1;
 
 	assignedclks[cnt - 1] = 200000000;
 	assignedclks[cnt - 2] = 200000000;

From 3bc6257e8048bccec95b369fd3c946ac5d8ee9ea Mon Sep 17 00:00:00 2001
From: Oliver Graute <oliver.graute@kococonnector.com>
Date: Fri, 21 Apr 2023 12:11:50 +0200
Subject: [PATCH 04/24] imx: support i.MX8QM DMSSE20 a1 board

Add i.MX8QM DMSSE20 a1 board support

U-Boot 2023.04-00030-g7be2f547b2 (Apr 21 2023 - 11:11:43 +0200)

Model: Advantech iMX8QM DMSSE20
Board: DMS-SE20A1 8GB
Build: SCFW 549b1e18, SECO-FW c9de51c0, ATF 5782363
Boot:  USB
DRAM:  8 GiB
Core:  100 devices, 19 uclasses, devicetree: separate
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial@5a060000
Out:   serial@5a060000
Err:   serial@5a060000
Net:   eth0: ethernet@5b040000
Warning: ethernet@5b050000 (eth1) using random MAC address - 32:05:0c:f9:5e:10
, eth1: ethernet@5b050000
Hit any key to stop autoboot:  0

Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
---
 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/imx8qm-dmsse20-a1.dts            | 397 ++++++++++++++++++
 arch/arm/mach-imx/imx8/Kconfig                |   8 +
 board/advantech/imx8qm_dmsse20_a1/Kconfig     |  15 +
 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS |   7 +
 board/advantech/imx8qm_dmsse20_a1/Makefile    |   8 +
 .../imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env   |  48 +++
 .../imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c     | 188 +++++++++
 .../advantech/imx8qm_dmsse20_a1/imximage.cfg  |  23 +
 board/advantech/imx8qm_dmsse20_a1/spl.c       | 223 ++++++++++
 common/Kconfig                                |   2 +-
 configs/imx8qm_dmsse20a1_defconfig            | 129 ++++++
 doc/board/advantech/imx8qm-dmsse20-a1.rst     |  58 +++
 doc/board/advantech/index.rst                 |   1 +
 include/configs/imx8qm_dmsse20.h              |  48 +++
 15 files changed, 1155 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8qm-dmsse20-a1.dts
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/Kconfig
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/Makefile
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/imximage.cfg
 create mode 100644 board/advantech/imx8qm_dmsse20_a1/spl.c
 create mode 100644 configs/imx8qm_dmsse20a1_defconfig
 create mode 100644 doc/board/advantech/imx8qm-dmsse20-a1.rst
 create mode 100644 include/configs/imx8qm_dmsse20.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3385948d22c..8a003f4e73a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -961,6 +961,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \
 	fsl-imx8qm-mek.dtb \
 	imx8qm-cgtqmx8.dtb \
+	imx8qm-dmsse20-a1.dtb \
 	imx8qm-rom7720-a1.dtb \
 	fsl-imx8qxp-ai_ml.dtb \
 	fsl-imx8qxp-colibri.dtb \
diff --git a/arch/arm/dts/imx8qm-dmsse20-a1.dts b/arch/arm/dts/imx8qm-dmsse20-a1.dts
new file mode 100644
index 00000000000..cff150de07c
--- /dev/null
+++ b/arch/arm/dts/imx8qm-dmsse20-a1.dts
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x80000000 0x00020000;
+
+#include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
+
+/ {
+	model = "Advantech iMX8QM DMSSE20";
+	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
+
+	aliases {
+		mmc0 = &usdhc1;
+		mmc2 = &usdhc3;
+	};
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon";
+		stdout-path = &lpuart0;
+	};
+
+	reg_usb_otg1_vbus: usb_otg1_vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_otg1_vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	reg_usdhc2_vmmc: usdhc2_vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "sw-3p3-sd1";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	imx8qm-mek {
+		pinctrl_hog: hoggrp {
+			fsl,pins = <
+				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	0x06000048
+			>;
+		};
+
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD	0x000014a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000060
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000060
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000060
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000060
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000060
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000060
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000060
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000060
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000060
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000060
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000060
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_fec2: fec2grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD	0x000014a0
+				SC_P_ENET1_MDC_CONN_ENET1_MDC			0x06000020
+				SC_P_ENET1_MDIO_CONN_ENET1_MDIO			0x06000020
+				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x00000060
+				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x00000060
+				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x00000060
+				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x00000060
+				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x00000060
+				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x00000060
+				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x00000060
+				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x00000060
+				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x00000060
+				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x00000060
+				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x00000060
+				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x00000060
+			>;
+		};
+
+		pinctrl_lpi2c1: lpi2c1grp {
+			fsl,pins = <
+				SC_P_GPT0_CLK_DMA_I2C1_SCL		0xc600004c
+				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA		0xc600004c
+			>;
+		};
+
+		pinctrl_lpi2c2: lpi2c2grp {
+			fsl,pins = <
+				SC_P_GPT1_CLK_DMA_I2C2_SCL		0xc600004c
+				SC_P_GPT1_CAPTURE_DMA_I2C2_SDA		0xc600004c
+			>;
+		};
+
+		pinctrl_lpuart0: lpuart0grp {
+			fsl,pins = <
+				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
+				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
+			>;
+		};
+
+		pinctrl_rtc_mc_8803: rtc-mc-8803-grp{
+			fsl,pins = <
+				SC_P_SIM0_POWER_EN_DMA_I2C3_SDA		0xc600004c
+				SC_P_SIM0_PD_DMA_I2C3_SCL		0xc600004c
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_gpio: usdhc2grpgpio {
+			fsl,pins = <
+				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000020
+				SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO08	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_gpio: usdhc3grpgpio {
+			fsl,pins = <
+				SC_P_USDHC2_WP_LSIO_GPIO4_IO11          0x00000021
+				SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12        0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000041
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000021
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000021
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000021
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000021
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000021
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000021
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC2_CLK_CONN_USDHC2_CLK         0x06000040
+				SC_P_USDHC2_CMD_CONN_USDHC2_CMD         0x00000020
+				SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0     0x00000020
+				SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1     0x00000020
+				SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2     0x00000020
+				SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3     0x00000020
+				SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT	0x00000020
+			>;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
+
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	bus-width = <4>;
+	cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
+	no-1-8-v;
+	pinctrl-names = "default","state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
+	wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&fec1 {
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&fec2 {
+	fsl,ar8031-phy-fixup;
+	fsl,magic-packet;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec2>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy1: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+&i2c1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	status = "okay";
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpi2c2>;
+	status = "okay";
+};
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rtc_mc_8803>;
+	status = "okay";
+
+	rv8803@32 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "microcrystal,rv8803";
+		reg = <0x32>;
+	};
+
+	24c02@50 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+	};
+};
+
+&lpuart0 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 018b87b85b7..15f844f5030 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -91,6 +91,13 @@ config TARGET_IMX8QM_ROM7720_A1
 	select SUPPORT_SPL
 	select IMX8QM
 
+config TARGET_IMX8QM_DMSSE20_A1
+	bool "Support i.MX8QM DMS-SE20-A1 board"
+	select BINMAN
+	select BOARD_LATE_INIT
+	select SUPPORT_SPL
+	select IMX8QM
+
 config TARGET_IMX8QXP_MEK
 	bool "Support i.MX8QXP MEK board"
 	select BINMAN
@@ -105,6 +112,7 @@ endchoice
 source "board/freescale/imx8qm_mek/Kconfig"
 source "board/freescale/imx8qxp_mek/Kconfig"
 source "board/congatec/cgtqmx8/Kconfig"
+source "board/advantech/imx8qm_dmsse20_a1/Kconfig"
 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
 source "board/toradex/apalis-imx8/Kconfig"
 source "board/toradex/colibri-imx8x/Kconfig"
diff --git a/board/advantech/imx8qm_dmsse20_a1/Kconfig b/board/advantech/imx8qm_dmsse20_a1/Kconfig
new file mode 100644
index 00000000000..f249ab446c2
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX8QM_DMSSE20_A1
+
+config SYS_BOARD
+	default "imx8qm_dmsse20_a1"
+
+config SYS_VENDOR
+	default "advantech"
+
+config SYS_CONFIG_NAME
+	default "imx8qm_dmsse20"
+
+config IMX_CONFIG
+	default "board/advantech/imx8qm_dmsse20_a1/imximage.cfg"
+
+endif
diff --git a/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
new file mode 100644
index 00000000000..8292c6ba712
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/MAINTAINERS
@@ -0,0 +1,7 @@
+i.MX8QM ROM DMSSE20 a1 BOARD
+M:	Oliver Graute <oliver.graute@kococonnector.com>
+S:	Maintained
+F:	board/advantech/imx8qm_dmsse20_a1/
+F:	arch/arm/dts/imx8qm-dmsse20-a1.dtb
+F:	include/configs/imx8qm_dmsse20.h
+F:	configs/imx8qm_dmsse20a1_defconfig
diff --git a/board/advantech/imx8qm_dmsse20_a1/Makefile b/board/advantech/imx8qm_dmsse20_a1/Makefile
new file mode 100644
index 00000000000..262ffcd6834
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += imx8qm_dmsse20_a1.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
new file mode 100644
index 00000000000..0c9f9c4178a
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env
@@ -0,0 +1,48 @@
+script=boot.scr
+image=Image
+panel=NULL
+console=ttyLP0
+earlycon=lpuart32,0x5a060000
+fdt_addr=0x83000000
+boot_fdt=try
+fdt_file=imx8qm-dmsse20-a1.dtb
+mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV)
+mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART)
+mmcroot=/dev/mmcblk1p2 rootwait rw
+mmcautodetect=yes
+mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}
+loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};
+bootscript=echo Running bootscript from mmc ...; source
+loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}
+loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}
+mmcboot=echo Booting from mmc ...;
+	run mmcargs;
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if run loadfdt; then
+			booti ${loadaddr} - ${fdt_addr};
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	else
+		echo wait for boot;
+	fi;
+netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate}
+	root=/dev/nfs
+	ip=dhcp mac=${ethaddr} nfsroot=${serverip}:${nfsroot},v3,tcp rw
+netboot=echo Booting from net ...;
+	run netargs;
+	if test ${ip_dyn} = yes; then
+		setenv get_cmd dhcp;
+	else
+		setenv get_cmd tftp;
+	fi;
+	${get_cmd} ${loadaddr} ${image};
+	if test ${boot_fdt} = yes || test ${boot_fdt} = try; then
+		if ${get_cmd} ${fdt_addr} ${fdt_file}; then
+			booti ${loadaddr} - ${fdt_addr};
+		else
+			echo WARN: Cannot load the DT;
+		fi;
+	else
+		booti;
+	fi;
diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
new file mode 100644
index 00000000000..867ceff9961
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c
@@ -0,0 +1,188 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+/* #include <power-domain.h> */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+			(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+			(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+			(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+	sc_pm_clock_rate_t rate = SC_80MHZ;
+	int ret;
+
+	/* Set UART0 clock root to 80 MHz */
+	ret = sc_pm_setup_uart(SC_R_UART_0, rate);
+	if (ret)
+		return ret;
+
+	setup_iomux_uart();
+
+	/* This is needed to because Kernel do not Power Up DC_0 */
+	sc_pm_set_resource_power_mode(-1, SC_R_DC_0, SC_PM_PW_MODE_ON);
+	sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
+
+	return 0;
+}
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+#include <miiphy.h>
+
+int board_phy_config(struct phy_device *phydev)
+{
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_MXC_GPIO
+
+#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
+#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
+
+#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
+#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
+#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
+
+static void board_gpio_init(void)
+{
+	/* Enable BB 3V3 */
+	gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
+	gpio_direction_output(BB_GPIO_3V3_1, 1);
+	gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
+	gpio_direction_output(BB_GPIO_3V3_2, 1);
+	gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
+	gpio_direction_output(BB_GPIO_3V3_3, 1);
+
+	/* enable LVDS SAS boards */
+	gpio_request(LVDS_ENABLE, "lvds_enable");
+	gpio_direction_output(LVDS_ENABLE, 1);
+
+	/* enable MIPI SAS boards */
+	gpio_request(MIPI_ENABLE, "mipi_enable");
+	gpio_direction_output(MIPI_ENABLE, 1);
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: DMS-SE20A1 8GB\n");
+	build_info();
+	print_bootinfo();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+#ifdef CONFIG_MXC_GPIO
+	board_gpio_init();
+#endif
+
+	return 0;
+}
+
+void board_quiesce_devices(void)
+{
+	if (IS_ENABLED(CONFIG_XEN)) {
+		/* Clear magic number to let xen know uboot is over */
+		writel(0x0, (void __iomem *)0x80000000);
+		return;
+	}
+}
+
+void detail_board_ddr_info(void)
+{
+	puts("\nDDR    ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(void)
+{
+	puts("SCI reboot request");
+
+	while (1)
+		putc('.');
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return devno;
+}
+
+int mmc_map_to_kernel_blk(int dev_no)
+{
+	/* Use EMMC */
+	if (IS_ENABLED(CONFIG_XEN))
+		return 0;
+
+	return dev_no;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "DMS-SE20A1");
+	env_set("board_rev", "iMX8QM");
+#endif
+
+	env_set("sec_boot", "no");
+#ifdef CONFIG_AHAB_BOOT
+	env_set("sec_boot", "yes");
+#endif
+
+	return 0;
+}
diff --git a/board/advantech/imx8qm_dmsse20_a1/imximage.cfg b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg
new file mode 100644
index 00000000000..2e51e5757cd
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/imximage.cfg
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier:	GPL-2.0-or-later */
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#define __ASSEMBLY__
+
+/* Boot from SD, sector size 0x400 */
+/* SoC type IMX8QM */
+BOOT_FROM	sd
+
+SOC_TYPE IMX8QM
+/* Append seco container image */
+APPEND mx8qm-ahab-container.img
+/* Create the 2nd container */
+CONTAINER
+/* Add scfw image with exec attribute */
+IMAGE SCU mx8qm-val-scfw-tcm.bin
+/* Add ATF image with exec attribute */
+IMAGE A35 bl31.bin 0x80000000
+/* Add U-Boot image with load attribute */
+DATA A35 u-boot-dtb.bin 0x80020000
diff --git a/board/advantech/imx8qm_dmsse20_a1/spl.c b/board/advantech/imx8qm_dmsse20_a1/spl.c
new file mode 100644
index 00000000000..49067bbfd65
--- /dev/null
+++ b/board/advantech/imx8qm_dmsse20_a1/spl.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright 2017-2018 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+#include <common.h>
+#include <dm.h>
+#include <spl.h>
+#include <init.h>
+
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <fsl_esdhc_imx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+#ifdef CONFIG_FSL_ESDHC_IMX
+
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)
+
+static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
+	{USDHC1_BASE_ADDR, 0, 8},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+static iomux_cfg_t emmc0[] = {
+	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t usdhc2_sd[] = {
+	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
+	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+void init_clk_usdhc(u32 index);
+
+int board_mmc_init(struct bd_info *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 * mmc2                    USDHC3
+	 */
+	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
+			init_clk_usdhc(0);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
+			if (ret != SC_ERR_NONE)
+				return ret;
+
+			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
+			init_clk_usdhc(2);
+			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
+			gpio_direction_input(USDHC2_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+		}
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+#endif /* CONFIG_FSL_ESDHC_IMX */
+
+void spl_board_init(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
+			puts("Warning: failed to initialize FSPI0\n");
+		}
+	}
+#endif
+
+	puts("Normal Boot\n");
+}
+
+void spl_board_prepare_for_boot(void)
+{
+#if defined(CONFIG_SPL_SPI_SUPPORT)
+	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
+		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
+			puts("Warning: failed to turn off FSPI0\n");
+		}
+	}
+#endif
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
diff --git a/common/Kconfig b/common/Kconfig
index f2783ee65d7..6345d5c4bae 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -559,7 +559,7 @@ config BOARD_TYPES
 
 config DISPLAY_CPUINFO
 	bool "Display information about the CPU during start up"
-	default y if ARC|| ARM || NIOS2 || X86 || XTENSA || M68K
+	default y if ARC || ARM || NIOS2 || X86 || XTENSA || M68K
 	help
 	  Display information about the CPU that U-Boot is running on
 	  when U-Boot starts up. The function print_cpuinfo() is called
diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig
new file mode 100644
index 00000000000..3341b5e447f
--- /dev/null
+++ b/configs/imx8qm_dmsse20a1_defconfig
@@ -0,0 +1,129 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8=y
+CONFIG_TEXT_BASE=0x80020000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_SYS_MALLOC_LEN=0x2800000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_SYS_MMC_IMG_LOAD_PART=0
+CONFIG_TARGET_IMX8QM_DMSSE20_A1=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_OFFSET=0x80000
+CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SPL=y
+CONFIG_SYS_LOAD_ADDR=0x80280000
+CONFIG_SYS_MEMTEST_START=0xA0000000
+CONFIG_SYS_MEMTEST_END=0xC0000000
+CONFIG_REMAKE_ELF=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
+CONFIG_CI_UDC=y
+CONFIG_DM_PCA953X=y
+CONFIG_EVENT=y
+CONFIG_DM_EVENT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else booti ${loadaddr} - ${fdt_addr}; fi"
+CONFIG_LOG=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SPL_BSS_START_ADDR=0x00128000
+CONFIG_SPL_MAX_SIZE=0x1f000
+CONFIG_SPL_BSS_MAX_SIZE=0x1000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_BOOTM_LEN=0x04000000
+CONFIG_HUSH_PARSER=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_FS_FAT=y
+CONFIG_FS_EXT4=y
+# CONFIG_BOOTM_NETBSD is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FUSE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8qm-dmsse20-a1"
+CONFIG_ENV_SOURCE_FILE="imx8qm_dmsse20-a1"
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_SYS_MMC_ENV_PART=0
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_IMX8=y
+CONFIG_CPU=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ADDR_ENABLE=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_PHY_GIGE=y
+CONFIG_DM_ETH=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_FEC_MXC_SHARE_MDIO=y
+CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
+CONFIG_FEC_MXC=y
+CONFIG_FEC1_ENET_DEV=0
+CONFIG_ETHPRIME="eth0"
+CONFIG_FEC1_MXC_PHYADDR=0x4
+CONFIG_FEC2_ENET_DEV=1
+CONFIG_ETHPRIME1="eth1"
+CONFIG_FEC2_MXC_PHYADDR=0x4
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+CONFIG_IMX_SMMU=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_BAUDRATE=115200
+CONFIG_MISC=y
+CONFIG_SMC_FUSE=y
+CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000
+CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_AHAB_BOOT=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_RV8803=y
+CONFIG_CMD_DATE=y
diff --git a/doc/board/advantech/imx8qm-dmsse20-a1.rst b/doc/board/advantech/imx8qm-dmsse20-a1.rst
new file mode 100644
index 00000000000..b83e678cd9a
--- /dev/null
+++ b/doc/board/advantech/imx8qm-dmsse20-a1.rst
@@ -0,0 +1,58 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+NXP i.MX8QM DMSSE20-a1 board
+============================
+
+Quick Start
+-----------
+
+- Build the ARM Trusted firmware binary
+- Get scfw_tcm.bin and ahab-container.img
+- Get imx-mkimage
+- Build U-Boot
+- Flash the binary into the SD card
+- Boot
+
+Get and Build the ARM Trusted Firmware
+--------------------------------------
+
+.. code-block:: bash
+
+     $ git clone https://github.com/nxp-imx/imx-atf
+     $ cd imx-atf/
+     $ git checkout lf-5.10.72-2.2.0 -b lf-5.10.72-2.2.0
+     $ make PLAT=imx8qm bl31
+     $ cp build/imx8qm/release/bl31.bin $(builddir)
+
+Get scfw_tcm.bin and ahab-container.img
+---------------------------------------
+
+.. code-block:: bash
+
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.11.0.bin
+     $ chmod +x imx-sc-firmware-1.11.0.bin
+     $ ./imx-sc-firmware-1.11.0.bin
+     $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-seco-3.8.5.bin
+     $ chmod +x imx-seco-3.8.5.bin
+     $ ./imx-seco-3.8.5.bin
+
+Or use this to avoid running random scripts from the internet,
+but note that you must agree to the license the script displays:
+
+.. code-block:: bash
+
+     $ dd if=imx-sc-firmware-1.11.0.bin of=imx-sc-firmware-1.11.0.tar.bz2 bs=42757 skip=1
+     $ tar -xf imx-sc-firmware-1.11.0.tar.bz2
+     $ cp imx-sc-firmware-1.11.0/mx8qm-val-scfw-tcm.bin $(builddir)
+     $ dd if=imx-seco-3.8.5.bin of=imx-seco-3.8.5.tar.bz2 bs=43978 skip=1
+     $ tar -xf imx-seco-3.8.5.tar.bz2
+     $ cp imx-seco-3.8.5/firmware/seco/mx8qmb0-ahab-container.img $(builddir)
+
+Build U-Boot
+------------
+.. code-block:: bash
+
+     $ export ATF_LOAD_ADDR=0x80000000
+     $ export BL33_LOAD_ADDR=0x80020000
+     $ make imx8qm_dmsse20a1_defconfig
+     $ make
diff --git a/doc/board/advantech/index.rst b/doc/board/advantech/index.rst
index e9b198c5c3e..125b98c1f76 100644
--- a/doc/board/advantech/index.rst
+++ b/doc/board/advantech/index.rst
@@ -7,3 +7,4 @@ Advantech
    :maxdepth: 2
 
    imx8qm-rom7720-a1.rst
+   imx8qm-dmsse20-a1.rst
diff --git a/include/configs/imx8qm_dmsse20.h b/include/configs/imx8qm_dmsse20.h
new file mode 100644
index 00000000000..f9cda5eec7d
--- /dev/null
+++ b/include/configs/imx8qm_dmsse20.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2019 NXP
+ * Copyright 2019-2023 Kococonnector GmbH
+ */
+
+#ifndef __IMX8QM_DMSSE20_H
+#define __IMX8QM_DMSSE20_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+/* Flat Device Tree Definitions */
+
+#define CFG_SYS_FSL_ESDHC_ADDR		0
+#define USDHC1_BASE_ADDR		0x5B010000
+#define USDHC2_BASE_ADDR		0x5B020000
+#define USDHC3_BASE_ADDR		0x5B030000
+
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE			0x5B040000
+/* FEC1 */
+#define IMX_FEC1_BASE			0x5B040000
+/* FEC2 */
+#define IMX_FEC2_BASE			0x5B050000
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+/* Incorporate settings into the U-Boot environment */
+#define CFG_EXTRA_ENV_SETTINGS
+
+#define CFG_SYS_FSL_USDHC_NUM		2
+
+#define CFG_SYS_SDRAM_BASE		0x080000000
+#define PHYS_SDRAM_1			0x080000000
+#define PHYS_SDRAM_2			0x880000000
+#define PHYS_SDRAM_1_SIZE		0x080000000	/* 2 GB */
+#define PHYS_SDRAM_2_SIZE		0x180000000	/* 6 GB */
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		8000000	/* 8MHz */
+
+#endif /* __IMX8QM_DMSSE20_H */

From 41d7a7da80ec7461cf57828db2c7ad5b29bbba33 Mon Sep 17 00:00:00 2001
From: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Date: Sat, 22 Apr 2023 16:11:17 +0200
Subject: [PATCH 05/24] imx6: clock: improve calculations to get the PLL video
 rate

During some tests to check the pixel clock rate in the transition from
U-Boot to the Linux kernel, I noticed that with the same configuration
of the registers the debug messages reported different rates.

The same Linux kernel calculations are now used to get the PLL video
rate.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
---
 arch/arm/mach-imx/mx6/clock.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index cb9d629be40..17d8dcd5c84 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -213,6 +213,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 {
 	u32 div, test_div, pll_num, pll_denom;
+	u64 temp64;
 
 	switch (pll) {
 	case PLL_SYS:
@@ -272,7 +273,10 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
 		}
 		test_div = 1 << (2 - test_div);
 
-		return infreq * (div + pll_num / pll_denom) / test_div;
+		temp64 = (u64)infreq;
+		temp64 *= pll_num;
+		do_div(temp64, pll_denom);
+		return infreq * div + (unsigned long)temp64;
 	default:
 		return 0;
 	}

From 82863a99c0c85ccb7406222701147586c43c4996 Mon Sep 17 00:00:00 2001
From: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Date: Sat, 22 Apr 2023 16:11:18 +0200
Subject: [PATCH 06/24] imx6: clock: add support to get LCD pixel clock rate

Add the get_lcd_clk() function to get the LCD pixel clock rate.

The patch has been tested on imx6ul platform.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
 arch/arm/include/asm/arch-mx6/clock.h |  2 +
 arch/arm/mach-imx/mx6/clock.c         | 58 +++++++++++++++++++++++++++
 2 files changed, 60 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 8ae49715789..81af89c631f 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -41,6 +41,8 @@ enum mxc_clock {
 	MXC_SATA_CLK,
 	MXC_NFC_CLK,
 	MXC_I2C_CLK,
+	MXC_LCDIF1_CLK,
+	MXC_LCDIF2_CLK,
 };
 
 enum ldb_di_clock {
diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 17d8dcd5c84..267d86ab419 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -418,6 +418,60 @@ static u32 get_uart_clk(void)
 	return freq / (uart_podf + 1);
 }
 
+static u32 get_lcd_clk(unsigned int ifnum)
+{
+	u32 pll_rate;
+	u32 pred, postd;
+
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl() &&
+	    !is_mx6sll()) {
+		debug("This chip does't support lcd\n");
+		return 0;
+	}
+
+	pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK);
+	if (ifnum == 1) {
+		if (!is_mx6sl()) {
+			pred = __raw_readl(&imx_ccm->cscdr2);
+			pred &= MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK;
+			pred = pred >> MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET;
+
+			postd = readl(&imx_ccm->cbcmr);
+			postd &= MXC_CCM_CBCMR_LCDIF1_PODF_MASK;
+			postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+		} else {
+			pred = __raw_readl(&imx_ccm->cscdr2);
+			pred &= MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK;
+			pred = pred >> MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET;
+
+			postd = readl(&imx_ccm->cscmr1);
+			postd &= MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET;
+			postd = postd >> MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET;
+		}
+	} else if (ifnum == 2) {
+		if (is_mx6sx()) {
+			pred = __raw_readl(&imx_ccm->cscdr2);
+			pred &= MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK;
+			pred = pred >> MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET;
+
+			postd = readl(&imx_ccm->cscmr1);
+			postd &= MXC_CCM_CSCMR1_LCDIF2_PODF_MASK;
+			postd = postd >> MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET;
+
+		} else {
+			goto if_err;
+		}
+	} else {
+		goto if_err;
+	}
+
+	return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1));
+
+if_err:
+	debug("This chip not support lcd iterface %d\n", ifnum);
+	return 0;
+}
+
 static u32 get_cspi_clk(void)
 {
 	u32 reg, cspi_podf;
@@ -1273,6 +1327,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 		return get_usdhc_clk(3);
 	case MXC_SATA_CLK:
 		return get_ahb_clk();
+	case MXC_LCDIF1_CLK:
+		return get_lcd_clk(1);
+	case MXC_LCDIF2_CLK:
+		return get_lcd_clk(2);
 	default:
 		printf("Unsupported MXC CLK: %d\n", clk);
 		break;

From 1490292a0775c89a7ab4e79eab9e3c859a38f106 Mon Sep 17 00:00:00 2001
From: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Date: Sat, 22 Apr 2023 16:11:19 +0200
Subject: [PATCH 07/24] imx6: clock: print real pixel clock rate

Add debug messages to print the real pixel clock rate, which may not be
the requested one.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
 arch/arm/mach-imx/mx6/clock.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c
index 267d86ab419..1bdc568f9b1 100644
--- a/arch/arm/mach-imx/mx6/clock.c
+++ b/arch/arm/mach-imx/mx6/clock.c
@@ -802,6 +802,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 		}
 
 		enable_lcdif_clock(base_addr, 1);
+		debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF1_CLK));
 	} else if (is_mx6sx()) {
 		/* Setting LCDIF2 for i.MX6SX */
 		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
@@ -823,6 +824,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 				 MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
 
 		enable_lcdif_clock(base_addr, 1);
+		debug("pixel clock = %u\n", mxc_get_clock(MXC_LCDIF2_CLK));
 	}
 }
 

From a48a824dbac4a33e4b27b9f568ea28c52b631658 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 24 Apr 2023 09:33:44 -0700
Subject: [PATCH 08/24] imx: fix get_boot_device() for imx8

commit 787f04bb6a0a ("imx: add USB2_BOOT type") broke get_boot_device()
for IMX8 which affects booting from SDP due to boot_instance being
non-zero.

Fix this by only using boot_instance for imx8ulp and imx9.

Fixes: 787f04bb6a0a ("imx: add USB2_BOOT type")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
---
 arch/arm/mach-imx/romapi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/romapi.c b/arch/arm/mach-imx/romapi.c
index b49e7f80a28..ff0522c2d11 100644
--- a/arch/arm/mach-imx/romapi.c
+++ b/arch/arm/mach-imx/romapi.c
@@ -70,6 +70,8 @@ enum boot_device get_boot_device(void)
 		boot_dev = SPI_NOR_BOOT;
 		break;
 	case BT_DEV_TYPE_USB:
+		if (!is_imx8ulp() && !is_imx9())
+			boot_instance = 0;
 		boot_dev = boot_instance + USB_BOOT;
 		break;
 	default:

From feb710b3816c8d2dd7b3215bf0253bff9092eee0 Mon Sep 17 00:00:00 2001
From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Date: Tue, 25 Apr 2023 10:19:35 -0400
Subject: [PATCH 09/24] arm: imx8m: remove unused and obsolete board_fix_fdt()
 in SOC context

It doesn't seem appropriate for arch/SOC to use a board-level
functionality (CONFIG_OF_BOARD_FIXUP), because this prevents boards
that need to do FDT fixup from using that feature.

Also, this code is completely dead and useless (from comments by
Rasmus Villemoes on the mailing list):

  - No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP
  - The nodes which that function wants to disable don't even exist in
    the U-Boot copy of imx8mp.dtsi.

This code was introduced in commit 35bb60787b88. It seems to be some
random import of code from downstream NXP U-Boot, with a commit
message that makes no sense in upstream context.

Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
---
 arch/arm/mach-imx/imx8m/soc.c | 34 ----------------------------------
 1 file changed, 34 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 20672ded961..4705e6c1192 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1397,40 +1397,6 @@ usb_modify_speed:
 }
 #endif
 
-#ifdef CONFIG_OF_BOARD_FIXUP
-#ifndef CONFIG_SPL_BUILD
-int board_fix_fdt(void *fdt)
-{
-	if (is_imx8mpul()) {
-		int i = 0;
-		int nodeoff, ret;
-		const char *status = "disabled";
-		static const char * const dsi_nodes[] = {
-			"/soc@0/bus@32c00000/mipi_dsi@32e60000",
-			"/soc@0/bus@32c00000/lcd-controller@32e80000",
-			"/dsi-host"
-		};
-
-		for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
-			nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
-			if (nodeoff > 0) {
-set_status:
-				ret = fdt_setprop(fdt, nodeoff, "status", status,
-						  strlen(status) + 1);
-				if (ret == -FDT_ERR_NOSPACE) {
-					ret = fdt_increase_size(fdt, 512);
-					if (!ret)
-						goto set_status;
-				}
-			}
-		}
-	}
-
-	return 0;
-}
-#endif
-#endif
-
 #if !CONFIG_IS_ENABLED(SYSRESET)
 void reset_cpu(void)
 {

From 7f932c6b84b61f3d23c8071370d5d857577cde7d Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:48 -0300
Subject: [PATCH 10/24] smegw01: Enable setting additional boot params

Introduce EXTRA_BOOTPARAMS to allow passing additional parameters
to kernel command line. This is useful for debugging purposes.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 include/configs/smegw01.h | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 11031744bef..a356f095a68 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -17,6 +17,11 @@
 /* MMC Config*/
 #define CFG_SYS_FSL_ESDHC_ADDR	0
 
+/* default to no extra bootparams, we need an empty define for stringification*/
+#ifndef EXTRA_BOOTPARAMS
+#define EXTRA_BOOTPARAMS
+#endif
+
 #define CFG_EXTRA_ENV_SETTINGS \
 	"image=zImage\0" \
 	"console=ttymxc0\0" \
@@ -26,7 +31,8 @@
 	"mmcdev=0\0" \
 	"mmcpart=1\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/mmcblk0p${mmcpart} rootwait rw\0" \
+		"root=/dev/mmcblk0p${mmcpart} rootwait rw " \
+		__stringify(EXTRA_BOOTPARAMS) "\0" \
 	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
 	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
 	"mmcboot=echo Booting from mmc ...; " \

From 21e81011a29dd1a15ece469c4a554194ce738b15 Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:49 -0300
Subject: [PATCH 11/24] smegw01: Select CONFIG_CMD_SQUASHFS

Select CONFIG_CMD_SQUASHFS so that the SquashFS U-Boot commands
are available.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/smegw01_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 1e0b9aa5be1..f15291f1dd0 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y

From 3bb2b48ed25cf10f0e2470d7cb5968ffb3978753 Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:50 -0300
Subject: [PATCH 12/24] smegw01: Select bootcount support

Add automatic boot counter that increases after every
reset. After a power-on reset, it will be initialized with 1,
and each reboot will increment the value by 1. By default it is
disabled if bootlimit isn't set.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/smegw01_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index f15291f1dd0..5d9d4194639 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -46,6 +46,8 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
 CONFIG_DFU_MMC=y
 CONFIG_DM_I2C=y
 CONFIG_SUPPORT_EMMC_BOOT=y

From ac52bb99cc7c9c288432f80710b21bd54e743f58 Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:51 -0300
Subject: [PATCH 13/24] smegw01: Add altbootcmd

Add an altbootcmd script, which is convenient way to integrate with
swupdate and perform a roll back of the previous working version in the
case of update failure.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/smegw01_defconfig | 2 +-
 include/configs/smegw01.h | 8 ++++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 5d9d4194639..418151a6de0 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -18,7 +18,7 @@ CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi; "
+CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; if run loadimage; then run mmcboot; fi; "
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index a356f095a68..6ee4acc70d2 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -33,6 +33,7 @@
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
 		"root=/dev/mmcblk0p${mmcpart} rootwait rw " \
 		__stringify(EXTRA_BOOTPARAMS) "\0" \
+	"bootlimit=3\0" \
 	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
 	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
@@ -40,6 +41,13 @@
 		"if run loadfdt; then " \
 			"bootz ${loadaddr} - ${fdt_addr}; " \
 		"fi;\0" \
+	"altbootcmd=echo Performing rollback...; " \
+		"if test \"${mmcpart}\" = 1; then " \
+			"setenv mmcpart 2; " \
+		"else " \
+			"setenv mmcpart 1; " \
+		"fi; setenv bootcount 0; setenv upgrade_available; setenv ustate 3; saveenv; " \
+		"run bootcmd;\0"
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR

From 440dc0694ba44ed8551f8809f76373f20800987f Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:52 -0300
Subject: [PATCH 14/24] smegw01: Run altbootcmd in the case of failure

Run the altbootcmd script if any step of bootcmd fails.

This ensures that always a valid image can be run.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/smegw01_defconfig | 2 +-
 include/configs/smegw01.h | 8 +++++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 418151a6de0..b3580d5d6e5 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -18,7 +18,7 @@ CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; if run loadimage; then run mmcboot; fi; "
+CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; if run loadimage; then run mmcboot; else run altbootcmd; fi; "
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 6ee4acc70d2..05edaac42f8 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -39,7 +39,13 @@
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if run loadfdt; then " \
-			"bootz ${loadaddr} - ${fdt_addr}; " \
+			"if bootz ${loadaddr} - ${fdt_addr}; then " \
+				"; " \
+			"else " \
+				"run altbootcmd; " \
+			"fi;" \
+		"else " \
+			"run altbootcmd; " \
 		"fi;\0" \
 	"altbootcmd=echo Performing rollback...; " \
 		"if test \"${mmcpart}\" = 1; then " \

From 52726d24d6c8e857f40d9125b0bce5f6272b6022 Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:53 -0300
Subject: [PATCH 15/24] smegw01: Only commit to new partition if update was
 successful

When performing rootfs update via swupdate, it is convenient to check the
'ustate' variable to decide whether the update succeeded or not.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 include/configs/smegw01.h | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 05edaac42f8..277c828d0e0 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -30,13 +30,19 @@
 	"bootm_size=0x10000000\0" \
 	"mmcdev=0\0" \
 	"mmcpart=1\0" \
+	"mmcpart_committed=1\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/mmcblk0p${mmcpart} rootwait rw " \
+		"root=/dev/mmcblk0p${mmcpart_committed} rootwait rw " \
 		__stringify(EXTRA_BOOTPARAMS) "\0" \
+	"commit_mmc=if test \"${ustate}\" = 1 -a \"${mmcpart}\" != \"${mmcpart_committed}\"; then " \
+	              "setenv mmcpart_committed ${mmcpart};" \
+								"saveenv;" \
+						  "fi;\0" \
 	"bootlimit=3\0" \
-	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
+	"loadimage=load mmc ${mmcdev}:${mmcpart_committed} ${loadaddr} boot/${image}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart_committed} ${fdt_addr} boot/${fdtfile}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
+	  "run commit_mmc; " \
 		"run mmcargs; " \
 		"if run loadfdt; then " \
 			"if bootz ${loadaddr} - ${fdt_addr}; then " \
@@ -48,10 +54,12 @@
 			"run altbootcmd; " \
 		"fi;\0" \
 	"altbootcmd=echo Performing rollback...; " \
-		"if test \"${mmcpart}\" = 1; then " \
+		"if test \"${mmcpart_committed}\" = 1; then " \
 			"setenv mmcpart 2; " \
+			"setenv mmcpart_committed 2;" \
 		"else " \
 			"setenv mmcpart 1; " \
+			"setenv mmcpart_committed 1;" \
 		"fi; setenv bootcount 0; setenv upgrade_available; setenv ustate 3; saveenv; " \
 		"run bootcmd;\0"
 

From 31c6c79a01c05dca9ab93b42f0f97d973a4db61f Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:54 -0300
Subject: [PATCH 16/24] smegw01: Enable EMMC boot from multiple partitions

GPT Partition labels are used for determining the right
root filesystem to boot from.

The U-Boot environment is configured to reside in the eMMC hardware
boot partition we are currently booted from.

This should enable a dual copy approach for upgrading the bootloader.
One can overwrite the inactive hardware partition with new bootloader
and environment and afterwards switch the eMMC boot partition for an
atomic bootloader switch.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 board/storopack/smegw01/smegw01.c | 10 ++++++++++
 configs/smegw01_defconfig         |  2 ++
 include/configs/smegw01.h         | 12 ++++++++----
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index e6bff80e556..7d4de9326d6 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -17,6 +17,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/setup.h>
 #include <asm/bootm.h>
+#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,3 +94,12 @@ int board_late_init(void)
 
 	return 0;
 }
+
+uint board_mmc_get_env_part(struct mmc *mmc)
+{
+	uint part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
+
+	if (part == 7)
+		part = 0;
+	return part;
+}
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index b3580d5d6e5..54cf1cfc1f1 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -30,6 +30,7 @@ CONFIG_CMD_MEMTEST=y
 CONFIG_CMD_UNZIP=y
 CONFIG_CMD_DFU=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PART=y
 CONFIG_CMD_DHCP=y
@@ -44,6 +45,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 277c828d0e0..71f2d9c8e85 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -32,17 +32,21 @@
 	"mmcpart=1\0" \
 	"mmcpart_committed=1\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/mmcblk0p${mmcpart_committed} rootwait rw " \
-		__stringify(EXTRA_BOOTPARAMS) "\0" \
+		"root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw " \
+		__stringify(EXTRA_BOOTPARAMS) " SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}\0" \
 	"commit_mmc=if test \"${ustate}\" = 1 -a \"${mmcpart}\" != \"${mmcpart_committed}\"; then " \
 	              "setenv mmcpart_committed ${mmcpart};" \
 								"saveenv;" \
 						  "fi;\0" \
 	"bootlimit=3\0" \
-	"loadimage=load mmc ${mmcdev}:${mmcpart_committed} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart_committed} ${fdt_addr} boot/${fdtfile}\0" \
+	"loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${loadaddr} boot/${image}\0" \
+	"loadfdt=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fdt_addr} boot/${fdtfile}\0" \
+	"loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
+	"loadbootpart=mmc partconf 1 boot_part\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 	  "run commit_mmc; " \
+		"run loadpart; " \
+		"run loadbootpart; " \
 		"run mmcargs; " \
 		"if run loadfdt; then " \
 			"if bootz ${loadaddr} - ${fdt_addr}; then " \

From b1bbdf15418c2c9bb16863ad45b17037dabb381b Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:55 -0300
Subject: [PATCH 17/24] smegw01: Change default boot device to eMMC

Let eMMC be the default boot medium.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 include/configs/smegw01.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 71f2d9c8e85..8f68472f5ba 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -28,7 +28,7 @@
 	"fdtfile=imx7d-smegw01.dtb\0" \
 	"fdt_addr=0x83000000\0" \
 	"bootm_size=0x10000000\0" \
-	"mmcdev=0\0" \
+	"mmcdev=1\0" \
 	"mmcpart=1\0" \
 	"mmcpart_committed=1\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} " \

From f3ce9db85a326468b71e23adb361f3fed679f2f4 Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:56 -0300
Subject: [PATCH 18/24] smegw01: Switch to fitImage

Instead of loading the zImage kernel and the devicetree separately, switch
to the fitImage format, which is more convenient when working with secure
boot, for example.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 include/configs/smegw01.h | 14 +++++---------
 1 file changed, 5 insertions(+), 9 deletions(-)

diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 8f68472f5ba..85218832777 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -23,7 +23,7 @@
 #endif
 
 #define CFG_EXTRA_ENV_SETTINGS \
-	"image=zImage\0" \
+	"image=fitImage\0" \
 	"console=ttymxc0\0" \
 	"fdtfile=imx7d-smegw01.dtb\0" \
 	"fdt_addr=0x83000000\0" \
@@ -39,8 +39,8 @@
 								"saveenv;" \
 						  "fi;\0" \
 	"bootlimit=3\0" \
-	"loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fdt_addr} boot/${fdtfile}\0" \
+	"fit_addr=0x88000000\0" \
+	"loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fit_addr} boot/${image}\0" \
 	"loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
 	"loadbootpart=mmc partconf 1 boot_part\0" \
 	"mmcboot=echo Booting from mmc ...; " \
@@ -48,12 +48,8 @@
 		"run loadpart; " \
 		"run loadbootpart; " \
 		"run mmcargs; " \
-		"if run loadfdt; then " \
-			"if bootz ${loadaddr} - ${fdt_addr}; then " \
-				"; " \
-			"else " \
-				"run altbootcmd; " \
-			"fi;" \
+		"if bootm ${fit_addr}; then " \
+			"; " \
 		"else " \
 			"run altbootcmd; " \
 		"fi;\0" \

From a1bc4f1937a04e70f45f3ac87aee0f168b5e7bef Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:57 -0300
Subject: [PATCH 19/24] smegw01: Add lockdown U-Boot env support

Add lockdown U-Boot env support so that only certain U-Boot environment
variables are allowed to be modified.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 board/storopack/smegw01/Kconfig   |  7 +++++
 board/storopack/smegw01/smegw01.c | 17 +++++++++++
 configs/smegw01_defconfig         | 11 ++++++-
 include/configs/smegw01.h         | 48 +++++++++++++++++++++++++++++--
 4 files changed, 79 insertions(+), 4 deletions(-)

diff --git a/board/storopack/smegw01/Kconfig b/board/storopack/smegw01/Kconfig
index d8f24695d0d..390214c285b 100644
--- a/board/storopack/smegw01/Kconfig
+++ b/board/storopack/smegw01/Kconfig
@@ -12,4 +12,11 @@ config SYS_CONFIG_NAME
 config IMX_CONFIG
 	default "board/storopack/smegw01/imximage.cfg"
 
+config SYS_BOOT_LOCKED
+	bool "Lock boot process to EMMC"
+	default y
+	help
+	  Say N here if you want to boot from eMMC and SD.
+	  Say Y to boot from eMMC.
+
 endif
diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index 7d4de9326d6..e648b196b9d 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -14,6 +14,7 @@
 #include <asm/io.h>
 #include <common.h>
 #include <env.h>
+#include <env_internal.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/setup.h>
 #include <asm/bootm.h>
@@ -103,3 +104,19 @@ uint board_mmc_get_env_part(struct mmc *mmc)
 		part = 0;
 	return part;
 }
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+	if (op == ENVOP_SAVE || op == ENVOP_ERASE)
+		return ENVL_MMC;
+
+	switch (prio) {
+	case 0:
+		return ENVL_NOWHERE;
+
+	case 1:
+		return ENVL_MMC;
+	}
+
+	return ENVL_UNKNOWN;
+}
diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index 54cf1cfc1f1..ea25b3b87ce 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0x100000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
 CONFIG_TARGET_SMEGW01=y
+# CONFIG_SYS_BOOT_LOCKED is not set
 CONFIG_ENV_OFFSET_REDUND=0x110000
 CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
 # CONFIG_ARMV7_VIRT is not set
@@ -17,13 +18,18 @@ CONFIG_SYS_MEMTEST_START=0x80000000
 CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_AUTOBOOT_MENU_SHOW=y
+CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; if run loadimage; then run mmcboot; else run altbootcmd; fi; "
+CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; "
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="run setup_boot_menu;"
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=32
 CONFIG_SYS_PBSIZE=532
 # CONFIG_CMD_BOOTD is not set
 CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_BOOTMENU=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_XIMG is not set
 CONFIG_CMD_MEMTEST=y
@@ -43,9 +49,12 @@ CONFIG_CMD_SQUASHFS=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_OF_CONTROL=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_WRITEABLE_LIST=y
+CONFIG_ENV_ACCESS_IGNORE_FORCE=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_BOUNCE_BUFFER=y
 CONFIG_BOOTCOUNT_LIMIT=y
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 85218832777..6f373973ab8 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -22,6 +22,32 @@
 #define EXTRA_BOOTPARAMS
 #endif
 
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define EXTRA_ENV_FLAGS
+#define SETUP_BOOT_MENU "setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd\0"
+#else
+#define EXTRA_ENV_FLAGS "mmcdev:dw,"
+#define SETUP_BOOT_MENU "setup_boot_menu=" \
+	"if test \"${mmcdev}\" = 1; then " \
+		"setenv emmc_priority 0;" \
+		"setenv sd_priority 1;" \
+	"else " \
+		"setenv emmc_priority 1;" \
+		"setenv sd_priority 0;" \
+	"fi;" \
+	"setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;" \
+	"setenv bootmenu_${sd_priority} SD=run boot_sd;\0"
+#endif
+
+#define CFG_ENV_FLAGS_LIST_STATIC \
+	"mmcpart:dw," \
+	"mmcpart_committed:dw," \
+	"ustate:dw," \
+	"bootcount:dw," \
+	"bootlimit:dw," \
+	"upgrade_available:dw," \
+	EXTRA_ENV_FLAGS
+
 #define CFG_EXTRA_ENV_SETTINGS \
 	"image=fitImage\0" \
 	"console=ttymxc0\0" \
@@ -40,13 +66,28 @@
 						  "fi;\0" \
 	"bootlimit=3\0" \
 	"fit_addr=0x88000000\0" \
-	"loadimage=load mmc ${mmcdev}#rootfs-${mmcpart_committed} ${fit_addr} boot/${image}\0" \
+	"loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} boot/${image}\0" \
 	"loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
 	"loadbootpart=mmc partconf 1 boot_part\0" \
-	"mmcboot=echo Booting from mmc ...; " \
+	"boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;\0" \
+	"boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;\0" \
+	"persist_mmcdev=" \
+		"if test \"${mmcdev}\" != \"${mmcdev_wanted}\"; then " \
+			"setenv mmcdev \"${mmcdev_wanted}\";" \
+			"saveenv;" \
+		"fi;\0" \
+	"mmcboot=echo Booting...; " \
+		"echo mmcdev: ${mmcdev}; " \
 	  "run commit_mmc; " \
+		"echo mmcpart: ${mmcpart_committed}; " \
 		"run loadpart; " \
+		"echo gptpart: ${gpt_partition_entry}; " \
 		"run loadbootpart; " \
+		"if run loadimage; then " \
+			"; " \
+		"else " \
+			"run altbootcmd; " \
+		"fi; " \
 		"run mmcargs; " \
 		"if bootm ${fit_addr}; then " \
 			"; " \
@@ -61,7 +102,8 @@
 			"setenv mmcpart 1; " \
 			"setenv mmcpart_committed 1;" \
 		"fi; setenv bootcount 0; setenv upgrade_available; setenv ustate 3; saveenv; " \
-		"run bootcmd;\0"
+		"run bootcmd;\0" \
+		SETUP_BOOT_MENU
 
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR

From ea99d227f95f6849d5523e8d327b1805bb828254 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@denx.de>
Date: Wed, 26 Apr 2023 13:04:58 -0300
Subject: [PATCH 20/24] smegw01: Read the second MAC address

Currently, only the first MAC address is read from the fuses.

The second MAC address is not read and Linux assigns a random one.

To prevent this behavior, read the second MAC address from the fuses
and store it into the eth1addr environment variable so that it
can be passed to Linux.

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 board/storopack/smegw01/smegw01.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/board/storopack/smegw01/smegw01.c b/board/storopack/smegw01/smegw01.c
index e648b196b9d..20c09700bf0 100644
--- a/board/storopack/smegw01/smegw01.c
+++ b/board/storopack/smegw01/smegw01.c
@@ -82,6 +82,7 @@ int board_init(void)
 int board_late_init(void)
 {
 	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+	unsigned char eth1addr[6];
 
 	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
 
@@ -93,6 +94,11 @@ int board_late_init(void)
 	 */
 	clrsetbits_le16(&wdog->wcr, 0, 0x10);
 
+	/* Get the second MAC address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!env_get("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_env_set_enetaddr("eth1addr", eth1addr);
+
 	return 0;
 }
 

From e13698bb669e70c511387051b62e025aabdc34af Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:04:59 -0300
Subject: [PATCH 21/24] smegw01: Disable additional boot menu options

Defaults have changed, we do not want the bootmenu to contain EFI
options.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/smegw01_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index ea25b3b87ce..fe8152f33e6 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -19,6 +19,8 @@ CONFIG_SYS_MEMTEST_END=0xa0000000
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_AUTOBOOT_MENU_SHOW=y
+# CONFIG_BOOTSTD is not set
+# CONFIG_CMD_BOOTEFI_BOOTMGR is not set
 CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; "

From fd20052662b53fa75b4ed3f7832b4dfe35ec75c5 Mon Sep 17 00:00:00 2001
From: Eduard Strehlau <eduard@lionizers.com>
Date: Wed, 26 Apr 2023 13:05:00 -0300
Subject: [PATCH 22/24] smegw01: Fix fallback to altbootcmd

The bootcmd/altbootcmd mechanism is not invoked for bootmenus.
Manually compare bootcount and bootlimit to implement fallback on all
codepaths.

Signed-off-by: Eduard Strehlau <eduard@lionizers.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
---
 configs/smegw01_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig
index fe8152f33e6..3d2713f5280 100644
--- a/configs/smegw01_defconfig
+++ b/configs/smegw01_defconfig
@@ -23,7 +23,7 @@ CONFIG_AUTOBOOT_MENU_SHOW=y
 # CONFIG_CMD_BOOTEFI_BOOTMGR is not set
 CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE=y
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; "
+CONFIG_BOOTCOMMAND="if test \"${bootcount}\" -gt \"${bootlimit}\"; then run altbootcmd; else if test \"${ustate}\" = 1; then setenv upgrade_available 1; saveenv; fi; run mmcboot; fi;"
 CONFIG_USE_PREBOOT=y
 CONFIG_PREBOOT="run setup_boot_menu;"
 CONFIG_HUSH_PARSER=y

From 61712787651bab960f43981de5cc05e07288e6b0 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <festevam@denx.de>
Date: Wed, 26 Apr 2023 13:05:01 -0300
Subject: [PATCH 23/24] smegw01: Convert CFG_EXTRA_ENV_SETTINGS to an env file

Currently, it is recommended to move from CFG_EXTRA_ENV_SETTINGS to
an env file, so do the conversion.

Suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
 board/storopack/smegw01/smegw01.env | 89 +++++++++++++++++++++++++++++
 include/configs/smegw01.h           | 68 ----------------------
 2 files changed, 89 insertions(+), 68 deletions(-)
 create mode 100644 board/storopack/smegw01/smegw01.env

diff --git a/board/storopack/smegw01/smegw01.env b/board/storopack/smegw01/smegw01.env
new file mode 100644
index 00000000000..25bc7cdbd28
--- /dev/null
+++ b/board/storopack/smegw01/smegw01.env
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0+
+#ifdef CONFIG_SYS_BOOT_LOCKED
+#define SETUP_BOOT_MENU setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd
+#else
+#define SETUP_BOOT_MENU setup_boot_menu= \
+			if test "${mmcdev}" = 1; then \
+				setenv emmc_priority 0; \
+				setenv sd_priority 1; \
+			else setenv emmc_priority 1; \
+				setenv sd_priority 0; \
+			fi; \
+			setenv bootmenu_${emmc_priority} eMMC=run boot_emmc; \
+			setenv bootmenu_${sd_priority} SD=run boot_sd;
+#endif
+
+altbootcmd=
+	echo Performing rollback...;
+	if test "${mmcpart_committed}" = 1; then
+		setenv mmcpart 2;
+		setenv mmcpart_committed 2;
+	else
+		setenv mmcpart 1;
+		setenv mmcpart_committed 1;
+	fi;
+	setenv bootcount 0;
+	setenv upgrade_available;
+	setenv ustate 3;
+	saveenv;
+	run bootcmd;
+boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;
+boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;
+bootcmd=run finduuid; run distro_bootcmd
+bootdelay=2
+bootlimit=3
+bootm_size=0x10000000
+commit_mmc=
+	if test "${ustate}" = 1 -a "${mmcpart}" != "${mmcpart_committed}"; then
+		setenv mmcpart_committed ${mmcpart};
+		saveenv;
+	fi;
+console=ttymxc0
+fdt_addr=0x83000000
+fdtfile=imx7d-smegw01.dtb
+fit_addr=0x88000000
+image=fitImage
+loadaddr=0x80800000
+loadbootpart=mmc partconf 1 boot_part
+loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} boot/${image}
+loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}
+mmcargs=
+	setenv bootargs console=${console},${baudrate} root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}
+mmcboot=
+	echo Booting...;
+	echo mmcdev: ${mmcdev};
+	run commit_mmc;
+	echo mmcpart: ${mmcpart_committed};
+	run loadpart;
+	echo gptpart: ${gpt_partition_entry};
+	run loadbootpart;
+	if run loadimage; then
+		;
+	else
+		run altbootcmd;
+	fi;
+	run mmcargs;
+	if bootm ${fit_addr}; then
+		;
+	else
+		run altbootcmd;
+	fi;
+mmcdev=1
+mmcpart=1
+mmcpart_committed=1
+persist_mmcdev=
+	if test "${mmcdev}" != "${mmcdev_wanted}"; then
+		setenv mmcdev "${mmcdev_wanted}";
+		saveenv;
+	fi;
+setup_boot_menu=
+	if test "${mmcdev}" = 1; then
+		setenv emmc_priority 0;
+		setenv sd_priority 1;
+	else
+		setenv emmc_priority 1;
+		setenv sd_priority 0;
+	fi;
+	setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;
+	setenv bootmenu_${sd_priority} SD=run boot_sd;
+SETUP_BOOT_MENU
diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h
index 6f373973ab8..0aa25f9e2ea 100644
--- a/include/configs/smegw01.h
+++ b/include/configs/smegw01.h
@@ -24,19 +24,8 @@
 
 #ifdef CONFIG_SYS_BOOT_LOCKED
 #define EXTRA_ENV_FLAGS
-#define SETUP_BOOT_MENU "setup_boot_menu=setenv bootmenu_0 eMMC=run bootcmd\0"
 #else
 #define EXTRA_ENV_FLAGS "mmcdev:dw,"
-#define SETUP_BOOT_MENU "setup_boot_menu=" \
-	"if test \"${mmcdev}\" = 1; then " \
-		"setenv emmc_priority 0;" \
-		"setenv sd_priority 1;" \
-	"else " \
-		"setenv emmc_priority 1;" \
-		"setenv sd_priority 0;" \
-	"fi;" \
-	"setenv bootmenu_${emmc_priority} eMMC=run boot_emmc;" \
-	"setenv bootmenu_${sd_priority} SD=run boot_sd;\0"
 #endif
 
 #define CFG_ENV_FLAGS_LIST_STATIC \
@@ -48,63 +37,6 @@
 	"upgrade_available:dw," \
 	EXTRA_ENV_FLAGS
 
-#define CFG_EXTRA_ENV_SETTINGS \
-	"image=fitImage\0" \
-	"console=ttymxc0\0" \
-	"fdtfile=imx7d-smegw01.dtb\0" \
-	"fdt_addr=0x83000000\0" \
-	"bootm_size=0x10000000\0" \
-	"mmcdev=1\0" \
-	"mmcpart=1\0" \
-	"mmcpart_committed=1\0" \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=/dev/mmcblk${mmcdev}p${gpt_partition_entry} rootwait rw " \
-		__stringify(EXTRA_BOOTPARAMS) " SM_ROOT_DEV=${mmcdev} SM_ROOT_PART=${gpt_partition_entry} SM_BOOT_PART=${boot_part}\0" \
-	"commit_mmc=if test \"${ustate}\" = 1 -a \"${mmcpart}\" != \"${mmcpart_committed}\"; then " \
-	              "setenv mmcpart_committed ${mmcpart};" \
-								"saveenv;" \
-						  "fi;\0" \
-	"bootlimit=3\0" \
-	"fit_addr=0x88000000\0" \
-	"loadimage=load mmc ${mmcdev}:${gpt_partition_entry} ${fit_addr} boot/${image}\0" \
-	"loadpart=gpt setenv mmc ${mmcdev} rootfs-${mmcpart_committed}\0" \
-	"loadbootpart=mmc partconf 1 boot_part\0" \
-	"boot_sd=setenv mmcdev_wanted 0; run persist_mmcdev; run bootcmd;\0" \
-	"boot_emmc=setenv mmcdev_wanted 1; run persist_mmcdev; run bootcmd;\0" \
-	"persist_mmcdev=" \
-		"if test \"${mmcdev}\" != \"${mmcdev_wanted}\"; then " \
-			"setenv mmcdev \"${mmcdev_wanted}\";" \
-			"saveenv;" \
-		"fi;\0" \
-	"mmcboot=echo Booting...; " \
-		"echo mmcdev: ${mmcdev}; " \
-	  "run commit_mmc; " \
-		"echo mmcpart: ${mmcpart_committed}; " \
-		"run loadpart; " \
-		"echo gptpart: ${gpt_partition_entry}; " \
-		"run loadbootpart; " \
-		"if run loadimage; then " \
-			"; " \
-		"else " \
-			"run altbootcmd; " \
-		"fi; " \
-		"run mmcargs; " \
-		"if bootm ${fit_addr}; then " \
-			"; " \
-		"else " \
-			"run altbootcmd; " \
-		"fi;\0" \
-	"altbootcmd=echo Performing rollback...; " \
-		"if test \"${mmcpart_committed}\" = 1; then " \
-			"setenv mmcpart 2; " \
-			"setenv mmcpart_committed 2;" \
-		"else " \
-			"setenv mmcpart 1; " \
-			"setenv mmcpart_committed 1;" \
-		"fi; setenv bootcount 0; setenv upgrade_available; setenv ustate 3; saveenv; " \
-		"run bootcmd;\0" \
-		SETUP_BOOT_MENU
-
 /* Physical Memory Map */
 #define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
 

From bb6ea0fe9290b4d64df8e716b58515b5325c2ea5 Mon Sep 17 00:00:00 2001
From: Tim Harvey <tharvey@gateworks.com>
Date: Fri, 28 Apr 2023 11:50:30 -0700
Subject: [PATCH 24/24] usb: ehci-mx6: move phy setup before register access

For the CONFIG_PHY case, move the PHY setup before the register access.

This avoids a hang when updating the imx8mm.dtsi which moves the
USB OTG power-domains to the PHY.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Fabio Estevam <festevam@denx.de>
---
 drivers/usb/host/ehci-mx6.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 91633f013a5..fae20838c60 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -703,6 +703,10 @@ static int ehci_usb_probe(struct udevice *dev)
 	usb_internal_phy_clock_gate(priv->phy_addr, 1);
 	usb_phy_enable(ehci, priv->phy_addr);
 #endif
+#else
+	ret = generic_setup_phy(dev, &priv->phy, 0);
+	if (ret)
+		goto err_regulator;
 #endif
 
 #if CONFIG_IS_ENABLED(DM_REGULATOR)
@@ -725,12 +729,6 @@ static int ehci_usb_probe(struct udevice *dev)
 
 	mdelay(10);
 
-#if defined(CONFIG_PHY)
-	ret = generic_setup_phy(dev, &priv->phy, 0);
-	if (ret)
-		goto err_regulator;
-#endif
-
 	hccr = (struct ehci_hccr *)((uintptr_t)&ehci->caplength);
 	hcor = (struct ehci_hcor *)((uintptr_t)hccr +
 			HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));