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integrator: rewrite the AP PCI driver
The PCI support for the Integrator AP has apparently never been finished and I strongly suspect that it has never worked, so let's fix it. This is a list of the more or less un-splittable changes done in this driver rewrite: - Replace the register definitions stashed into the config file (!) with a copy if the register file from the Linux kernels arch/arm/include/asm/hardware/pci_v3.h - Delete the unreadable gigantic macros that perform the config accesses and replace them with copyedited code from Linux arch/arm/mach-integrator/pci_v3.c - Rewrite the rest of the setup code to use the v3_[read|write][lwb]() accessors. - Enable PCI by default in the AP board configuration. - Fix checkpatch warnings and make code more conformant. Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
committed by
Albert ARIBAUD
Albert ARIBAUD
parent
4ae6a91a86
commit
2458716a5b
@@ -82,17 +82,7 @@
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_IMLS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADS
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#include <config_cmd_default.h>
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty"
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@@ -157,142 +147,16 @@
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* PCI definitions
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*/
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#ifdef CONFIG_PCI /* pci support */
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#undef CONFIG_PCI_PNP
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#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
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#define DEBUG
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#define CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_NET_MULTI
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#define CONFIG_TULIP
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#define CONFIG_EEPRO100
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#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
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#define INTEGRATOR_BOOT_ROM_BASE 0x20000000
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#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000
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/* PCI Base area */
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#define INTEGRATOR_PCI_BASE 0x40000000
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#define INTEGRATOR_PCI_SIZE 0x3FFFFFFF
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/* memory map as seen by the CPU on the local bus */
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#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */
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#define CPU_PCI_IO_SIZE 0x10000
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#define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */
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#define CPU_PCI_CNFG_SIZE 0x1000000
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#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */
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/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */
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#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */
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/* unused (128-16)M from B1000000-B7FFFFFF */
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#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */
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/* unused ((128-16)M - 64K) from XXX */
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#define PCI_V3_BASE 0x62000000
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/* V3 PCI bridge controller */
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#define V3_BASE 0x62000000 /* V360EPC registers */
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#define PCI_ENET0_IOADDR (CPU_PCI_IO_ADRS)
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#define PCI_ENET0_MEMADDR (PCI_MEM_BASE)
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#define V3_PCI_VENDOR 0x00000000
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#define V3_PCI_DEVICE 0x00000002
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#define V3_PCI_CMD 0x00000004
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#define V3_PCI_STAT 0x00000006
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#define V3_PCI_CC_REV 0x00000008
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#define V3_PCI_HDR_CF 0x0000000C
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#define V3_PCI_IO_BASE 0x00000010
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#define V3_PCI_BASE0 0x00000014
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#define V3_PCI_BASE1 0x00000018
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#define V3_PCI_SUB_VENDOR 0x0000002C
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#define V3_PCI_SUB_ID 0x0000002E
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#define V3_PCI_ROM 0x00000030
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#define V3_PCI_BPARAM 0x0000003C
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#define V3_PCI_MAP0 0x00000040
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#define V3_PCI_MAP1 0x00000044
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#define V3_PCI_INT_STAT 0x00000048
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#define V3_PCI_INT_CFG 0x0000004C
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#define V3_LB_BASE0 0x00000054
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#define V3_LB_BASE1 0x00000058
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#define V3_LB_MAP0 0x0000005E
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#define V3_LB_MAP1 0x00000062
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#define V3_LB_BASE2 0x00000064
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#define V3_LB_MAP2 0x00000066
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#define V3_LB_SIZE 0x00000068
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#define V3_LB_IO_BASE 0x0000006E
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#define V3_FIFO_CFG 0x00000070
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#define V3_FIFO_PRIORITY 0x00000072
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#define V3_FIFO_STAT 0x00000074
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#define V3_LB_ISTAT 0x00000076
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#define V3_LB_IMASK 0x00000077
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#define V3_SYSTEM 0x00000078
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#define V3_LB_CFG 0x0000007A
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#define V3_PCI_CFG 0x0000007C
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#define V3_DMA_PCI_ADR0 0x00000080
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#define V3_DMA_PCI_ADR1 0x00000090
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#define V3_DMA_LOCAL_ADR0 0x00000084
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#define V3_DMA_LOCAL_ADR1 0x00000094
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#define V3_DMA_LENGTH0 0x00000088
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#define V3_DMA_LENGTH1 0x00000098
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#define V3_DMA_CSR0 0x0000008B
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#define V3_DMA_CSR1 0x0000009B
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#define V3_DMA_CTLB_ADR0 0x0000008C
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#define V3_DMA_CTLB_ADR1 0x0000009C
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#define V3_DMA_DELAY 0x000000E0
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#define V3_MAIL_DATA 0x000000C0
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#define V3_PCI_MAIL_IEWR 0x000000D0
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#define V3_PCI_MAIL_IERD 0x000000D2
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#define V3_LB_MAIL_IEWR 0x000000D4
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#define V3_LB_MAIL_IERD 0x000000D6
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#define V3_MAIL_WR_STAT 0x000000D8
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#define V3_MAIL_RD_STAT 0x000000DA
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#define V3_QBA_MAP 0x000000DC
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/* SYSTEM register bits */
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#define V3_SYSTEM_M_RST_OUT (1 << 15)
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#define V3_SYSTEM_M_LOCK (1 << 14)
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/* PCI_CFG bits */
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#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
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#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
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#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
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/* PCI MAP register bits (PCI -> Local bus) */
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#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
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#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
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#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10)
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#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8)
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#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
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#define V3_PCI_MAP_M_REG_EN (1 << 1)
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#define V3_PCI_MAP_M_ENABLE (1 << 0)
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/* 9 => 512M window size */
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#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090
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/* A => 1024M window size */
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#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0
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/* LB_BASE register bits (Local bus -> PCI) */
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#define V3_LB_BASE_M_MAP_ADR 0xFFF00000
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#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9)
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#define V3_LB_BASE_M_ADR_SIZE 0x000000F0
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#define V3_LB_BASE_M_PREFETCH (1 << 3)
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#define V3_LB_BASE_M_ENABLE (1 << 0)
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/* PCI COMMAND REGISTER bits */
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#define V3_COMMAND_M_FBB_EN (1 << 9)
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#define V3_COMMAND_M_SERR_EN (1 << 8)
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#define V3_COMMAND_M_PAR_EN (1 << 6)
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#define V3_COMMAND_M_MASTER_EN (1 << 2)
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#define V3_COMMAND_M_MEM_EN (1 << 1)
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#define V3_COMMAND_M_IO_EN (1 << 0)
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#define INTEGRATOR_SC_BASE 0x11000000
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#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
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#define INTEGRATOR_SC_PCIENABLE \
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(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
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#endif /* CONFIG_PCI */
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/*-----------------------------------------------------------------------
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* There are various dependencies on the core module (CM) fitted
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* Users should refer to their CM user guide
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