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Merge tag 'xilinx-for-v2022.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

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Xilinx changes for v2022.04-rc3

microblaze:
- Fix exception handler

zynqmp:
- Show information about secure images
- DT changes (som u-boot file removal)
- Fix zynqmp_pm_cfg_obj_convert.py
- Fix platform boot

xilinx:
- Fix bootm_size calculation
- Remove GPIO_EXTRA_HEADER selection

power:
- Add zynqmp power management driver

scsi:
- Add phy support to ceva driver

zynq qspi:
- Fix unaligned accesses and check baudrate setup
- Add support for spi memory operations

net:
- Fix 64bit calculation in axi_emac

video:
- Add missing gpio dependency for seps driver
This commit is contained in:
Tom Rini
2022-02-21 08:32:02 -05:00
parent 55e9cef143 9bd4232f95
commit 24b628a8f8
34 changed files with 495 additions and 130 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
include/configs/microblaze-generic.h
View File

@@ -11,9 +11,6 @@
/* Microblaze is microblaze_0 */
#define XILINX_FSL_NUMBER 3
/* MicroBlaze CPU */
#define MICROBLAZE_V5 1
#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024)
/* uart */

47
include/zynqmp_firmware.h
View File

@@ -342,20 +342,20 @@ enum pm_ioctl_id {
IOCTL_AIE_ISR_CLEAR = 24,
};
#define PM_SIP_SVC 0xc2000000
#define PM_SIP_SVC 0xc2000000
#define ZYNQMP_PM_VERSION_MAJOR 1
#define ZYNQMP_PM_VERSION_MINOR 0
#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
#define ZYNQMP_PM_VERSION_MAJOR 1
#define ZYNQMP_PM_VERSION_MINOR 0
#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
#define ZYNQMP_PM_VERSION \
((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
ZYNQMP_PM_VERSION_MINOR)
#define ZYNQMP_PM_VERSION_INVALID ~0
#define ZYNQMP_PM_VERSION_INVALID ~0
#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
#define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0)
/*
* Return payload size
@@ -367,8 +367,41 @@ enum pm_ioctl_id {
#define PAYLOAD_ARG_CNT 5U
unsigned int zynqmp_firmware_version(void);
int zynqmp_pmufw_node(u32 id);
int zynqmp_pmufw_config_close(void);
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
/* Type of Config Object */
#define PM_CONFIG_OBJECT_TYPE_BASE 0x1U
#define PM_CONFIG_OBJECT_TYPE_OVERLAY 0x2U
/* Section Id */
#define PM_CONFIG_SLAVE_SECTION_ID 0x102U
#define PM_CONFIG_SET_CONFIG_SECTION_ID 0x107U
/* Flag Option */
#define PM_SLAVE_FLAG_IS_SHAREABLE 0x1U
#define PM_MASTER_USING_SLAVE_MASK 0x2U
/* IPI Mask for Master */
#define PM_CONFIG_IPI_PSU_CORTEXA53_0_MASK 0x00000001
#define PM_CONFIG_IPI_PSU_CORTEXR5_0_MASK 0x00000100
#define PM_CONFIG_IPI_PSU_CORTEXR5_1_MASK 0x00000200
enum zynqmp_pm_request_ack {
ZYNQMP_PM_REQUEST_ACK_NO = 1,
ZYNQMP_PM_REQUEST_ACK_BLOCKING = 2,
ZYNQMP_PM_REQUEST_ACK_NON_BLOCKING = 3,
};
/* Node capabilities */
#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
#define ZYNQMP_PM_MAX_QOS 100U
#endif /* _ZYNQMP_FIRMWARE_H_ */