dm: video: Repurpose the 'displayport' uclass to 'display'

The current DisplayPort uclass is too specific. The operations it provides
are shared with other types of output devices, such as HDMI and LVDS LCD
displays.

Generalise the uclass so that it can be used with these devices as well.
Adjust the uclass to handle the EDID reading and conversion to
display_timing internally.

Also update nyan-big which is affected by this.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
2016-01-21 19:45:00 -07:00
parent cd9c2070ea
commit 2dcf143398
10 changed files with 95 additions and 71 deletions

View File

@@ -25,7 +25,7 @@ CONFIG_TEGRA114_SPI=y
CONFIG_TPM_TIS_INFINEON=y CONFIG_TPM_TIS_INFINEON=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_DM_USB=y CONFIG_DM_USB=y
CONFIG_DISPLAY_PORT=y CONFIG_DISPLAY=y
CONFIG_VIDEO_TEGRA124=y CONFIG_VIDEO_TEGRA124=y
CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_TPM=y CONFIG_TPM=y

View File

@@ -293,12 +293,15 @@ config VIDEO_LCD_SPI_MISO
option takes a string in the format understood by 'name_to_gpio' option takes a string in the format understood by 'name_to_gpio'
function, e.g. PH1 for pin 1 of port H. function, e.g. PH1 for pin 1 of port H.
config DISPLAY_PORT config DISPLAY
bool "Enable DisplayPort support" bool "Enable Display support"
depends on DM
default y
help help
eDP (Embedded DisplayPort) is a standard widely used in laptops This supports drivers that provide a display, such as eDP (Embedded
to drive LCD panels. This framework provides support for enabling DisplayPort) and HDMI (High Definition Multimedia Interface).
these displays where supported by the video hardware. The devices provide a simple interface to start up the display,
read display information and enable it.
config VIDEO_SANDBOX_SDL config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL" bool "Enable sandbox video console using SDL"

View File

@@ -6,7 +6,7 @@
# #
ifdef CONFIG_DM ifdef CONFIG_DM
obj-$(CONFIG_DISPLAY_PORT) += dp-uclass.o obj-$(CONFIG_DISPLAY) += display-uclass.o
obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o obj-$(CONFIG_DM_VIDEO) += panel-uclass.o simple_panel.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o console_normal.o

View File

@@ -0,0 +1,52 @@
/*
* Copyright 2014 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <display.h>
#include <edid.h>
#include <errno.h>
int display_read_edid(struct udevice *dev, u8 *buf, int buf_size)
{
struct dm_display_ops *ops = display_get_ops(dev);
if (!ops || !ops->read_edid)
return -ENOSYS;
return ops->read_edid(dev, buf, buf_size);
}
int display_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing)
{
struct dm_display_ops *ops = display_get_ops(dev);
if (!ops || !ops->enable)
return -ENOSYS;
return ops->enable(dev, panel_bpp, timing);
}
int display_read_timing(struct udevice *dev, struct display_timing *timing)
{
struct dm_display_ops *ops = display_get_ops(dev);
int panel_bits_per_colour;
u8 buf[EDID_EXT_SIZE];
int ret;
if (!ops || !ops->read_edid)
return -ENOSYS;
ret = ops->read_edid(dev, buf, sizeof(buf));
if (ret < 0)
return ret;
return edid_get_timing(buf, ret, timing, &panel_bits_per_colour);
}
UCLASS_DRIVER(display) = {
.id = UCLASS_DISPLAY,
.name = "display",
.per_device_platdata_auto_alloc_size = sizeof(struct display_plat),
};

View File

@@ -1,34 +0,0 @@
/*
* Copyright 2014 Google Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <displayport.h>
#include <errno.h>
int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size)
{
struct dm_display_port_ops *ops = display_port_get_ops(dev);
if (!ops || !ops->read_edid)
return -ENOSYS;
return ops->read_edid(dev, buf, buf_size);
}
int display_port_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing)
{
struct dm_display_port_ops *ops = display_port_get_ops(dev);
if (!ops || !ops->enable)
return -ENOSYS;
return ops->enable(dev, panel_bpp, timing);
}
UCLASS_DRIVER(display_port) = {
.id = UCLASS_DISPLAY_PORT,
.name = "display_port",
};

View File

@@ -10,7 +10,7 @@
#include <dm.h> #include <dm.h>
#include <edid.h> #include <edid.h>
#include <errno.h> #include <errno.h>
#include <displayport.h> #include <display.h>
#include <edid.h> #include <edid.h>
#include <fdtdec.h> #include <fdtdec.h>
#include <lcd.h> #include <lcd.h>
@@ -324,20 +324,12 @@ static int display_update_config_from_edid(struct udevice *dp_dev,
int *panel_bppp, int *panel_bppp,
struct display_timing *timing) struct display_timing *timing)
{ {
u8 buf[EDID_SIZE]; int ret;
int bpc, ret;
ret = display_port_read_edid(dp_dev, buf, sizeof(buf)); ret = display_read_timing(dp_dev, timing);
if (ret < 0)
return ret;
ret = edid_get_timing(buf, ret, timing, &bpc);
if (ret) if (ret)
return ret; return ret;
/* Use this information if valid */
if (bpc != -1)
*panel_bppp = bpc * 3;
return 0; return 0;
} }
@@ -398,7 +390,7 @@ int display_init(void *lcdbase, int fb_bits_per_pixel,
int node; int node;
int ret; int ret;
ret = uclass_get_device(UCLASS_DISPLAY_PORT, 0, &dp_dev); ret = uclass_get_device(UCLASS_DISPLAY, 0, &dp_dev);
if (ret) if (ret)
return ret; return ret;
@@ -450,7 +442,7 @@ int display_init(void *lcdbase, int fb_bits_per_pixel,
} }
/* Enable dp */ /* Enable dp */
ret = display_port_enable(dp_dev, panel_bpp, timing); ret = display_enable(dp_dev, panel_bpp, timing);
if (ret) if (ret)
return ret; return ret;

View File

@@ -6,16 +6,17 @@
*/ */
#include <common.h> #include <common.h>
#include <displayport.h> #include <display.h>
#include <dm.h> #include <dm.h>
#include <div64.h> #include <div64.h>
#include <errno.h> #include <errno.h>
#include <fdtdec.h> #include <fdtdec.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch-tegra/dc.h> #include <asm/arch-tegra/dc.h>
#include "displayport.h" #include "display.h"
#include "edid.h" #include "edid.h"
#include "sor.h" #include "sor.h"
#include "displayport.h"
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@@ -1573,7 +1574,7 @@ static int tegra_dp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
buf_size, &aux_stat); buf_size, &aux_stat);
} }
static const struct dm_display_port_ops dp_tegra_ops = { static const struct dm_display_ops dp_tegra_ops = {
.read_edid = tegra_dp_read_edid, .read_edid = tegra_dp_read_edid,
.enable = tegra_dp_enable, .enable = tegra_dp_enable,
}; };
@@ -1596,7 +1597,7 @@ static const struct udevice_id tegra_dp_ids[] = {
U_BOOT_DRIVER(dp_tegra) = { U_BOOT_DRIVER(dp_tegra) = {
.name = "dpaux_tegra", .name = "dpaux_tegra",
.id = UCLASS_DISPLAY_PORT, .id = UCLASS_DISPLAY,
.of_match = tegra_dp_ids, .of_match = tegra_dp_ids,
.ofdata_to_platdata = tegra_dp_ofdata_to_platdata, .ofdata_to_platdata = tegra_dp_ofdata_to_platdata,
.probe = dp_tegra_probe, .probe = dp_tegra_probe,

View File

@@ -4,21 +4,31 @@
* SPDX-License-Identifier: GPL-2.0+ * SPDX-License-Identifier: GPL-2.0+
*/ */
#ifndef _DISPLAYPORT_H #ifndef _DISPLAY_H
#define _DISPLAYPORT_H #define _DISPLAY_H
struct udevice; struct udevice;
struct display_timing; struct display_timing;
/** /**
* display_port_read_edid() - Read information from EDID * Display uclass platform data for each device
*
* @source_id: ID for the source of the display data, typically a video
* controller
* @src_dev: Source device providing the video
*/
struct display_plat {
int source_id;
struct udevice *src_dev;
};
/**
* display_read_timing() - Read timing information from EDID
* *
* @dev: Device to read from * @dev: Device to read from
* @buf: Buffer to read into (should be EDID_SIZE bytes) * @return 0 if OK, -ve on error
* @buf_size: Buffer size (should be EDID_SIZE)
* @return number of bytes read, <=0 for error
*/ */
int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size); int display_read_timing(struct udevice *dev, struct display_timing *timing);
/** /**
* display_port_enable() - Enable a display port device * display_port_enable() - Enable a display port device
@@ -28,10 +38,10 @@ int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size);
* @timing: Display timings * @timing: Display timings
* @return 0 if OK, -ve on error * @return 0 if OK, -ve on error
*/ */
int display_port_enable(struct udevice *dev, int panel_bpp, int display_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing); const struct display_timing *timing);
struct dm_display_port_ops { struct dm_display_ops {
/** /**
* read_edid() - Read information from EDID * read_edid() - Read information from EDID
* *
@@ -54,7 +64,6 @@ struct dm_display_port_ops {
const struct display_timing *timing); const struct display_timing *timing);
}; };
#define display_port_get_ops(dev) \ #define display_get_ops(dev) ((struct dm_display_ops *)(dev)->driver->ops)
((struct dm_display_port_ops *)(dev)->driver->ops)
#endif #endif

View File

@@ -29,7 +29,7 @@ enum uclass_id {
UCLASS_CLK, /* Clock source, e.g. used by peripherals */ UCLASS_CLK, /* Clock source, e.g. used by peripherals */
UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */ UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DISPLAY_PORT, /* Display port video */ UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
UCLASS_RAM, /* RAM controller */ UCLASS_RAM, /* RAM controller */
UCLASS_ETH, /* Ethernet device */ UCLASS_ETH, /* Ethernet device */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */

View File

@@ -17,6 +17,7 @@
/* Size of the EDID data */ /* Size of the EDID data */
#define EDID_SIZE 128 #define EDID_SIZE 128
#define EDID_EXT_SIZE 256
#define GET_BIT(_x, _pos) \ #define GET_BIT(_x, _pos) \
(((_x) >> (_pos)) & 1) (((_x) >> (_pos)) & 1)