For 2023.04
-----------

- several conversion to DM_SERIAL and DM_I2C
- fixes for Toradex boards
- PSCI

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/14965
This commit is contained in:
Tom Rini
2023-02-01 09:30:52 -05:00
155 changed files with 4678 additions and 598 deletions

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@@ -9,57 +9,51 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#define CFG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5b010000
#define USDHC2_BASE_ADDR 0x5b020000
/* Networking */
#define MEM_LAYOUT_ENV_SETTINGS \
"fdt_addr_r=0x84000000\0" \
"kernel_addr_r=0x82000000\0" \
"ramdisk_addr_r=0x94400000\0" \
"scriptaddr=0x87000000\0"
"fdt_addr_r=0x9d400000\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_comp_addr_r=0xf0000000\0" \
"kernel_comp_size=0x08000000\0" \
"ramdisk_addr_r=0x9d500000\0" \
"scriptaddr=0x9d480000\0"
/* Boot M4 */
#define M4_BOOT_ENV \
"m4_0_image=m4_0.bin\0" \
"m4_1_image=m4_1.bin\0" \
"loadm4image_0=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
"loadm4image_1=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
"m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
/* Enable Distro Boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(MMC, mmc, 0) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#undef BOOTENV_RUN_NET_USB_START
#define BOOTENV_RUN_NET_USB_START ""
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS \
BOOTENV \
M4_BOOT_ENV \
MEM_LAYOUT_ENV_SETTINGS \
"boot_file=Image\0" \
"boot_script_dhcp=boot.scr\0" \
"console=ttyLP1 earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \
"fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"console=ttyLP1\0" \
"fdt_board=eval\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=PARTUUID=${uuid} rootwait " \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"panel=NULL\0" \
"script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"setup=setenv setupargs console=tty1 console=${console},${baudrate} " \
"consoleblank=0 earlycon\0" \
"update_uboot=askenv confirm Did you load flash.bin resp. u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \
"${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \
"${blkcnt}; fi\0"
/* Link Definitions */
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */
#define CFG_SYS_FSL_USDHC_NUM 3
#define CFG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000

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@@ -77,7 +77,6 @@
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"panel=NULL\0" \
"script=boot.scr\0" \
"update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \
"if test \"$confirm\" = \"y\"; then " \
"setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \

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@@ -0,0 +1,41 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#ifndef __IMX8MM_PHG_H
#define __IMX8MM_PHG_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#include <config_distro_bootcmd.h>
#define CFG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD
/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
#define CFG_MALLOC_F_ADDR 0x930000
#endif
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 1) \
func(MMC, mmc, 2) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
/* Initial environment variables */
#define CFG_EXTRA_ENV_SETTINGS BOOTENV
/* Link Definitions */
#define CFG_SYS_INIT_RAM_ADDR 0x40000000
#define CFG_SYS_INIT_RAM_SIZE 0x200000
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
#endif

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@@ -46,9 +46,11 @@
#define CFG_SYS_INIT_RAM_SIZE 0x80000
/* Totally 2GB DDR */
/* Totally 6GB DDR */
#define CFG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x80000000
#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
#define PHYS_SDRAM_2 0x100000000
#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
#endif

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@@ -21,8 +21,4 @@
#include <asm/arch/imx-regs.h>
#include <asm/mach-imx/gpio.h>
/* Miscellaneous configurable options */
/* MMC */
#endif

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@@ -16,16 +16,4 @@
/* Timer settings */
#define CFG_SC_TIMER_CLK 8000000 /* 8Mhz */
/* Miscellaneous configurable options */
/* UART */
/* MMC */
/*
* If we have defined the OPTEE ram size and not OPTEE it means that we were
* launched by OPTEE, because of that we shall skip all the low level
* initialization since it was already done by ATF or OPTEE
*/
#endif

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@@ -97,9 +97,6 @@
#define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* PMIC */
#define CFG_POWER_PFUZE3000_I2C_ADDR 0x08
/* FLASH and environment organization */
/* Environment starts at 768k = 768 * 1024 = 786432 */

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@@ -67,4 +67,8 @@ enum {
#define PCA9450_LDO34_MASK 0x1f
#define PCA9450_LDO5_MASK 0x0f
#define PCA9450_PMIC_RESET_WDOG_B_CFG_MASK 0xc0
#define PCA9450_PMIC_RESET_WDOG_B_CFG_WARM 0x40
#define PCA9450_PMIC_RESET_WDOG_B_CFG_COLD_LDO12 0x80
#endif