From ddb0f26dc45ff2f2528c5e11629c490308ccc708 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 1 Jan 2025 20:19:04 +0100 Subject: [PATCH 1/3] arm64: Convert core type check macros into inline functions Turn the core type check macros into inline functions to perform better type checking on them. The inline functions get optimized out in case they are not used. Indent the MIDR_PARTNUM_CORTEX_An macros in preparation for addition of future three-digit cores and use MIDR_PARTNUM_SHIFT in MIDR_PARTNUM_MASK to be consistent. Reviewed-by: Paul Barker Reviewed-by: Peter Robinson Signed-off-by: Marek Vasut --- arch/arm/include/asm/armv8/cpu.h | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index 40d54dc85ab..aa1470bb72d 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -3,11 +3,11 @@ * Copyright 2018 NXP */ -#define MIDR_PARTNUM_CORTEX_A35 0xD04 -#define MIDR_PARTNUM_CORTEX_A53 0xD03 -#define MIDR_PARTNUM_CORTEX_A72 0xD08 -#define MIDR_PARTNUM_SHIFT 0x4 -#define MIDR_PARTNUM_MASK (0xFFF << 0x4) +#define MIDR_PARTNUM_CORTEX_A35 0xD04 +#define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_SHIFT 0x4 +#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) static inline unsigned int read_midr(void) { @@ -18,9 +18,15 @@ static inline unsigned int read_midr(void) return val; } -#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35) -#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53) -#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\ - MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72) +#define is_cortex_a(__n) \ + static inline int is_cortex_a##__n(void) \ + { \ + unsigned int midr = read_midr(); \ + midr &= MIDR_PARTNUM_MASK; \ + midr >>= MIDR_PARTNUM_SHIFT; \ + return midr == MIDR_PARTNUM_CORTEX_A##__n; \ + } + +is_cortex_a(35) +is_cortex_a(53) +is_cortex_a(72) From 2fca3cf79970e6a8bb55bcd73f62a36fda2ffb2e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 1 Jan 2025 20:19:05 +0100 Subject: [PATCH 2/3] arm64: Add MIDR entries for Cortex-A57 and Cortex-A76 Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively. Reviewed-by: Paul Barker Reviewed-by: Peter Robinson Signed-off-by: Marek Vasut --- arch/arm/include/asm/armv8/cpu.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/include/asm/armv8/cpu.h b/arch/arm/include/asm/armv8/cpu.h index aa1470bb72d..4dbb589aab8 100644 --- a/arch/arm/include/asm/armv8/cpu.h +++ b/arch/arm/include/asm/armv8/cpu.h @@ -5,7 +5,9 @@ #define MIDR_PARTNUM_CORTEX_A35 0xD04 #define MIDR_PARTNUM_CORTEX_A53 0xD03 +#define MIDR_PARTNUM_CORTEX_A57 0xD07 #define MIDR_PARTNUM_CORTEX_A72 0xD08 +#define MIDR_PARTNUM_CORTEX_A76 0xD0B #define MIDR_PARTNUM_SHIFT 0x4 #define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT) @@ -29,4 +31,6 @@ static inline unsigned int read_midr(void) is_cortex_a(35) is_cortex_a(53) +is_cortex_a(57) is_cortex_a(72) +is_cortex_a(76) From 46a7999160da3167497e08a444417aea26171197 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 1 Jan 2025 20:19:06 +0100 Subject: [PATCH 3/3] arm64: renesas: Convert boards over to is_cortex_a() functions Use generic is_cortex_a() functions instead of open-coded midr_el1 read. No functional change. Reviewed-by: Paul Barker Signed-off-by: Marek Vasut --- board/hoperun/hihope-rzg2/hihope-rzg2.c | 8 ++------ board/renesas/rcar-common/gen3-common.c | 10 +++------- 2 files changed, 5 insertions(+), 13 deletions(-) diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 8b635ef71ac..d2c5aaacf66 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -6,6 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation */ +#include #include #include #include @@ -66,12 +67,7 @@ int board_init(void) void reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); else writel(RST_CA57_CODE, RST_CA57RESCNT); diff --git a/board/renesas/rcar-common/gen3-common.c b/board/renesas/rcar-common/gen3-common.c index 4291e1d5bcb..004feca6180 100644 --- a/board/renesas/rcar-common/gen3-common.c +++ b/board/renesas/rcar-common/gen3-common.c @@ -7,6 +7,7 @@ * Copyright (C) 2015 Nobuhiro Iwamatsu */ +#include #include #include #include @@ -50,14 +51,9 @@ int fdtdec_board_setup(const void *fdt_blob) void __weak reset_cpu(void) { - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) + if (is_cortex_a53()) writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) + else if (is_cortex_a57()) writel(RST_CA57_CODE, RST_CA57RESCNT); else hang();