From a7670e6c5b0e90039ec71e2377f37ef5a5ad5ded Mon Sep 17 00:00:00 2001 From: Venkatesh Yadav Abbarapu Date: Thu, 6 Feb 2025 14:45:33 +0530 Subject: [PATCH 1/5] clk: versal: Update the reference clocks as per bindings As per the bindings the reference clocks naming has changed from "pl_alt_ref_clk" to "pl_alt_ref" and "ref_clk" to "ref". Update the same in the clock driver. Also add the fallback option for older DT bindings. Signed-off-by: Venkatesh Yadav Abbarapu Link: https://lore.kernel.org/r/20250206091533.1447234-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek --- drivers/clk/clk_versal.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 35ee56d0693..3e471670a87 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -679,12 +679,21 @@ static int versal_clk_probe(struct udevice *dev) debug("%s\n", __func__); - ret = versal_clock_get_freq_by_name("pl_alt_ref_clk", + ret = versal_clock_get_freq_by_name("pl_alt_ref", dev, &pl_alt_ref_clk); + if (ret == -ENODATA) { + /* Fallback to old DT binding clk name "pl_alt_ref_clk" */ + ret = versal_clock_get_freq_by_name("pl_alt_ref_clk", + dev, &pl_alt_ref_clk); + } if (ret < 0) return -EINVAL; - ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk); + ret = versal_clock_get_freq_by_name("ref", dev, &ref_clk); + if (ret == -ENODATA) { + /* Fallback to old DT binding clk name "ref_clk" */ + ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk); + } if (ret < 0) return -EINVAL; From e2ef5ff765c9603ba4232c9f85f898ad34162069 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 7 Feb 2025 07:43:23 +0100 Subject: [PATCH 2/5] xilinx: zynq: Guard code around SPL_FS_LOAD_PAYLOAD_NAME Guard code around CONFIG_SPL_FS_LOAD_PAYLOAD_NAME usage to avoid compilation failure. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/f15a9762494945814b06a71db90ee4db59dd17ed.1738910601.git.michal.simek@amd.com --- board/xilinx/zynq/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index a852d5b8ed5..8dbfa560423 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -179,6 +179,7 @@ void set_dfu_alt_info(char *interface, char *devstr) memset(buf, 0, sizeof(buf)); switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { +#if defined(CONFIG_SPL_FS_LOAD_PAYLOAD_NAME) case ZYNQ_BM_SD: snprintf(buf, DFU_ALT_BUF_LEN, "mmc 0=boot.bin fat 0 1;" @@ -192,6 +193,7 @@ void set_dfu_alt_info(char *interface, char *devstr) CONFIG_SPL_FS_LOAD_PAYLOAD_NAME, CONFIG_SYS_SPI_U_BOOT_OFFS); break; +#endif #endif default: return; From 96f47ae89a4ce16a59c14d229ff707bdeb1064f4 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Tue, 18 Feb 2025 10:54:19 +0530 Subject: [PATCH 3/5] clk: versal: Store driver data in data section Line 171 in README is describing that before relocation no code should use global variable because global variables are placed to BSS section which is initialized to 0 after relocation. On Versal platforms clock driver is initialized before relocation (via using dm,bootph-all flag in DT) and global variables are initialized which works if this is used only before relocation. But the variables are used after relocation too but values are zeroed which is ending up incorrect behavior. That's why place variables to data section to ensure that values are not cleared which is for now the quickest temporary solution. The correct way to do it is to move all global variables to private data to avoid it. Signed-off-by: Padmarao Begari Link: https://lore.kernel.org/r/20250218052419.1141139-1-padmarao.begari@amd.com Signed-off-by: Michal Simek --- drivers/clk/clk_versal.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c index 3e471670a87..cb98f34b5ec 100644 --- a/drivers/clk/clk_versal.c +++ b/drivers/clk/clk_versal.c @@ -106,8 +106,8 @@ struct versal_clk_priv { struct versal_clock *clk; }; -static ulong pl_alt_ref_clk; -static ulong ref_clk; +static ulong pl_alt_ref_clk __section(".data"); +static ulong ref_clk __section(".data"); struct versal_pm_query_data { u32 qid; @@ -116,8 +116,8 @@ struct versal_pm_query_data { u32 arg3; }; -static struct versal_clock *clock; -static unsigned int clock_max_idx; +static struct versal_clock *clock __section(".data"); +static unsigned int clock_max_idx __section(".data"); #define PM_QUERY_DATA 35 From f92623704e58e80814c087a10d0ee385221df20b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 18 Feb 2025 13:43:07 +0100 Subject: [PATCH 4/5] arm64: versal2: Show major and minor silicon version ES1 silicon is 0x10 (16) and production is 0x20 (32) but correct number to see are v1.0 or v2.0 instead of v16 or v32. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20095339334fe07f373ffae3bdbfec51f5a00dc7.1739882585.git.michal.simek@amd.com --- arch/arm/mach-versal2/include/mach/hardware.h | 3 ++- drivers/soc/soc_amd_versal2.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-versal2/include/mach/hardware.h b/arch/arm/mach-versal2/include/mach/hardware.h index 42e3061a0ae..15085f941e0 100644 --- a/arch/arm/mach-versal2/include/mach/hardware.h +++ b/arch/arm/mach-versal2/include/mach/hardware.h @@ -51,7 +51,8 @@ struct crp_regs { #define PMC_TAP_VERSION (PMC_TAP + 0x4) # define PMC_VERSION_MASK GENMASK(7, 0) # define PS_VERSION_MASK GENMASK(15, 8) -# define PS_VERSION_PRODUCTION 0x20 +# define PS_VERSION_MAJOR GENMASK(7, 4) +# define PS_VERSION_MINOR GENMASK(3, 0) # define RTL_VERSION_MASK GENMASK(23, 16) # define PLATFORM_MASK GENMASK(27, 24) # define PLATFORM_VERSION_MASK GENMASK(31, 28) diff --git a/drivers/soc/soc_amd_versal2.c b/drivers/soc/soc_amd_versal2.c index 66bcb22b4fa..8507da0bd22 100644 --- a/drivers/soc/soc_amd_versal2.c +++ b/drivers/soc/soc_amd_versal2.c @@ -35,7 +35,9 @@ static int soc_amd_versal2_get_revision(struct udevice *dev, char *buf, int size { struct soc_amd_versal2_priv *priv = dev_get_priv(dev); - return snprintf(buf, size, "v%d", priv->revision); + return snprintf(buf, size, "v%d.%d", + (u32)FIELD_GET(PS_VERSION_MAJOR, priv->revision), + (u32)FIELD_GET(PS_VERSION_MINOR, priv->revision)); } static const struct soc_ops soc_amd_versal2_ops = { From 8d2d615f14435c8d2d4e80509310691443b3a3d5 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Tue, 4 Mar 2025 10:00:30 +0530 Subject: [PATCH 5/5] xilinx: Remove tftp block size 4096 The zynqmp gem driver support max MTU size 1536, so remove tftp block size 4096 from defconfig and use default tftp block size. Fixes: a33b4b96b3cf ("xilinx: Enable MBEDTLS/LWIP/WGET and WGET_HTTPS") Signed-off-by: Padmarao Begari Link: https://lore.kernel.org/r/20250304043030.2344536-1-padmarao.begari@amd.com Signed-off-by: Michal Simek --- configs/amd_versal2_virt_defconfig | 1 - configs/xilinx_versal_net_virt_defconfig | 1 - configs/xilinx_versal_virt_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 8bee002777a..9911caa0e46 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -70,7 +70,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_CCF=y CONFIG_CLK_SCMI=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index 5ef5fd44fd3..1604b5915db 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -70,7 +70,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_RAM=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index f228eef7c95..baa4b8e412e 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -74,7 +74,6 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_TFTP_BLOCKSIZE=4096 CONFIG_SIMPLE_PM_BUS=y CONFIG_CLK_VERSAL=y CONFIG_DFU_TIMEOUT=y