From 380ddb473c6bdf87e66c0fb93e256d1e233c6f5b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 26 Jan 2026 10:28:32 -0600 Subject: [PATCH] arm: spl: Correct alignment of .rel.dyn section With commit 0535e46d55d7 ("scripts/dtc: Update to upstream version v1.7.2-35-g52f07dcca47c") we now require the correct, 8 byte alignment of a device tree in order to work with it ourselves. This has exposed a number of issues. In the case of using arch/arm/cpu/u-boot-spl.lds for an xPL phase and having the BSS be overlayed with the dynamic relocations sections (here, .rel.dyn) we had missed adding the comment about our asm memset requirements. Then, when adjusting ALIGN statements we later missed this one. In turn, when we use objcopy to create our binary image we end up in the situation where where the BSS must start out 8 byte aligned as well as end 8 byte aligned because for appended device tree the requirement is that the whole BSS (which we add as padding to the binary) must be 8 byte aligned. Otherwise we end up with the situation where __bss_end (where we look for the device tree at run time) is aligned but the size of the BSS we add Fixes: 7828a1eeb2a1 ("arm: remove redundant section alignments") Fixes: 52caad0d14a3 ("ARM: Align image end to 8 bytes to fit DT alignment") Reported-by: Fabio Estevam Tested-by: Fabio Estevam Signed-off-by: Tom Rini --- Cc: Ilias Apalodimas Cc: Marek Vasut --- arch/arm/cpu/u-boot-spl.lds | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index d780a506077..b4e55e2bdc8 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -47,7 +47,11 @@ SECTIONS __image_copy_end = .; - .rel.dyn : { + /* + * if CONFIG_SPL_USE_ARCH_MEMSET is not selected __bss_end - __bss_start + * needs to be a multiple of 8 and we overlay .bss with .rel.dyn + */ + .rel.dyn ALIGN(8) : { __rel_dyn_start = .; *(.rel*) __rel_dyn_end = .;