mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
include: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
committed by
Tom Rini
Tom Rini
parent
853ce2ee9c
commit
3b98b57fa7
@@ -1,35 +0,0 @@
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/*
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* Copyright (C) 2006 CodeHermit.
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* Bryan O'Donoghue <bodonoghue@codehermit.ie>
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*
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* Provides support for USB console on the Analogue & Micro Adder87x
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ADDERUSB__
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#define __ADDERUSB__
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/* Include the board port */
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#include "Adder.h"
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#define CONFIG_USB_DEVICE /* Include UDC driver */
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#define CONFIG_USB_TTY /* Bind the TTY driver to UDC */
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#define CONFIG_SYS_USB_EXTC_CLK 0x02 /* Oscillator on EXTC_CLK 2 */
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#define CONFIG_SYS_USB_BRG_CLK 0x04 /* or use Baud rate generator 0x04 */
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Console is in env */
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/* If you have a USB-IF assigned VendorID then you may wish to define
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* your own vendor specific values either in BoardName.h or directly in
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* usbd_vendor_info.h
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*/
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/*
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#define CONFIG_USBD_MANUFACTURER "CodeHermit.ie"
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#define CONFIG_USBD_PRODUCT_NAME "Das U-Boot"
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#define CONFIG_USBD_VENDORID 0xFFFF
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#define CONFIG_USBD_PRODUCTID_GSERIAL 0xFFFF
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#define CONFIG_USBD_PRODUCTID_CDCACM 0xFFFE
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*/
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#endif /* __ADDERUSB_H__ */
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@@ -1,190 +0,0 @@
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/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
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#define CONFIG_4xx 1 /* ...member of PPC4xx family */
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#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
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/* I2C configuration */
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#define CONFIG_SYS_I2C_SPEED 40000 /* I2C speed */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
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/* environment is in EEPROM */
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#define CONFIG_ENV_IS_IN_EEPROM 1
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#undef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_NVRAM
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#ifdef CONFIG_ENV_IS_IN_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 /* 1010110 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 4 bytes per page */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 40 /* write takes up to 40 msec */
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#define CONFIG_ENV_OFFSET 4 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 350 /* that is 350 bytes only! */
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#endif
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#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
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/* Explanation:
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autbooting is altogether disabled and cannot be
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enabled if CONFIG_BOOTDELAY is negative.
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If you want shorter bootdelay, then
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- "setenv bootdelay <delay>" to the proper value
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*/
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#define CONFIG_BOOTCOMMAND "bootm 20400000 20800000"
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#define CONFIG_BOOTARGS "root=/dev/ram " \
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"ramdisk_size=32768 " \
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"console=ttyS0,115200 " \
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"ram=128M debug"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 0 /* PHY address */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_PPC4xx_EMAC
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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/* UART configuration */
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#define CONFIG_SYS_BASE_BAUD 691200
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/* Default baud rate */
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#define CONFIG_BAUDRATE 115200
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/* The following table includes the supported baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
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57600, 115200, 230400, 460800, 921600 }
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_PCI /* no pci support */
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/*-----------------------------------------------------------------------
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* External peripheral base address
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*-----------------------------------------------------------------------
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*/
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#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000
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#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000
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#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH0_BASE 0xFFF80000
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#define CONFIG_SYS_FLASH0_SIZE 0x00080000
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#define CONFIG_SYS_FLASH1_BASE 0x20000000
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#define CONFIG_SYS_FLASH1_SIZE 0x02000000
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#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
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#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
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#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
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#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH0_BASE
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#define CONFIG_SYS_RAMSTART
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 5 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#ifdef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_OFFSET 0x00060000 /* Offset of Environment Sector */
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#define CONFIG_ENV_SIZE 0x00010000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE 0x00010000 /* see README - env sector total size */
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#endif
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/* On Chip Memory location/size */
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#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
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#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
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/* Global info and initial stack */
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of on-chip SRAM */
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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#endif /* __CONFIG_H */
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@@ -1,384 +0,0 @@
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/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
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#define CONFIG_MVS 1 /* ...on a MVsensor module */
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#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
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#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
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#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
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#undef CONFIG_8xx_CONS_SMC1 /* Console is *NOT* on SMC1 */
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#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 115200 /* console baudrate */
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#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
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#define CONFIG_PREBOOT "echo;" \
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"echo To mount root over NFS use \"run bootnet\";" \
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"echo To mount root from FLASH use \"run bootflash\";" \
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"echo"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
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#define CONFIG_BOOTCOMMAND \
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"bootp; " \
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"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
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"bootm"
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
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#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
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#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
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#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_VENDOREX
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#undef CONFIG_MAC_PARTITION
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#undef CONFIG_DOS_PARTITION
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#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_RUN
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/*
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* Miscellaneous configurable options
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*/
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#undef CONFIG_SYS_LONGHELP /* undef to save memory */
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#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFFF00000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0x40000000
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#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
|
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* have to be in the first 8 MB of memory, since this is
|
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* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
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#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
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#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
|
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*-----------------------------------------------------------------------
|
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* Reset PLL lock status sticky bit, timer expired status bit and timer
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* interrupt status bit
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*
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*/
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#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK SCCR_EBDF11
|
||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \
|
||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||
SCCR_DFALCD00)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
|
||||
#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
|
||||
#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||
#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
|
||||
#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_PCCARD 0 /* **DON'T** Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
|
||||
#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
|
||||
|
||||
|
||||
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
/*#define CONFIG_SYS_DER 0x2002000F*/
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||
#undef FLASH_BASE1_PRELIM
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
|
||||
/*
|
||||
* FLASH timing:
|
||||
*/
|
||||
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
|
||||
/*
|
||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
|
||||
OR_SCY_5_CLK | OR_EHTR)
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
||||
#ifdef CONFIG_MVS_16BIT_FLASH
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
|
||||
#endif
|
||||
|
||||
#undef CONFIG_SYS_OR1_REMAP
|
||||
#undef CONFIG_SYS_OR1_PRELIM
|
||||
#undef CONFIG_SYS_BR1_PRELIM
|
||||
/*
|
||||
* BR2/3 and OR2/3 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#undef SDRAM_BASE3_PRELIM
|
||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
|
||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||
|
||||
#undef CONFIG_SYS_OR3_PRELIM
|
||||
#undef CONFIG_SYS_BR3_PRELIM
|
||||
|
||||
|
||||
/*
|
||||
* Memory Periodic Timer Prescaler
|
||||
*
|
||||
* The Divider for PTA (refresh timer) configuration is based on an
|
||||
* example SDRAM configuration (64 MBit, one bank). The adjustment to
|
||||
* the number of chip selects (NCS) and the actually needed refresh
|
||||
* rate is done by setting MPTPR.
|
||||
*
|
||||
* PTA is calculated from
|
||||
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
|
||||
*
|
||||
* gclk CPU clock (not bus clock!)
|
||||
* Trefresh Refresh cycle * 4 (four word bursts used)
|
||||
*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
* --------------------------------------------
|
||||
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
|
||||
*
|
||||
* 50 MHz => 50.000.000 / Divider = 98
|
||||
* 66 Mhz => 66.000.000 / Divider = 129
|
||||
* 80 Mhz => 80.000.000 / Divider = 156
|
||||
*/
|
||||
#define CONFIG_SYS_MAMR_PTA 98
|
||||
|
||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||
|
||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||
|
||||
/*
|
||||
* MAMR settings for SDRAM
|
||||
*/
|
||||
|
||||
/* 8 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
/* 9 column SDRAM */
|
||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 | \
|
||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,282 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
|
||||
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
|
||||
#define CONFIG_ORSG 1 /* ...on a ORSG board */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
|
||||
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
#define CONFIG_BOOTCOMMAND "go fff00100"
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_PPC4xx_EMAC
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_PHY_ADDR 0 /* PHY address */
|
||||
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_EEPROM
|
||||
|
||||
|
||||
#define CONFIG_MAC_PARTITION
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
|
||||
|
||||
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
|
||||
#define CONFIG_SYS_BASE_BAUD 691200
|
||||
|
||||
/* The following table includes the supported baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
|
||||
57600, 115200, 230400, 460800, 921600 }
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
|
||||
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
|
||||
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
|
||||
#define PCI_HOST_FORCE 1 /* configure as pci host */
|
||||
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
|
||||
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
|
||||
#undef CONFIG_PCI_PNP /* no pci plug-and-play */
|
||||
/* resource configuration */
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */
|
||||
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
|
||||
#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
|
||||
#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
|
||||
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
|
||||
#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
|
||||
#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
|
||||
#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
|
||||
#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
|
||||
#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
|
||||
/*
|
||||
* The following defines are added for buggy IOP480 byte interface.
|
||||
* All other boards should use the standard values (CPCI405 etc.)
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
|
||||
#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#if 0 /* Use NVRAM for environment variables */
|
||||
/*-----------------------------------------------------------------------
|
||||
* NVRAM organization
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
|
||||
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
|
||||
#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
|
||||
#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
|
||||
#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
|
||||
|
||||
#else /* Use EEPROM for environment variables */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
|
||||
#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
|
||||
/* total size of a CAT24WC08 is 1024 bytes */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C EEPROM (CAT24WC08) for environment
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_PPC4XX
|
||||
#define CONFIG_SYS_I2C_PPC4XX_CH0
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
|
||||
/* mask of address bits that overflow into the "EEPROM chip address" */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
|
||||
/* 16 byte page write mode using*/
|
||||
/* last 4 bits of the address */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
|
||||
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*/
|
||||
|
||||
/* Memory Bank 0 (Flash Bank 0) initialization */
|
||||
#define CONFIG_SYS_EBC_PB0AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 1 (Flash Bank 1) initialization */
|
||||
#define CONFIG_SYS_EBC_PB1AP 0x92015480
|
||||
#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
|
||||
|
||||
/* Memory Bank 2 (PLD - FPGA-boot) initialization */
|
||||
#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
|
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
|
||||
#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 3 (PLD - OSL) initialization */
|
||||
#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
|
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
|
||||
#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
|
||||
|
||||
/* Memory Bank 4 (Spartan2 1) initialization */
|
||||
#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
|
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
|
||||
#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
|
||||
|
||||
/* Memory Bank 5 (Spartan2 2) initialization */
|
||||
#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
|
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
|
||||
#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
|
||||
|
||||
/* Memory Bank 6 (Virtex 1) initialization */
|
||||
#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
|
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
|
||||
#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
|
||||
|
||||
/* Memory Bank 7 (Virtex 2) initialization */
|
||||
#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
|
||||
/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
|
||||
#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
|
||||
|
||||
|
||||
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
|
||||
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
|
||||
/* On Chip Memory location */
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
|
||||
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,359 +0,0 @@
|
||||
/*
|
||||
* Copyright 2011 Alex Dubov <oakad@yahoo.com>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Merury Computers MPQ101 board configuration file
|
||||
*
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#ifdef CONFIG_36BIT
|
||||
# define CONFIG_PHYS_64BIT
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE /* BOOKE */
|
||||
#define CONFIG_E500 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
|
||||
#define CONFIG_MPC8548 /* MPC8548 specific */
|
||||
#define CONFIG_MPQ101 /* MPQ101 board specific */
|
||||
|
||||
#define CONFIG_SYS_SRIO /* enable serial RapidIO */
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_PANIC_HANG
|
||||
|
||||
/*
|
||||
* Only possible on E500 Version 2 or newer cores.
|
||||
*/
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
# define CONFIG_ADDR_MAP
|
||||
# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xe0000000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_SYS_FSL_DDR2
|
||||
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
/* Fixed 512MB DDR2 parameters */
|
||||
#define CONFIG_SYS_SDRAM_SIZE_LOG 29 /* DDR is 512MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00010000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x5c47a432
|
||||
#define CONFIG_SYS_DDR_TIMING_1_PERF 0x49352322
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x03984cce
|
||||
#define CONFIG_SYS_DDR_TIMING_2_PERF 0x14904cca
|
||||
#define CONFIG_SYS_DDR_MODE_1 0x00400442
|
||||
#define CONFIG_SYS_DDR_MODE_1_PERF 0x00480432
|
||||
#define CONFIG_SYS_DDR_MODE_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_MODE_2_PERF 0x00000000
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x08200100
|
||||
#define CONFIG_SYS_DDR_INTERVAL_PERF 0x06180100
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xc3008000 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL2 0x04400000
|
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x0ffffffc
|
||||
|
||||
/*
|
||||
* RAM definitions
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
|
||||
|
||||
/*
|
||||
* FLASH on the Local Bus
|
||||
* One bank, 128M, using the CFI driver.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
# define CONFIG_SYS_FLASH_BASE_PHYS 0xff8000000ull
|
||||
#else
|
||||
# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
/* 0xf8001801 */
|
||||
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BR_PS_32 | BR_V)
|
||||
|
||||
/* 0xf8006ff7 */
|
||||
#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(128) | OR_GPCM_XAM | OR_GPCM_CSNT \
|
||||
| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
|
||||
| OR_GPCM_SCY_15 | OR_GPCM_TRLX \
|
||||
| OR_GPCM_EHTR | OR_GPCM_EAD)
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID,
|
||||
* assume this is the AMD flash.
|
||||
*/
|
||||
#define CONFIG_ASSUME_AMD_FLASH
|
||||
|
||||
/*
|
||||
* Environment parameters
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
#define CONFIG_SYS_USE_PPCENV
|
||||
#define ENV_IS_EMBEDDED
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */
|
||||
#define CONFIG_ENV_SIZE 0x800
|
||||
|
||||
/* Environment at the start of flash sector, before text. */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SIZE)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#define CONFIG_SYS_TEXT_BASE 0xfffc0800
|
||||
#define CONFIG_SYS_LDSCRIPT "board/mercury/mpq101/u-boot.lds"
|
||||
|
||||
/*
|
||||
* Cypress CY7C67200 USB controller on the Local Bus.
|
||||
* Not supported by u-boot at present.
|
||||
*/
|
||||
#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull
|
||||
#else
|
||||
# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE
|
||||
#endif
|
||||
|
||||
/* 0xf0001001 */
|
||||
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \
|
||||
| BR_PS_16 | BR_V)
|
||||
|
||||
/* fffff002 */
|
||||
#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \
|
||||
| OR_GPCM_BCTLD | OR_GPCM_EHTR)
|
||||
|
||||
/*
|
||||
* Serial Ports
|
||||
*/
|
||||
#define CONFIG_CONS_INDEX 2
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \
|
||||
19200, 38400, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
|
||||
/*
|
||||
* I2C buses and peripherals
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
|
||||
|
||||
/* I2C RTC - M41T81 */
|
||||
#define CONFIG_RTC_M41T62
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
|
||||
|
||||
/* I2C EEPROM - 24C256 */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1
|
||||
|
||||
/*
|
||||
* RapidIO MMU
|
||||
*/
|
||||
#ifdef CONFIG_SYS_SRIO
|
||||
# define CONFIG_SRIO1
|
||||
# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
|
||||
# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
|
||||
|
||||
# ifdef CONFIG_PHYS_64BIT
|
||||
# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull
|
||||
# else
|
||||
# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Ethernet
|
||||
*/
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
|
||||
# define CONFIG_MII /* MII PHY management */
|
||||
# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
|
||||
# define CONFIG_TSEC1
|
||||
# define CONFIG_TSEC1_NAME "eTSEC0"
|
||||
# define TSEC1_PHY_ADDR 0x10
|
||||
# define TSEC1_PHYIDX 0
|
||||
# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
# define CONFIG_TSEC2
|
||||
# define CONFIG_TSEC2_NAME "eTSEC1"
|
||||
# define TSEC2_PHY_ADDR 0x11
|
||||
# define TSEC2_PHYIDX 0
|
||||
# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
# define CONFIG_TSEC3
|
||||
# define CONFIG_TSEC3_NAME "eTSEC2"
|
||||
# define TSEC3_PHY_ADDR 0x12
|
||||
# define TSEC3_PHYIDX 0
|
||||
# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
# define CONFIG_TSEC4
|
||||
# define CONFIG_TSEC4_NAME "eTSEC3"
|
||||
# define TSEC4_PHY_ADDR 0x13
|
||||
# define TSEC4_PHYIDX 0
|
||||
# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
/* Options are: eTSEC[0-3] */
|
||||
# define CONFIG_ETHPRIME "eTSEC0"
|
||||
# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_SNTP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_EEPROM
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_IRQ
|
||||
#define CONFIG_CMD_SETEXPR
|
||||
#define CONFIG_CMD_JFFS2
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS
|
||||
|
||||
#define CONFIG_FIT /* new uImage format support */
|
||||
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
|
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "MPQ-101=> " /* Monitor Command Prompt */
|
||||
|
||||
/* Console I/O Buffer Size */
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
# define CONFIG_SYS_CBSIZE 1024
|
||||
#else
|
||||
# define CONFIG_SYS_CBSIZE 256
|
||||
#endif
|
||||
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Basic Environment Configuration
|
||||
*/
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
/*default location for tftp and bootm*/
|
||||
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -1,175 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2003
|
||||
* Masami Komiya <mkomiya@sonare.it>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/*
|
||||
* Config header file for TANBAC TB0229 board using an VR4131 CPU module
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */
|
||||
#define CONFIG_TB0229 1 /* on a TB0229 Board */
|
||||
|
||||
#ifndef CPU_CLOCK_RATE
|
||||
#define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */
|
||||
#endif
|
||||
#define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \
|
||||
"echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \
|
||||
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
|
||||
"echo Type \\\"run flash_local\\\" to mount local root filesystem;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netboot=dhcp;tftp;run netargs; bootm\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \
|
||||
"localargs=setenv bootargs root=1F02 ip=dhcp\0" \
|
||||
"addmisc=setenv bootargs ${bootargs} " \
|
||||
"console=ttyS0,${baudrate} " \
|
||||
"read-only=readonly\0" \
|
||||
"netargs=run nfsargs addmisc\0" \
|
||||
"flash_nfs=run nfsargs addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_local=run localargs addmisc;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \
|
||||
"setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\
|
||||
"run addmisc;" \
|
||||
"bootm 80400000 80600000\0" \
|
||||
"rootpath=/export/miniroot-mipsel\0" \
|
||||
"autoload=no\0" \
|
||||
"kernel_addr=BFC60000\0" \
|
||||
"ramdisk_addr=B0100000\0" \
|
||||
"u-boot=u-boot.bin\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"load=dhcp;tftp 80400000 ${u-boot}\0" \
|
||||
"load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \
|
||||
"update_uboot=run load;" \
|
||||
"protect off BFC00000 BFC3FFFF;" \
|
||||
"erase BFC00000 BFC3FFFF;" \
|
||||
"cp.b 80400000 BFC00000 ${filesize}\0" \
|
||||
"update_kernel=run load_kernel;" \
|
||||
"erase BFC60000 BFD5FFFF;" \
|
||||
"cp.b 80400000 BFC60000 ${filesize}\0" \
|
||||
"initenv=erase bfc40000 bfc5ffff\0" \
|
||||
""
|
||||
/*#define CONFIG_BOOTCOMMAND "run flash_local" */
|
||||
#define CONFIG_BOOTCOMMAND "run netboot"
|
||||
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||
#define CONFIG_BOOTP_BOOTPATH
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_PCI
|
||||
#define CONFIG_CMD_ELF
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN 128*1024
|
||||
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
|
||||
|
||||
#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END 0x80800000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
|
||||
|
||||
#define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */
|
||||
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
/* Address and size of Primary Environment Sector */
|
||||
#define CONFIG_ENV_ADDR 0xBFC40000
|
||||
#define CONFIG_ENV_SIZE 0x20000
|
||||
|
||||
#define CONFIG_SYS_DIRECT_FLASH_TFTP
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_DCACHE_SIZE 16384
|
||||
#define CONFIG_SYS_ICACHE_SIZE 16384
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK 18432000
|
||||
#define CONFIG_SYS_NS16550_COM1 0xaf000800
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*/
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
#define CONFIG_EEPRO100
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
|
||||
|
||||
#define CONFIG_RTL8139
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Reference in New Issue
Block a user