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arm: renesas: Generate u-boot-elf.scif for R-Car Gen5 RSIP

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Add target to generate u-boot-elf.scif for R-Car Gen5 Cortex-M33
RSIP core. The resulting .scif SREC file can be loaded using the
SCIF loader to start U-Boot on the RSIP core.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
This commit is contained in:
Marek Vasut
2026-05-08 01:25:35 +02:00
parent 5fa536f698
commit 3bcee350f0
1 changed files with 11 additions and 0 deletions
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11
arch/arm/mach-renesas/Makefile
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@@ -40,6 +40,13 @@ else
srec_cat_le_cmd := "-l-e-constant"
endif
ifneq ($(CONFIG_RCAR_GEN5),)
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
-Output_Block_Size 16 \
-generate 0x18402010 0x18402014 $(srec_cat_le_cmd) $(CONFIG_SYS_UBOOT_START) 4 \
-generate 0x18402014 0x18402018 $(srec_cat_le_cmd) 0x1ef000 4
else
ifneq ($(CONFIG_RCAR_GEN4),)
quiet_cmd_srec_cat = SRECCAT $@
cmd_srec_cat = srec_cat -output $@ -M 8 $< -M 8 \
@@ -106,10 +113,14 @@ quiet_cmd_srec_cat = SRECCAT $@
-generate 0xe6301264 0xe6301268 $(srec_cat_le_cmd) $2 4
endif
endif
endif
spl/u-boot-spl.scif: spl/u-boot-spl.srec spl/u-boot-spl.bin
$(call cmd,srec_cat,$(shell wc -c spl/u-boot-spl.bin | awk '{printf("0x%08x\n",$$1)}'))
u-boot-elf.scif: u-boot-elf.srec u-boot.bin
$(call cmd,srec_cat,$(shell wc -c u-boot-dtb.bin | awk '{printf("0x%08x\n",$$1)}'))
# if srec_cat is present build u-boot-spl.scif by default
has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)
INPUTS-$(has_srec_cat) += u-boot-spl.scif