board: toradex: add aquila am69 support

Add initial support for the Toradex Aquila AM69 module. The Aquila AM69 SoM is based on the TI AM69 SoC from the Jacinto 7 family and is designed for high-end embedded computing, featuring up to 32GB of LPDDR4 and 256GB eMMC storage, extensive multimedia support (3x Quad CSI, 2x Quad DSI, DisplayPort, 5x Audio I2S/TDM), six Ethernet interfaces (1x 1G, 4x 2.5G SGMII, 1x 10G), USB 3.2 Host/DRD support, and a Wi-Fi 7/BT 5.3 module, alongside an RX8130 RTC, I2C EEPROM and Temperature Sensor, and optional TPM 2.0 module. Link: https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69 Link: https://www.toradex.com/products/carrier-board/aquila-development-board-kit Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Co-developed-by: Parth Pancholi <parth.pancholi@toradex.com> Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Co-developed-by: Franz Schnyder <franz.schnyder@toradex.com> Signed-off-by: Franz Schnyder <franz.schnyder@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
2026-06-02 17:56:44 +03:00 · 2025-12-05 09:06:11 +01:00
parent 6c8dee07c3
commit 3f0528882c
28 changed files with 18734 additions and 1 deletions
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1091,7 +1091,9 @@ dtb-$(CONFIG_SOC_K3_J7200) += k3-j7200-r5-common-proc-board.dtb
 dtb-$(CONFIG_SOC_K3_J721S2) += k3-am68-sk-r5-base-board.dtb\
 			       k3-j721s2-r5-common-proc-board.dtb

-dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-r5-sk.dtb \
+dtb-$(CONFIG_SOC_K3_J784S4) += k3-am69-aquila-dev.dtb \
+			       k3-am69-r5-aquila-dev.dtb \
+			       k3-am69-r5-sk.dtb \
 			       k3-j784s4-r5-evm.dtb

 dtb-$(CONFIG_SOC_K3_J722S) += k3-j722s-r5-evm.dtb \
--- a/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
+++ b/arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#define SPL_BOARD_DTB "spl/dts/k3-am69-aquila-dev.dtb"
+#define BOARD_DESCRIPTION "k3-am69-aquila"
+#define UBOOT_BOARD_DESCRIPTION "U-Boot for AM69 Aquila board"
+
+#include "k3-j784s4-binman.dtsi"
+
+#if defined(CONFIG_CPU_V7R)
+
+&binman {
+	tiboot3-am69-hs {
+		insert-template = <&tiboot3_j784s4_hs>;
+		filename = "tiboot3-am69-hs-aquila.bin";
+	};
+
+	tiboot3-am69-hs-fs {
+		insert-template = <&tiboot3_j784s4_hs_fs>;
+		filename = "tiboot3-am69-hs-fs-aquila.bin";
+		symlink = "tiboot3.bin";
+	};
+};
+
+&ti_fs_enc {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-enc.bin";
+};
+
+&sysfw_inner_cert {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-cert.bin";
+};
+
+&ti_fs_enc_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-enc.bin";
+};
+
+&sysfw_inner_cert_fs {
+	filename = "ti-sysfw/ti-fs-firmware-j784s4-hs-fs-cert.bin";
+};
+
+#else // CONFIG_ARM64
+
+&binman {
+	tispl {
+		insert-template = <&ti_spl>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+						filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+			};
+		};
+	};
+
+	u-boot {
+		insert-template = <&u_boot>;
+	};
+
+	tispl-unsigned {
+		insert-template = <&ti_spl_unsigned>;
+
+		fit {
+			images {
+				dm {
+					ti-dm {
+						filename = "ti-dm/j784s4/ipc_echo_testb_mcu1_0_release_strip.xer5f";
+					};
+				};
+			};
+		};
+	};
+
+	u-boot-unsigned {
+		insert-template = <&u_boot_unsigned>;
+	};
+};
+
+#endif
+
+/ {
+	memory@80000000 {
+		bootph-all;
+	};
+
+	sysinfo {
+		compatible = "toradex,sysinfo";
+	};
+};
+
+&main_pmx0 {
+	bootph-pre-ram;
+};
+
+&main_sdhci0 {
+	bootph-pre-ram;
+};
+
+&main_uart8 {
+	bootph-pre-ram;
+};
+
+&mcu_udmap {
+	reg =   <0x0 0x285c0000 0x0 0x100>,
+		<0x0 0x284c0000 0x0 0x4000>,
+		<0x0 0x2a800000 0x0 0x40000>,
+		<0x0 0x284a0000 0x0 0x4000>,
+		<0x0 0x2aa00000 0x0 0x40000>,
+		<0x0 0x28400000 0x0 0x2000>;
+	reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+		    "tchanrt", "rflow";
+	bootph-pre-ram;
+};
+
+&pinctrl_main_uart8 {
+	bootph-pre-ram;
+};
+
+&pinctrl_wkup_i2c0 {
+	bootph-pre-ram;
+};
+
+&pmic_tps6594 {
+	bootph-pre-ram;
+	regulators {
+		bootph-pre-ram;
+	};
+};
+
+&tps62873a {
+	bootph-pre-ram;
+};
+
+&usb0 {
+	/delete-property/ phys;
+	/delete-property/ phy-names;
+	dr_mode = "peripheral";
+	maximum-speed = "high-speed";
+	bootph-pre-ram;
+};
+
+&usbss0 {
+	ti,usb2-only;
+	bootph-pre-ram;
+};
+
+&wkup_gpio0 {
+	bootph-pre-ram;
+};
+
+&wkup_i2c0 {
+	bootph-pre-ram;
+};
--- a/arch/arm/dts/k3-am69-aquila-dev.dts
+++ b/arch/arm/dts/k3-am69-aquila-dev.dts
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
+ * https://www.toradex.com/products/carrier-board/aquila-development-board-kit
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/pwm/pwm.h>
+#include "k3-am69-aquila.dtsi"
+
+/ {
+	model = "Toradex Aquila AM69 on Aquila Development Board";
+	compatible = "toradex,aquila-am69-dev",
+		     "toradex,aquila-am69",
+		     "ti,j784s4";
+
+	aliases {
+		eeprom1 = &carrier_eeprom;
+	};
+
+	reg_1v8_sw: regulator-1v8-sw {
+		compatible = "regulator-fixed";
+		regulator-max-microvolt = <1800000>;
+		regulator-min-microvolt = <1800000>;
+		regulator-name = "Carrier_1V8";
+	};
+
+	reg_3v3_dp: regulator-3v3-dp {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_21_dp>;
+		/* Aquila GPIO_21_DP (AQUILA B57) */
+		gpio = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-max-microvolt = <3300000>;
+		regulator-min-microvolt = <3300000>;
+		regulator-name = "DP_3V3";
+		startup-delay-us = <10000>;
+	};
+
+	dp0-connector {
+		compatible = "dp-connector";
+		dp-pwr-supply = <&reg_3v3_dp>;
+		label = "Display Port";
+		type = "full-size";
+
+		port {
+			dp0_connector_in: endpoint {
+				remote-endpoint = <&dp0_out>;
+			};
+		};
+	};
+
+	sound {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,name = "aquila-wm8904";
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"Microphone Jack", "MICBIAS",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Digital Mic";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Microphone", "Digital Mic",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&wm8904_1a>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&mcasp4>;
+		};
+	};
+};
+
+/* Aquila CTRL_PWR_BTN_MICO# */
+&aquila_key_power {
+	status = "okay";
+};
+
+/* Aquila CTRL_WAKE1_MICO# */
+&aquila_key_wake {
+	status = "okay";
+};
+
+/* On-module ETH_1 MDIO */
+&davinci_mdio {
+	status = "okay";
+};
+
+&dp0_ports {
+	port@4 {
+		reg = <4>;
+		dp0_out: endpoint {
+			remote-endpoint = <&dp0_connector_in>;
+		};
+	};
+};
+
+&dss {
+	status = "okay";
+};
+
+&main0_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main0_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main0_alert1>;
+		};
+	};
+};
+
+&main1_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main1_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main1_alert1>;
+		};
+	};
+};
+
+&main2_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main2_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main2_alert1>;
+		};
+	};
+};
+
+&main3_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main3_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main3_alert1>;
+		};
+	};
+};
+
+&main4_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&main4_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&main4_alert1>;
+		};
+	};
+};
+
+/* Aquila ETH_2 */
+&main_cpsw0 {
+	status = "okay";
+};
+
+/* Aquila ETH_2 SGMII PHY */
+&main_cpsw0_port8 {
+	phy-handle = <&cpsw0_port8_phy4>;
+	status = "okay";
+};
+
+/* Aquila ETH_2_XGMII_MDIO */
+&main_cpsw0_mdio {
+	status = "okay";
+
+	cpsw0_port8_phy4: ethernet-phy@4 {
+		reg = <4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_eth2_int>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <44 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
+
+/* Aquila PWM_1 */
+&main_ehrpwm0 {
+	status = "okay";
+};
+
+/* Aquila PWM_4_DP */
+&main_ehrpwm2 {
+	status = "okay";
+};
+
+/* Aquila PWM_2 */
+&main_ehrpwm1 {
+	status = "okay";
+};
+
+/* Aquila PWM_3_DSI */
+&main_ehrpwm5 {
+	status = "okay";
+};
+
+&main_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_01>,  /* Aquila GPIO_01 */
+		    <&pinctrl_gpio_02>,  /* Aquila GPIO_02 */
+		    <&pinctrl_gpio_03>;  /* Aquila GPIO_03 */
+};
+
+/* Aquila I2C_3_DSI1 */
+&main_i2c0 {
+	status = "okay";
+
+	i2c-mux@70 {
+		compatible = "nxp,pca9543";
+		reg = <0x70>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* I2C on DSI Connector Pin #4 and #6 */
+		i2c_dsi_0: i2c@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		/* I2C on DSI Connector Pin #52 and #54 */
+		i2c_dsi_1: i2c@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};
+
+/* Aquila I2C_4_CSI1 */
+&main_i2c1 {
+	status = "okay";
+};
+
+/* Aquila I2C_5_CSI2 */
+&main_i2c2 {
+	status = "okay";
+};
+
+/* Aquila I2C_6 */
+&main_i2c5 {
+	status = "okay";
+};
+
+/* Aquila CAN_1 */
+&main_mcan10 {
+	status = "okay";
+};
+
+/* Aquila CAN_3 */
+&main_mcan13 {
+	status = "okay";
+};
+
+/* Aquila SD_1 */
+&main_sdhci1 {
+	status = "okay";
+};
+
+/* Aquila SPI_2 */
+&main_spi0 {
+	status = "okay";
+};
+
+/* Aquila SPI_1 */
+&main_spi2 {
+	status = "okay";
+};
+
+/* Aquila UART_1 */
+&main_uart4 {
+	status = "okay";
+};
+
+/* Aquila UART_3, used as the Linux console */
+&main_uart8 {
+	status = "okay";
+};
+
+/* Aquila I2S_1 */
+&mcasp4 {
+	status = "okay";
+};
+
+&mcu_cpsw {
+	status = "okay";
+};
+
+/* On-module ETH_1 RGMII */
+&mcu_cpsw_port1 {
+	status = "okay";
+};
+
+/* Aquila I2C_1 */
+&mcu_i2c0 {
+	clock-frequency = <100000>;
+	status = "okay";
+
+	fan_controller: fan@18 {
+		compatible = "ti,amc6821";
+		reg = <0x18>;
+		#pwm-cells = <2>;
+
+		fan: fan {
+			cooling-levels = <102 179 255>;
+			#cooling-cells = <2>;
+			pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	wm8904_1a: audio-codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_audio_extrefclk1>;
+		#sound-dai-cells = <0>;
+		clocks = <&audio_refclk1>;
+		clock-names = "mclk";
+		AVDD-supply = <&reg_1v8_sw>;
+		CPVDD-supply = <&reg_1v8_sw>;
+		DBVDD-supply = <&reg_1v8_sw>;
+		DCVDD-supply = <&reg_1v8_sw>;
+		MICVDD-supply = <&reg_1v8_sw>;
+
+		wlf,drc-cfg-names = "default", "peaklimiter";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>;
+
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+
+		wlf,in1r-as-dmicdat2;
+	};
+
+	/* Current measurement into module VCC */
+	hwmon@41 {
+		compatible = "ti,ina226";
+		reg = <0x41>;
+		shunt-resistor = <5000>;
+	};
+
+	temperature-sensor@4f {
+		compatible = "ti,tmp1075";
+		reg = <0x4f>;
+	};
+
+	/* USB-C OTG (TCPC USB PD PHY) */
+	tcpc@52 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x52>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usb1_int>;
+		interrupt-parent = <&main_gpio0>;
+		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
+
+		connector {
+			compatible = "usb-c-connector";
+			data-role = "dual";
+			label = "USB-C OTG";
+			power-role = "dual";
+			try-power-role = "sink";
+			self-powered;
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			op-sink-microwatt = <1000000>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					usb_1_con_hs: endpoint {
+						remote-endpoint = <&usb0_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					usb_1_con_ss: endpoint {
+						remote-endpoint = <&usb0_ss_mux>;
+					};
+				};
+			};
+		};
+	};
+
+	carrier_eeprom: eeprom@57 {
+		compatible = "st,24c02", "atmel,24c02";
+		reg = <0x57>;
+		pagesize = <16>;
+	};
+};
+
+/* Aquila I2C_2 */
+&mcu_i2c1 {
+	status = "okay";
+};
+
+/* Aquila CAN_2 */
+&mcu_mcan0 {
+	status = "okay";
+};
+
+/* Aquila CAN_4 */
+&mcu_mcan1 {
+	status = "okay";
+};
+
+/* Aquila UART_4 */
+&mcu_uart0 {
+	status = "okay";
+};
+
+&mhdp {
+	status = "okay";
+};
+
+/* Aquila QSPI_1 */
+&ospi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_mcu_ospi0_4bit>, <&pinctrl_mcu_ospi0_cs0>;
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <66000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <4>;
+		cdns,read-delay = <0>;
+		cdns,tchsh-ns = <3>;
+		cdns,tsd2d-ns = <10>;
+		cdns,tshsl-ns = <30>;
+		cdns,tslch-ns = <8>;
+	};
+};
+
+/* Aquila PCIE_1 */
+&pcie0_rc {
+	status = "okay";
+};
+
+/* Aquila PCIE_2 */
+&pcie1_rc {
+	status = "okay";
+};
+
+&serdes2 {
+	status = "okay";
+};
+
+&serdes4 {
+	status = "okay";
+};
+
+&serdes_wiz2 {
+	status = "okay";
+};
+
+&serdes_wiz4 {
+	status = "okay";
+};
+
+/* Aquila ADC_[1-4] */
+&tscadc0 {
+	status = "okay";
+};
+
+&usbss0 {
+	status = "okay";
+};
+
+&usb0ss_mux {
+	status = "okay";
+
+	port {
+		usb0_ss_mux: endpoint {
+			remote-endpoint = <&usb_1_con_ss>;
+		};
+	};
+};
+
+&usb0 {
+	status = "okay";
+
+	port {
+		usb0_hs: endpoint {
+			remote-endpoint = <&usb_1_con_hs>;
+		};
+	};
+};
+
+&wkup0_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&wkup0_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&wkup0_alert1>;
+		};
+	};
+};
+
+&wkup1_thermal {
+	cooling-maps {
+		map0 {
+			cooling-device = <&fan 1 1>;
+			trip = <&wkup1_alert0>;
+		};
+
+		map1 {
+			cooling-device = <&fan 2 2>;
+			trip = <&wkup1_alert1>;
+		};
+	};
+};
+
+&wkup_gpio0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpio_04>,       /* Aquila GPIO_04 */
+		    <&pinctrl_gpio_05>,       /* Aquila GPIO_05 */
+		    <&pinctrl_gpio_06>,       /* Aquila GPIO_06 */
+		    <&pinctrl_gpio_07>,       /* Aquila GPIO_07 */
+		    <&pinctrl_gpio_08>;       /* Aquila GPIO_08 */
+};
+
+/* Aquila UART_2, through RS485 transceiver */
+&wkup_uart0 {
+	linux,rs485-enabled-at-boot-time;
+	rs485-rx-during-tx;
+	status = "okay";
+};
--- a/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
+++ b/arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
--- a/arch/arm/dts/k3-am69-aquila.dtsi
+++ b/arch/arm/dts/k3-am69-aquila.dtsi
--- a/arch/arm/dts/k3-am69-r5-aquila-dev.dts
+++ b/arch/arm/dts/k3-am69-r5-aquila-dev.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am69-aquila-dev.dts"
+#include "k3-am69-aquila-lpddr4-4266.dtsi"
+#include "k3-j784s4-ddr.dtsi"
+#include "k3-am69-aquila-dev-u-boot.dtsi"
+#include "k3-j784s4-r5.dtsi"
+
+&pmic_tps6594 {
+	esm: esm {
+		compatible = "ti,tps659413-esm";
+		bootph-pre-ram;
+	};
+};
--- a/arch/arm/mach-k3/j784s4/Kconfig
+++ b/arch/arm/mach-k3/j784s4/Kconfig
@@ -9,6 +9,23 @@ choice
 	prompt "K3 J784S4 board"
 	optional

+config TARGET_AQUILA_AM69_A72
+	bool "Toradex Aquila AM69 running on A72"
+	select ARM64
+	select SYS_DISABLE_DCACHE_OPS
+	select BINMAN
+
+config TARGET_AQUILA_AM69_R5
+	bool "Toradex Aquila AM69 running on R5"
+	select CPU_V7R
+	select SYS_THUMB_BUILD
+	select K3_LOAD_SYSFW
+	select RAM
+	select SPL_RAM
+	select K3_DDRSS
+	select BINMAN
+	imply SYS_K3_SPL_ATF
+
 config TARGET_J784S4_A72_EVM
 	bool "TI K3 based J784S4 EVM running on A72"
 	select ARM64
@@ -48,5 +65,6 @@ config TARGET_J742S2_R5_EVM
 endchoice

 source "board/ti/j784s4/Kconfig"
+source "board/toradex/aquila-am69/Kconfig"

 endif
--- a/board/toradex/aquila-am69/Kconfig
+++ b/board/toradex/aquila-am69/Kconfig
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+
+if TARGET_AQUILA_AM69_A72
+
+config SYS_BOARD
+       default "aquila-am69"
+
+config SYS_VENDOR
+       default "toradex"
+
+config SYS_CONFIG_NAME
+       default "aquila-am69"
+
+config TDX_CFG_BLOCK
+	default y
+
+config TDX_CFG_BLOCK_2ND_ETHADDR
+	default y
+
+config TDX_CFG_BLOCK_DEV
+	default "0"
+
+config TDX_CFG_BLOCK_EXTRA
+	default y
+
+config TDX_CFG_BLOCK_OFFSET
+	default "-512"
+
+config TDX_CFG_BLOCK_PART
+	default "1"
+
+config TDX_HAVE_EEPROM_EXTRA
+	default y
+
+config TDX_HAVE_MMC
+	default y
+
+source "board/toradex/common/Kconfig"
+
+endif
+
+if TARGET_AQUILA_AM69_R5
+
+config SYS_BOARD
+       default "aquila-am69"
+
+config SYS_VENDOR
+       default "toradex"
+
+config SYS_CONFIG_NAME
+       default "aquila-am69"
+
+config SPL_LDSCRIPT
+	default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
--- a/board/toradex/aquila-am69/MAINTAINERS
+++ b/board/toradex/aquila-am69/MAINTAINERS
@@ -0,0 +1,13 @@
+AQUILA AM69
+M:	Francesco Dolcini <francesco.dolcini@toradex.com>
+W:	https://www.toradex.com/computer-on-modules/aquila-arm-family/ti-am69
+S:	Maintained
+F:	arch/arm/dts/k3-am69-aquila-dev-u-boot.dtsi
+F:	arch/arm/dts/k3-am69-aquila-dev.dts
+F:	arch/arm/dts/k3-am69-aquila-lpddr4-4266.dtsi
+F:	arch/arm/dts/k3-am69-aquila.dtsi
+F:	arch/arm/dts/k3-am69-r5-aquila-dev.dts
+F:	board/toradex/aquila-am69
+F:	configs/aquila-am69_a72_defconfig
+F:	configs/aquila-am69_r5_defconfig
+F:	include/configs/aquila-am69.h
--- a/board/toradex/aquila-am69/Makefile
+++ b/board/toradex/aquila-am69/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+
+obj-y	+= aquila-am69.o
+obj-y	+= ddrs_patch.o
+obj-y	+= aquila_ddrs_16GB.o
+obj-y	+= aquila_ddrs_8GB.o
--- a/board/toradex/aquila-am69/aquila-am69.c
+++ b/board/toradex/aquila-am69/aquila-am69.c
@@ -0,0 +1,208 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Board specific initialization for Aquila AM69 SoM
+ *
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#include <asm/arch/k3-common-fdt.h>
+#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <env.h>
+#include <fdt_support.h>
+#include <i2c.h>
+#include <linux/sizes.h>
+#include <spl.h>
+
+#include "../common/tdx-common.h"
+#include "aquila_ddrs_16GB.h"
+#include "aquila_ddrs_8GB.h"
+#include "ddrs_patch.h"
+
+#define CTRL_MMR_CFG0_MCU_ADC1_CTRL	0x40F040B4
+#define CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL	0x40F08010
+#define MCU_CLKOUT0_CTRL_CLK_EN		BIT(4)
+
+#define HW_CFG_MEM_SZ_32GB		0x00
+#define HW_CFG_MEM_SZ_16GB		0x01
+#define HW_CFG_MEM_SZ_8GB		0x02
+
+#define HW_CFG_MEM_SZ_MASK		0x03
+
+DECLARE_GLOBAL_DATA_PTR;
+static u8 hw_cfg;
+
+static u64 aquila_am69_memory_size(void)
+{
+	switch (hw_cfg & HW_CFG_MEM_SZ_MASK) {
+	case HW_CFG_MEM_SZ_32GB:
+		return SZ_32G;
+	case HW_CFG_MEM_SZ_16GB:
+		return SZ_16G;
+	case HW_CFG_MEM_SZ_8GB:
+		return SZ_8G;
+	default:
+		puts("Invalid memory size configuration\n");
+		return -EINVAL;
+	}
+}
+
+static void read_hw_cfg(void)
+{
+	struct gpio_desc gpio_hw_cfg;
+	char gpio_name[20];
+	int i;
+
+	printf("HW CFG: ");
+	for (i = 0; i < 5; i++) {
+		sprintf(gpio_name, "gpio@42110000_%d", 82 + i);
+		if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) {
+			printf("Lookup named gpio error\n");
+			return;
+		}
+
+		if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) {
+			printf("gpio request error\n");
+			return;
+		}
+
+		if (dm_gpio_get_value(&gpio_hw_cfg) == 1)
+			hw_cfg |= BIT(i);
+
+		dm_gpio_free(NULL, &gpio_hw_cfg);
+	}
+	printf("0x%02x\n", hw_cfg);
+}
+
+static void update_ddr_timings(void)
+{
+	int ret = 0;
+	void *fdt = (void *)gd->fdt_blob;
+
+	switch (aquila_am69_memory_size()) {
+	case SZ_8G:
+		ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_8GB,
+						      MULTI_DDR_CFG_INTRLV_SIZE_8GB);
+		break;
+	case SZ_16G:
+		ret = aquila_am69_fdt_apply_ddr_patch(fdt, aquila_am69_ddrss_patch_16GB,
+						      MULTI_DDR_CFG_INTRLV_SIZE_16GB);
+		break;
+	}
+
+	if (ret)
+		printf("Applying DDR patch error: %d\n", ret);
+}
+
+static int aquila_am69_fdt_fixup_memory_size(u64 total_sz)
+{
+	void *blob = (void *)gd->fdt_blob;
+
+	u64 s[CONFIG_NR_DRAM_BANKS] = {
+		CFG_SYS_SDRAM_BASE,
+		CFG_SYS_SDRAM_BASE1
+	};
+
+	u64 e[CONFIG_NR_DRAM_BANKS] = {
+		SZ_2G,
+		total_sz - SZ_2G
+	};
+
+	return fdt_fixup_memory_banks(blob, s, e, CONFIG_NR_DRAM_BANKS);
+}
+
+void do_board_detect(void)
+{
+	/* MCU_ADC1 pins used as General Purpose Inputs */
+	writel(readl(CTRL_MMR_CFG0_MCU_ADC1_CTRL) | BIT(16),
+	       CTRL_MMR_CFG0_MCU_ADC1_CTRL);
+
+	read_hw_cfg();
+
+	if (IS_ENABLED(CONFIG_K3_DDRSS))
+		update_ddr_timings();
+}
+
+int dram_init(void)
+{
+	s32 ret;
+
+	ret = fdtdec_setup_mem_size_base_lowest();
+	if (ret)
+		printf("Error setting up mem size and base. %d\n", ret);
+
+	return ret;
+}
+
+int dram_init_banksize(void)
+{
+	s32 ret;
+
+	ret = aquila_am69_fdt_fixup_memory_size(aquila_am69_memory_size());
+	if (ret)
+		printf("Error setting memory size. %d\n", ret);
+
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		printf("Error setting up memory banksize. %d\n", ret);
+
+	return ret;
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+	/* Limit RAM used by U-Boot to the DDR low region */
+	if (gd->ram_top > 0x100000000)
+		return 0x100000000;
+#endif
+
+	return gd->ram_top;
+}
+
+#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	int ret;
+
+	ret = fdt_fixup_msmc_ram_k3(blob);
+	if (ret)
+		return ret;
+
+	return ft_common_board_setup(blob, bd);
+}
+#endif
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+	int ret;
+
+	if (IS_ENABLED(CONFIG_ESM_K3)) {
+		const char * const esms[] = {"esm@700000", "esm@40800000", "esm@42080000"};
+
+		for (int i = 0; i < ARRAY_SIZE(esms); ++i) {
+			ret = uclass_get_device_by_name(UCLASS_MISC, esms[i],
+							&dev);
+			if (ret) {
+				printf("MISC init for %s failed: %d\n", esms[i], ret);
+				break;
+			}
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_ESM_PMIC) && ret == 0) {
+		ret = uclass_get_device_by_driver(UCLASS_MISC,
+						  DM_DRIVER_GET(pmic_esm),
+						  &dev);
+		if (ret)
+			printf("ESM PMIC init failed: %d\n", ret);
+	}
+
+	if (IS_ENABLED(CONFIG_TARGET_AQUILA_AM69_R5))
+		writel(readl(CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL) |
+		       MCU_CLKOUT0_CTRL_CLK_EN,
+		       CTRL_MMR_CFG0_MCU_CLKOUT0_CTRL);
+}
--- a/board/toradex/aquila-am69/aquila-am69.env
+++ b/board/toradex/aquila-am69/aquila-am69.env
@@ -0,0 +1,41 @@
+#define CFG_RAMDISK_ADDR_R		0x90300000
+#define CFG_SCRIPTADDR			0x90280000
+
+boot_script_dhcp=boot.scr
+boot_targets=mmc1 mmc0 dhcp
+console=ttyS2
+fdt_addr_r=0x90200000
+fdt_board=dev
+kernel_addr_r=CONFIG_SYS_LOAD_ADDR
+kernel_comp_addr_r=0x80200000
+kernel_comp_size=0x08000000
+ramdisk_addr_r=CFG_RAMDISK_ADDR_R
+scriptaddr=CFG_SCRIPTADDR
+
+dfu_alt_info_ram=
+	tispl.bin ram 0x80080000 0x200000;
+	u-boot.img ram 0x81000000 0x400000;
+	loadaddr ram CONFIG_SYS_LOAD_ADDR 0x80000;
+	scriptaddr ram CFG_SCRIPTADDR 0x80000;
+	ramdisk_addr_r ram CFG_RAMDISK_ADDR_R 0x8000000
+
+update_tiboot3=
+		askenv confirm Did you load tiboot3.bin (y/N)?;
+		if test $confirm = y; then
+			setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200;
+			mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt};
+		fi
+
+update_tispl=
+		askenv confirm Did you load tispl.bin (y/N)?;
+		if test $confirm = y; then
+			setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200;
+			mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt};
+		fi
+
+update_uboot=
+		askenv confirm Did you load u-boot.img (y/N)?;
+		if test $confirm = y; then
+			setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200;
+			mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt};
+		fi
--- a/board/toradex/aquila-am69/aquila_ddrs_16GB.c
+++ b/board/toradex/aquila-am69/aquila_ddrs_16GB.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ * This contains a diff against the 32GB register settings created from the 16GB tool output.
+
+ * The 16GB dtsi file was generated with the following tool revisions:
+ *     - SysConfig: Revision 1.23.1+4034
+ *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0
+ * It was generated on Fri May 16 2025 17:28:31 GMT+0200 (Central European Summer Time)
+ */
+
+#include <asm/u-boot.h>
+#include <linux/kernel.h>
+#include "ddrs_patch.h"
+
+#define DDRSS_PLL_FHS_CNT 3
+
+#define DDRSS_CTL_267_DATA 0x01010101
+#define DDRSS_CTL_271_DATA 0xFFFFFFFF
+#define DDRSS_CTL_273_DATA 0x000003FF
+#define DDRSS_CTL_278_DATA 0x00010000
+#define DDRSS_CTL_287_DATA 0x00000100
+
+#define DDRSS_PI_14_DATA 0x08000005
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_45_DATA 0x00050500
+#define DDRSS_PI_55_DATA 0x05000000
+#define DDRSS_PI_67_DATA 0x00020205
+
+static struct ddr_reg_patch ctl_patch[] = {
+	{ 267, DDRSS_CTL_267_DATA},
+	{ 271, DDRSS_CTL_271_DATA},
+	{ 273, DDRSS_CTL_273_DATA},
+	{ 278, DDRSS_CTL_278_DATA},
+	{ 287, DDRSS_CTL_287_DATA}
+};
+
+static struct ddr_reg_patch pi_patch[] = {
+	{ 14, DDRSS_PI_14_DATA},
+	{ 29, DDRSS_PI_29_DATA},
+	{ 45, DDRSS_PI_45_DATA},
+	{ 55, DDRSS_PI_55_DATA},
+	{ 67, DDRSS_PI_67_DATA},
+};
+
+static struct ddrss_patch ddrss_ctrl_patch = {
+	.ddr_fhs_cnt = DDRSS_PLL_FHS_CNT,
+	.ctl_patch = ctl_patch,
+	.ctl_patch_num = ARRAY_SIZE(ctl_patch),
+	.pi_patch = pi_patch,
+	.pi_patch_num = ARRAY_SIZE(pi_patch),
+	.phy_patch = NULL,
+	.phy_patch_num = 0
+};
+
+struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4] = {
+	&ddrss_ctrl_patch,
+	&ddrss_ctrl_patch,
+	&ddrss_ctrl_patch,
+	&ddrss_ctrl_patch
+};
--- a/board/toradex/aquila-am69/aquila_ddrs_16GB.h
+++ b/board/toradex/aquila-am69/aquila_ddrs_16GB.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+#ifndef __AQUILA_DDRS_16GB_H
+#define __AQUILA_DDRS_16GB_H
+
+#define MULTI_DDR_CFG_INTRLV_SIZE_16GB 11
+extern struct ddrss_patch *aquila_am69_ddrss_patch_16GB[4];
+
+#endif // __AQUILA_DDRS_16GB_H
--- a/board/toradex/aquila-am69/aquila_ddrs_8GB.c
+++ b/board/toradex/aquila-am69/aquila_ddrs_8GB.c
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ * This contains a diff against the 32GB register settings created from the 8GB tool output.
+
+ * The 8GB dtsi file was generated with the following tool revisions:
+ *     - SysConfig: Revision 1.23.1+4034
+ *     - Jacinto7_DDRSS_RegConfigTool: Revision 0.11.0
+ * It was generated on Thu May 15 2025 10:35:37 GMT+0200 (Central European Summer Time)
+ */
+
+#include <asm/u-boot.h>
+#include <linux/kernel.h>
+#include "ddrs_patch.h"
+
+#define DDRSS_PLL_FHS_CNT 3
+
+#define DDRSS_CTL_60_DATA 0x00001008
+#define DDRSS_CTL_62_DATA 0x00000256
+#define DDRSS_CTL_64_DATA 0x00000256
+#define DDRSS_CTL_67_DATA 0x00040000
+#define DDRSS_CTL_68_DATA 0x00950005
+#define DDRSS_CTL_69_DATA 0x00950200
+#define DDRSS_CTL_79_DATA 0x00100010
+#define DDRSS_CTL_80_DATA 0x02660266
+#define DDRSS_CTL_81_DATA 0x02660266
+#define DDRSS_CTL_267_DATA 0x01010101
+#define DDRSS_CTL_268_DATA 0x01010000
+#define DDRSS_CTL_270_DATA 0x00000FFF
+#define DDRSS_CTL_271_DATA 0xFFFFFFFF
+#define DDRSS_CTL_272_DATA 0x01FF0000
+#define DDRSS_CTL_273_DATA 0x000001FF
+#define DDRSS_CTL_278_DATA 0x00010000
+#define DDRSS_CTL_287_DATA 0x00000100
+
+#define DDRSS_PI_14_DATA 0x08000005
+#define DDRSS_PI_29_DATA 0x05000000
+#define DDRSS_PI_45_DATA 0x00050500
+#define DDRSS_PI_55_DATA 0x05000000
+#define DDRSS_PI_67_DATA 0x00020205
+#define DDRSS_PI_73_DATA 0x00080100
+#define DDRSS_PI_169_DATA 0x00105012
+#define DDRSS_PI_171_DATA 0x00000256
+#define DDRSS_PI_173_DATA 0x00000256
+#define DDRSS_PI_235_DATA 0x02660010
+#define DDRSS_PI_236_DATA 0x03030266
+#define DDRSS_PI_241_DATA 0x00000010
+#define DDRSS_PI_246_DATA 0x00000266
+#define DDRSS_PI_251_DATA 0x01000266
+
+static struct ddr_reg_patch ctl_patch[] = {
+	{ 60, DDRSS_CTL_60_DATA},
+	{ 62, DDRSS_CTL_62_DATA},
+	{ 64, DDRSS_CTL_64_DATA},
+	{ 67, DDRSS_CTL_67_DATA},
+	{ 68, DDRSS_CTL_68_DATA},
+	{ 69, DDRSS_CTL_69_DATA},
+	{ 79, DDRSS_CTL_79_DATA},
+	{ 80, DDRSS_CTL_80_DATA},
+	{ 81, DDRSS_CTL_81_DATA},
+	{ 267, DDRSS_CTL_267_DATA},
+	{ 268, DDRSS_CTL_268_DATA},
+	{ 270, DDRSS_CTL_270_DATA},
+	{ 271, DDRSS_CTL_271_DATA},
+	{ 272, DDRSS_CTL_272_DATA},
+	{ 273, DDRSS_CTL_273_DATA},
+	{ 278, DDRSS_CTL_278_DATA},
+	{ 287, DDRSS_CTL_287_DATA}
+};
+
+static struct ddr_reg_patch pi_patch[] = {
+	{ 14, DDRSS_PI_14_DATA},
+	{ 29, DDRSS_PI_29_DATA},
+	{ 45, DDRSS_PI_45_DATA},
+	{ 55, DDRSS_PI_55_DATA},
+	{ 67, DDRSS_PI_67_DATA},
+	{ 73, DDRSS_PI_73_DATA},
+	{ 169, DDRSS_PI_169_DATA},
+	{ 171, DDRSS_PI_171_DATA},
+	{ 173, DDRSS_PI_173_DATA},
+	{ 235, DDRSS_PI_235_DATA},
+	{ 236, DDRSS_PI_236_DATA},
+	{ 241, DDRSS_PI_241_DATA},
+	{ 246, DDRSS_PI_246_DATA},
+	{ 251, DDRSS_PI_251_DATA}
+};
+
+static struct ddrss_patch ddrss_ctrl_patch = {
+	.ddr_fhs_cnt = DDRSS_PLL_FHS_CNT,
+	.ctl_patch = ctl_patch,
+	.ctl_patch_num = ARRAY_SIZE(ctl_patch),
+	.pi_patch = pi_patch,
+	.pi_patch_num = ARRAY_SIZE(pi_patch),
+	.phy_patch = NULL,
+	.phy_patch_num = 0
+};
+
+struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4] = {
+	&ddrss_ctrl_patch,
+	&ddrss_ctrl_patch,
+	&ddrss_ctrl_patch,
+	&ddrss_ctrl_patch
+};
--- a/board/toradex/aquila-am69/aquila_ddrs_8GB.h
+++ b/board/toradex/aquila-am69/aquila_ddrs_8GB.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+#ifndef __AQUILA_DDRS_8GB_H
+#define __AQUILA_DDRS_8GB_H
+
+#define MULTI_DDR_CFG_INTRLV_SIZE_8GB 9
+extern struct ddrss_patch *aquila_am69_ddrss_patch_8GB[4];
+
+#endif // __AQUILA_DDRS_8GB_H
--- a/board/toradex/aquila-am69/board-cfg.yaml
+++ b/board/toradex/aquila-am69/board-cfg.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+# Board configuration for AM69
+#
+
+---
+
+board-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
+    control:
+        subhdr:
+            magic: 0xC1D3
+            size: 7
+        main_isolation_enable: 0x5A
+        main_isolation_hostid: 0x2
+    secproxy:
+        subhdr:
+            magic: 0x1207
+            size: 7
+        scaling_factor: 0x1
+        scaling_profile: 0x1
+        disable_main_nav_secure_proxy: 0
+    msmc:
+        subhdr:
+            magic: 0xA5C3
+            size: 5
+        msmc_cache_size: 0x8
+    debug_cfg:
+        subhdr:
+            magic: 0x020C
+            size: 8
+        trace_dst_enables: 0x00
+        trace_src_enables: 0x00
--- a/board/toradex/aquila-am69/ddrs_patch.c
+++ b/board/toradex/aquila-am69/ddrs_patch.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#include <fdt_support.h>
+#include <linux/errno.h>
+#include <stdint.h>
+
+#include "ddrs_patch.h"
+
+static int ftd_apply_ddrss_prop_patch(void *fdt, int mem_offset, const char *prop_name,
+				      const struct ddr_reg_patch *patch_set, int patch_num)
+{
+	int ret;
+	int i;
+	u32 val;
+
+	for (i = 0; i < patch_num; i++, patch_set++) {
+		val = cpu_to_be32(patch_set->val);
+		ret = fdt_setprop_inplace_namelen_partial(fdt, mem_offset,
+							  prop_name, strlen(prop_name),
+							  patch_set->off * sizeof(u32),
+							  &val, sizeof(u32));
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int fdt_apply_ddrss_patch(void *fdt, int msmc_offset, const char *ddrs_ctrl,
+				 const struct ddrss_patch *ddrss_patch)
+{
+	int ret;
+	int mem_offset;
+
+	mem_offset = fdt_subnode_offset(fdt, msmc_offset, ddrs_ctrl);
+	if (mem_offset < 0)
+		return -ENODEV;
+
+	ret = fdt_setprop_inplace_u32(fdt, mem_offset, "ti,ddr-fhs-cnt", ddrss_patch->ddr_fhs_cnt);
+	if (ret)
+		return ret;
+
+	ret = ftd_apply_ddrss_prop_patch(fdt, mem_offset, "ti,ctl-data",
+					 ddrss_patch->ctl_patch, ddrss_patch->ctl_patch_num);
+	if (ret)
+		return ret;
+
+	ret = ftd_apply_ddrss_prop_patch(fdt, mem_offset, "ti,pi-data",
+					 ddrss_patch->pi_patch, ddrss_patch->pi_patch_num);
+	if (ret)
+		return ret;
+
+	ret = ftd_apply_ddrss_prop_patch(fdt, mem_offset, "ti,phy-data",
+					 ddrss_patch->phy_patch, ddrss_patch->phy_patch_num);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int aquila_am69_fdt_apply_ddr_patch(void *fdt, struct ddrss_patch *ddrss_patch[4], u32 intrlv_size)
+{
+	int ret;
+	int msmc_offset;
+
+	msmc_offset = fdt_path_offset(fdt, "/bus@100000/bus@30000000/msmc");
+	if (msmc_offset < 0)
+		return -ENODEV;
+
+	ret = fdt_setprop_inplace_u32(fdt, msmc_offset, "intrlv-size", intrlv_size);
+	if (ret)
+		return ret;
+
+	ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller@2990000", ddrss_patch[0]);
+	if (ret)
+		return ret;
+
+	ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller@29b0000", ddrss_patch[1]);
+	if (ret)
+		return ret;
+
+	ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller@29d0000", ddrss_patch[2]);
+	if (ret)
+		return ret;
+
+	ret = fdt_apply_ddrss_patch(fdt, msmc_offset, "memorycontroller@29f0000", ddrss_patch[3]);
+	if (ret)
+		return ret;
+
+	return 0;
+}
--- a/board/toradex/aquila-am69/ddrs_patch.h
+++ b/board/toradex/aquila-am69/ddrs_patch.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#ifndef __AQUILA_AM69_DDRS_PATCH_H
+#define __AQUILA_AM69_DDRS_PATCH_H
+
+struct ddr_reg_patch {
+	u32 off;
+	u32 val;
+};
+
+struct ddrss_patch {
+	u32 ddr_fhs_cnt;
+	struct ddr_reg_patch *ctl_patch;
+	u32 ctl_patch_num;
+	struct ddr_reg_patch *pi_patch;
+	u32 pi_patch_num;
+	struct ddr_reg_patch *phy_patch;
+	u32 phy_patch_num;
+};
+
+/**
+ * aquila_am69_fdt_apply_ddr_patch - Apply DDRSS patches to the R5 U-Boot device tree
+ * @fdt:         Pointer to the flattened device tree (FDT) blob in memory
+ * @ddrss_patch: Array of pointers to DDRSS patch structures (one per controller)
+ * @intrlv_size: Value to set for the "intrlv-size" property
+ *
+ * This function updates the MSMC node in the device tree by setting the
+ * "intrlv-size" property and applying DDRSS patches to each of the four
+ * memory controller nodes.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int aquila_am69_fdt_apply_ddr_patch(void *fdt, struct ddrss_patch *ddrss_patch[4], u32 intrlv_size);
+
+#endif // __AQUILA_AM69_DDRS_PATCH_H
--- a/board/toradex/aquila-am69/pm-cfg.yaml
+++ b/board/toradex/aquila-am69/pm-cfg.yaml
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+# Power management configuration for AM69
+#
+
+---
+
+pm-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
--- a/board/toradex/aquila-am69/rm-cfg.yaml
+++ b/board/toradex/aquila-am69/rm-cfg.yaml
--- a/board/toradex/aquila-am69/sec-cfg.yaml
+++ b/board/toradex/aquila-am69/sec-cfg.yaml
@@ -0,0 +1,380 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2025 Toradex
+#
+# Security management configuration for AM69
+#
+
+---
+
+sec-cfg:
+    rev:
+        boardcfg_abi_maj: 0x0
+        boardcfg_abi_min: 0x1
+    processor_acl_list:
+        subhdr:
+            magic: 0xF1EA
+            size: 164
+        proc_acl_entries:
+            -  # 1
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 2
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 3
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 4
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 5
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 6
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 7
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 8
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 9
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 10
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 11
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 12
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 13
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 14
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 15
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 16
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 17
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 18
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 19
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 20
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 21
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 22
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 23
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 24
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 25
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 26
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 27
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 28
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 29
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 30
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 31
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+            -  # 32
+                processor_id: 0
+                proc_access_master: 0
+                proc_access_secondary: [0, 0, 0]
+    host_hierarchy:
+        subhdr:
+            magic: 0x8D27
+            size: 68
+        host_hierarchy_entries:
+            -  # 1
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 2
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 3
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 4
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 5
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 6
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 7
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 8
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 9
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 10
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 11
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 12
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 13
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 14
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 15
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 16
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 17
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 18
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 19
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 20
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 21
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 22
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 23
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 24
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 25
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 26
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 27
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 28
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 29
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 30
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 31
+                host_id: 0
+                supervisor_host_id: 0
+            -  # 32
+                host_id: 0
+                supervisor_host_id: 0
+    otp_config:
+        subhdr:
+            magic: 0x4081
+            size: 69
+        otp_entry:
+            -  # 1
+                host_id: 0
+                host_perms: 0
+            -  # 2
+                host_id: 0
+                host_perms: 0
+            -  # 3
+                host_id: 0
+                host_perms: 0
+            -  # 4
+                host_id: 0
+                host_perms: 0
+            -  # 5
+                host_id: 0
+                host_perms: 0
+            -  # 6
+                host_id: 0
+                host_perms: 0
+            -  # 7
+                host_id: 0
+                host_perms: 0
+            -  # 8
+                host_id: 0
+                host_perms: 0
+            -  # 9
+                host_id: 0
+                host_perms: 0
+            -  # 10
+                host_id: 0
+                host_perms: 0
+            -  # 11
+                host_id: 0
+                host_perms: 0
+            -  # 12
+                host_id: 0
+                host_perms: 0
+            -  # 13
+                host_id: 0
+                host_perms: 0
+            -  # 14
+                host_id: 0
+                host_perms: 0
+            -  # 15
+                host_id: 0
+                host_perms: 0
+            -  # 16
+                host_id: 0
+                host_perms: 0
+            -  # 17
+                host_id: 0
+                host_perms: 0
+            -  # 18
+                host_id: 0
+                host_perms: 0
+            -  # 19
+                host_id: 0
+                host_perms: 0
+            -  # 20
+                host_id: 0
+                host_perms: 0
+            -  # 21
+                host_id: 0
+                host_perms: 0
+            -  # 22
+                host_id: 0
+                host_perms: 0
+            -  # 23
+                host_id: 0
+                host_perms: 0
+            -  # 24
+                host_id: 0
+                host_perms: 0
+            -  # 25
+                host_id: 0
+                host_perms: 0
+            -  # 26
+                host_id: 0
+                host_perms: 0
+            -  # 27
+                host_id: 0
+                host_perms: 0
+            -  # 28
+                host_id: 0
+                host_perms: 0
+            -  # 29
+                host_id: 0
+                host_perms: 0
+            -  # 30
+                host_id: 0
+                host_perms: 0
+            -  # 31
+                host_id: 0
+                host_perms: 0
+            -  # 32
+                host_id: 0
+                host_perms: 0
+        write_host_id: 0
+    dkek_config:
+        subhdr:
+            magic: 0x5170
+            size: 12
+        allowed_hosts: [128, 0, 0, 0]
+        allow_dkek_export_tisci: 0x5A
+        rsvd: [0, 0, 0]
+    sa2ul_cfg:
+        subhdr:
+            magic: 0x23BE
+            size: 0
+        auth_resource_owner: 0
+        enable_saul_psil_global_config_writes: 0
+        rsvd: [0, 0]
+    sec_dbg_config:
+        subhdr:
+            magic: 0x42AF
+            size: 16
+        allow_jtag_unlock: 0x0
+        allow_wildcard_unlock: 0x0
+        allowed_debug_level_rsvd: 0
+        rsvd: 0
+        min_cert_rev: 0x0
+        jtag_unlock_hosts: [0, 0, 0, 0]
+    sec_handover_cfg:
+        subhdr:
+            magic: 0x608F
+            size: 10
+        handover_msg_sender: 0
+        handover_to_host_id: 0
+        rsvd: [0, 0, 0, 0]
--- a/board/toradex/aquila-am69/tifs-rm-cfg.yaml
+++ b/board/toradex/aquila-am69/tifs-rm-cfg.yaml
--- a/configs/aquila-am69_a72_defconfig
+++ b/configs/aquila-am69_a72_defconfig
@@ -0,0 +1,179 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_TARGET_AQUILA_AM69_A72=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am69-aquila-dev"
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x80a00000
+CONFIG_SPL_BSS_MAX_SIZE=0x80000
+CONFIG_SPL_STACK_R=y
+CONFIG_SYS_LOAD_ADDR=0x88200000
+CONFIG_SPL_SIZE_LIMIT=0x80000
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_MEMTEST_START=0x80000000
+CONFIG_SYS_MEMTEST_END=0xB0000000
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTSTD_FULL=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="bootflow scan -b"
+CONFIG_USE_PREBOOT=y
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am69-aquila-${fdt_board}.dtb"
+CONFIG_LOG=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_BOARD_INIT is not set
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SYS_PROMPT="Aquila AM69 # "
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_EXPORTENV is not set
+CONFIG_CRC32_VERIFY=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_MD5SUM_VERIFY=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_BOOTCOUNT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_USE_ETHPRIME=y
+CONFIG_ETHPRIME="eth0"
+CONFIG_VERSION_VARIABLE=y
+CONFIG_IP_DEFRAG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_BOOTCOUNT_ENV=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_CCF=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
+CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_UUU_SUPPORT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_TORRENT=y
+CONFIG_PHY_J721E_WIZ=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_USB_GADGET_OS_DESCRIPTORS=y
+CONFIG_SPL_DFU=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_HEXDUMP=y
+# CONFIG_OPTEE_LIB is not set
--- a/configs/aquila-am69_r5_defconfig
+++ b/configs/aquila-am69_r5_defconfig
@@ -0,0 +1,134 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SOC_K3_J784S4=y
+CONFIG_K3_EARLY_CONS=y
+CONFIG_K3_QOS=y
+CONFIG_TARGET_AQUILA_AM69_R5=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am69-r5-aquila-dev"
+CONFIG_DM_RESET=y
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_TEXT_BASE=0x41c00000
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x41c76000
+CONFIG_SPL_BSS_MAX_SIZE=0xa000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x140000
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SPL_SIZE_LIMIT=0x100000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_LIBDISK_SUPPORT=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=4
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_BOARD_INIT is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_MAX_SIZE=0xc0000
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_THERMAL=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_ESM_K3=y
+CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_TPS65941=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR_TPS6287X=y
+CONFIG_DM_REGULATOR_TPS65941=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Toradex"
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
+CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_SPL_DFU=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
--- a/doc/board/toradex/aquila-am69.rst
+++ b/doc/board/toradex/aquila-am69.rst
@@ -0,0 +1,219 @@
+.. SPDX-License-Identifier: GPL-2.0-only
+.. sectionauthor:: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
+
+Aquila AM69 Module
+==================
+
+Quick Start
+-----------
+
+- Setup environment variables
+- Get binary-only TI Linux firmware
+- Build the ARM trusted firmware binary
+- Build the OPTEE binary
+- Build U-Boot for the R5
+- Build U-Boot for the A72
+- Flash to eMMC
+- Boot
+
+Setup environment
+-----------------
+
+Suggested current toolchains are ARM 11.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads):
+
+- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz
+- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz
+
+.. code-block:: console
+
+    $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf-
+    $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu-
+
+Get the TI Linux Firmware
+-------------------------
+
+.. code-block:: console
+
+    $ echo "Downloading TI Linux Firmware..."
+    $ git clone -b ti-linux-firmware https://git.ti.com/git/processor-firmware/ti-linux-firmware.git
+
+Get and Build the ARM Trusted Firmware (Trusted Firmware A)
+-----------------------------------------------------------
+
+.. code-block:: console
+
+    $ echo "Downloading and building TF-A..."
+    $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+    $ cd trusted-firmware-a
+
+Then build ATF (TF-A):
+
+.. code-block:: console
+
+    $ export CROSS_COMPILE="$CROSS_COMPILE_64"
+    $ make PLAT=k3 TARGET_BOARD=j784s4 SPD=opteed K3_USART=0x8
+
+Get and Build OPTEE
+-------------------
+
+.. code-block:: console
+
+    $ echo "Downloading and building OPTEE..."
+    $ git clone https://github.com/OP-TEE/optee_os.git
+    $ cd optee_os
+
+Then build OPTEE:
+
+.. code-block:: console
+
+    $ export CROSS_COMPILE="$CROSS_COMPILE_32"
+    $ export CROSS_COMPILE64="$CROSS_COMPILE_64"
+    $ export CFG_CONSOLE_UART=0x8
+    $ make PLATFORM=k3-j784s4 CFG_ARM64_core=y
+
+Build U-Boot for R5
+-------------------
+
+.. code-block:: console
+
+    $ export CROSS_COMPILE="$CROSS_COMPILE_32"
+    $ export BINMAN_INDIRS=<path/to/ti-linux-firmware>
+    $ make O=/tmp/aquila-r5 aquila-am69_r5_config
+    $ make O=/tmp/aquila-r5
+
+Build U-Boot for A72
+--------------------
+
+.. code-block:: console
+
+    $ export CROSS_COMPILE=$CROSS_COMPILE_64
+    $ export BL31=<path/to/atf>/build/k3/j784s4/release/bl31.bin
+    $ export TEE=<path/to/optee>/out/arm-plat-k3/core/tee-pager_v2.bin
+    $ export BINMAN_INDIRS="<path/to/ti-linux-firmware> /tmp/aquila-r5"
+    $ make O=/tmp/aquila-a72 aquila-am69_a72_config
+    $ make O=/tmp/aquila-a72
+
+Flash to eMMC
+-------------
+
+.. code-block:: console
+
+    => mmc dev 0 1
+    => fatload mmc 1 ${loadaddr} tiboot3.bin
+    => mmc write ${loadaddr} 0x0 0x400
+    => fatload mmc 1 ${loadaddr} tispl.bin
+    => mmc write ${loadaddr} 0x400 0x1000
+    => fatload mmc 1 ${loadaddr} u-boot.img
+    => mmc write ${loadaddr} 0x1400 0xc00
+
+As a convenience, instead of having to remember all those addresses and sizes,
+one may also use the update U-Boot wrappers:
+
+.. code-block:: console
+
+    => tftpboot ${loadaddr} tiboot3.bin
+    => run update_tiboot3
+
+    => tftpboot ${loadaddr} tispl.bin
+    => run update_tispl
+
+    => tftpboot ${loadaddr} u-boot.img
+    => run update_uboot
+
+Boot
+----
+
+Output::
+
+  U-Boot SPL 2026.01-rc1-00200-g39abfe677ff5-dirty (Nov 03 2025 - 18:09:30 +0100)
+  SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
+  HW CFG: 0x00
+  Initialized 4 DRAM controllers
+  SPL initial stack usage: 13552 bytes
+  Trying to boot from MMC1
+  Authentication passed
+  Authentication passed
+  Authentication passed
+  Loading Environment from nowhere... OK
+  init_env from device 17 not supported!
+  Authentication passed
+  Authentication passed
+  Starting ATF on ARM64 core...
+
+  NOTICE:  BL31: v2.13.0(release):v2.13.0-1063-g7a0a320df
+  NOTICE:  BL31: Built : 13:30:07, Oct 28 2025
+  I/TC: 
+  I/TC: OP-TEE version: 4.8.0 (gcc version 11.3.1 20220712 (Arm GNU Toolchain 11.3.Rel1)) #1 Tue Oct 28 12:32:30 UTC 2025 aarch64
+  I/TC: WARNING: This OP-TEE configuration might be insecure!
+  I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
+  I/TC: Primary CPU initializing
+  I/TC: GIC redistributor base address not provided
+  I/TC: Assuming default GIC group status and modifier
+  I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
+  I/TC: Activated SA2UL device
+  I/TC: Enabled firewalls for SA2UL TRNG device
+  I/TC: EIP76D TRNG initialized
+  I/TC: SA2UL Drivers initialized
+  I/TC: HUK Initialized
+  I/TC: Disabling output console
+
+  U-Boot SPL 2026.01-rc1-00200-g39abfe677ff5-dirty (Nov 03 2025 - 18:11:30 +0100)
+  Unable to shutdown MCU R5 core 1, -22
+  SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
+  DM ABI: 3.0 (firmware ver 0x000b 'PSDK.11.01.00.04--v11.01.08a' patch_ver: 8)
+  HW CFG: 0x00
+  Trying to boot from MMC1
+  Authentication passed
+  Authentication passed
+
+
+  U-Boot 2026.01-rc1-00200-g39abfe677ff5-dirty (Nov 03 2025 - 18:11:30 +0100)
+
+  SoC:   J784S4 SR1.0 HS-FS
+  DRAM:  2 GiB (total 32 GiB)
+  optee optee: OP-TEE: revision 4.8 (86660925433a8d4d)
+  Core:  191 devices, 35 uclasses, devicetree: separate
+  MMC:   mmc@4f80000: 0, mmc@4fb0000: 1
+  Loading Environment from MMC... Reading from MMC(0)... OK
+  MISSING TORADEX CARRIER CONFIG BLOCKS
+  In:    serial@2880000
+  Out:   serial@2880000
+  Err:   serial@2880000
+  Model: Toradex 0088 Aquila AM69 Octa 32GB WB IT V1.1A
+  Serial#: 12593784
+  Net:   am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1
+
+  Warning: ethernet@46000000port@1 MAC addresses don't match:
+  Address in ROM is               c0:d6:0a:de:0e:e6
+  Address in environment is       00:14:2d:c0:2a:78
+  eth0: ethernet@46000000port@1 [PRIME]
+  Hit any key to stop autoboot: 0
+  MMC: no card present
+  Cannot persist EFI variables without system partition
+  ** Booting bootflow '<NULL>' with efi_mgr
+  Loading Boot0000 'mmc 0' failed
+  EFI boot manager: Cannot load any image
+  Boot failed (err=-14)
+  MMC: no card present
+  MMC: no card present
+  MMC: no card present
+  MMC: no card present
+  ** Booting bootflow 'mmc@4f80000.bootdev.part_1' with script
+  Loading DeviceTree: k3-am69-aquila-dev.dtb
+  142461 bytes read in 2 ms (67.9 MiB/s)
+  87 bytes read in 1 ms (85 KiB/s)
+  Working FDT set to 90200000
+  Applying Overlay: aquila-am69_spi1_spidev_overlay.dtbo
+  560 bytes read in 1 ms (546.9 KiB/s)
+  Applying Overlay: aquila-am69_spi2_spidev_overlay.dtbo
+  560 bytes read in 1 ms (546.9 KiB/s)
+  7937825 bytes read in 28 ms (270.4 MiB/s)
+  Bootargs: root=PARTUUID=1d80c51f-02 ro rootwait console=tty1 console=ttyS2,115200
+     Uncompressing Kernel Image to 0
+  ## Flattened Device Tree blob at 90200000
+     Booting using the fdt blob at 0x90200000
+  Working FDT set to 90200000
+     Loading Device Tree to 00000000fce5c000, end 00000000fcea1fff ... OK
+  Working FDT set to fce5c000
+
+  Starting kernel ...
--- a/doc/board/toradex/index.rst
+++ b/doc/board/toradex/index.rst
@@ -7,6 +7,7 @@ Toradex
   :maxdepth: 2

   apalis-imx8
+   aquila-am69
   colibri_imx7
   colibri-imx8x
   smarc-imx8mp
--- a/include/configs/aquila-am69.h
+++ b/include/configs/aquila-am69.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Configuration header file for Aquila AM69 SoM
+ *
+ * Copyright (C) 2025 Toradex - https://www.toradex.com/
+ */
+
+#ifndef __CONFIG_AQUILA_AM69_H
+#define __CONFIG_AQUILA_AM69_H
+
+/* DDR Configuration */
+#define CFG_SYS_SDRAM_BASE		0x80000000
+#define CFG_SYS_SDRAM_BASE1		0x880000000
+
+#endif /* __CONFIG_AQUILA_AM69_H */