armv7: Add CPLD support via IFC to the ls1021a-iot board.

This patch adds CPLD support via IFC to the ls1021a-iot board.

Signed-off-by: Mateus Lima Alves <mateuslima.ti@gmail.com>

board/freescale/ls1021aiot/ls1021aiot.c

@@ -21,6 +21,7 @@
 #include <asm/sections.h>
 #include <fsl_csu.h>
 #include <fsl_immap.h>
+#include <fsl_ifc.h>
 #include <netdev.h>
 #include <fsl_mdio.h>
 #include <tsec.h>
@@ -120,6 +121,10 @@ int board_early_init_f(void)
 
 #endif
 
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+
 	arch_soc_init();
 
 	return 0;

configs/ls1021aiot_sdcard_defconfig

@@ -106,3 +106,4 @@ CONFIG_FSL_QSPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
+CONFIG_FSL_IFC=y

drivers/misc/Kconfig

@@ -694,7 +694,12 @@ config ESM_PMIC
 	  typically to reboot the board in error condition.
 
 config FSL_IFC
-	bool
+	bool "Freescale Integrated Flash Controller"
+	depends on ARM
+	help
+	  This driver is for the Integrated Flash Controller(IFC) module
+	  available in Freescale SoCs. This controller allows to handle
+	  devices such as NOR, NAND, FPGA and ASIC etc.
 
 config SL28CPLD
 	bool "Enable Kontron sl28cpld multi-function driver"

include/configs/ls1021aiot.h

@@ -44,6 +44,40 @@
 #define CFG_SYS_DDR_SDRAM_BASE	0x80000000UL
 #define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
+/* CPLD */
+
+#define CFG_SYS_CPLD_BASE              0x7fb00000
+#define CPLD_BASE_PHYS                 CFG_SYS_CPLD_BASE
+
+#define CFG_SYS_FPGA_CSPR_EXT          (0x0)
+#define CFG_SYS_FPGA_CSPR              (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
+                                        CSPR_PORT_SIZE_8 | \
+                                        CSPR_MSEL_GPCM | \
+                                        CSPR_V)
+#define CFG_SYS_FPGA_AMASK             IFC_AMASK(64 * 1024)
+#define CFG_SYS_FPGA_CSOR              (CSOR_NOR_ADM_SHIFT(4) | \
+                                        CSOR_NOR_NOR_MODE_AVD_NOR | \
+                                        CSOR_NOR_TRHZ_80)
+
+/* CPLD Timing parameters for IFC GPCM */
+#define CFG_SYS_FPGA_FTIM0             (FTIM0_GPCM_TACSE(0xf) | \
+                                        FTIM0_GPCM_TEADC(0xf) | \
+                                        FTIM0_GPCM_TEAHC(0xf))
+#define CFG_SYS_FPGA_FTIM1             (FTIM1_GPCM_TACO(0xff) | \
+                                        FTIM1_GPCM_TRAD(0x3f))
+#define CFG_SYS_FPGA_FTIM2             (FTIM2_GPCM_TCS(0xf) | \
+                                        FTIM2_GPCM_TCH(0xf) | \
+                                        FTIM2_GPCM_TWP(0xff))
+#define CFG_SYS_FPGA_FTIM3             0x0
+#define CFG_SYS_CSPR0_EXT              CFG_SYS_FPGA_CSPR_EXT
+#define CFG_SYS_CSPR0                  CFG_SYS_FPGA_CSPR
+#define CFG_SYS_AMASK0                 CFG_SYS_FPGA_AMASK
+#define CFG_SYS_CSOR0                  CFG_SYS_FPGA_CSOR
+#define CFG_SYS_CS0_FTIM0              CFG_SYS_FPGA_FTIM0
+#define CFG_SYS_CS0_FTIM1              CFG_SYS_FPGA_FTIM1
+#define CFG_SYS_CS0_FTIM2              CFG_SYS_FPGA_FTIM2
+#define CFG_SYS_CS0_FTIM3              CFG_SYS_FPGA_FTIM3
+
 /*
  * Serial Port
  */