mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
* Patch by Robert Schwebel, 21 Jan 2003:
- Add support for Innokom board - Don't complain if "install" fails - README cleanup (remove duplicated lines) - Update PXA header files * Add documentation for existing POST code (doc/README.POST) * Patch by Laudney Ren, 15 Jan 2003: Fix handling of redundand environment in "tools/envcrc.c" * Patch by Detlev Zundel, 28 Feb 2003: Add bedbug support for 824x systems * Add support for 16 MB flash configuration of TRAB board * Patch by Erwin Rol, 27 Feb 2003: Add support for RTEMS * Add image information to README * Fix dual PCMCIA slot support (when running with just one slot populated) * Add VFD type detection to trab board * extend drivers/cs8900.c driver to synchronize ethaddr environment variable with value in the EEPROM
This commit is contained in:
wdenk
@@ -10,6 +10,8 @@
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* published by the Free Software Foundation.
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*/
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#ifndef PXA_REGS_H
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#define PXA_REGS_H 1
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/* FIXME hack so that SA-1111.h will work [cb] */
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@@ -425,6 +427,38 @@ typedef void (*ExcpHndlr) (void) ;
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#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
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#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
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/* ----- Control register bits ---------------------------------------- */
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#define ICR_START 0x1 /* start bit */
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#define ICR_STOP 0x2 /* stop bit */
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
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#define ICR_SCLE 0x20 /* master clock enable */
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#define ICR_IUE 0x40 /* unit enable */
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#define ICR_GCD 0x80 /* general call disable */
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#define ICR_ITEIE 0x100 /* enable tx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts */
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#define ICR_BEIE 0x400 /* enable bus error ints */
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#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
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#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
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#define ICR_SADIE 0x2000 /* slave address detected int enable */
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#define ICR_UR 0x4000 /* unit reset */
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/* ----- Status register bits ----------------------------------------- */
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#define ISR_RWM 0x1 /* read/write mode */
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#define ISR_ACKNAK 0x2 /* ack/nak status */
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#define ISR_UB 0x4 /* unit busy */
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#define ISR_IBB 0x8 /* bus busy */
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#define ISR_SSD 0x10 /* slave stop detected */
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#define ISR_ALD 0x20 /* arbitration loss detected */
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#define ISR_ITE 0x40 /* tx buffer empty */
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#define ISR_IRF 0x80 /* rx buffer full */
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#define ISR_GCAD 0x100 /* general call address detected */
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#define ISR_SAD 0x200 /* slave address detected */
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#define ISR_BED 0x400 /* bus error no ACK/NAK */
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/*
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* Serial Audio Controller
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@@ -1128,6 +1162,6 @@ typedef void (*ExcpHndlr) (void) ;
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#define MCIO1_OFFSET 0x3C
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#define MDMRS_OFFSET 0x40
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#endif /* PXA_REGS_H */
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@@ -1,15 +1,23 @@
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/*
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* linux/include/asm-arm/arch-pxa/pxa-regs.h
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*
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
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* Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
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* Added include for hardware.h (for __REG definition)
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*/
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#ifndef _PXA_REGS_H_
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#define _PXA_REGS_H_
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#include "bitfield.h"
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#include "hardware.h"
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/* FIXME hack so that SA-1111.h will work [cb] */
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@@ -22,13 +30,6 @@ typedef void *Address ;
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typedef void (*ExcpHndlr) (void) ;
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#endif
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#ifndef __ASSEMBLY__
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#define io_p2v(PhAdd) (PhAdd)
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#define __REG(x) (*((volatile u32 *)io_p2v(x)))
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#else
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#define __REG(x) (x)
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#endif
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/*
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* PXA Chip selects
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*/
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@@ -369,7 +370,7 @@ typedef void (*ExcpHndlr) (void) ;
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#define LSR_OE (1 << 1) /* Overrun Error */
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#define LSR_DR (1 << 0) /* Data Ready */
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#define MCR_LOOP (1 << 4) */
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#define MCR_LOOP (1 << 4) */
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#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
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#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
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#define MCR_RTS (1 << 1) /* Request to Send */
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@@ -414,7 +415,6 @@ typedef void (*ExcpHndlr) (void) ;
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IrSR_RCVEIR_UART_MODE | \
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IrSR_XMITIR_IR_MODE)
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/*
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* I2C registers
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*/
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@@ -425,6 +425,38 @@ typedef void (*ExcpHndlr) (void) ;
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#define ISR __REG(0x40301698) /* I2C Status Register - ISR */
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#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
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/* ----- Control register bits ---------------------------------------- */
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#define ICR_START 0x1 /* start bit */
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#define ICR_STOP 0x2 /* stop bit */
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
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#define ICR_SCLE 0x20 /* master clock enable */
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#define ICR_IUE 0x40 /* unit enable */
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#define ICR_GCD 0x80 /* general call disable */
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#define ICR_ITEIE 0x100 /* enable tx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts */
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#define ICR_BEIE 0x400 /* enable bus error ints */
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#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
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#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
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#define ICR_SADIE 0x2000 /* slave address detected int enable */
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#define ICR_UR 0x4000 /* unit reset */
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#define ICR_FM 0x8000 /* Fast Mode */
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/* ----- Status register bits ----------------------------------------- */
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#define ISR_RWM 0x1 /* read/write mode */
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#define ISR_ACKNAK 0x2 /* ack/nak status */
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#define ISR_UB 0x4 /* unit busy */
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#define ISR_IBB 0x8 /* bus busy */
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#define ISR_SSD 0x10 /* slave stop detected */
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#define ISR_ALD 0x20 /* arbitration loss detected */
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#define ISR_ITE 0x40 /* tx buffer empty */
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#define ISR_IRF 0x80 /* rx buffer full */
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#define ISR_GCAD 0x100 /* general call address detected */
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#define ISR_SAD 0x200 /* slave address detected */
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#define ISR_BED 0x400 /* bus error no ACK/NAK */
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/*
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* Serial Audio Controller
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@@ -524,24 +556,92 @@ typedef void (*ExcpHndlr) (void) ;
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/*
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* USB Device Controller
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*/
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#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
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#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
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#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
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#define UDCCR __REG(0x40600000) /* UDC Control Register */
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#define UDCCR_UDE (1 << 0) /* UDC enable */
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#define UDCCR_UDA (1 << 1) /* UDC active */
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#define UDCCR_RSM (1 << 2) /* Device resume */
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#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
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#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
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#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
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#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
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#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
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#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
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#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
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#define UDCCS0_IPR (1 << 1) /* IN packet ready */
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#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
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#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
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#define UDCCS0_SST (1 << 4) /* Sent stall */
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#define UDCCS0_FST (1 << 5) /* Force stall */
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#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
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#define UDCCS0_SA (1 << 7) /* Setup active */
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/* Bulk IN - Endpoint 1,6,11 */
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#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
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#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
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#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
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#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
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#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
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#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
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#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
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#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
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#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
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#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
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#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
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#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
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#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
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#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
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#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
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#define UDCCS_BI_SST (1 << 4) /* Sent stall */
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#define UDCCS_BI_FST (1 << 5) /* Force stall */
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#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
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/* Bulk OUT - Endpoint 2,7,12 */
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#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
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#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
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#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
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#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
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#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
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#define UDCCS_BO_DME (1 << 3) /* DMA enable */
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#define UDCCS_BO_SST (1 << 4) /* Sent stall */
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#define UDCCS_BO_FST (1 << 5) /* Force stall */
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#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
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#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
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/* Isochronous IN - Endpoint 3,8,13 */
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#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
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#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
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#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
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#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
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#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
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#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
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#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
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#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
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/* Isochronous OUT - Endpoint 4,9,14 */
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#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
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#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
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#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
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#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
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#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
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#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
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#define UDCCS_IO_DME (1 << 3) /* DMA enable */
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#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
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#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
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/* Interrupt IN - Endpoint 5,10,15 */
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#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
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#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
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#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
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#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
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#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
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#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
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#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
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#define UDCCS_INT_SST (1 << 4) /* Sent stall */
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#define UDCCS_INT_FST (1 << 5) /* Force stall */
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#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
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#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
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#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
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#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
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@@ -566,11 +666,51 @@ typedef void (*ExcpHndlr) (void) ;
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#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
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#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
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#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
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#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
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#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
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#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
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#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
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#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
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#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
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#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
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#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
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#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
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#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
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#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
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#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
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#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
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#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
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#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
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#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
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#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
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#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
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#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
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#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
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#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
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#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
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#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
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#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
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#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
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#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
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#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
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#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
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#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
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#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
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#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
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#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
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#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
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#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
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#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
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#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
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/*
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* Fast Infrared Communication Port
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@@ -917,6 +1057,22 @@ typedef void (*ExcpHndlr) (void) ;
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#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
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#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
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#define PSSR_RDH (1 << 5) /* Read Disable Hold */
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#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
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#define PSSR_VFS (1 << 2) /* VDD Fault Status */
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#define PSSR_BFS (1 << 1) /* Battery Fault Status */
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#define PSSR_SSS (1 << 0) /* Software Sleep Status */
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#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
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#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
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#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
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#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
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#define RCSR_GPR (1 << 3) /* GPIO Reset */
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#define RCSR_SMR (1 << 2) /* Sleep Mode */
|
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#define RCSR_WDR (1 << 1) /* Watchdog Reset */
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#define RCSR_HWR (1 << 0) /* Hardware Reset */
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/*
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* SSP Serial Port Registers
|
||||
@@ -1040,19 +1196,105 @@ typedef void (*ExcpHndlr) (void) ;
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#define LCCR0_BM (1 << 20) /* Branch mask */
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#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
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#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
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#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
|
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(((Pixel) - 1) << FShft (LCCR1_PPL))
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||||
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||||
#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
|
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#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
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/* pulse Width [1..64 Tpix] */ \
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(((Tpix) - 1) << FShft (LCCR1_HSW))
|
||||
|
||||
#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
|
||||
/* count - 1 [Tpix] */
|
||||
#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
|
||||
/* [1..256 Tpix] */ \
|
||||
(((Tpix) - 1) << FShft (LCCR1_ELW))
|
||||
|
||||
#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
|
||||
/* Wait count - 1 [Tpix] */
|
||||
#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
|
||||
/* [1..256 Tpix] */ \
|
||||
(((Tpix) - 1) << FShft (LCCR1_BLW))
|
||||
|
||||
|
||||
#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
|
||||
#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
|
||||
(((Line) - 1) << FShft (LCCR2_LPP))
|
||||
|
||||
#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
|
||||
/* Width - 1 [Tln] (L_FCLK) */
|
||||
#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
|
||||
/* Width [1..64 Tln] */ \
|
||||
(((Tln) - 1) << FShft (LCCR2_VSW))
|
||||
|
||||
#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
|
||||
/* count [Tln] */
|
||||
#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
|
||||
/* [0..255 Tln] */ \
|
||||
((Tln) << FShft (LCCR2_EFW))
|
||||
|
||||
#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
|
||||
/* Wait count [Tln] */
|
||||
#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
|
||||
/* [0..255 Tln] */ \
|
||||
((Tln) << FShft (LCCR2_BFW))
|
||||
|
||||
#if 0
|
||||
#define LCCR3_PCD (0xff) /* Pixel clock divisor */
|
||||
#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
|
||||
#define LCCR3_ACB_S 8
|
||||
#endif
|
||||
|
||||
#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
|
||||
#define LCCR3_API_S 16
|
||||
#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
|
||||
#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
|
||||
#define LCCR3_PCP (1 << 22) /* pixel clock polarity */
|
||||
#define LCCR3_OEP (1 << 23) /* output enable polarity */
|
||||
#if 0
|
||||
#define LCCR3_BPP (7 << 24) /* bits per pixel */
|
||||
#define LCCR3_BPP_S 24
|
||||
#endif
|
||||
#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
|
||||
|
||||
|
||||
#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
|
||||
#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
|
||||
(((Div) << FShft (LCCR3_PCD)))
|
||||
|
||||
|
||||
#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
|
||||
#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
|
||||
(((Bpp) << FShft (LCCR3_BPP)))
|
||||
|
||||
#define LCCR3_ACB Fld (8, 8) /* AC Bias */
|
||||
#define LCCR3_Acb(Acb) /* BAC Bias */ \
|
||||
(((Acb) << FShft (LCCR3_ACB)))
|
||||
|
||||
#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
|
||||
/* pulse active High */
|
||||
#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
|
||||
|
||||
#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
|
||||
/* active High */
|
||||
#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
|
||||
/* active Low */
|
||||
|
||||
#define LCSR_LDD (1 << 0) /* LCD Disable Done */
|
||||
#define LCSR_SOF (1 << 1) /* Start of frame */
|
||||
#define LCSR_BER (1 << 2) /* Bus error */
|
||||
#define LCSR_ABC (1 << 3) /* AC Bias count */
|
||||
#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
|
||||
#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
|
||||
#define LCSR_OU (1 << 6) /* output FIFO underrun */
|
||||
#define LCSR_QD (1 << 7) /* quick disable */
|
||||
#define LCSR_EOF (1 << 8) /* end of frame */
|
||||
#define LCSR_BS (1 << 9) /* branch status */
|
||||
#define LCSR_SINT (1 << 10) /* subsequent interrupt */
|
||||
|
||||
#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
|
||||
|
||||
#define LCSR_LDD (1 << 0) /* LCD Disable Done */
|
||||
#define LCSR_SOF (1 << 1) /* Start of frame */
|
||||
#define LCSR_BER (1 << 2) /* Bus error */
|
||||
@@ -1071,45 +1313,7 @@ typedef void (*ExcpHndlr) (void) ;
|
||||
* Memory controller
|
||||
*/
|
||||
|
||||
#define MEMC_BASE __REG(0x48000000) /* Base of Memoriy Controller */
|
||||
#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
|
||||
#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
|
||||
#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
|
||||
#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
|
||||
#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
|
||||
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
|
||||
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
|
||||
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
|
||||
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
|
||||
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
|
||||
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
|
||||
#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
|
||||
#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
|
||||
#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
|
||||
#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
|
||||
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
|
||||
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
|
||||
|
||||
#define MDCNFG_DE0 0x00000001
|
||||
#define MDCNFG_DE1 0x00000002
|
||||
#define MDCNFG_DE2 0x00010000
|
||||
#define MDCNFG_DE3 0x00020000
|
||||
#define MDCNFG_DWID0 0x00000004
|
||||
|
||||
#define MDREFR_E0PIN 0x00001000
|
||||
#define MDREFR_K0RUN 0x00002000
|
||||
#define MDREFR_K0DB2 0x00004000
|
||||
#define MDREFR_E1PIN 0x00008000
|
||||
#define MDREFR_K1RUN 0x00010000
|
||||
#define MDREFR_K1DB2 0x00020000
|
||||
#define MDREFR_K2RUN 0x00040000
|
||||
#define MDREFR_K2DB2 0x00080000
|
||||
#define MDREFR_APD 0x00100000
|
||||
#define MDREFR_SLFRSH 0x00400000
|
||||
#define MDREFR_K0FREE 0x00800000
|
||||
#define MDREFR_K1FREE 0x01000000
|
||||
#define MDREFR_K2FREE 0x02000000
|
||||
|
||||
#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
|
||||
#define MDCNFG_OFFSET 0x0
|
||||
#define MDREFR_OFFSET 0x4
|
||||
#define MSC0_OFFSET 0x8
|
||||
@@ -1127,7 +1331,44 @@ typedef void (*ExcpHndlr) (void) ;
|
||||
#define MCIO0_OFFSET 0x38
|
||||
#define MCIO1_OFFSET 0x3C
|
||||
#define MDMRS_OFFSET 0x40
|
||||
|
||||
#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
|
||||
#define MDCNFG_DE0 0x00000001
|
||||
#define MDCNFG_DE1 0x00000002
|
||||
#define MDCNFG_DE2 0x00010000
|
||||
#define MDCNFG_DE3 0x00020000
|
||||
#define MDCNFG_DWID0 0x00000004
|
||||
|
||||
#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
|
||||
#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
|
||||
#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
|
||||
#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
|
||||
#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
|
||||
#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
|
||||
#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
|
||||
#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
|
||||
#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
|
||||
#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
|
||||
#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
|
||||
#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
|
||||
#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
|
||||
#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
|
||||
#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
|
||||
#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
|
||||
|
||||
#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
|
||||
#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
|
||||
#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
|
||||
#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
|
||||
#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
|
||||
#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
|
||||
#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
|
||||
#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
|
||||
#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
|
||||
#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
|
||||
#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
|
||||
#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
|
||||
#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -61,6 +61,8 @@ struct pt_regs {
|
||||
#define ARM_r0 uregs[0]
|
||||
#define ARM_ORIG_r0 uregs[17]
|
||||
|
||||
#define instruction_pointer(regs) ((regs)->ARM_ip)
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define user_mode(regs) \
|
||||
|
||||
444
include/configs/innokom.h
Normal file
444
include/configs/innokom.h
Normal file
@@ -0,0 +1,444 @@
|
||||
/*
|
||||
* (C) Copyright 2000, 2001, 2002
|
||||
* Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
|
||||
*
|
||||
* Configuration for the Auerswald Innokom CPU board.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* include/configs/innokom.h - configuration options, board specific
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define DEBUG 1
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start U-Boot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#define CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
|
||||
#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
/* for timer/console/ethernet */
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 19200
|
||||
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_I2C | CFG_CMD_EEPROM) & ~CFG_CMD_NET)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */
|
||||
#define CONFIG_BOOTARGS "console=ttyS0,19200"
|
||||
#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 192.168.1.56
|
||||
#define CONFIG_SERVERIP 192.168.1.2
|
||||
#define CONFIG_BOOTCOMMAND "bootm 0x40000"
|
||||
#define CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
|
||||
/*
|
||||
* Size of malloc() pool; this lives below the uppermost 128 KiB which are
|
||||
* used for the RAM copy of the uboot code
|
||||
*/
|
||||
/* #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) */
|
||||
#define CFG_MALLOC_LEN (128*1024)
|
||||
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 128 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */
|
||||
/* RS: where is this documented? */
|
||||
/* RS: is this where U-Boot is */
|
||||
/* RS: relocated to in RAM? */
|
||||
|
||||
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
|
||||
/* RS: the oscillator is actually 3680130?? */
|
||||
|
||||
#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
|
||||
/* 0101000001 */
|
||||
/* ^^^^^ Memory Speed 99.53 MHz */
|
||||
/* ^^ Run Mode Speed = 2x Mem Speed */
|
||||
/* ^^ Turbo Mode Sp. = 1x Run M. Sp. */
|
||||
|
||||
#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*
|
||||
* I2C bus
|
||||
*/
|
||||
#define CONFIG_HARD_I2C 1
|
||||
#define CFG_I2C_SPEED 50000
|
||||
#define CFG_I2C_SLAVE 0xfe
|
||||
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
|
||||
#define CFG_ENV_OFFSET 0x00 /* environment starts here */
|
||||
#define CFG_ENV_SIZE 1024 /* 1 KiB */
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */
|
||||
#define CFG_EEPROM_SIZE 4096 /* size in bytes */
|
||||
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
|
||||
|
||||
#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */
|
||||
#define CFG_DRAM_SIZE 0x04000000
|
||||
|
||||
#define CFG_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*
|
||||
* GPIO settings;
|
||||
*/
|
||||
|
||||
/* GP15 == nCS1 is 1
|
||||
* GP24 == SFRM is 1
|
||||
* GP25 == TXD is 1
|
||||
* GP33 == nCS5 is 1
|
||||
* GP39 == FFTXD is 1
|
||||
* GP41 == RTS is 1
|
||||
* GP47 == TXD is 1
|
||||
* GP49 == nPWE is 1
|
||||
* GP62 == LED_B is 1
|
||||
* GP63 == TDM_OE is 1
|
||||
* GP78 == nCS2 is 1
|
||||
* GP79 == nCS3 is 1
|
||||
* GP80 == nCS4 is 1
|
||||
*/
|
||||
#define CFG_GPSR0_VAL 0x03008000
|
||||
#define CFG_GPSR1_VAL 0xC0028282
|
||||
#define CFG_GPSR2_VAL 0x0001C000
|
||||
|
||||
/* GP02 == DON_RST is 0
|
||||
* GP23 == SCLK is 0
|
||||
* GP45 == USB_ACT is 0
|
||||
* GP60 == PLLEN is 0
|
||||
* GP61 == LED_A is 0
|
||||
* GP73 == SWUPD_LED is 0
|
||||
*/
|
||||
#define CFG_GPCR0_VAL 0x00800004
|
||||
#define CFG_GPCR1_VAL 0x30002000
|
||||
#define CFG_GPCR2_VAL 0x00000100
|
||||
|
||||
/* GP00 == DON_READY is input
|
||||
* GP01 == DON_OK is input
|
||||
* GP02 == DON_RST is output
|
||||
* GP03 == RESET_IND is input
|
||||
* GP07 == RES11 is input
|
||||
* GP09 == RES12 is input
|
||||
* GP11 == SWUPDATE is input
|
||||
* GP14 == nPOWEROK is input
|
||||
* GP15 == nCS1 is output
|
||||
* GP17 == RES22 is input
|
||||
* GP18 == RDY is input
|
||||
* GP23 == SCLK is output
|
||||
* GP24 == SFRM is output
|
||||
* GP25 == TXD is output
|
||||
* GP26 == RXD is input
|
||||
* GP32 == RES21 is input
|
||||
* GP33 == nCS5 is output
|
||||
* GP34 == FFRXD is input
|
||||
* GP35 == CTS is input
|
||||
* GP39 == FFTXD is output
|
||||
* GP41 == RTS is output
|
||||
* GP42 == USB_OK is input
|
||||
* GP45 == USB_ACT is output
|
||||
* GP46 == RXD is input
|
||||
* GP47 == TXD is output
|
||||
* GP49 == nPWE is output
|
||||
* GP58 == nCPUBUSINT is input
|
||||
* GP59 == LANINT is input
|
||||
* GP60 == PLLEN is output
|
||||
* GP61 == LED_A is output
|
||||
* GP62 == LED_B is output
|
||||
* GP63 == TDM_OE is output
|
||||
* GP64 == nDSPINT is input
|
||||
* GP65 == STRAP0 is input
|
||||
* GP67 == STRAP1 is input
|
||||
* GP69 == STRAP2 is input
|
||||
* GP70 == STRAP3 is input
|
||||
* GP71 == STRAP4 is input
|
||||
* GP73 == SWUPD_LED is output
|
||||
* GP78 == nCS2 is output
|
||||
* GP79 == nCS3 is output
|
||||
* GP80 == nCS4 is output
|
||||
*/
|
||||
#define CFG_GPDR0_VAL 0x03808004
|
||||
#define CFG_GPDR1_VAL 0xF002A282
|
||||
#define CFG_GPDR2_VAL 0x0001C200
|
||||
|
||||
/* GP15 == nCS1 is AF10
|
||||
* GP18 == RDY is AF01
|
||||
* GP23 == SCLK is AF10
|
||||
* GP24 == SFRM is AF10
|
||||
* GP25 == TXD is AF10
|
||||
* GP26 == RXD is AF01
|
||||
* GP33 == nCS5 is AF10
|
||||
* GP34 == FFRXD is AF01
|
||||
* GP35 == CTS is AF01
|
||||
* GP39 == FFTXD is AF10
|
||||
* GP41 == RTS is AF10
|
||||
* GP46 == RXD is AF10
|
||||
* GP47 == TXD is AF01
|
||||
* GP49 == nPWE is AF10
|
||||
* GP78 == nCS2 is AF10
|
||||
* GP79 == nCS3 is AF10
|
||||
* GP80 == nCS4 is AF10
|
||||
*/
|
||||
#define CFG_GAFR0_L_VAL 0x80000000
|
||||
#define CFG_GAFR0_U_VAL 0x001A8010
|
||||
#define CFG_GAFR1_L_VAL 0x60088058
|
||||
#define CFG_GAFR1_U_VAL 0x00000008
|
||||
#define CFG_GAFR2_L_VAL 0xA0000000
|
||||
#define CFG_GAFR2_U_VAL 0x00000002
|
||||
|
||||
/* FIXME: set GPIO_RER/FER */
|
||||
|
||||
/* RDH = 1
|
||||
* PH = 1
|
||||
* VFS = 1
|
||||
* BFS = 1
|
||||
* SSS = 1
|
||||
*/
|
||||
#define CFG_PSSR_VAL 0x37
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
|
||||
/* This is the configuration for nCS0/1 -> flash banks
|
||||
* configuration for nCS1:
|
||||
* [31] 0 - Slower Device
|
||||
* [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
|
||||
* [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
|
||||
* [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns
|
||||
* [19] 1 - 16 Bit bus width
|
||||
* [18:16] 000 - nonburst RAM or FLASH
|
||||
* configuration for nCS0:
|
||||
* [15] 0 - Slower Device
|
||||
* [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns
|
||||
* [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns
|
||||
* [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns
|
||||
* [03] 1 - 16 Bit bus width
|
||||
* [02:00] 000 - nonburst RAM or FLASH
|
||||
*/
|
||||
#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */
|
||||
|
||||
/* This is the configuration for nCS2/3 -> TDM-Switch, DSP
|
||||
* configuration for nCS3: DSP
|
||||
* [31] 0 - Slower Device
|
||||
* [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns
|
||||
* [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns
|
||||
* [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns
|
||||
* [19] 1 - 16 Bit bus width
|
||||
* [18:16] 100 - variable latency I/O
|
||||
* configuration for nCS2: TDM-Switch
|
||||
* [15] 0 - Slower Device
|
||||
* [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns
|
||||
* [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns
|
||||
* [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns
|
||||
* [03] 1 - 16 Bit bus width
|
||||
* [02:00] 100 - variable latency I/O
|
||||
*/
|
||||
#define CFG_MSC1_VAL 0x132C593C /* TDM switch, DSP */
|
||||
|
||||
/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller
|
||||
*
|
||||
* configuration for nCS5: LAN Controller
|
||||
* [31] 0 - Slower Device
|
||||
* [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns
|
||||
* [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns
|
||||
* [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns
|
||||
* [19] 1 - 16 Bit bus width
|
||||
* [18:16] 100 - variable latency I/O
|
||||
* configuration for nCS4: ExtBus
|
||||
* [15] 0 - Slower Device
|
||||
* [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns
|
||||
* [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns
|
||||
* [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns
|
||||
* [03] 1 - 16 Bit bus width
|
||||
* [02:00] 100 - variable latency I/O
|
||||
*/
|
||||
#define CFG_MSC2_VAL 0x132C6CDC /* extra bus, LAN controller */
|
||||
|
||||
/* MDCNFG: SDRAM Configuration Register
|
||||
*
|
||||
* [31:29] 000 - reserved
|
||||
* [28] 0 - no SA1111 compatiblity mode
|
||||
* [27] 0 - latch return data with return clock
|
||||
* [26] 0 - alternate addressing for pair 2/3
|
||||
* [25:24] 00 - timings
|
||||
* [23] 0 - internal banks in lower partition 2/3 (not used)
|
||||
* [22:21] 00 - row address bits for partition 2/3 (not used)
|
||||
* [20:19] 00 - column address bits for partition 2/3 (not used)
|
||||
* [18] 0 - SDRAM partition 2/3 width is 32 bit
|
||||
* [17] 0 - SDRAM partition 3 disabled
|
||||
* [16] 0 - SDRAM partition 2 disabled
|
||||
* [15:13] 000 - reserved
|
||||
* [12] 1 - SA1111 compatiblity mode
|
||||
* [11] 1 - latch return data with return clock
|
||||
* [10] 0 - no alternate addressing for pair 0/1
|
||||
* [09:08] 01 - tRP=2*MemClk; CL=2; tRCD=2*MemClk; tRAS=5*MemClk; tRC=8*MemClk
|
||||
* [7] 1 - 4 internal banks in lower partition pair
|
||||
* [06:05] 10 - 13 row address bits for partition 0/1
|
||||
* [04:03] 01 - 9 column address bits for partition 0/1
|
||||
* [02] 0 - SDRAM partition 0/1 width is 32 bit
|
||||
* [01] 0 - disable SDRAM partition 1
|
||||
* [00] 1 - enable SDRAM partition 0
|
||||
*
|
||||
* use the configuration above but disable partition 0
|
||||
*/
|
||||
#define CFG_MDCNFG_VAL 0x000019c8
|
||||
|
||||
/* MDREFR: SDRAM Refresh Control Register
|
||||
*
|
||||
* [32:26] 0 - reserved
|
||||
* [25] 0 - K2FREE: not free running
|
||||
* [24] 0 - K1FREE: not free running
|
||||
* [23] 0 - K0FREE: not free running
|
||||
* [22] 0 - SLFRSH: self refresh disabled
|
||||
* [21] 0 - reserved
|
||||
* [20] 0 - APD: no auto power down
|
||||
* [19] 0 - K2DB2: SDCLK2 is MemClk
|
||||
* [18] 0 - K2RUN: disable SDCLK2
|
||||
* [17] 0 - K1DB2: SDCLK1 is MemClk
|
||||
* [16] 1 - K1RUN: enable SDCLK1
|
||||
* [15] 1 - E1PIN: SDRAM clock enable
|
||||
* [14] 1 - K0DB2: SDCLK0 is MemClk
|
||||
* [13] 1 - K0RUN: disable SDCLK0
|
||||
* [12] 1 - E0PIN: disable SDCKE0
|
||||
* [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24
|
||||
*/
|
||||
#define CFG_MDREFR_VAL 0x0001F018
|
||||
|
||||
/* MDMRS: Mode Register Set Configuration Register
|
||||
*
|
||||
* [31] 0 - reserved
|
||||
* [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used)
|
||||
* [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used)
|
||||
* [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used)
|
||||
* [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used)
|
||||
* [15] 0 - reserved
|
||||
* [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value.
|
||||
* [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency.
|
||||
* [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential.
|
||||
* [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4.
|
||||
*/
|
||||
#define CFG_MDMRS_VAL 0x00020022
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
#define CFG_MECR_VAL 0x00000000
|
||||
#define CFG_MCMEM0_VAL 0x00000000
|
||||
#define CFG_MCMEM1_VAL 0x00000000
|
||||
#define CFG_MCATT0_VAL 0x00000000
|
||||
#define CFG_MCATT1_VAL 0x00000000
|
||||
#define CFG_MCIO0_VAL 0x00000000
|
||||
#define CFG_MCIO1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
#define CSB226_USER_LED0 0x00000008
|
||||
#define CSB226_USER_LED1 0x00000010
|
||||
#define CSB226_USER_LED2 0x00000020
|
||||
*/
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
|
||||
|
||||
#if 0
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000)
|
||||
/* Addr of Environment Sector */
|
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@@ -123,6 +123,7 @@
|
||||
#define CONFIG_BOOTARGS "console=ttyS0"
|
||||
#define CONFIG_NETMASK 255.255.0.0
|
||||
#define CONFIG_IPADDR 192.168.3.68
|
||||
#define CONFIG_HOSTNAME trab
|
||||
#define CONFIG_SERVERIP 192.168.3.1
|
||||
#define CONFIG_BOOTCOMMAND "run flash_nfs"
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
@@ -220,7 +221,11 @@
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#ifndef CONFIG_BIG_FLASH
|
||||
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
|
||||
#else
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
#endif
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
|
||||
@@ -229,11 +234,18 @@
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
|
||||
/* Address and size of Primary Environment Sector */
|
||||
#ifndef CONFIG_BIG_FLASH
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000)
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x4000
|
||||
#else
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000)
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#define CFG_ENV_SECT_SIZE 0x20000
|
||||
#endif
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Reference in New Issue
Block a user