From e7b5aee706fa36f20727a59c95da6eb77c8fa8d3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 25 Mar 2026 02:09:05 +0100 Subject: [PATCH 1/2] net: rswitch: Avoid NULL pointer dereference during PHY access At the very early stage when PHY ID is being auto-detected, the PHY device is not yet instantiated and rswitch_etha .phydev is still NULL. Add missing check for this condition and perform C22 fallback access in this PHY ID auto-detection case. Signed-off-by: Marek Vasut --- drivers/net/rswitch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/rswitch.c b/drivers/net/rswitch.c index 801c22bbdc7..c51908ed8f3 100644 --- a/drivers/net/rswitch.c +++ b/drivers/net/rswitch.c @@ -482,7 +482,7 @@ static int rswitch_mii_read_c45(struct mii_dev *miidev, int phyad, int devad, in /* Access PHY register */ if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ val = rswitch_mii_access_c45(etha_mii, true, phyad, devad, regad, 0); - else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + else if (etha->phydev && etha->phydev->is_c45) /* C22 access to C45 PHY */ val = rswitch_mii_access_c45(etha_mii, true, phyad, 1, regad, 0); else val = rswitch_mii_access_c22(etha_mii, true, phyad, regad, 0); @@ -516,7 +516,7 @@ int rswitch_mii_write_c45(struct mii_dev *miidev, int phyad, int devad, int rega /* Access PHY register */ if (devad != MDIO_DEVAD_NONE) /* Definitelly C45 */ rswitch_mii_access_c45(etha_mii, false, phyad, devad, regad, data); - else if (etha->phydev->is_c45) /* C22 access to C45 PHY */ + else if (etha->phydev && etha->phydev->is_c45) /* C22 access to C45 PHY */ rswitch_mii_access_c45(etha_mii, false, phyad, 1, regad, data); else rswitch_mii_access_c22(etha_mii, false, phyad, regad, data); From d8bd70741f0d0258088a306c39bf8af3c1be3c4b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 16 Mar 2026 00:51:59 +0100 Subject: [PATCH 2/2] arm64: dts: renesas: Disable SCIF1 in Renesas R-Car X5H R8A78000 SoC DT Disable incorrectly enabled SCIF1 in Renesas R-Car X5H R8A78000 SoC DT. The SCIF1 should be enabled on board DT level in case it is needed, but should be disabled in SoC DT by default. This had no adverse effect on the currently upstream platforms, because those managed to probe only the HSCIF0 device and SCIF1 was ignored. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a78000.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi index 0d0c24503e2..89c2881fa94 100644 --- a/arch/arm/dts/r8a78000.dtsi +++ b/arch/arm/dts/r8a78000.dtsi @@ -763,7 +763,7 @@ interrupts = ; clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; - status = "okay"; + status = "disabled"; }; scif3: serial@c0708000 {