From 212875e707b6bc75780386c2cb28fbac7e2ab8f3 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 15 Feb 2022 16:23:22 +0100 Subject: [PATCH 1/4] mmc: fix error message for unaligned erase request Fix the end address in the message for unaligned erase request in mmc_berase() when start + blkcnt is aligned to erase_grp_size. for example: - start = 0x2000 - 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x27ff But no issue when the end address is not aligned, for example - start = 0x2000 - 2 * 26 - count = 26 - erase_grp_size = 0x400 Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x23ff Signed-off-by: Patrick Delaunay Reviewed-by: Jaehoon Chung Reviewed-by: Patrice Chotard --- drivers/mmc/mmc_write.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c index d23b7d9729f..eab94c7b607 100644 --- a/drivers/mmc/mmc_write.c +++ b/drivers/mmc/mmc_write.c @@ -102,7 +102,7 @@ ulong mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt) "The erase range would be change to " "0x" LBAF "~0x" LBAF "\n\n", mmc->erase_grp_size, start & ~(mmc->erase_grp_size - 1), - ((start + blkcnt + mmc->erase_grp_size) + ((start + blkcnt + mmc->erase_grp_size - 1) & ~(mmc->erase_grp_size - 1)) - 1); while (blk < blkcnt) { From d72267049b484577294e17140b369dee339b2352 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 15 Feb 2022 16:23:23 +0100 Subject: [PATCH 2/4] env: mmc : align erase address and size on erase_grp_size On eMMC device, the erase_grp_size > 1 so the address and size for the erase block command in env/mmc.c can be unaligned on erase group size and some strange trace occurs and the result is not guarantee by MMC devices. The SD-Card behavior doesn't change as erase_grp_size = 1 for SD-Card. For example, on eMMC present on STM32MP15C-EV1 and before the patch: STM32MP> env erase Erasing Environment on MMC... Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x27ff 16 blocks erased: OK Caution! Your devices Erase group is 0x400 The erase range would be change to 0x2000~0x23ff 16 blocks erased: OK OK After this patch: STM32MP> env erase Erasing Environment on MMC... 1024 blocks erased at 0x2000: OK 1024 blocks erased at 0x2000: OK OK Here the 2 copies of U-Boot environment are in the same devices Erase group: it is erased twice. Signed-off-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- env/mmc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/env/mmc.c b/env/mmc.c index 465b104559b..0c498d9a46b 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -257,12 +257,15 @@ static inline int erase_env(struct mmc *mmc, unsigned long size, { uint blk_start, blk_cnt, n; struct blk_desc *desc = mmc_get_blk_desc(mmc); + u32 erase_size; - blk_start = ALIGN(offset, mmc->write_bl_len) / mmc->write_bl_len; - blk_cnt = ALIGN(size, mmc->write_bl_len) / mmc->write_bl_len; + erase_size = mmc->erase_grp_size * desc->blksz; + blk_start = ALIGN_DOWN(offset, erase_size) / desc->blksz; + blk_cnt = ALIGN(size, erase_size) / desc->blksz; n = blk_derase(desc, blk_start, blk_cnt); - printf("%d blocks erased: %s\n", n, (n == blk_cnt) ? "OK" : "ERROR"); + printf("%d blocks erased at 0x%x: %s\n", n, blk_start, + (n == blk_cnt) ? "OK" : "ERROR"); return (n == blk_cnt) ? 0 : 1; } @@ -286,6 +289,7 @@ static int env_mmc_erase(void) goto fini; } + printf("\n"); ret = erase_env(mmc, CONFIG_ENV_SIZE, offset); #ifdef CONFIG_ENV_OFFSET_REDUND From d6ad5a0af9e6a12f47008141259f77b568c73ab2 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 26 May 2022 16:37:21 +0200 Subject: [PATCH 3/4] mmc: Add support for wait_dat0 callback There is no wait_dat0 mmc ops, causing operations waiting for data line state change (e.g mmc_switch_voltage) to fallback to a 250ms active delay. mmc_ops still used when DM_MMC is not enabled, which is often the case for SPL. The result can be unexpectly long SPL boot time. This change adds support for wait_dat0() mmc operation. Signed-off-by: Loic Poulain Reviewed-by: Jaehoon Chung --- drivers/mmc/mmc.c | 3 +++ include/mmc.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 8a7d0739006..12d29da528a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -34,6 +34,9 @@ static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us) { + if (mmc->cfg->ops->wait_dat0) + return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us); + return -ENOSYS; } diff --git a/include/mmc.h b/include/mmc.h index 9b4dc683110..073b01f82b3 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -561,6 +561,7 @@ struct mmc_ops { int (*getwp)(struct mmc *mmc); int (*host_power_cycle)(struct mmc *mmc); int (*get_b_max)(struct mmc *mmc, void *dst, lbaint_t blkcnt); + int (*wait_dat0)(struct mmc *mmc, int state, int timeout_us); }; static inline int mmc_hs400_prepare_ddr(struct mmc *mmc) From 12a29d3b851029212ca3b3e0f233fc7b62aa0a39 Mon Sep 17 00:00:00 2001 From: Loic Poulain Date: Thu, 26 May 2022 16:37:22 +0200 Subject: [PATCH 4/4] mmc: fsl_esdhc_imx: Implement wait_dat0 mmc ops Implement wait_dat0 mmc ops callbac, allowing to reduce SPL boot time. Before (using grabserial): [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.028257 0.028257] DDRINFO: start DRAM init [0.028500 0.000243] DDRINFO: DRAM rate 3000MTS [0.304627 0.276127] DDRINFO:ddrphy calibration done [0.305647 0.001020] DDRINFO: ddrmix config done [0.352584 0.046937] SEC0: RNG instantiated [0.374299 0.021715] Normal Boot [0.374675 0.000376] Trying to boot from MMC2 [1.250580 0.875905] NOTICE: BL31: v2.4(release):lf-5.10.72-2.2.0-0-g5782363f9 [1.251985 0.001405] NOTICE: BL31: Built : 08:02:40, Apr 12 2022 [1.522560 0.270575] [1.522734 0.000174] [1.522788 0.000054] U-Boot 2021.04-xxxx After: [0.000001 0.000001] U-Boot SPL 2021.04-xxxx [0.001614 0.001614] DDRINFO: start DRAM init [0.002377 0.000763] DDRINFO: DRAM rate 3000MTS [0.278494 0.276117] DDRINFO:ddrphy calibration done [0.279266 0.000772] DDRINFO: ddrmix config done [0.338432 0.059166] SEC0: RNG instantiated [0.339051 0.000619] Normal Boot [0.339431 0.000380] Trying to boot from MMC2 [0.412587 0.073156] NOTICE: BL31: v2.4(release):lf-5.15.5-1.0.0-0-g05f788b [0.414191 0.001604] NOTICE: BL31: Built : 10:35:26, Apr 6 2022 [0.700685 0.286494] [0.700793 0.000108] [0.700845 0.000052] U-Boot 2021.04-xxxx Signed-off-by: Loic Poulain Reviewed-by: Jaehoon Chung --- drivers/mmc/fsl_esdhc_imx.c | 50 ++++++++++++++++++++++++------------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 893d7e241f2..9befb190bdf 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1060,6 +1060,30 @@ static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) return timeout > 0; } +static int esdhc_wait_dat0_common(struct fsl_esdhc_priv *priv, int state, + int timeout_us) +{ + struct fsl_esdhc *regs = priv->esdhc_regs; + int ret, err; + u32 tmp; + + /* make sure the card clock keep on */ + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, + !!(tmp & PRSSTAT_DAT0) == !!state, + timeout_us); + + /* change to default setting, let host control the card clock */ + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + + err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (err) + pr_warn("card clock not gate off as expect.\n"); + + return ret; +} + static int esdhc_reset(struct fsl_esdhc *regs) { ulong start; @@ -1109,11 +1133,19 @@ static int esdhc_set_ios(struct mmc *mmc) return esdhc_set_ios_common(priv, mmc); } +static int esdhc_wait_dat0(struct mmc *mmc, int state, int timeout_us) +{ + struct fsl_esdhc_priv *priv = mmc->priv; + + return esdhc_wait_dat0_common(priv, state, timeout_us); +} + static const struct mmc_ops esdhc_ops = { .getcd = esdhc_getcd, .init = esdhc_init, .send_cmd = esdhc_send_cmd, .set_ios = esdhc_set_ios, + .wait_dat0 = esdhc_wait_dat0, }; #endif @@ -1576,25 +1608,9 @@ static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, int timeout_us) { - int ret, err; - u32 tmp; struct fsl_esdhc_priv *priv = dev_get_priv(dev); - struct fsl_esdhc *regs = priv->esdhc_regs; - /* make sure the card clock keep on */ - esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - - ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, - !!(tmp & PRSSTAT_DAT0) == !!state, - timeout_us); - - /* change to default setting, let host control the card clock */ - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); - err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); - if (err) - dev_warn(dev, "card clock not gate off as expect.\n"); - - return ret; + return esdhc_wait_dat0_common(priv, state, timeout_us); } static const struct dm_mmc_ops fsl_esdhc_ops = {