Mirrors/u-boot
1
0
Fork 0
mirror of https://source.denx.de/u-boot/u-boot.git synced 2026-06-13 15:03:58 +03:00
Code Issues Packages Projects Releases Wiki Activity

arm: dts: sync dts for Action Semi S900

Browse Source 
Synchronize device tree bindings with v5.5-rc6 tag with commit id
"b3a987b0264d".

Also, it removes older clock binding defined for S900 along with undocumented
compatible string "actions,s900-serial" from serial driver and adapts clock
driver to cater to new bindings.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
This commit is contained in:
Amit Singh Tomar
2020-04-19 19:28:28 +05:30
committed by Tom Rini
parent bf66584336
commit 4939beea8e
7 changed files with 500 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

129
include/dt-bindings/clock/actions,s900-cmu.h Normal file
View File

@@ -0,0 +1,129 @@
// SPDX-License-Identifier: GPL-2.0+
//
// Device Tree binding constants for Actions Semi S900 Clock Management Unit
//
// Copyright (c) 2014 Actions Semi Inc.
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H
#define __DT_BINDINGS_CLOCK_S900_CMU_H
#define CLK_NONE 0
/* fixed rate clocks */
#define CLK_LOSC 1
#define CLK_HOSC 2
/* pll clocks */
#define CLK_CORE_PLL 3
#define CLK_DEV_PLL 4
#define CLK_DDR_PLL 5
#define CLK_NAND_PLL 6
#define CLK_DISPLAY_PLL 7
#define CLK_DSI_PLL 8
#define CLK_ASSIST_PLL 9
#define CLK_AUDIO_PLL 10
/* system clock */
#define CLK_CPU 15
#define CLK_DEV 16
#define CLK_NOC 17
#define CLK_NOC_MUX 18
#define CLK_NOC_DIV 19
#define CLK_AHB 20
#define CLK_APB 21
#define CLK_DMAC 22
/* peripheral device clock */
#define CLK_GPIO 23
#define CLK_BISP 24
#define CLK_CSI0 25
#define CLK_CSI1 26
#define CLK_DE0 27
#define CLK_DE1 28
#define CLK_DE2 29
#define CLK_DE3 30
#define CLK_DSI 32
#define CLK_GPU 33
#define CLK_GPU_CORE 34
#define CLK_GPU_MEM 35
#define CLK_GPU_SYS 36
#define CLK_HDE 37
#define CLK_I2C0 38
#define CLK_I2C1 39
#define CLK_I2C2 40
#define CLK_I2C3 41
#define CLK_I2C4 42
#define CLK_I2C5 43
#define CLK_I2SRX 44
#define CLK_I2STX 45
#define CLK_IMX 46
#define CLK_LCD 47
#define CLK_NAND0 48
#define CLK_NAND1 49
#define CLK_PWM0 50
#define CLK_PWM1 51
#define CLK_PWM2 52
#define CLK_PWM3 53
#define CLK_PWM4 54
#define CLK_PWM5 55
#define CLK_SD0 56
#define CLK_SD1 57
#define CLK_SD2 58
#define CLK_SD3 59
#define CLK_SENSOR 60
#define CLK_SPEED_SENSOR 61
#define CLK_SPI0 62
#define CLK_SPI1 63
#define CLK_SPI2 64
#define CLK_SPI3 65
#define CLK_THERMAL_SENSOR 66
#define CLK_UART0 67
#define CLK_UART1 68
#define CLK_UART2 69
#define CLK_UART3 70
#define CLK_UART4 71
#define CLK_UART5 72
#define CLK_UART6 73
#define CLK_VCE 74
#define CLK_VDE 75
#define CLK_USB3_480MPLL0 76
#define CLK_USB3_480MPHY0 77
#define CLK_USB3_5GPHY 78
#define CLK_USB3_CCE 79
#define CLK_USB3_MAC 80
#define CLK_TIMER 83
#define CLK_HDMI_AUDIO 84
#define CLK_24M 85
#define CLK_EDP 86
#define CLK_24M_EDP 87
#define CLK_EDP_PLL 88
#define CLK_EDP_LINK 89
#define CLK_USB2H0_PLLEN 90
#define CLK_USB2H0_PHY 91
#define CLK_USB2H0_CCE 92
#define CLK_USB2H1_PLLEN 93
#define CLK_USB2H1_PHY 94
#define CLK_USB2H1_CCE 95
#define CLK_DDR0 96
#define CLK_DDR1 97
#define CLK_DMM 98
#define CLK_ETH_MAC 99
#define CLK_RMII_REF 100
#define CLK_NR_CLKS (CLK_RMII_REF + 1)
#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */

77
include/dt-bindings/clock/s900_cmu.h
View File

@@ -1,77 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Actions Semi Co., Ltd.
* Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
*
*/
#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
#define _DT_BINDINGS_CLOCK_S900_CMU_H_
/* Module Clock ID */
#define CLOCK_DDRCH1 0
#define CLOCK_DMAC 1
#define CLOCK_DDRCH0 2
#define CLOCK_BROM 3
#define CLOCK_NANDC0 4
#define CLOCK_SD0 5
#define CLOCK_SD1 6
#define CLOCK_SD2 7
#define CLOCK_DE 8
#define CLOCK_LVDS 9
#define CLOCK_EDP 10
#define CLOCK_NANDC1 11
#define CLOCK_DSI 12
#define CLOCK_CSI0 13
#define CLOCK_BISP 14
#define CLOCK_CSI1 15
#define CLOCK_SD3 16
#define CLOCK_I2C4 17
#define CLOCK_GPIO 18
#define CLOCK_DMM 19
#define CLOCK_I2STX 20
#define CLOCK_I2SRX 21
#define CLOCK_HDMIA 22
#define CLOCK_SPDIF 23
#define CLOCK_PCM0 24
#define CLOCK_VDE 25
#define CLOCK_VCE 26
#define CLOCK_HDE 27
#define CLOCK_SHARESRAM 28
#define CLOCK_CMU_DDR1 29
#define CLOCK_GPU3D 30
#define CLOCK_CMUDDR0 31
#define CLOCK_SPEED 32
#define CLOCK_I2C5 33
#define CLOCK_THERMAL 34
#define CLOCK_HDMI 35
#define CLOCK_PWM4 36
#define CLOCK_PWM5 37
#define CLOCK_UART0 38
#define CLOCK_UART1 39
#define CLOCK_UART2 40
#define CLOCK_IRC 41
#define CLOCK_SPI0 42
#define CLOCK_SPI1 43
#define CLOCK_SPI2 44
#define CLOCK_SPI3 45
#define CLOCK_I2C0 46
#define CLOCK_I2C1 47
#define CLOCK_PCM1 48
#define CLOCK_IMX 49
#define CLOCK_UART6 50
#define CLOCK_UART3 51
#define CLOCK_UART4 52
#define CLOCK_UART5 53
#define CLOCK_ETHERNET 54
#define CLOCK_PWM0 55
#define CLOCK_PWM1 56
#define CLOCK_PWM2 57
#define CLOCK_PWM3 58
#define CLOCK_TIMER 59
#define CLOCK_SE 60
#define CLOCK_HDCP2TX 61
#define CLOCK_I2C2 62
#define CLOCK_I2C3 63
#endif

65
include/dt-bindings/reset/actions,s900-reset.h Normal file
View File

@@ -0,0 +1,65 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
//
// Device Tree binding constants for Actions Semi S900 Reset Management Unit
//
// Copyright (c) 2018 Linaro Ltd.
#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H
#define __DT_BINDINGS_ACTIONS_S900_RESET_H
#define RESET_CHIPID 0
#define RESET_CPU_SCNT 1
#define RESET_SRAMI 2
#define RESET_DDR_CTL_PHY 3
#define RESET_DMAC 4
#define RESET_GPIO 5
#define RESET_BISP_AXI 6
#define RESET_CSI0 7
#define RESET_CSI1 8
#define RESET_DE 9
#define RESET_DSI 10
#define RESET_GPU3D_PA 11
#define RESET_GPU3D_PB 12
#define RESET_HDE 13
#define RESET_I2C0 14
#define RESET_I2C1 15
#define RESET_I2C2 16
#define RESET_I2C3 17
#define RESET_I2C4 18
#define RESET_I2C5 19
#define RESET_IMX 20
#define RESET_NANDC0 21
#define RESET_NANDC1 22
#define RESET_SD0 23
#define RESET_SD1 24
#define RESET_SD2 25
#define RESET_SD3 26
#define RESET_SPI0 27
#define RESET_SPI1 28
#define RESET_SPI2 29
#define RESET_SPI3 30
#define RESET_UART0 31
#define RESET_UART1 32
#define RESET_UART2 33
#define RESET_UART3 34
#define RESET_UART4 35
#define RESET_UART5 36
#define RESET_UART6 37
#define RESET_HDMI 38
#define RESET_LVDS 39
#define RESET_EDP 40
#define RESET_USB2HUB 41
#define RESET_USB2HSIC 42
#define RESET_USB3 43
#define RESET_PCM1 44
#define RESET_AUDIO 45
#define RESET_PCM0 46
#define RESET_SE 47
#define RESET_GIC 48
#define RESET_DDR_CTL_PHY_AXI 49
#define RESET_CMU_DDR 50
#define RESET_DMM 51
#define RESET_HDCP2TX 52
#define RESET_ETHERNET 53
#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */