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Merge branch 'staging' of https://source.denx.de/u-boot/custodians/u-boot-tegra into next

Browse Source 
- More Tegra video improvements
This commit is contained in:
Tom Rini
2025-03-26 14:07:37 -06:00
parent df11ac859d 03f61b1539
commit 4adbf64ff8
56 changed files with 4721 additions and 491 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/dts/Makefile
View File

@@ -113,6 +113,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += \
tegra30-lg-p880.dtb \
tegra30-lg-p895.dtb \
tegra30-microsoft-surface-rt.dtb \
tegra30-ouya.dtb \
tegra30-tec-ng.dtb \
tegra30-wexler-qc750.dtb \
tegra114-dalmore.dtb \

14
arch/arm/dts/tegra124-xiaomi-mocha.dts
View File

@@ -215,8 +215,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,open-drain = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -225,8 +225,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,open-drain = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -235,8 +235,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,open-drain = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -253,7 +253,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <1>;
nvidia,open-drain = <TEGRA_PIN_DISABLE>;
};
dsi-b {

40
arch/arm/dts/tegra30-asus-p1801-t.dts
View File

@@ -34,20 +34,10 @@
host1x@50000000 {
dc@54200000 {
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
rgb {
status = "okay";
nvidia,panel = <&hdmi>;
};
status = "disabled";
};
hdmi: hdmi@54280000 {
clocks = <&tegra_car TEGRA30_CLK_HDMI>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
status = "okay";
hdmi-supply = <&hdmi_5v0_sys>;
@@ -118,8 +108,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -203,7 +193,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -213,7 +203,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -223,7 +213,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -232,7 +222,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -242,7 +232,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
nvidia,pins = "pu4";
@@ -260,7 +250,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hdmi_hpd {
nvidia,pins = "hdmi_int_pn7";
@@ -632,8 +622,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -718,8 +708,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_d10_pt2 {
nvidia,pins = "vi_d10_pt2",
@@ -838,8 +828,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
nvidia,pins = "vi_mclk_pt1";

44
arch/arm/dts/tegra30-asus-tf600t.dts
View File

@@ -90,8 +90,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC2 pinmux */
@@ -107,8 +107,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -142,8 +142,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4_cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -159,8 +159,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4_rst_n {
nvidia,pins = "sdmmc4_rst_n_pcc3";
@@ -186,7 +186,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -196,7 +196,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -206,7 +206,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -215,7 +215,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -225,7 +225,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
nvidia,pins = "pu4";
@@ -243,7 +243,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hdmi_hpd {
nvidia,pins = "hdmi_int_pn7";
@@ -613,8 +613,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -701,8 +701,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
pbb0 {
nvidia,pins = "pbb0";
@@ -827,8 +827,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -836,8 +836,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
jtag {

96
arch/arm/dts/tegra30-asus-tf700t.dts
View File

@@ -15,7 +15,14 @@
rgb {
status = "okay";
nvidia,panel = <&tc358768>;
/delete-property/ nvidia,panel;
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
@@ -118,38 +125,69 @@
vddio-supply = <&vdd_1v8_vio>;
vddmipi-supply = <&vdd_1v2_mipi>;
panel = <&panel>;
/*
* Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1
* LCD SuperIPS+ Full HD panel.
*/
panel@1 {
compatible = "panasonic,vvx10f004b00";
reg = <1>;
power-supply = <&vdd_pnl_reg>;
backlight = <&backlight>;
display-timings {
timing@0 {
/* 1920x1200@60Hz */
clock-frequency = <154000000>;
hactive = <1920>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
hsync-active = <1>;
vactive = <1200>;
vfront-porch = <3>;
vback-porch = <26>;
vsync-len = <6>;
vsync-active = <1>;
};
};
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
bus-width = <24>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
};
};
panel: panel {
compatible = "panasonic,vvx10f004b00";
power-supply = <&vdd_pnl_reg>;
backlight = <&backlight>;
/delete-property/ enable-gpios;
display-timings {
timing@0 {
/* 1920x1200@60Hz */
clock-frequency = <154000000>;
hactive = <1920>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
hsync-active = <1>;
vactive = <1200>;
vfront-porch = <3>;
vback-porch = <26>;
vsync-len = <6>;
vsync-active = <1>;
};
};
};
/delete-node/ panel;
vdd_1v2_mipi: regulator-mipi {
compatible = "regulator-fixed";

26
arch/arm/dts/tegra30-asus-transformer.dtsi
View File

@@ -99,8 +99,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* SDMMC3 pinmux */
@@ -189,7 +189,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2_i2c {
@@ -200,7 +200,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam_i2c {
@@ -211,7 +211,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc_i2c {
@@ -221,7 +221,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr_i2c {
@@ -232,7 +232,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
hotplug_i2c {
@@ -647,8 +647,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* GPIO keys pinmux */
@@ -741,8 +741,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_d10_pt2 {
@@ -879,8 +879,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi_mclk_pt1 {

17
arch/arm/dts/tegra30-htc-endeavoru.dts
View File

@@ -33,13 +33,11 @@
host1x@50000000 {
dc@54200000 {
clocks = <&tegra_car TEGRA30_CLK_DISP1>,
<&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
rgb {
status = "okay";
nvidia,panel = <&dsia>;
nvidia,pwm-source = <1>;
nvidia,default-brightness = <0x8E>;
};
};
@@ -1265,13 +1263,6 @@
nvidia,xcvr-lsrslew = <2>;
};
backlight: backlight {
compatible = "nvidia,tegra-pwm-backlight";
nvidia,pwm-source = <1>;
nvidia,default-brightness = <0x8E>;
};
/* PMIC has a built-in 32KHz oscillator which is used by PMC */
clk32k_in: clock-32k {
compatible = "fixed-clock";

46
arch/arm/dts/tegra30-lenovo-ideapad-yoga-11.dts
View File

@@ -109,8 +109,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -127,8 +127,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
cam-mclk {
nvidia,pins = "cam_mclk_pcc0";
@@ -147,7 +147,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -157,7 +157,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -167,7 +167,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -176,7 +176,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -186,7 +186,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
@@ -724,8 +724,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-vsync-pd6 {
nvidia,pins = "vi_vsync_pd6",
@@ -736,8 +736,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <2>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_ENABLE>;
};
vi-hsync-pd7 {
nvidia,pins = "vi_hsync_pd7",
@@ -749,8 +749,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d2-pl0 {
nvidia,pins = "vi_d2_pl0",
@@ -760,8 +760,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-mclk-pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -769,8 +769,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <2>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_ENABLE>;
};
vi-d11-pt3 {
nvidia,pins = "vi_d11_pt3";
@@ -778,8 +778,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d5-pl3 {
nvidia,pins = "vi_d5_pl3";
@@ -787,8 +787,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* PORT U */

34
arch/arm/dts/tegra30-lg-p880.dts
View File

@@ -101,6 +101,31 @@
};
};
spi@7000dc00 {
bridge-spi@2 {
/*
* JDI 4.57" 720x1280 DX12D100VM0EAA MIPI DSI panel
*/
panel@0 {
compatible = "jdi,dx12d100vm0eaa";
reg = <0>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
vdd-supply = <&vcc_3v0_lcd>;
vddio-supply = <&iovcc_1v8_lcd>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
sdmmc3: sdhci@78000400 {
status = "okay";
bus-width = <4>;
@@ -118,13 +143,4 @@
linux,code = <KEY_UP>;
};
};
panel: panel {
compatible = "jdi,dx12d100vm0eaa";
enable-gpios = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
};

47
arch/arm/dts/tegra30-lg-p895.dts
View File

@@ -108,36 +108,37 @@
};
};
panel: panel {
compatible = "hitachi,tx13d100vm0eaa";
spi@7000dc00 {
bridge-spi@2 {
/*
* HITACHI/KOE 5" 768x1024 TX13D100VM0EAA MIPI DSI panel
*/
panel@0 {
compatible = "koe,tx13d100vm0eaa";
reg = <0>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_LOW>;
renesas,gamma = <3>;
renesas,inversion;
renesas,contrast;
renesas,gamma = <3>;
renesas,inversion;
renesas,contrast;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
vcc-supply = <&vcc_3v0_lcd>;
iovcc-supply = <&iovcc_1v8_lcd>;
backlight = <&backlight>;
backlight = <&backlight>;
port {
panel_input: endpoint {
remote-endpoint = <&bridge_output>;
};
};
};
};
};
vcc_3v0_lcd: regulator-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-lcd3v {
gpio = <&gpio TEGRA_GPIO(BB, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
iovcc_1v8_lcd: regulator-lcdvio {
compatible = "regulator-fixed";
regulator-name = "iovcc_1v8_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

82
arch/arm/dts/tegra30-lg-x3.dtsi
View File

@@ -32,7 +32,12 @@
rgb {
status = "okay";
nvidia,panel = <&bridge>;
port {
dpi_output: endpoint {
remote-endpoint = <&bridge_input>;
bus-width = <24>;
};
};
};
};
};
@@ -890,12 +895,22 @@
status = "okay";
clock-frequency = <400000>;
backlight: lm3533@36 {
backlight: led-controller@36 {
compatible = "ti,lm3533";
reg = <0x36>;
enable-gpios = <&gpio TEGRA_GPIO(N, 6) GPIO_ACTIVE_HIGH>;
default-brightness-level = <128>;
ti,boost-ovp-microvolt = <24000000>;
ti,boost-freq-hz = <500000>;
backlight-0 {
compatible = "ti,lm3533-backlight";
ti,max-current-microamp = <23400>;
ti,linear-mapping-mode;
ti,hardware-controlled;
};
};
muic@44 {
@@ -969,18 +984,46 @@
compatible = "solomon,ssd2825";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
spi-cpol;
spi-cpha;
spi-max-frequency = <1000000>;
power-gpios = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio TEGRA_GPIO(O, 2) GPIO_ACTIVE_LOW>;
dvdd-supply = <&vdd_1v2_rgb>;
avdd-supply = <&vdd_1v2_rgb>;
vddio-supply = <&vdd_1v8_vio>;
solomon,hs-zero-delay-ns = <300>;
solomon,hs-prep-delay-ns = <65>;
clocks = <&ssd2825_refclk>;
clock-names = "tx_clk";
panel = <&panel>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_input: endpoint {
remote-endpoint = <&dpi_output>;
bus-width = <24>;
};
};
port@1 {
reg = <1>;
bridge_output: endpoint {
remote-endpoint = <&panel_input>;
};
};
};
};
};
@@ -1036,4 +1079,29 @@
linux,code = <KEY_DOWN>;
};
};
vdd_1v2_rgb: regulator-rgb1v2 {
compatible = "regulator-fixed";
regulator-name = "vdd_1v2_rgb";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
gpio = <&gpio TEGRA_GPIO(B, 1) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vcc_3v0_lcd: regulator-lcd3v {
compatible = "regulator-fixed";
regulator-name = "vcc_3v0_lcd";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
iovcc_1v8_lcd: regulator-lcd1v8 {
compatible = "regulator-fixed";
regulator-name = "iovcc_1v8_lcd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio TEGRA_GPIO(Y, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

38
arch/arm/dts/tegra30-microsoft-surface-rt.dts
View File

@@ -103,8 +103,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
sdmmc4-cmd {
nvidia,pins = "sdmmc4_cmd_pt7",
@@ -121,8 +121,8 @@
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
cam-mclk {
nvidia,pins = "cam_mclk_pcc0";
@@ -141,7 +141,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -151,7 +151,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -161,7 +161,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -170,7 +170,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -180,7 +180,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */
@@ -703,8 +703,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d3-pl1 {
nvidia,pins = "vi_d3_pl1";
@@ -712,8 +712,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-hsync-pd7 {
nvidia,pins = "vi_hsync_pd7",
@@ -724,8 +724,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-mclk-pt1 {
nvidia,pins = "vi_mclk_pt1";
@@ -733,8 +733,8 @@
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
vi-d11-pt3 {
nvidia,pins = "vi_d11_pt3";
@@ -742,8 +742,8 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,lock = <1>;
nvidia,io-reset = <1>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
nvidia,io-reset = <TEGRA_PIN_DISABLE>;
};
/* PORT U */

2063
arch/arm/dts/tegra30-ouya.dts Normal file
View File

File diff suppressed because it is too large Load Diff

10
arch/arm/dts/tegra30-wexler-qc750.dts
View File

@@ -157,7 +157,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
gen2-i2c {
nvidia,pins = "gen2_i2c_scl_pt5",
@@ -167,7 +167,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
cam-i2c {
nvidia,pins = "cam_i2c_scl_pbb1",
@@ -177,7 +177,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
ddc-i2c {
nvidia,pins = "ddc_scl_pv4",
@@ -186,7 +186,7 @@
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
pwr-i2c {
nvidia,pins = "pwr_i2c_scl_pz6",
@@ -196,7 +196,7 @@
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,open-drain = <TEGRA_PIN_ENABLE>;
nvidia,lock = <0>;
nvidia,lock = <TEGRA_PIN_DISABLE>;
};
/* HDMI pinmux */

46
arch/arm/include/asm/arch-tegra/dc.h
View File

@@ -448,6 +448,11 @@ enum win_color_depth_id {
#define LVS_OUTPUT_POLARITY_LOW BIT(28)
#define LSC0_OUTPUT_POLARITY_LOW BIT(24)
/* DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 */
#define H_PULSE0_ENABLE BIT(8)
#define H_PULSE1_ENABLE BIT(10)
#define H_PULSE2_ENABLE BIT(12)
/* DC_DISP_DISP_WIN_OPTIONS 0x402 */
#define CURSOR_ENABLE BIT(16)
#define SOR_ENABLE BIT(25)
@@ -504,6 +509,22 @@ enum {
DATA_ORDER_BLUE_RED,
};
/* DC_DISP_DISP_COLOR_CONTROL 0x430 */
#define DITHER_CONTROL_DISABLE (0 << 8)
#define DITHER_CONTROL_ORDERED (2 << 8)
#define DITHER_CONTROL_ERRDIFF (3 << 8)
enum {
BASE_COLOR_SIZE_666,
BASE_COLOR_SIZE_111,
BASE_COLOR_SIZE_222,
BASE_COLOR_SIZE_333,
BASE_COLOR_SIZE_444,
BASE_COLOR_SIZE_555,
BASE_COLOR_SIZE_565,
BASE_COLOR_SIZE_332,
BASE_COLOR_SIZE_888,
};
/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */
#define DE_SELECT_SHIFT 0
#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT)
@@ -570,8 +591,27 @@ enum {
#define V_DDA_INC_SHIFT 16
#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT)
#define DC_POLL_TIMEOUT_MS 50
#define DC_N_WINDOWS 5
#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
#define DC_POLL_TIMEOUT_MS 50
#define DC_N_WINDOWS 5
#define DC_REG_SAVE_SPACE (DC_N_WINDOWS + 5)
#define PULSE_MODE_NORMAL (0 << 3)
#define PULSE_MODE_ONE_CLOCK (1 << 3)
#define PULSE_POLARITY_HIGH (0 << 4)
#define PULSE_POLARITY_LOW (1 << 4)
#define PULSE_QUAL_ALWAYS (0 << 6)
#define PULSE_QUAL_VACTIVE (2 << 6)
#define PULSE_QUAL_VACTIVE1 (3 << 6)
#define PULSE_LAST_START_A (0 << 8)
#define PULSE_LAST_END_A (1 << 8)
#define PULSE_LAST_START_B (2 << 8)
#define PULSE_LAST_END_B (3 << 8)
#define PULSE_LAST_START_C (4 << 8)
#define PULSE_LAST_END_C (5 << 8)
#define PULSE_LAST_START_D (6 << 8)
#define PULSE_LAST_END_D (7 << 8)
#define PULSE_START(x) (((x) & 0xfff) << 0)
#define PULSE_END(x) (((x) & 0xfff) << 16)
#endif /* __ASM_ARCH_TEGRA_DC_H */

20
arch/arm/include/asm/arch-tegra/pinmux.h
View File

@@ -34,41 +34,41 @@ enum pmux_pin_io {
#ifdef TEGRA_PMX_PINS_HAVE_LOCK
enum pmux_pin_lock {
PMUX_PIN_LOCK_DEFAULT = 0,
PMUX_PIN_LOCK_DISABLE,
PMUX_PIN_LOCK_DISABLE = 0,
PMUX_PIN_LOCK_ENABLE,
PMUX_PIN_LOCK_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_OD
enum pmux_pin_od {
PMUX_PIN_OD_DEFAULT = 0,
PMUX_PIN_OD_DISABLE,
PMUX_PIN_OD_DISABLE = 0,
PMUX_PIN_OD_ENABLE,
PMUX_PIN_OD_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
enum pmux_pin_ioreset {
PMUX_PIN_IO_RESET_DEFAULT = 0,
PMUX_PIN_IO_RESET_DISABLE,
PMUX_PIN_IO_RESET_DISABLE = 0,
PMUX_PIN_IO_RESET_ENABLE,
PMUX_PIN_IO_RESET_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
enum pmux_pin_rcv_sel {
PMUX_PIN_RCV_SEL_DEFAULT = 0,
PMUX_PIN_RCV_SEL_NORMAL,
PMUX_PIN_RCV_SEL_NORMAL = 0,
PMUX_PIN_RCV_SEL_HIGH,
PMUX_PIN_RCV_SEL_DEFAULT,
};
#endif
#ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
enum pmux_pin_e_io_hv {
PMUX_PIN_E_IO_HV_DEFAULT = 0,
PMUX_PIN_E_IO_HV_NORMAL,
PMUX_PIN_E_IO_HV_NORMAL = 0,
PMUX_PIN_E_IO_HV_HIGH,
PMUX_PIN_E_IO_HV_DEFAULT,
};
#endif

6
arch/arm/include/asm/arch-tegra20/pinmux.h
View File

@@ -467,14 +467,14 @@ static const char * const tegra_pinctrl_to_func[] = {
[PMUX_FUNC_DAP3] = "dap3",
[PMUX_FUNC_DAP4] = "dap4",
[PMUX_FUNC_DAP5] = "dap5",
[PMUX_FUNC_DISPA] = "dispa",
[PMUX_FUNC_DISPB] = "dispb",
[PMUX_FUNC_DISPA] = "displaya",
[PMUX_FUNC_DISPB] = "displayb",
[PMUX_FUNC_EMC_TEST0_DLL] = "emc_test0_dll",
[PMUX_FUNC_EMC_TEST1_DLL] = "emc_test1_dll",
[PMUX_FUNC_GMI] = "gmi",
[PMUX_FUNC_GMI_INT] = "gmi_int",
[PMUX_FUNC_HDMI] = "hdmi",
[PMUX_FUNC_I2C] = "i2c",
[PMUX_FUNC_I2C] = "i2c1",
[PMUX_FUNC_I2C2] = "i2c2",
[PMUX_FUNC_I2C3] = "i2c3",
[PMUX_FUNC_IDE] = "ide",

5
arch/arm/mach-tegra/tegra30/Kconfig
View File

@@ -32,6 +32,10 @@ config TARGET_IDEAPAD_YOGA_11
bool "Lenovo Ideapad Yoga 11 board"
select BOARD_LATE_INIT
config TARGET_OUYA
bool "Ouya Game Console board"
select BOARD_LATE_INIT
config TARGET_QC750
bool "Wexler QC750 board"
select BOARD_LATE_INIT
@@ -64,6 +68,7 @@ source "board/toradex/colibri_t30/Kconfig"
source "board/htc/endeavoru/Kconfig"
source "board/asus/grouper/Kconfig"
source "board/lenovo/ideapad-yoga-11/Kconfig"
source "board/ouya/ouya/Kconfig"
source "board/wexler/qc750/Kconfig"
source "board/microsoft/surface-rt/Kconfig"
source "board/avionic-design/tec-ng/Kconfig"