mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge branch 'master' of git://git.denx.de/u-boot-blackfin
This commit is contained in:
Wolfgang Denk
@@ -20,7 +20,7 @@
|
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#define CONFIG_SYS_BFIN_CMD_OTP 0x04
|
||||
#define CONFIG_SYS_BFIN_CMD_CACHE_DUMP 0x08
|
||||
|
||||
/* Bootmode defines -- your config needs to select this via BFIN_BOOT_MODE.
|
||||
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
|
||||
* Depending on your cpu, some of these may not be valid, check your HRM.
|
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* The actual values here are meaningless as long as they're unique.
|
||||
*/
|
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@@ -36,5 +36,6 @@
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#define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */
|
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#define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
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#define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
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#define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
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#endif
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@@ -73,9 +73,4 @@
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#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
|
||||
#endif
|
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|
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#if defined(CONFIG_BF561)
|
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#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */
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#else
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#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */
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#endif
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#endif /* _CPLB_H */
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|
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@@ -337,8 +337,5 @@
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#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
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#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
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#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
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#define pDSPID ((uint32_t volatile *)DSPID)
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#define bfin_read_DSPID() bfin_read32(DSPID)
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#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
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#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */
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|
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@@ -119,7 +119,6 @@
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#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
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#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
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#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
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#define DSPID 0xFFE05000
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#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
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#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
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#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
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@@ -337,8 +337,5 @@
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#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
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#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
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#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
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#define pDSPID ((uint32_t volatile *)DSPID)
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#define bfin_read_DSPID() bfin_read32(DSPID)
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#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
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#endif /* __BFIN_CDEF_ADSP_BF523_proc__ */
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|
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@@ -119,7 +119,6 @@
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#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
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#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
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#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
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#define DSPID 0xFFE05000
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#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
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#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
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#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
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@@ -337,9 +337,6 @@
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#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
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#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
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#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
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#define pDSPID ((uint32_t volatile *)DSPID)
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#define bfin_read_DSPID() bfin_read32(DSPID)
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#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
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#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
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#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
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#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
|
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|
||||
@@ -119,7 +119,6 @@
|
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#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define USB_FADDR 0xFFC03800 /* Function address register */
|
||||
#define USB_POWER 0xFFC03804 /* Power management register */
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||||
#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
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|
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@@ -337,9 +337,6 @@
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#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
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#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
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#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
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#define pDSPID ((uint32_t volatile *)DSPID)
|
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#define bfin_read_DSPID() bfin_read32(DSPID)
|
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#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
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#define pUSB_FADDR ((uint16_t volatile *)USB_FADDR) /* Function address register */
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#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
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#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
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|
||||
@@ -119,7 +119,6 @@
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||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
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||||
#define DSPID 0xFFE05000
|
||||
#define USB_FADDR 0xFFC03800 /* Function address register */
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||||
#define USB_POWER 0xFFC03804 /* Power management register */
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||||
#define USB_INTRTX 0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
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||||
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@@ -337,9 +337,6 @@
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#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
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#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
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#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
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#define pDSPID ((uint32_t volatile *)DSPID)
|
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#define bfin_read_DSPID() bfin_read32(DSPID)
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#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
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#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
|
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#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
|
||||
#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
|
||||
|
||||
@@ -119,7 +119,6 @@
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define DSPID 0xFFE05000
|
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#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
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#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
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||||
#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
|
||||
|
||||
@@ -337,9 +337,6 @@
|
||||
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
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||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
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#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
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#define pEMAC_OPMODE ((uint32_t volatile *)EMAC_OPMODE) /* Operating Mode Register */
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#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
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#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
|
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@@ -119,7 +119,6 @@
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||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define DSPID 0xFFE05000
|
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#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
|
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#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
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#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
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||||
|
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@@ -2,12 +2,12 @@
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* File: include/asm-blackfin/mach-bf527/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
|
||||
* - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
|
||||
*/
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||||
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#ifndef _MACH_ANOMALY_H_
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@@ -23,20 +23,66 @@
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
|
||||
#define ANOMALY_05000265 (1)
|
||||
/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
|
||||
#define ANOMALY_05000301 (1)
|
||||
/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
|
||||
#define ANOMALY_05000312 (1)
|
||||
/* Incorrect Access of OTP_STATUS During otp_write() Function */
|
||||
#define ANOMALY_05000328 (1)
|
||||
/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
|
||||
#define ANOMALY_05000337 (1)
|
||||
/* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
|
||||
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
|
||||
#define ANOMALY_05000341 (1)
|
||||
/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
|
||||
#define ANOMALY_05000342 (1)
|
||||
/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
|
||||
/* USB Calibration Value Is Not Initialized */
|
||||
#define ANOMALY_05000346 (1)
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (1)
|
||||
/* Security Features Are Not Functional */
|
||||
#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* Incorrect Revision Number in DSPID Register */
|
||||
#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* New Feature: Higher Default CCLK Rate */
|
||||
#define ANOMALY_05000368 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* Authentication Fails To Initiate */
|
||||
#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
|
||||
/* Data Read From L3 Memory by USB DMA May be Corrupted */
|
||||
#define ANOMALY_05000380 (1)
|
||||
/* USB Full-speed Mode not Fully Tested */
|
||||
#define ANOMALY_05000381 (1)
|
||||
/* New Feature: Boot from OTP Memory */
|
||||
#define ANOMALY_05000385 (1)
|
||||
/* New Feature: bfrom_SysControl() Routine */
|
||||
#define ANOMALY_05000386 (1)
|
||||
/* New Feature: Programmable Preboot Settings */
|
||||
#define ANOMALY_05000387 (1)
|
||||
/* Reset Vector Must Not Be in SDRAM Memory Space */
|
||||
#define ANOMALY_05000389 (1)
|
||||
/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000392 (1)
|
||||
/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000393 (1)
|
||||
/* New Feature: Log Buffer Functionality */
|
||||
#define ANOMALY_05000394 (1)
|
||||
/* New Feature: Hook Routine Functionality */
|
||||
#define ANOMALY_05000395 (1)
|
||||
/* New Feature: Header Indirect Bit */
|
||||
#define ANOMALY_05000396 (1)
|
||||
/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
|
||||
#define ANOMALY_05000397 (1)
|
||||
/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
|
||||
#define ANOMALY_05000398 (1)
|
||||
/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
|
||||
#define ANOMALY_05000399 (1)
|
||||
/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
|
||||
#define ANOMALY_05000401 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
@@ -49,7 +95,10 @@
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -2,12 +2,12 @@
|
||||
* File: include/asm-blackfin/mach-bf533/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision B, 12/10/2007; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
|
||||
* - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
@@ -164,6 +164,8 @@
|
||||
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
|
||||
/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
|
||||
#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
|
||||
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
|
||||
#define ANOMALY_05000307 (1)
|
||||
/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
|
||||
#define ANOMALY_05000310 (1)
|
||||
/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
|
||||
@@ -176,6 +178,21 @@
|
||||
#define ANOMALY_05000315 (1)
|
||||
/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
|
||||
#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* UART Break Signal Issues */
|
||||
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* PPI Does Not Start Properly In Specific Mode */
|
||||
#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
|
||||
|
||||
/* These anomalies have been "phased" out of analog.com anomaly sheets and are
|
||||
* here to show running on older silicon just isn't feasible.
|
||||
@@ -249,15 +266,10 @@
|
||||
#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
|
||||
/* Internal Voltage Regulator may not start up */
|
||||
#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -2721,9 +2721,6 @@
|
||||
#define pTCOUNT ((uint32_t volatile *)TCOUNT) /* Core Timer Count Register */
|
||||
#define bfin_read_TCOUNT() bfin_read32(TCOUNT)
|
||||
#define bfin_write_TCOUNT(val) bfin_write32(TCOUNT, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pCHIPID ((uint32_t volatile *)CHIPID)
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
|
||||
@@ -911,7 +911,6 @@
|
||||
#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
|
||||
#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
|
||||
#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define CHIPID 0xFFC00014
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
|
||||
@@ -2,12 +2,12 @@
|
||||
* File: include/asm-blackfin/mach-bf537/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision A, 09/04/2007; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
* - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
@@ -132,12 +132,22 @@
|
||||
#define ANOMALY_05000322 (1)
|
||||
/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
|
||||
#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
|
||||
/* New Feature: UART Remains Enabled after UART Boot */
|
||||
#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
||||
#define ANOMALY_05000359 (1)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
|
||||
#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
@@ -148,5 +158,7 @@
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
#define ANOMALY_05000363 (0)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -310,9 +310,6 @@
|
||||
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
|
||||
@@ -110,7 +110,6 @@
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
@@ -310,9 +310,6 @@
|
||||
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
|
||||
@@ -110,7 +110,6 @@
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
@@ -310,9 +310,6 @@
|
||||
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
|
||||
@@ -110,7 +110,6 @@
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
@@ -310,9 +310,6 @@
|
||||
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
|
||||
@@ -110,7 +110,6 @@
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
@@ -310,9 +310,6 @@
|
||||
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
|
||||
@@ -110,7 +110,6 @@
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
@@ -310,9 +310,6 @@
|
||||
#define pIPRIO ((uint32_t volatile *)IPRIO) /* Interrupt Priority Register */
|
||||
#define bfin_read_IPRIO() bfin_read32(IPRIO)
|
||||
#define bfin_write_IPRIO(val) bfin_write32(IPRIO, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pTBUFCTL ((uint32_t volatile *)TBUFCTL) /* Trace Buffer Control Register */
|
||||
#define bfin_read_TBUFCTL() bfin_read32(TBUFCTL)
|
||||
#define bfin_write_TBUFCTL(val) bfin_write32(TBUFCTL, val)
|
||||
|
||||
@@ -110,7 +110,6 @@
|
||||
#define IMASK 0xFFE02104 /* Interrupt Mask Register */
|
||||
#define IPEND 0xFFE02108 /* Interrupt Pending Register */
|
||||
#define IPRIO 0xFFE02110 /* Interrupt Priority Register */
|
||||
#define DSPID 0xFFE05000
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
#define TBUF 0xFFE06100 /* Trace Buffer */
|
||||
|
||||
@@ -2,18 +2,18 @@
|
||||
* File: include/asm-blackfin/mach-bf548/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
* - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
#define _MACH_ANOMALY_H_
|
||||
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
|
||||
/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
|
||||
#define ANOMALY_05000074 (1)
|
||||
/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
|
||||
#define ANOMALY_05000119 (1)
|
||||
@@ -43,7 +43,7 @@
|
||||
#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
|
||||
/* Synchronous Burst Flash Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
|
||||
/* Host DMA Boot Mode Is Not Functional */
|
||||
/* Host DMA Boot Modes Are Not Functional */
|
||||
#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
|
||||
/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
|
||||
#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
|
||||
@@ -61,26 +61,90 @@
|
||||
#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
|
||||
/* USB Calibration Value Is Not Intialized */
|
||||
#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
|
||||
/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
|
||||
/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
|
||||
#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
|
||||
/* Data Lost when Core Reads SDH Data FIFO */
|
||||
#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
|
||||
/* PLL Status Register Is Inaccurate */
|
||||
#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
|
||||
#define ANOMALY_05000353 (1)
|
||||
/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
|
||||
#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
|
||||
/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
|
||||
#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
|
||||
/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* External Memory Read Access Hangs Core With PLL Bypass */
|
||||
#define ANOMALY_05000360 (1)
|
||||
/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
|
||||
#define ANOMALY_05000365 (1)
|
||||
/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
|
||||
#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
|
||||
/* Addressing Conflict between Boot ROM and Asynchronous Memory */
|
||||
#define ANOMALY_05000369 (1)
|
||||
/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
|
||||
#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (__SILICON_REVISION__ < 1)
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
|
||||
#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
|
||||
/* Mobile DDR Operation Not Functional */
|
||||
#define ANOMALY_05000377 (1)
|
||||
/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
|
||||
#define ANOMALY_05000378 (1)
|
||||
/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000379 (1)
|
||||
/* 8-Bit NAND Flash Boot Mode Not Functional */
|
||||
#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
|
||||
/* Some ATAPI Modes Are Not Functional */
|
||||
#define ANOMALY_05000383 (1)
|
||||
/* Boot from OTP Memory Not Functional */
|
||||
#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
|
||||
/* bfrom_SysControl() Firmware Routine Not Functional */
|
||||
#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
|
||||
/* Programmable Preboot Settings Not Functional */
|
||||
#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
|
||||
/* CRC32 Checksum Support Not Functional */
|
||||
#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
|
||||
/* Reset Vector Must Not Be in SDRAM Memory Space */
|
||||
#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
|
||||
/* Changed Meaning of BCODE Field in SYSCR Register */
|
||||
#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
|
||||
/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
|
||||
#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
|
||||
/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
|
||||
/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
|
||||
#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
|
||||
/* Log Buffer Not Functional */
|
||||
#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
|
||||
/* Hook Routine Not Functional */
|
||||
#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
|
||||
/* Header Indirect Bit Not Functional */
|
||||
#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
|
||||
/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
|
||||
#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
|
||||
/* Lockbox SESR Disallows Certain User Interrupts */
|
||||
#define ANOMALY_05000404 (1)
|
||||
/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
|
||||
#define ANOMALY_05000405 (1)
|
||||
/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
|
||||
#define ANOMALY_05000406 (1)
|
||||
/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
|
||||
#define ANOMALY_05000407 (1)
|
||||
/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
|
||||
#define ANOMALY_05000408 (1)
|
||||
/* Lockbox firmware leaves MDMA0 channel enabled */
|
||||
#define ANOMALY_05000409 (1)
|
||||
/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
|
||||
#define ANOMALY_05000411 (1)
|
||||
/* FIFO Boot Mode Is Not Functional */
|
||||
#define ANOMALY_05000412 (1)
|
||||
/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
|
||||
#define ANOMALY_05000413 (1)
|
||||
/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
|
||||
#define ANOMALY_05000414 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000125 (0)
|
||||
@@ -93,7 +157,9 @@
|
||||
#define ANOMALY_05000263 (0)
|
||||
#define ANOMALY_05000266 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000307 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000323 (0)
|
||||
#define ANOMALY_05000363 (0)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -59,38 +59,38 @@
|
||||
#define PORT_x_MUX_7_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_7_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_7_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 14)
|
||||
#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 14)
|
||||
#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 14)
|
||||
#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 14)
|
||||
#define PORT_x_MUX_8_FUNC_1 (PORT_x_MUX_FUNC_1 << 16)
|
||||
#define PORT_x_MUX_8_FUNC_2 (PORT_x_MUX_FUNC_2 << 16)
|
||||
#define PORT_x_MUX_8_FUNC_3 (PORT_x_MUX_FUNC_3 << 16)
|
||||
#define PORT_x_MUX_8_FUNC_4 (PORT_x_MUX_FUNC_4 << 16)
|
||||
#define PORT_x_MUX_9_FUNC_1 (PORT_x_MUX_FUNC_1 << 18)
|
||||
#define PORT_x_MUX_9_FUNC_2 (PORT_x_MUX_FUNC_2 << 18)
|
||||
#define PORT_x_MUX_9_FUNC_3 (PORT_x_MUX_FUNC_3 << 18)
|
||||
#define PORT_x_MUX_9_FUNC_4 (PORT_x_MUX_FUNC_4 << 18)
|
||||
#define PORT_x_MUX_10_FUNC_1 (PORT_x_MUX_FUNC_1 << 20)
|
||||
#define PORT_x_MUX_10_FUNC_2 (PORT_x_MUX_FUNC_2 << 20)
|
||||
#define PORT_x_MUX_10_FUNC_3 (PORT_x_MUX_FUNC_3 << 20)
|
||||
#define PORT_x_MUX_10_FUNC_4 (PORT_x_MUX_FUNC_4 << 20)
|
||||
#define PORT_x_MUX_11_FUNC_1 (PORT_x_MUX_FUNC_1 << 22)
|
||||
#define PORT_x_MUX_11_FUNC_2 (PORT_x_MUX_FUNC_2 << 22)
|
||||
#define PORT_x_MUX_11_FUNC_3 (PORT_x_MUX_FUNC_3 << 22)
|
||||
#define PORT_x_MUX_11_FUNC_4 (PORT_x_MUX_FUNC_4 << 22)
|
||||
#define PORT_x_MUX_12_FUNC_1 (PORT_x_MUX_FUNC_1 << 24)
|
||||
#define PORT_x_MUX_12_FUNC_2 (PORT_x_MUX_FUNC_2 << 24)
|
||||
#define PORT_x_MUX_12_FUNC_3 (PORT_x_MUX_FUNC_3 << 24)
|
||||
#define PORT_x_MUX_12_FUNC_4 (PORT_x_MUX_FUNC_4 << 24)
|
||||
#define PORT_x_MUX_13_FUNC_1 (PORT_x_MUX_FUNC_1 << 26)
|
||||
#define PORT_x_MUX_13_FUNC_2 (PORT_x_MUX_FUNC_2 << 26)
|
||||
#define PORT_x_MUX_13_FUNC_3 (PORT_x_MUX_FUNC_3 << 26)
|
||||
#define PORT_x_MUX_13_FUNC_4 (PORT_x_MUX_FUNC_4 << 26)
|
||||
#define PORT_x_MUX_14_FUNC_1 (PORT_x_MUX_FUNC_1 << 28)
|
||||
#define PORT_x_MUX_14_FUNC_2 (PORT_x_MUX_FUNC_2 << 28)
|
||||
#define PORT_x_MUX_14_FUNC_3 (PORT_x_MUX_FUNC_3 << 28)
|
||||
#define PORT_x_MUX_14_FUNC_4 (PORT_x_MUX_FUNC_4 << 28)
|
||||
#define PORT_x_MUX_15_FUNC_1 (PORT_x_MUX_FUNC_1 << 30)
|
||||
#define PORT_x_MUX_15_FUNC_2 (PORT_x_MUX_FUNC_2 << 30)
|
||||
#define PORT_x_MUX_15_FUNC_3 (PORT_x_MUX_FUNC_3 << 30)
|
||||
#define PORT_x_MUX_15_FUNC_4 (PORT_x_MUX_FUNC_4 << 30)
|
||||
|
||||
/* Port A Masks */
|
||||
#define PA0 0x0001
|
||||
|
||||
@@ -241,9 +241,9 @@
|
||||
#define pITEST_DATA1 ((uint32_t volatile *)ITEST_DATA1)
|
||||
#define bfin_read_ITEST_DATA1() bfin_read32(ITEST_DATA1)
|
||||
#define bfin_write_ITEST_DATA1(val) bfin_write32(ITEST_DATA1, val)
|
||||
#define pSICA_SWRST ((uint32_t volatile *)SICA_SWRST)
|
||||
#define bfin_read_SICA_SWRST() bfin_read32(SICA_SWRST)
|
||||
#define bfin_write_SICA_SWRST(val) bfin_write32(SICA_SWRST, val)
|
||||
#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST)
|
||||
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
|
||||
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
|
||||
#define pSICA_SYSCR ((uint32_t volatile *)SICA_SYSCR)
|
||||
#define bfin_read_SICA_SYSCR() bfin_read32(SICA_SYSCR)
|
||||
#define bfin_write_SICA_SYSCR(val) bfin_write32(SICA_SYSCR, val)
|
||||
@@ -292,9 +292,9 @@
|
||||
#define pSICA_IAR7 ((uint32_t volatile *)SICA_IAR7)
|
||||
#define bfin_read_SICA_IAR7() bfin_read32(SICA_IAR7)
|
||||
#define bfin_write_SICA_IAR7(val) bfin_write32(SICA_IAR7, val)
|
||||
#define pSICB_SWRST ((uint32_t volatile *)SICB_SWRST)
|
||||
#define bfin_read_SICB_SWRST() bfin_read32(SICB_SWRST)
|
||||
#define bfin_write_SICB_SWRST(val) bfin_write32(SICB_SWRST, val)
|
||||
#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST)
|
||||
#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
|
||||
#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val)
|
||||
#define pSICB_SYSCR ((uint32_t volatile *)SICB_SYSCR)
|
||||
#define bfin_read_SICB_SYSCR() bfin_read32(SICB_SYSCR)
|
||||
#define bfin_write_SICB_SYSCR(val) bfin_write32(SICB_SYSCR, val)
|
||||
@@ -400,12 +400,6 @@
|
||||
#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
|
||||
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
|
||||
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pDBGSTAT ((uint32_t volatile *)DBGSTAT)
|
||||
#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
|
||||
#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
|
||||
#define pUART_THR ((uint16_t volatile *)UART_THR)
|
||||
#define bfin_read_UART_THR() bfin_read16(UART_THR)
|
||||
#define bfin_write_UART_THR(val) bfin_write16(UART_THR, val)
|
||||
|
||||
@@ -140,8 +140,6 @@
|
||||
#define SRAM_BASE_ADDR_CORE_A 0xFFE00000
|
||||
#define SRAM_BASE_ADDR_CORE_B 0xFFE00000
|
||||
#define EVT_OVERRIDE 0xFFE02100
|
||||
#define DSPID 0xFFE05000
|
||||
#define DBGSTAT 0xFFE05008
|
||||
#define UART_THR 0xFFC00400
|
||||
#define UART_RBR 0xFFC00400
|
||||
#define UART_DLL 0xFFC00400
|
||||
|
||||
@@ -2,12 +2,12 @@
|
||||
* File: include/asm-blackfin/mach-bf561/anomaly.h
|
||||
* Bugs: Enter bugs at http://blackfin.uclinux.org/
|
||||
*
|
||||
* Copyright (C) 2004-2007 Analog Devices Inc.
|
||||
* Copyright (C) 2004-2008 Analog Devices Inc.
|
||||
* Licensed under the GPL-2 or later.
|
||||
*/
|
||||
|
||||
/* This file shoule be up to date with:
|
||||
* - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
* - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
|
||||
*/
|
||||
|
||||
#ifndef _MACH_ANOMALY_H_
|
||||
@@ -256,15 +256,20 @@
|
||||
#define ANOMALY_05000357 (1)
|
||||
/* Conflicting Column Address Widths Causes SDRAM Errors */
|
||||
#define ANOMALY_05000362 (1)
|
||||
/* UART Break Signal Issues */
|
||||
#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
|
||||
/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
|
||||
#define ANOMALY_05000366 (1)
|
||||
/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
|
||||
#define ANOMALY_05000371 (1)
|
||||
/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
|
||||
#define ANOMALY_05000403 (1)
|
||||
|
||||
/* Anomalies that don't exist on this proc */
|
||||
#define ANOMALY_05000158 (0)
|
||||
#define ANOMALY_05000183 (0)
|
||||
#define ANOMALY_05000273 (0)
|
||||
#define ANOMALY_05000311 (0)
|
||||
#define ANOMALY_05000353 (1)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -63,5 +63,11 @@
|
||||
#define pWPSTAT ((uint32_t volatile *)WPSTAT)
|
||||
#define bfin_read_WPSTAT() bfin_read32(WPSTAT)
|
||||
#define bfin_write_WPSTAT(val) bfin_write32(WPSTAT, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pDBGSTAT ((uint32_t volatile *)DBGSTAT)
|
||||
#define bfin_read_DBGSTAT() bfin_read32(DBGSTAT)
|
||||
#define bfin_write_DBGSTAT(val) bfin_write32(DBGSTAT, val)
|
||||
|
||||
#endif /* __BFIN_CDEF_ADSP_EDN_core__ */
|
||||
|
||||
@@ -25,5 +25,7 @@
|
||||
#define WPDACNT0 0xFFE07180
|
||||
#define WPDACNT1 0xFFE07184
|
||||
#define WPSTAT 0xFFE07200
|
||||
#define DSPID 0xFFE05000
|
||||
#define DBGSTAT 0xFFE05008
|
||||
|
||||
#endif /* __BFIN_DEF_ADSP_EDN_core__ */
|
||||
|
||||
@@ -897,18 +897,15 @@
|
||||
#define pPLL_LOCKCNT ((uint16_t volatile *)PLL_LOCKCNT) /* PLL Lock Count register (16-bit) */
|
||||
#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
|
||||
#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
|
||||
#define pSWRST ((uint32_t volatile *)SWRST) /* Software Reset Register (16-bit) */
|
||||
#define bfin_read_SWRST() bfin_read32(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write32(SWRST, val)
|
||||
#define pSWRST ((uint16_t volatile *)SWRST) /* Software Reset Register (16-bit) */
|
||||
#define bfin_read_SWRST() bfin_read16(SWRST)
|
||||
#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
|
||||
#define pSYSCR ((uint32_t volatile *)SYSCR) /* System Configuration register */
|
||||
#define bfin_read_SYSCR() bfin_read32(SYSCR)
|
||||
#define bfin_write_SYSCR(val) bfin_write32(SYSCR, val)
|
||||
#define pEVT_OVERRIDE ((uint32_t volatile *)EVT_OVERRIDE)
|
||||
#define bfin_read_EVT_OVERRIDE() bfin_read32(EVT_OVERRIDE)
|
||||
#define bfin_write_EVT_OVERRIDE(val) bfin_write32(EVT_OVERRIDE, val)
|
||||
#define pDSPID ((uint32_t volatile *)DSPID)
|
||||
#define bfin_read_DSPID() bfin_read32(DSPID)
|
||||
#define bfin_write_DSPID(val) bfin_write32(DSPID, val)
|
||||
#define pCHIPID ((uint32_t volatile *)CHIPID)
|
||||
#define bfin_read_CHIPID() bfin_read32(CHIPID)
|
||||
#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
|
||||
|
||||
@@ -306,7 +306,6 @@
|
||||
#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
|
||||
#define SYSCR 0xFFC00104 /* System Configuration register */
|
||||
#define EVT_OVERRIDE 0xFFE02100
|
||||
#define DSPID 0xFFE05000
|
||||
#define CHIPID 0xFFC00014
|
||||
#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
|
||||
#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
|
||||
|
||||
@@ -1,321 +0,0 @@
|
||||
/*
|
||||
* U-boot - mem_init.h Header file for memory initialization
|
||||
*
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \
|
||||
CONFIG_MEM_MT48LC64M4A2FB_7E || \
|
||||
CONFIG_MEM_MT48LC16M8A2TG_75 || \
|
||||
CONFIG_MEM_MT48LC8M16A2TG_7E || \
|
||||
CONFIG_MEM_MT48LC8M32B2B5_7 || \
|
||||
CONFIG_MEM_MT48LC32M8A2_75)
|
||||
|
||||
#if ( CONFIG_SCLK_HZ > 119402985 )
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_7
|
||||
#define SDRAM_tRAS_num 7
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 104477612 ) && ( CONFIG_SCLK_HZ <= 119402985 )
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_6
|
||||
#define SDRAM_tRAS_num 6
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 89552239 ) && ( CONFIG_SCLK_HZ <= 104477612 )
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_5
|
||||
#define SDRAM_tRAS_num 5
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 74626866 ) && ( CONFIG_SCLK_HZ <= 89552239 )
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_4
|
||||
#define SDRAM_tRAS_num 4
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 66666667 ) && ( CONFIG_SCLK_HZ <= 74626866 )
|
||||
#define SDRAM_tRP TRP_2
|
||||
#define SDRAM_tRP_num 2
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_2
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 )
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 44776119 ) && ( CONFIG_SCLK_HZ <= 59701493 )
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_3
|
||||
#define SDRAM_tRAS_num 3
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ > 29850746 ) && ( CONFIG_SCLK_HZ <= 44776119 )
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_2
|
||||
#define SDRAM_tRAS_num 2
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#if ( CONFIG_SCLK_HZ <= 29850746 )
|
||||
#define SDRAM_tRP TRP_1
|
||||
#define SDRAM_tRP_num 1
|
||||
#define SDRAM_tRAS TRAS_1
|
||||
#define SDRAM_tRAS_num 1
|
||||
#define SDRAM_tRCD TRCD_1
|
||||
#define SDRAM_tWR TWR_2
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC16M16A2TG_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_2
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC16M8A2TG_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC32M8A2_75)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC8M16A2TG_7E)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_2
|
||||
#endif
|
||||
|
||||
#if (CONFIG_MEM_MT48LC8M32B2B5_7)
|
||||
/*SDRAM INFORMATION: */
|
||||
#define SDRAM_Tref 64 /* Refresh period in milliseconds */
|
||||
#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
|
||||
#define SDRAM_CL CL_3
|
||||
#endif
|
||||
|
||||
#if ( CONFIG_MEM_SIZE == 128 )
|
||||
#define SDRAM_SIZE EBSZ_128
|
||||
#endif
|
||||
#if ( CONFIG_MEM_SIZE == 64 )
|
||||
#define SDRAM_SIZE EBSZ_64
|
||||
#endif
|
||||
#if ( CONFIG_MEM_SIZE == 32 )
|
||||
#define SDRAM_SIZE EBSZ_32
|
||||
#endif
|
||||
#if ( CONFIG_MEM_SIZE == 16 )
|
||||
#define SDRAM_SIZE EBSZ_16
|
||||
#endif
|
||||
#if ( CONFIG_MEM_ADD_WDTH == 11 )
|
||||
#define SDRAM_WIDTH EBCAW_11
|
||||
#endif
|
||||
#if ( CONFIG_MEM_ADD_WDTH == 10 )
|
||||
#define SDRAM_WIDTH EBCAW_10
|
||||
#endif
|
||||
#if ( CONFIG_MEM_ADD_WDTH == 9 )
|
||||
#define SDRAM_WIDTH EBCAW_9
|
||||
#endif
|
||||
#if ( CONFIG_MEM_ADD_WDTH == 8 )
|
||||
#define SDRAM_WIDTH EBCAW_8
|
||||
#endif
|
||||
|
||||
#define mem_SDBCTL SDRAM_WIDTH | SDRAM_SIZE | EBE
|
||||
|
||||
/* Equation from section 17 (p17-46) of BF533 HRM */
|
||||
#define mem_SDRRC ((( CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
|
||||
|
||||
/* Enable SCLK Out */
|
||||
#define mem_SDGCTL ( SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS )
|
||||
|
||||
#define flash_EBIU_AMBCTL_WAT ( ( CONFIG_FLASH_SPEED_BWAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
|
||||
#define flash_EBIU_AMBCTL_RAT ( ( CONFIG_FLASH_SPEED_BRAT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
|
||||
#define flash_EBIU_AMBCTL_HT ( ( CONFIG_FLASH_SPEED_BHT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) )
|
||||
#define flash_EBIU_AMBCTL_ST ( ( CONFIG_FLASH_SPEED_BST * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
|
||||
#define flash_EBIU_AMBCTL_TT ( ( CONFIG_FLASH_SPEED_BTT * 4 ) / ( 4000000000 / CONFIG_SCLK_HZ ) ) + 1
|
||||
|
||||
#if (flash_EBIU_AMBCTL_TT > 3 )
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_TT == 3 )
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_TT == 2 )
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_TT < 2 )
|
||||
#define flash_EBIU_AMBCTL0_TT B0TT_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_ST > 3 )
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_ST == 3 )
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_ST == 2 )
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_ST < 2 )
|
||||
#define flash_EBIU_AMBCTL0_ST B0ST_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_HT > 2 )
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 2 )
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 1 )
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_1
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_0
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
|
||||
#define flash_EBIU_AMBCTL0_HT B0HT_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_WAT > 14)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_15
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 14)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_14
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 13)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_13
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 12)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_12
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 11)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_11
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 10)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_10
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 9)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_9
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 8)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_8
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 7)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_7
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 6)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_6
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 5)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_5
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 4)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 3)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 2)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_WAT == 1)
|
||||
#define flash_EBIU_AMBCTL0_WAT B0WAT_1
|
||||
#endif
|
||||
|
||||
#if (flash_EBIU_AMBCTL_RAT > 14)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_15
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 14)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_14
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 13)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_13
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 12)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_12
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 11)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_11
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 10)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_10
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 9)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_9
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 8)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_8
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 7)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_7
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 6)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_6
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 5)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_5
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 4)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_4
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 3)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_3
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 2)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_2
|
||||
#endif
|
||||
#if (flash_EBIU_AMBCTL_RAT == 1)
|
||||
#define flash_EBIU_AMBCTL0_RAT B0RAT_1
|
||||
#endif
|
||||
|
||||
#define flash_EBIU_AMBCTL0 flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN
|
||||
Reference in New Issue
Block a user