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mtd: spi-nor-core: Track flash's internal address mode
The nor->addr_width tracks number of address bytes used in read/program/erase ops and eventually set to 4 for >16MB chips, regardless of flash's internal address mode. For Infineon SEMPER flash's, we use Read/Write Any Register commands for configuration and status check. These commands take 3- or 4-byte address depending on flash's internal address mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
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committed by
Jagan Teki
parent
ee1c709cfd
commit
4d60001fdf
@@ -2238,10 +2238,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
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case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
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case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
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nor->addr_width = 3;
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nor->addr_mode_nbytes = 3;
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break;
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case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
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nor->addr_width = 4;
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nor->addr_mode_nbytes = 4;
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break;
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default:
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