mtd: spi-nor-core: Track flash's internal address mode

The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Takahiro Kuwano
2022-09-01 15:05:31 +09:00
committed by Jagan Teki
parent ee1c709cfd
commit 4d60001fdf
2 changed files with 7 additions and 0 deletions

View File

@@ -2238,10 +2238,12 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
nor->addr_width = 3;
nor->addr_mode_nbytes = 3;
break;
case BFPT_DWORD1_ADDRESS_BYTES_4_ONLY:
nor->addr_width = 4;
nor->addr_mode_nbytes = 4;
break;
default: