mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2026-06-13 15:03:58 +03:00
Merge branch 'arm/master' into arm/next
Conflicts: board/AtmarkTechno/suzaku/Makefile board/amcc/acadia/acadia.c board/amcc/katmai/katmai.c board/amcc/luan/luan.c board/amcc/ocotea/ocotea.c board/cm-bf537u/Makefile board/cray/L1/L1.c board/csb272/csb272.c board/csb472/csb472.c board/eric/eric.c board/eric/init.S board/eukrea/cpuat91/Makefile board/exbitgen/exbitgen.c board/exbitgen/init.S board/freescale/mpc8536ds/config.mk board/g2000/g2000.c board/jse/sdram.c board/mpl/mip405/mip405.c board/mpl/pip405/pip405.c board/netstal/hcu5/hcu5.c board/netstal/mcu25/mcu25.c board/sc3/sc3.c board/w7o/init.S board/w7o/w7o.c common/cmd_reginfo.c cpu/ppc4xx/40x_spd_sdram.c cpu/ppc4xx/44x_spd_ddr.c doc/README.sbc8548 drivers/misc/fsl_law.c fs/ubifs/ubifs.c include/asm-ppc/immap_85xx.h Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
This commit is contained in:
Tom Rix
File diff suppressed because it is too large
Load Diff
@@ -30,32 +30,27 @@
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* SDRAM Controller
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*/
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/*
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* XXX - ToDo: Revisit file to change all these lower case defines into
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* upper case. Also needs to be done in the controller setup code too
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* of course. sr, 2008-06-02
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*/
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#ifndef CONFIG_405EP
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#define mem_besra 0x00 /* bus error syndrome reg a */
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#define mem_besrsa 0x04 /* bus error syndrome reg set a */
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#define mem_besrb 0x08 /* bus error syndrome reg b */
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#define mem_besrsb 0x0c /* bus error syndrome reg set b */
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#define mem_bear 0x10 /* bus error address reg */
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#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */
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#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */
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#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */
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#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */
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#define SDRAM0_BEAR 0x10 /* bus error address reg */
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#endif
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#define mem_mcopt1 0x20 /* memory controller options 1 */
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#define mem_status 0x24 /* memory status */
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#define mem_rtr 0x30 /* refresh timer reg */
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#define mem_pmit 0x34 /* power management idle timer */
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#define mem_mb0cf 0x40 /* memory bank 0 configuration */
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#define mem_mb1cf 0x44 /* memory bank 1 configuration */
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#define SDRAM0_CFG 0x20 /* memory controller options 1 */
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#define SDRAM0_STATUS 0x24 /* memory status */
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#define SDRAM0_RTR 0x30 /* refresh timer reg */
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#define SDRAM0_PMIT 0x34 /* power management idle timer */
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#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */
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#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */
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#ifndef CONFIG_405EP
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#define mem_mb2cf 0x48 /* memory bank 2 configuration */
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#define mem_mb3cf 0x4c /* memory bank 3 configuration */
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#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */
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#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */
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#endif
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#define mem_sdtr1 0x80 /* timing reg 1 */
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#define SDRAM0_TR 0x80 /* timing reg 1 */
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#ifndef CONFIG_405EP
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#define mem_ecccf 0x94 /* ECC configuration */
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#define mem_eccerr 0x98 /* ECC error status */
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#define SDRAM0_ECCCFG 0x94 /* ECC configuration */
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#define SDRAM0_ECCESR 0x98 /* ECC error status */
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#endif
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#endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */
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@@ -68,36 +63,25 @@
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#define SDRAM_CFG0 0x20 /* memory controller options 0 */
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#define SDRAM_CFG1 0x21 /* memory controller options 1 */
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/*
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* XXX - ToDo: Revisit file to change all these lower case defines into
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* upper case. Also needs to be done in the controller setup code too
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* of course. sr, 2008-06-02
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*/
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#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
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#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
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#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
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#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
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#define mem_bear 0x0010 /* bus error address reg */
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#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
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#define mem_mirq_set 0x0012 /* bus master interrupt (set) */
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#define mem_slio 0x0018 /* ddr sdram slave interface options */
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#define mem_cfg0 0x0020 /* ddr sdram options 0 */
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#define mem_cfg1 0x0021 /* ddr sdram options 1 */
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#define mem_devopt 0x0022 /* ddr sdram device options */
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#define mem_mcsts 0x0024 /* memory controller status */
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#define mem_rtr 0x0030 /* refresh timer register */
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#define mem_pmit 0x0034 /* power management idle timer */
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#define mem_uabba 0x0038 /* plb UABus base address */
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#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
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#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
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#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
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#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
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#define mem_tr0 0x0080 /* sdram timing register 0 */
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#define mem_tr1 0x0081 /* sdram timing register 1 */
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#define mem_clktr 0x0082 /* ddr clock timing register */
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#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
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#define mem_dlycal 0x0084 /* delay line calibration register */
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#define mem_eccesr 0x0098 /* ECC error status */
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#define SDRAM0_BEAR 0x0010 /* bus error address reg */
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#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */
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#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */
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#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */
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#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */
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#define SDRAM0_MCSTS 0x0024 /* memory controller status */
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#define SDRAM0_RTR 0x0030 /* refresh timer register */
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#define SDRAM0_PMIT 0x0034 /* power management idle timer */
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#define SDRAM0_UABBA 0x0038 /* plb UABus base address */
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#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */
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#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */
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#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */
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#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */
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#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */
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#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */
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#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */
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#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */
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#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */
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#define SDRAM0_ECCESR 0x0098 /* ECC error status */
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/*
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* Memory Controller Options 0
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@@ -1,7 +1,7 @@
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/*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* (C) Copyright 2008
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* (C) Copyright 2008-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@@ -43,7 +43,7 @@
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#define UIC_MAX 1
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#endif
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#define IRQ_MAX UIC_MAX * 32
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#define IRQ_MAX (UIC_MAX * 32)
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/*
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* UIC register
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@@ -74,53 +74,41 @@
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#define UIC3_DCR_BASE 0xf0
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#endif
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#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
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#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
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#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
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#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
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#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
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#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
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#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
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#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
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#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */
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#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */
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#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */
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#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
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#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
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#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
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#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */
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#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
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#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
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#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
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#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
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#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
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#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
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#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
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#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
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#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
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#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */
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#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */
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#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */
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#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
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#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
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#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
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#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */
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#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
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#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
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#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
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#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
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#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
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#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
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#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
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#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
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#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
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#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
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#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
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#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */
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#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */
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#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
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#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
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#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
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#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */
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#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
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#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
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#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
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#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
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#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
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#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
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#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
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#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
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#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
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#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
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/* The following is for compatibility with 405 code */
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#define uicsr uic0sr
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#define uicer uic0er
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#define uiccr uic0cr
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#define uicpr uic0pr
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#define uictr uic0tr
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#define uicmsr uic0msr
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#define uicvr uic0vr
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#define uicvcr uic0vcr
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#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
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#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */
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#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */
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#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
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#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
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#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
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#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */
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#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
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/*
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* Now the interrupt vector definitions. They are different for most of
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@@ -216,7 +216,8 @@
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/*
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* Local Bus LCRR and LBCR regs
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*/
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#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \
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| (0xFF << LBCR_BMT_SHIFT) \
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| 0xF ) /* 0x0004ff0f */
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@@ -182,7 +182,8 @@
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR 0x00040000
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/*
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@@ -170,7 +170,8 @@
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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@@ -159,7 +159,8 @@
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2)
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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@@ -206,7 +206,8 @@
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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@@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */
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* External Local Bus rate is
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* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
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@@ -185,7 +185,8 @@
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/*
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* Local Bus Configuration & Clock Setup
|
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*/
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#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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/*
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@@ -382,6 +383,8 @@
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_HWCONFIG 1
|
||||
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/*
|
||||
* QE UEC ethernet configuration
|
||||
*/
|
||||
@@ -397,7 +400,7 @@
|
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
|
||||
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
|
||||
#define CONFIG_SYS_UEC1_PHY_ADDR 0
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII
|
||||
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
|
||||
#endif
|
||||
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#define CONFIG_UEC_ETH2 /* GETH2 */
|
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@@ -408,7 +411,7 @@
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#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
|
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#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
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#define CONFIG_SYS_UEC2_PHY_ADDR 1
|
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#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII
|
||||
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
|
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#endif
|
||||
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||||
/*
|
||||
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||||
@@ -177,7 +177,8 @@
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
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||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
/*
|
||||
|
||||
@@ -220,7 +220,8 @@
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
/*
|
||||
|
||||
@@ -243,7 +243,8 @@
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
/*
|
||||
|
||||
@@ -31,6 +31,22 @@
|
||||
#define CONFIG_PHYS_64BIT 1
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MK_NAND
|
||||
#define CONFIG_NAND_U_BOOT 1
|
||||
#define CONFIG_RAMBOOT_NAND 1
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MK_SDCARD
|
||||
#define CONFIG_RAMBOOT_SDCARD 1
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MK_SPIFLASH
|
||||
#define CONFIG_RAMBOOT_SPIFLASH 1
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
@@ -86,27 +102,44 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
|
||||
#define CONFIG_PANIC_HANG /* do not reset board on panic */
|
||||
|
||||
/*
|
||||
* Config the L2 Cache as L2 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#endif
|
||||
#define CONFIG_SYS_L2_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
|
||||
#else
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
|
||||
#endif
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
|
||||
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
|
||||
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
|
||||
#else
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
@@ -131,9 +164,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
|
||||
/* These are used when DDR doesn't use SPD. */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
|
||||
@@ -145,7 +178,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
|
||||
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
|
||||
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL2 0x04400010
|
||||
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
|
||||
@@ -190,24 +223,36 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
|
||||
#define CONFIG_FLASH_BR_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
|
||||
| BR_PS_16 | BR_V)
|
||||
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_BR1_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
|
||||
CONFIG_SYS_FLASH_BASE_PHYS }
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|
||||
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
@@ -224,7 +269,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
|
||||
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
|
||||
#define PIXIS_VER 0x1 /* Board version at offset 1 */
|
||||
@@ -260,6 +305,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
|
||||
#define PIXIS_LED 0x25 /* LED Register */
|
||||
|
||||
#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
|
||||
|
||||
/* old pixis referenced names */
|
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
|
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
|
||||
@@ -270,18 +317,28 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xfff00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
|
||||
CONFIG_SYS_NAND_BASE + 0x40000, \
|
||||
CONFIG_SYS_NAND_BASE + 0x80000, \
|
||||
@@ -292,43 +349,66 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
/* NAND boot: 4K NAND loader config */
|
||||
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START \
|
||||
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
||||
|
||||
/* NAND flash config */
|
||||
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_NAND_BR_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#ifdef CONFIG_RAMBOOT_NAND
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR4_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR5_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR6_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
@@ -344,8 +424,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
@@ -360,8 +440,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
#define CONFIG_SYS_64BIT_STRTOUL 1
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF 1
|
||||
#define CONFIG_SYS_64BIT_STRTOUL 1
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF 1
|
||||
|
||||
|
||||
/*
|
||||
@@ -526,15 +606,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
@@ -569,14 +640,27 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
@@ -617,7 +701,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
@@ -625,9 +709,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
@@ -635,7 +720,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
@@ -671,7 +756,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_HOSTNAME unknown
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
|
||||
@@ -137,7 +137,8 @@
|
||||
* External Local Bus rate is
|
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
/* LB sdram refresh timer, about 6us */
|
||||
|
||||
@@ -111,7 +111,9 @@
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
|
||||
#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
|
||||
| (0xFF << LBCR_BMT_SHIFT) \
|
||||
| 0xF ) /* 0x0004ff0f */
|
||||
|
||||
@@ -52,7 +52,8 @@
|
||||
* External Local Bus rate is
|
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
|
||||
|
||||
/* board pre init: do not call, nothing to do */
|
||||
#undef CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
@@ -170,7 +170,9 @@
|
||||
/*
|
||||
* Local Bus Configuration & Clock Setup
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
|
||||
/*
|
||||
* Init Local Bus Memory Controller:
|
||||
|
||||
@@ -31,6 +31,21 @@
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* Top level Makefile configuration choices
|
||||
*/
|
||||
#ifdef CONFIG_MK_PCI
|
||||
#define CONFIG_PCI
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MK_66
|
||||
#define PCI_66M
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MK_33
|
||||
#define PCI_33M
|
||||
#endif
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
*/
|
||||
@@ -182,7 +197,8 @@
|
||||
* External Local Bus rate is
|
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
|
||||
|
||||
@@ -330,7 +330,14 @@
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
/*
|
||||
* For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
|
||||
* one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
|
||||
* flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
|
||||
* (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
|
||||
* thing for MONITOR_LEN in both cases.
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
@@ -448,9 +455,16 @@
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
|
||||
#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#else
|
||||
#warning undefined environment size/location.
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
@@ -178,7 +178,8 @@
|
||||
* External Local Bus rate is
|
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
|
||||
*/
|
||||
#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4)
|
||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
||||
#define CONFIG_SYS_LBC_LBCR 0x00000000
|
||||
|
||||
#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */
|
||||
|
||||
Reference in New Issue
Block a user