From 4e184ff5a0e3d6c569e5a5f5a1ad8e3c495ddff9 Mon Sep 17 00:00:00 2001 From: David Lechner Date: Fri, 6 Mar 2026 16:05:50 -0600 Subject: [PATCH] clk: mediatek: add MUX_GATE_MIXED macros Add new MUX_GATE_MIXED and MUX_GATE_MIXED_FLAGS macros for mixed parent muxes that have a gate. These will be used in a few drivers where we already have this type of mux clocks. Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260306-clk-mtk-remove-clk-bypass-xtal-flag-v2-3-b253b49f17b2@baylibre.com Signed-off-by: David Lechner --- drivers/clk/mediatek/clk-mtk.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index d33e5cd2480..5a48f2e002d 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -178,6 +178,22 @@ struct mtk_composite { #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \ MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) +#define MUX_GATE_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _gate,\ + _flags) { \ + .id = _id, \ + .mux_reg = _reg, \ + .mux_shift = _shift, \ + .mux_mask = BIT(_width) - 1, \ + .gate_reg = _reg, \ + .gate_shift = _gate, \ + .parent_flags = _parents, \ + .num_parents = ARRAY_SIZE(_parents), \ + .flags = (_flags) | CLK_PARENT_MIXED, \ + } + +#define MUX_GATE_MIXED(_id, _parents, _reg, _shift, _width, _gate) \ + MUX_GATE_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0) + #define MUX_MIXED_FLAGS(_id, _parents, _reg, _shift, _width, _flags) { \ .id = _id, \ .mux_reg = _reg, \