Xilinx changes for v2023.01-rc3

microblaze:
- Enable 32 bit addressing mode for SPIs

zynq:
- Minor DT fixes (PL clock enabling)

zynqmp:
- Disable watchdog by default
- Remove unused xlnx,eeprom chosen support
- Add missing symlink for vck190 SC revB
- Use mdio bus with ethernet-phy-id description

versal:
- Add mini qspi/ospi configuration

versal-net:
- Add soc driver
- Fix Kconfig entry for SOC
- Fix loading address location for MINI configuration
- Disable LMB for mini configuration

net:
- Fix ethernet-phy-id usage in the code

pinctrl:
- Revert high impedance/output enable support

timer:
- Fix timer relocation for Microblaze
- Fix timer wrap in 32bit Xilinx timer driver
This commit is contained in:
Tom Rini
2022-11-22 12:33:48 -05:00
31 changed files with 468 additions and 74 deletions

View File

@@ -6,6 +6,8 @@
#ifndef _TIMER_H_
#define _TIMER_H_
#define timer_get_ops(dev) ((struct timer_ops *)(dev)->driver->ops)
/**
* dm_timer_init() - initialize a timer for time keeping. On success
* initializes gd->timer so that lib/timer can use it for future