From 81b56a55c21cf3de3e8faa4de3830a9036bf3e5c Mon Sep 17 00:00:00 2001 From: Nikita Shubin Date: Wed, 14 Dec 2022 08:58:43 +0300 Subject: [PATCH 1/6] riscv: cpu: check U-Mode before counteren write The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by: Nikita Shubin Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/cpu.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index d34c8efce09..e1ed4ec01d0 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -33,7 +33,9 @@ u32 available_harts_lock = 1; static inline bool supports_extension(char ext) { -#ifdef CONFIG_CPU +#if CONFIG_IS_ENABLED(RISCV_MMODE) + return csr_read(CSR_MISA) & (1 << (ext - 'a')); +#elif CONFIG_CPU struct udevice *dev; char desc[32]; int i; @@ -58,13 +60,9 @@ static inline bool supports_extension(char ext) return false; #else /* !CONFIG_CPU */ -#if CONFIG_IS_ENABLED(RISCV_MMODE) - return csr_read(CSR_MISA) & (1 << (ext - 'a')); -#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */ #warning "There is no way to determine the available extensions in S-mode." #warning "Please convert your board to use the RISC-V CPU driver." return false; -#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ #endif /* CONFIG_CPU */ } @@ -112,12 +110,14 @@ int riscv_cpu_setup(void *ctx, struct event *event) * Enable perf counters for cycle, time, * and instret counters only */ + if (supports_extension('u')) { #ifdef CONFIG_RISCV_PRIV_1_9 - csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); - csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0)); #else - csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); + csr_write(CSR_MCOUNTEREN, GENMASK(2, 0)); #endif + } /* Disable paging */ if (supports_extension('s')) From c83f64b77dfa08717d697672881dbe33db6786b8 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Tue, 3 Jan 2023 16:17:13 +0800 Subject: [PATCH 2/6] riscv: ae350: Enable CCTL_SUEN CCTL operations are available to Supervisor/User-mode software under the control of the mcache_ctl.CCTL_SUEN control bit. Enable it to support Supervisor(and User) CCTL operations. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/ax25/cpu.c | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c index c4c2de2ef05..a46674f7c25 100644 --- a/arch/riscv/cpu/ax25/cpu.c +++ b/arch/riscv/cpu/ax25/cpu.c @@ -12,18 +12,20 @@ #include #define CSR_MCACHE_CTL 0x7ca -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 +#define CSR_MMISC_CTL 0x7d0 +#define CSR_MARCHID 0xf12 #define V5_MCACHE_CTL_IC_EN_OFFSET 0 #define V5_MCACHE_CTL_DC_EN_OFFSET 1 -#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 +#define V5_MCACHE_CTL_CCTL_SUEN_OFFSET 8 +#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20 -#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) -#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) -#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) +#define V5_MCACHE_CTL_IC_EN BIT(V5_MCACHE_CTL_IC_EN_OFFSET) +#define V5_MCACHE_CTL_DC_EN BIT(V5_MCACHE_CTL_DC_EN_OFFSET) +#define V5_MCACHE_CTL_CCTL_SUEN BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET) +#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET) +#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET) /* @@ -55,6 +57,8 @@ void harts_early_init(void) mcache_ctl_val |= V5_MCACHE_CTL_IC_EN; if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN)) mcache_ctl_val |= V5_MCACHE_CTL_DC_EN; + if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN)) + mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN; csr_write(CSR_MCACHE_CTL, mcache_ctl_val); /* From 5b71b7bf92dd12dfb768180fc25ab4616f077642 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 4 Jan 2023 09:55:43 +0800 Subject: [PATCH 3/6] riscv: ax25: bypass malloc when spl fit boots from ram When fit image boots from ram, the payload will be prepared in the address of SPL_LOAD_FIT_ADDRESS. In spl fit generic flow, it will malloc another memory address and copy whole fit image to this malloc address. But it is un-necessary for booting from RAM. This patch improves this flow by declare the board_spl_fit_buffer_addr() to replace the original one. The larger image size (eq: Kernel Image 10~20MB), it can save more booting time. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/ax25/Makefile | 1 + arch/riscv/cpu/ax25/spl.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/riscv/cpu/ax25/spl.c diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Makefile index 318baccb09c..35a1a2fb836 100644 --- a/arch/riscv/cpu/ax25/Makefile +++ b/arch/riscv/cpu/ax25/Makefile @@ -5,3 +5,4 @@ obj-y := cpu.o obj-y += cache.o +obj-y += spl.o diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/ax25/spl.c new file mode 100644 index 00000000000..413849043b1 --- /dev/null +++ b/arch/riscv/cpu/ax25/spl.c @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation + */ +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if CONFIG_IS_ENABLED(RAM_SUPPORT) +struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) +{ + return (void *)(CONFIG_SPL_LOAD_FIT_ADDRESS + offset); +} + +void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return spl_get_load_buffer(0, sectors * bl_len); +} +#endif From 3c60e59a4f540ae28dc51a4044f9733169cd7081 Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 4 Jan 2023 09:56:28 +0800 Subject: [PATCH 4/6] riscv: memcpy: check src and dst before copy Add src and dst address checking, if they are the same address, just return and don't copy data anymore. Signed-off-by: Rick Chen Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/lib/memcpy.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S index 00672c19ad9..9884077c933 100644 --- a/arch/riscv/lib/memcpy.S +++ b/arch/riscv/lib/memcpy.S @@ -9,6 +9,7 @@ /* void *memcpy(void *, const void *, size_t) */ ENTRY(__memcpy) WEAK(memcpy) + beq a0, a1, .copy_end /* Save for return value */ mv t6, a0 @@ -121,6 +122,7 @@ WEAK(memcpy) 2: mv a0, t6 +.copy_end: ret .Lmisaligned_word_copy: From c5740bc1b2f069a58fae28bee28dbda0e5c6f5dc Mon Sep 17 00:00:00 2001 From: Rick Chen Date: Wed, 4 Jan 2023 10:37:48 +0800 Subject: [PATCH 5/6] riscv: ae350: support OpenSBI 1.0+ which enable FW_PIC Original OpenSBI (without FW_PIC) will relocate itself from 0x1000000 to 0x0. After OpenSBI added FW_PIC codes, it will not relocate any more and always run at 0x1000000. Hence, it may overlap with Kernel memory region. So it is necessary to change OpenSBI address from 0x1000000 to 0x0. More details can refer to commit cb052d771200 ("riscv: qemu: spl: Fix booting Linux kernel with OpenSBI 1.0+") Signed-off-by: Rick Chen Reviewed-by: Samuel Holland Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 36b67f0b524..4bb33b07936 100644 --- a/board/AndesTech/ax25-ae350/Kconfig +++ b/board/AndesTech/ax25-ae350/Kconfig @@ -25,7 +25,7 @@ config SPL_TEXT_BASE default 0x800000 config SPL_OPENSBI_LOAD_ADDR - default 0x01000000 + default 0x00000000 config SYS_FDT_BASE hex From 2b0af9feb594b68a75e4f111bde7f55ddb14995d Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sat, 7 Jan 2023 23:32:39 +0100 Subject: [PATCH 6/6] board: sifive: unmatched: enable booting on a second NVME device The HiFive Unmatched board has a M2 slot for NVME and a PCIe slot that can also be used for NVME. Enable support for a second NVME device, so that software RAID-1 configurations can be supported at the u-boot level. Signed-off-by: Aurelien Jarno Reviewed-by: Heinrich Schuchardt --- include/configs/sifive-unmatched.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h index 24904aa2387..74150b7d4b0 100644 --- a/include/configs/sifive-unmatched.h +++ b/include/configs/sifive-unmatched.h @@ -17,6 +17,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(NVME, nvme, 0) \ + func(NVME, nvme, 1) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ func(SCSI, scsi, 0) \