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i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure

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Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
This commit is contained in:
Graeme Russ
2009-08-23 12:59:56 +10:00
committed by Tom Rix
parent 8866040f6d
commit 5aaeb2a3d4
9 changed files with 539 additions and 534 deletions
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71
cpu/i386/sc520/sc520.c
View File

@@ -33,75 +33,35 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* utility functions for boards based on the AMD sc520
*
* void write_mmcr_byte(u16 mmcr, u8 data)
* void write_mmcr_word(u16 mmcr, u16 data)
* void write_mmcr_long(u16 mmcr, u32 data)
*
* u8 read_mmcr_byte(u16 mmcr)
* u16 read_mmcr_word(u16 mmcr)
* u32 read_mmcr_long(u16 mmcr)
*
* void init_sc520(void)
* unsigned long init_sc520_dram(void)
*/
static u32 mmcr_base= 0xfffef000;
void write_mmcr_byte(u16 mmcr, u8 data)
{
writeb(data, mmcr+mmcr_base);
}
void write_mmcr_word(u16 mmcr, u16 data)
{
writew(data, mmcr+mmcr_base);
}
void write_mmcr_long(u16 mmcr, u32 data)
{
writel(data, mmcr+mmcr_base);
}
u8 read_mmcr_byte(u16 mmcr)
{
return readb(mmcr+mmcr_base);
}
u16 read_mmcr_word(u16 mmcr)
{
return readw(mmcr+mmcr_base);
}
u32 read_mmcr_long(u16 mmcr)
{
return readl(mmcr+mmcr_base);
}
volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
void init_sc520(void)
{
/* Set the UARTxCTL register at it's slower,
* baud clock giving us a 1.8432 MHz reference
*/
write_mmcr_byte(SC520_UART1CTL, 7);
write_mmcr_byte(SC520_UART2CTL, 7);
sc520_mmcr->uart1ctl = 0x07;
sc520_mmcr->uart2ctl = 0x07;
/* first set the timer pin mapping */
write_mmcr_byte(SC520_CLKSEL, 0x72); /* no clock frequency selected, use 1.1892MHz */
sc520_mmcr->clksel = 0x72; /* no clock frequency selected, use 1.1892MHz */
/* enable PCI bus arbitrer */
write_mmcr_byte(SC520_SYSARBCTL,0x02); /* enable concurrent mode */
write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
write_mmcr_word(SC520_HBCTL,0x04); /* enable posted-writes */
sc520_mmcr->sysarbctl = 0x02; /* enable concurrent mode */
sc520_mmcr->sysarbmenb = 0x1f; /* enable external grants */
sc520_mmcr->hbctl = 0x04; /* enable posted-writes */
if (CONFIG_SYS_SC520_HIGH_SPEED) {
write_mmcr_byte(SC520_CPUCTL, 0x2); /* set it to 133 MHz and write back */
sc520_mmcr->cpuctl = 0x02; /* set it to 133 MHz and write back */
gd->cpu_clk = 133000000;
printf("## CPU Speed set to 133MHz\n");
} else {
write_mmcr_byte(SC520_CPUCTL, 1); /* set CPU to 100 MHz and write back cache */
sc520_mmcr->cpuctl = 0x01; /* set it to 100 MHz and write back */
printf("## CPU Speed set to 100MHz\n");
gd->cpu_clk = 100000000;
}
@@ -114,7 +74,7 @@ void init_sc520(void)
"loop 0b\n": : : "ecx");
/* turn on the SDRAM write buffer */
write_mmcr_byte(SC520_DBCTL, 0x11);
sc520_mmcr->dbctl = 0x11;
/* turn on the cache and disable write through */
asm("movl %%cr0, %%eax\n"
@@ -156,10 +116,9 @@ unsigned long init_sc520_dram(void)
val = 3; /* 62.4us */
}
write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4);
val = read_mmcr_byte(SC520_DRCTMCTL);
val &= 0xf0;
val = sc520_mmcr->drctmctl & 0xf0;
if (cas_precharge_delay==3) {
val |= 0x04; /* 3T */
@@ -174,12 +133,12 @@ unsigned long init_sc520_dram(void)
} else {
val |= 1;
}
write_mmcr_byte(SC520_DRCTMCTL, val);
sc520_mmcr->drctmctl = val;
#endif
/* We read-back the configuration of the dram
* controller that the assembly code wrote */
dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
dram_ctrl = sc520_mmcr->drcbendadr;
bd->bi_dram[0].start = 0;
if (dram_ctrl & 0x80) {
@@ -232,7 +191,7 @@ void reset_cpu(ulong addr)
{
printf("Resetting using SC520 MMCR\n");
/* Write a '1' to the SYS_RST of the RESCFG MMCR */
write_mmcr_word(SC520_RESCFG, 0x0001);
sc520_mmcr->rescfg = 0x01;
/* NOTREACHED */
}

64
cpu/i386/sc520/sc520_pci.c
View File

@@ -33,23 +33,23 @@ static struct {
u16 level_reg;
u8 level_bit;
} sc520_irq[] = {
{ SC520_IRQ0, SC520_MPICMODE, 0x01 },
{ SC520_IRQ1, SC520_MPICMODE, 0x02 },
{ SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
{ SC520_IRQ3, SC520_MPICMODE, 0x08 },
{ SC520_IRQ4, SC520_MPICMODE, 0x10 },
{ SC520_IRQ5, SC520_MPICMODE, 0x20 },
{ SC520_IRQ6, SC520_MPICMODE, 0x40 },
{ SC520_IRQ7, SC520_MPICMODE, 0x80 },
{ SC520_IRQ0, 0, 0x01 },
{ SC520_IRQ1, 0, 0x02 },
{ SC520_IRQ2, 1, 0x02 },
{ SC520_IRQ3, 0, 0x08 },
{ SC520_IRQ4, 0, 0x10 },
{ SC520_IRQ5, 0, 0x20 },
{ SC520_IRQ6, 0, 0x40 },
{ SC520_IRQ7, 0, 0x80 },
{ SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
{ SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
{ SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
{ SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
{ SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
{ SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
{ SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
{ SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
{ SC520_IRQ8, 1, 0x01 },
{ SC520_IRQ9, 1, 0x02 },
{ SC520_IRQ10, 1, 0x04 },
{ SC520_IRQ11, 1, 0x08 },
{ SC520_IRQ12, 1, 0x10 },
{ SC520_IRQ13, 1, 0x20 },
{ SC520_IRQ14, 1, 0x40 },
{ SC520_IRQ15, 1, 0x80 }
};
@@ -77,34 +77,34 @@ int pci_sc520_set_irq(int pci_pin, int irq)
/* first disable any non-pci interrupt source that use
* this level */
for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
continue;
}
if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
write_mmcr_byte(i, SC520_IRQ_DISABLED);
}
/* PCI interrupt mapping (A through D)*/
for (i=0; i<=3 ;i++) {
if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority)
sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED;
}
/* GP IRQ interrupt mapping */
for (i=0; i<=10 ;i++) {
if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority)
sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED;
}
/* Set the trigger to level */
write_mmcr_byte(sc520_irq[irq].level_reg,
read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] =
sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit;
if (pci_pin < 4) {
/* PCI INTA-INTD */
/* route the interrupt */
write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority;
} else {
/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority;
/* also set the polarity in this case */
write_mmcr_word(SC520_INTPINPOL,
read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4));
}
/* register the pin */

28
cpu/i386/sc520/sc520_ssi.c
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@@ -61,32 +61,34 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
temp |= PHS_INV_ENB;
}
write_mmcr_byte(SC520_SSICTL, temp);
sc520_mmcr->ssictl = temp;
return 0;
}
u8 ssi_txrx_byte(u8 data)
{
write_mmcr_byte(SC520_SSIXMIT, data);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
return read_mmcr_byte(SC520_SSIRCV);
sc520_mmcr->ssixmit = data;
while (sc520_mmcr->ssista & SSISTA_BSY);
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV;
while (sc520_mmcr->ssista & SSISTA_BSY);
return sc520_mmcr->ssircv;
}
void ssi_tx_byte(u8 data)
{
write_mmcr_byte(SC520_SSIXMIT, data);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
sc520_mmcr->ssixmit = data;
while (sc520_mmcr->ssista & SSISTA_BSY);
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT;
}
u8 ssi_rx_byte(void)
{
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
return read_mmcr_byte(SC520_SSIRCV);
while (sc520_mmcr->ssista & SSISTA_BSY);
sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV;
while (sc520_mmcr->ssista & SSISTA_BSY);
return sc520_mmcr->ssircv;
}

31
cpu/i386/sc520/sc520_timer.c
View File

@@ -30,29 +30,29 @@
void sc520_timer_isr(void)
{
/* Ack the GP Timer Interrupt */
write_mmcr_byte (SC520_GPTMRSTA, 0x02);
sc520_mmcr->gptmrsta = 0x02;
}
int timer_init(void)
{
/* Map GP Timer 1 to Master PIC IR0 */
write_mmcr_byte (SC520_GPTMR1MAP, 0x01);
sc520_mmcr->gp_tmr_int_map[1] = 0x01;
/* Disable GP Timers 1 & 2 - Allow configuration writes */
write_mmcr_word (SC520_GPTMR1CTL, 0x4000);
write_mmcr_word (SC520_GPTMR2CTL, 0x4000);
sc520_mmcr->gptmr1ctl = 0x4000;
sc520_mmcr->gptmr2ctl = 0x4000;
/* Reset GP Timers 1 & 2 */
write_mmcr_word (SC520_GPTMR1CNT, 0x0000);
write_mmcr_word (SC520_GPTMR2CNT, 0x0000);
sc520_mmcr->gptmr1cnt = 0x0000;
sc520_mmcr->gptmr2cnt = 0x0000;
/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
write_mmcr_word (SC520_GPTMR2MAXCMPA, 83);
write_mmcr_word (SC520_GPTMR2CTL, 0xc001);
sc520_mmcr->gptmr2maxcmpa = 83;
sc520_mmcr->gptmr2ctl = 0xc001;
/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
write_mmcr_word (SC520_GPTMR1MAXCMPA, 100);
write_mmcr_word (SC520_GPTMR1CTL, 0xe009);
sc520_mmcr->gptmr1maxcmpa = 100;
sc520_mmcr->gptmr1ctl = 0xe009;
/* Register the SC520 specific timer interrupt handler */
register_timer_isr (sc520_timer_isr);
@@ -62,7 +62,7 @@ int timer_init(void)
unmask_irq (0);
/* Clear the GP Timer 1 status register to get the show rolling*/
write_mmcr_byte (SC520_GPTMRSTA, 0x02);
sc520_mmcr->gptmrsta = 0x02;
return 0;
}
@@ -71,12 +71,13 @@ void udelay(unsigned long usec)
{
int m = 0;
long u;
long temp;
read_mmcr_word (SC520_SWTMRMILLI);
read_mmcr_word (SC520_SWTMRMICRO);
temp = sc520_mmcr->swtmrmilli;
temp = sc520_mmcr->swtmrmicro;
do {
m += read_mmcr_word (SC520_SWTMRMILLI);
u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000);
m += sc520_mmcr->swtmrmilli;
u = sc520_mmcr->swtmrmicro + (m * 1000);
} while (u < usec);
}